CN101937415A

CN101937415A - Processor internal and external data exchange system of embedded signal processing platform

Info

Publication number: CN101937415A
Application number: CN 201010286014
Authority: CN
Inventors: 赵佳; 张涌; 汤心溢; 李丹; 孔军
Original assignee: Shanghai Institute of Technical Physics of CAS
Current assignee: Shanghai Institute of Technical Physics of CAS
Priority date: 2010-09-17
Filing date: 2010-09-17
Publication date: 2011-01-05

Abstract

The invention discloses a processor internal and external data exchange system of an embedded signal processing platform, which is mainly applied to the internal and external data exchange of the embedded signal processing platform based on programmable logic. The technical scheme adopted by the invention comprises a hardware part and a software part. The hardware part mainly comprises a data receiving and transmitting module which is self-developed according to an external data format, and the hardware part is hung on a bus to be used as one of peripheral equipment. The software part mainly comprises interrupt processing and DMA (Direct Memory Access) transmission. The invention has the advantages that the exchange of processor memory and external data is realized by utilizing the data receiving and transmitting module self-developed in an FPGA (Field Programmable Logic Array) and through the interconnection with an embedded system bus, thereby effectively simplifying the steps of inputting and outputting the external data to the memory, saving resources, markedly improving the data exchange rate and satisfying the requirements of large high-frame-frequency and multiband infrared image data quantity.

Description

The inside and outside data exchange system of the processor of embedded signal processing platform

Technical field

The present invention relates to the inside and outside data exchange system of a kind of processor, specifically be meant a kind of inside and outside data exchange system of processor of embedded signal processing platform, it is mainly used in the inside and outside exchanges data of processor of direct interconnection in the embedded infrared signal processing platform.

Background technology

Be accompanied by the trend of miniaturization in design, low-power consumption, increasing people wishes to realize function as much as possible on single chips.SOPC (programmable system on chip) combines the advantage of embedded system and FPGA (programmable gate array) as a kind of special embedded processor system, has more design flexible mode, and possesses the ability of software and hardware at system programmable.And making rapid progress of semiconductor technology makes that the infrared eye frame frequency is more and more faster, the face battle array is increasing, and wave band is more and more, and this just directly causes data volume sharply to increase.This has just proposed higher technical requirement to embedded infrared signal processing platform.At this situation, in infrared information and signal Processing field, taking a kind of effective method solution big data quantity to exchange problem inside and outside flush bonding processor must have very application prospects.

Data exchange inside and outside flush bonding processor in the internal memory of data by certain method importing embedded system that is meant the outside and participate in the algorithm computing, and operation result is delivered to outside next stage treatment facility again.Traditional method is: deposit external data in external memory storage earlier, then by hanging in EMC (external memory controller) the module reading external memory and writing system internal memory on the system bus, the main cause of using EMC is that EMC module one end meets the on-chip bus standard and can be connected with direct bus, the other end can directly be controlled external memory storage, and is easy to operate during use.Its defective is that system overhead is bigger, and several bus cycles just can be converted into the read-write operation of primary memory, and needs other external hardware resources of overhead.Its structured flowchart such as accompanying drawing 1.

To infrared acquisition high resolving power and multispectral application demand, impelled developing rapidly of infrared focal plane device, its face battle array size is increasing and the spectrum dimension is more and more.The data volume that needs to handle is also in continuous increase, embedded system is carried out information and signal Processing, must earlier external data source be imported internal memory, therefore seek a kind of practicality inside and outside data receiving-transmitting method of embedded system fast, current demand is significant for satisfying.

Summary of the invention

Purpose of the present invention is to develop a kind of rapid data receive-transmit system of embedded signal processing platform flush bonding processor, has solved the inside and outside exchanges data problem of embedded signal processing platform processor.

Native system is a SOC (system on a chip) as shown in Figure 2, and the chief component of system is included in a FPGA inside, is made up of microprocessor, internal memory, self-defined transceiver module and DMA (directly storage access) controller.The self-defined transceiver module that can directly be connected with external data is affiliated on internal bus, same microprocessor, and internal memory and DMA (directly storage access) controller and other peripheral hardwares also are connected on the internal bus.Direct like this external data stream is connected to embedded SOC (system on a chip), cooperate independently developed interrupt management module, external data can directly be delivered to flush bonding processor, removed unnecessary data loading procedure in the classic method, simplify transfer process, improve transfer efficiency, thereby realized that embedded system inside and outside data rapidly and efficiently exchange, and the external data demand that satisfies various different-formats.

The self-defined transceiver module of native system is the invention characteristics place of native system, specifically comprises the data transmit-receive coding/decoding module and the interrupt management module of independent development, and existing bus interface module.Its structured flowchart as shown in Figure 3.Data transmit-receive coding/decoding module and interrupt management module are connected to bus interface module directly are connected, obtain bus command, finish control communication with on-chip bus.

Wherein data transmit-receive coding/decoding module work flow diagram as shown in Figure 4, this module is write according to the external data stream format is self-defined.When receiving data, at first buffer memory external data stream is decoded from data stream then and is obtained the binary format of valid data, and it is sent into bus interface FIFO by specified order, waits for that bus command reads write memory.When sending data, at first obtaining the binary format of valid data from bus interface FIFO, and according to the external data call format it is encoded to output block, is continuous data stream with discrete data-block cache then, sends system.

Wherein interrupt management module work flow diagram is write the interrupt management module and is realized interrupt management as shown in Figure 5.Flow when effective when parsing obtains external data, produce look-at-me and also generate the interrupt source identification number, then look-at-me and interrupt source identification number are sent into bus interface together, produce the interrupt notification embedded microprocessor and receive data.Have no progeny during processor obtains and start dma controller reception external data.

Total work flow process of native system is, at first external data flows to into self-defined transceiver module, enter bus interface module after data decode and the unloading, the interrupt management module then is responsible for producing interrupt notification dma controller reception data and is entered internal memory, then can handle the data in the internal memory, but data transmit-receive and data handling procedure line production.When data processing is finished need send as a result the time, at first flush bonding processor sends bus line command, notify self-defined transceiver module to have internal data to arrive from bus, simultaneously bus is transferred to DMA control, data are transferred to the interface buffer memory of self-defined transceiver module from internal memory, self-defined transceiver module forms data stream and delivers to outside the sheet then according to demand with digital coding.

The present invention is characterised in that:

(1) external data is directly injected embedded SOC (system on a chip), the direct and on-chip bus interconnection by the self-defining data transceiver module.

(2) data transmit-receive module of use self defined interface according to external data formal definition interface and transmitting-receiving logic, can be changed according to demand at any time.

Advantage of the present invention is:

(1) data flow is simple and direct, has both saved hardware resource, has reduced the sequential expense of system again to a great extent.

(2) external data that can satisfy various different-formats flows, and satisfies the dirigibility of design more, and simple in structure being easy to realized.

Description of drawings

Fig. 1 is the classic method structured flowchart.

Fig. 2 is this method system architecture diagram.

Fig. 3 is the data transmit-receive module cut-away view.

Fig. 4 is a data transmit-receive form coding/decoding module work flow diagram.

Fig. 5 is an interrupt management module work flow diagram.

Embodiment

One embodiment of the present of invention are as follows:

Implement on an embedded infrared signal processing platform, the main hardware environment is: the FPGA device adopts the XC5VFX70T-FF1136-1 programmable logic device (PLD) of XILINX company, and flush bonding processor adopts device inside stone PowerPC440 processor.System reference clock 100MHZ, processor clock 300MHZ (the highest 400MHZ), bus clock 125MHZ.At sheet Memory64KB, Installed System Memory DDR2_SDRAM256MB.System bus PLB_v4.6 version.External data source adopts infrared big battle array Digital Simulation video flowing, and its form is a face battle array 512 * 512, and frame frequency can be self-defined.Test result shows, first bus cycles are fallen by system overhead after the DMA transmission is opened, each bus cycles can be finished a data manipulation later on, the live width of bus is 32bit in the experiment, the data of the fully loaded transmission of bus are the most large stretch of, and to go up speed be 125MHZ * 32bit=4000Mbit/s, can satisfy this experiment external data and flow to transmission requirement into internal memory.When PLB bus live width reaches the theoretical maximum 125MHZ * 128bit of speed on the data slice during for 128bit, be 16000Mbit/s.Consider the transmission requirement of signal integrity and external data stream signal, further checking is not done in this experiment to this.This method can satisfy the data signaling rate requirement of most of high frame frequency large area array infrared detectors, and the succinct easily realization of system constructing, and very big application prospect is arranged.

Claims

1. the inside and outside data exchange system of the processor of an embedded signal processing platform, it by microprocessor, internal memory, self-defined transceiver module and directly the storage access controller form, it is characterized in that:

Described by data transmit-receive coding/decoding module, interrupt management module, and self-defined transceiver module, microprocessor, internal memory and direct storage access controller that existing bus interface module is formed are connected on the FPGA internal bus;

Data stream from the outside enters self-defined transceiver module, enters bus interface module after data decode and the unloading, and the interrupt management module then is responsible for producing the direct storage access controller receiving data of interrupt notification and is entered internal memory, and the data in the internal memory are handled; When data processing is finished need send as a result the time, at first flush bonding processor sends bus line command, notify self-defined transceiver module to have internal data to arrive from bus, simultaneously bus is transferred to direct storage access controller control, data are transferred to the interface buffer memory of self-defined transceiver module from internal memory, self-defined transceiver module forms data stream and delivers to outside the sheet then according to demand with digital coding.

2. the inside and outside data exchange system of the processor of a kind of embedded signal processing platform according to claim 1, it is characterized in that, the workflow of the data transmit-receive coding/decoding module in the described self-defined transceiver module is: when receiving data, at first the buffer memory external data flows, obtain the binary format of valid data then from the data stream decoding, and it is sent into bus interface FIFO by specified order, wait for that bus command reads write memory.When sending data, at first obtaining the binary format of valid data from bus interface FIFO, and according to the external data call format it is encoded to output block, is continuous data stream with discrete data-block cache then, sends system.

3. the inside and outside data exchange system of the processor of a kind of embedded signal processing platform according to claim 1, it is characterized in that, interrupt management module workflow in the described self-defined transceiver module is: flow when effective when parsing obtains external data, produce look-at-me and generate the interrupt source identification number, then look-at-me and interrupt source identification number are sent into bus interface together, produce the interrupt notification embedded microprocessor and receive data.