CN101930479A - Peripheral-component interface express (PCIE)-based multi-channel data acquisition unit - Google Patents

Peripheral-component interface express (PCIE)-based multi-channel data acquisition unit Download PDF

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CN101930479A
CN101930479A CN 201010267027 CN201010267027A CN101930479A CN 101930479 A CN101930479 A CN 101930479A CN 201010267027 CN201010267027 CN 201010267027 CN 201010267027 A CN201010267027 A CN 201010267027A CN 101930479 A CN101930479 A CN 101930479A
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data
channel
pcie
multi
unit
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CN101930479B (en )
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余金培
刘会杰
梁广
龚文斌
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中国科学院上海微系统与信息技术研究所
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Abstract

The invention discloses a PCIE-based multi-channel data acquisition unit. By adopting a PCIE protocol, a feedback type enhanced phase lock loop and a pingpong buffer structure, the multi-channel high-rate data sampling, the clock synchronization among channels and the data transmission real-time property of each channel can be realized.

Description

一种基于PCIE协议的多通道数据采集装置 Based on multi-channel data collection device protocol PCIE

技术领域 FIELD

[0001] 本发明涉及一种数据采集装置,特别涉及一种基于PCIE协议的多通道数据采集 [0001] The present invention relates to a data acquisition device, and particularly relates to a multi-channel protocol based data acquisition PCIE

直ο Straight ο

背景技术 Background technique

[0002] 当前数字信号处理技术以日新月异的速度发展,“软件无线电”的设计理念日益得到业界认可。 [0002] Current digital signal processing technology to the rapid pace of development, "software radio" design concept is increasingly recognized by the industry. “软件无线电”技术的核心就是将模数转换更靠近射频天线,即希望更多应用数字信号处理技术。 Core "software radio" techniques is closer to the analog to digital conversion RF antenna, i.e. more desirable application of digital signal processing techniques. 当前关于数字信号处理的基础理论已经发展很成熟,这样可以更好利用这些先进技术成果,提高系统的整体质量。 The current theory on the basis of digital signal processing has developed very mature, so you can better take advantage of these advanced techniques to improve the overall quality of the system.

[0003] 但是“软件无线电”技术核心需要高速的数据采集装置支持,因为根据奈奎斯特定理,模数转换越靠近射频天线,采样信号频点越高,则数据采样率越高(奈奎斯特定理中,最低采样速率一般为采样信号最高频率的2倍)。 [0003] However, "Software Radio" technology requires high-speed data acquisition core support means, because, according to the Nyquist theorem, the closer analog to digital conversion RF antenna, the higher the sampling signal frequency, the higher the data sampling rate (Naikui 's theorem, the minimum sampling rate of the highest frequency sampled signal is typically 2 times). 采样速率越高,则后端数据总线的传输压力越大。 The higher the sampling rate, the delivery pressure of the rear end of the data bus increases. 以采样率300MHz、量化比特为12bit的单通道模数转换为例,数据传输率为3. 6Gbps,这是当前常规总线接口如USB、以太网口不能支持的。 At a sampling rate of 300MHz, a single-channel quantization bits 12bit analog-digital conversion, for example, the data transfer rate of 3. 6Gbps, which is the current conventional bus interface such as USB, Ethernet port can not support. 若是多通道数据并行采样处理,则数据传输率更为惊人。 If multi-channel data sampling processing in parallel, the data transfer rate is even more striking.

[0004] 当前数字通信发展越来越迅速,相控阵天线、智能天线等阵列信号处理场景需要并行的多通道模数采样,对各通道之间的时钟同步性要求很高。 [0004] The more rapid development of current digital communication, a phased array antenna, and other smart antenna array signal processing scenarios require concurrent multi-channel analog to digital sampling, high requirements on clock synchronization between the various channels. 各通道之间的时钟同步性甚至成为相控阵天线中波束形成效果的关键因素,因此对多通道数据采集装置的时钟设计提出了很高的要求。 Clock synchronization even become a key factor in the phased array antenna beam forming effect between the channels, so the clock design multichannel data acquisition device makes high requirements. 此外,随着数据采集的通道越多,各通道的数据传输实时性成为多通道数据采集设计的一个难点。 In addition, as more data acquisition channels, each channel data transmission of real-time into a multichannel data acquisition difficult design.

发明内容 SUMMARY

[0005] 本发明的目的在于提供一种基于PCIE协议的多通道数据采集装置,有效实现多通道的高速数据采样、各通道之间的时钟同步性以及各通道的数据传输实时性。 [0005] The object of the present invention is to provide a multi-channel data acquisition means based PCIE protocol, effective multi-channel high-speed data sampling clock synchronization of real-time data transmission as well as the respective channels between the various channels.

[0006] 本发明提供一种基于PCIE协议的多通道数据采集装置,其包括模数转换模块、通道状态设置模块、微处理器模块、以及PCIE协议接口模块,其中,所述模数转换模块包括多个模数转换通道,每一模数转换通道实现一路模拟信号的模数转换;所述通道状态设置模块根据用户的要求设置每一模数转换通道的接入状态;所述微处理器模块根据所述通道状态设置模块的设置,通过反馈式增强型锁相环为所述多个模数转换通道提供采样时钟,并且,利用乒乓buffer结构对所述多个模数转换通道输出的数据进行实时接收和暂存,所述数据经合路复接、PCIE协议层处理及PCIE物理层处理后发送给所述PCIE协议接口模块; 所述PCIE协议接口模块包括PCIE接口的接插件,用于与用户数据处理装置的PCIE插槽连接,以将数据传输给所述用户数据处理装置。 [0006] The present invention provides a multi-channel data acquisition means PCIE based protocol, including analog to digital conversion module, channel status setting module, microprocessor module and PCIE protocol interface module, wherein the analog to digital conversion module comprises a plurality of analog to digital conversion channels, each channel ADC way to achieve analog to digital conversion of the analog signal; a channel status setting module the access channel state of each analog to digital conversion according to the user's requirements; the microprocessor module the setting module sets the channel status of the channel of the plurality of analog to digital conversion a sampling clock provided by the phase-locked loop feedback is enhanced, and the ping-pong buffer structure using a plurality of analog to digital conversion of the data channel outputted receiving and temporarily storing in real time, the data multiplexed by the combiner is sent to the protocol interface module after PCIE PCIE PCIE protocol layer and the physical layer processing process; the protocol interface module connector includes PCIE PCIE interface for the PCIE slot user data processing device is connected, to transmit data to the user data processing apparatus.

[0007] 在上述基于PCIE协议的多通道数据采集装置中,所述通道状态设置模块包括与所述多个模数转换通道对应的多通道的拨码开关,每一通道的拨码开关用于设置对应的模数转换通道的接入或断开。 [0007] In the multi-channel data acquisition means based PCIE protocol, the channel state DIP switch DIP switch setting module comprises a multi-channel analog to digital conversion of the plurality of corresponding channels, for each channel set the access channel corresponding to the analog to digital conversion or disconnection. [0008] 在上述基于PCIE协议的多通道数据采集装置中,所述微处理器模块配置成具有通道状态控制单元、模数转换接口单元、各通道数据暂存单元、数据合路复接单元、PCIE协议层处理单元、以及PCIE物理层处理单元,其中,所述通道状态控制单元根据所述通道状态设置模块发送来的各模数转换通道的接入状态,形成各模数转换通道的使能控制信号, 决定所述模数转换接口单元向对应的模数转换通道提供采样时钟、所述各通道数据暂存单元的读使能信号以及所述数据合路复接单元中的时隙控制;所述模数转换接口单元利用反馈式增强型锁相环向对应的模数转换通道提供采样时钟,并且,在各模数转换通道完成模数转换处理后,对各模数转换通道通过数字总线发送来的数据进行对应的物理层和协议层处理;所述各通道数据暂存单元利用乒乓buffer结构对所 [0008] In the multi-channel data acquisition means based PCIE protocol, the microprocessor module is configured to have a channel state control unit, an interface unit analog-digital conversion, the channel data temporary storing unit, the data unit multiplexing combiner, PCIE protocol layer processing unit, and PCIE physical layer processing unit, wherein the channel state control unit according to the channel status setting module sent by the access states of the respective analog to digital conversion channels, forming each ADC channel enable control signal, determines the analog-digital conversion channel interface unit to a corresponding conversion module to provide a sampling clock, the temporary storage data of each channel read enable signal means and said data combiner multiplexing time slot control unit; after digital conversion interface unit using the phase-locked loop to provide enhanced feedback to the analog to digital conversion a sampling clock corresponding to the channels, and the analog to digital conversion process in the analog to digital conversion channels, each channel analog to digital conversion through the digital bus data to be transmitted and the physical layer corresponding to the protocol layer processing; the temporary storage unit by using the channel data structure of the ping-pong buffer 模数转换接口单元输出的数据进行暂存;所述数据合路复接单元将所述各通道数据暂存单元输出的数据合路复接成一路信号;所述PCIE协议层处理单元对所述数据合路复接单元输出的数据进行PCIE协议层处理;所述PCIE物理层处理单元对所述PCIE协议层处理单元输出的数据进行PCIE物理层处理。 Analog to digital conversion data storing temporarily an output interface unit; said data combiner unit multiplexing the data combiner temporary storage unit outputs the respective data channels multiplexed into one signal; PCIE said processing unit to said protocol layer data combiner unit outputs multiplexed PCIE protocol layer processing is performed; PCIE the physical layer processing unit of the data processing unit outputs the PCIE protocol layer PCIE physical layer processing.

[0009] 在上述基于PCIE协议的多通道数据采集装置中,所述多个模数转换通道输出的数据通过采用源同步总线标准的数字总线传输给所述模数转换接口单元。 [0009] In the multi-channel data acquisition means based PCIE protocol, said plurality of analog to digital conversion of data output from the digital bus channel transmission using source synchronous bus standard to digital conversion by the interface unit.

[0010] 在上述基于PCIE协议的多通道数据采集装置中,还包括微处理器辅助工作模块, 所述微处理器辅助工作模块与所述微处理器模块相连,其包括RC电路、固化存储器以及晶振电路,所述RC电路为所述微处理模块提供电源去耦,所述固化存储器为所述微处理器模块的配置程序提供存储空间,所述晶振电路为所述微处理器模块提供源时钟。 [0010] In the multi-channel data acquisition means based PCIE protocol, further comprising a microprocessor connected to an auxiliary operating module, the microprocessor module and the auxiliary work microprocessor module, which comprises an RC circuit, a memory and cured crystal oscillator circuit, the micro-processing module provides power decoupling, the cured module microprocessor program memory is configured to provide storage space for the microprocessor module of the source clock of the RC circuit, the said oscillating circuit .

[0011] 在上述基于PCIE协议的多通道数据采集装置中,通过所述PCIE协议接口模块接入所述用户数据处理装置的电源,实现电力供给。 [0011] In the multi-channel data acquisition means based PCIE protocol by the protocol interface module PCIE user access to the data processing apparatus power supply, the power supply to achieve.

[0012] 与现有技术相比,本发明提供的基于PCIE协议的多通道数据采集装置具有以下优点: [0012] Compared with the prior art, multi-channel data acquisition device based on the present invention provides the following advantages PCIE protocol:

[0013] 1、本发明通过采用PCIE协议,传输数据吞吐量最高可达5GB/s,同时还可以提供多个模数转换通道,每通道最高采样率可以达到300MHz,量化比特可以达到12bit,数据采集功能强大,可应用于高速阵列信号处理中; [0013] 1, PCIE protocol by using the present invention, data transmission throughput of up to 5GB / s, while providing a plurality of analog to digital conversion channels, each maximum sampling rate can reach 300MHz, 12bit quantization bits can be achieved, the data powerful collection, can be applied to high-speed signal processing array;

[0014] 2、本发明通过采用反馈式增强型锁相环,各模数转换通道间的时钟偏斜在20ps 以内,时钟同步性能优异,在时钟同步性能要求很高的应用场景(如相控阵天线波束形成网络的设计等)中有极大的优势; [0014] 2, the present invention is enhanced by employing a phase-locked loop feedback, among ADC channels within 20ps clock skew, clock synchronization excellent performance, high performance requirements of the application scenario clock synchronization (e.g., phase control ) has great advantages in design of array antenna beam forming network;

[0015] 3、本发明通过采用乒乓buffer结构,保证采样数据传输中的读写过程不碰撞,从而确保无帧丢失的实时性数据传输,最大限度保护采集数据的完整性; [0015] 3, according to the present invention by using a ping-pong buffer structure, reading and writing process to ensure that the sample does not collide with data transmission, thus ensuring data transmission in real time with no frame loss, the maximum protection of the integrity of the data collection;

[0016] 4、本发明提供通过采用通道状态设置模块,可以根据用户需要,灵活选择模数转换通道数目,同时也减轻计算机的PCIE总线的传输压力; [0016] 4, the present invention provides a use channel status setting module, according to user needs, the flexibility to choose the number of analog to digital conversion channels, but also reduce the pressure transmission PCIE bus of the computer;

[0017] 5、本发明在物理外形上采用具有热插拔特性的PCIE插卡结构,可灵活插入当前各种计算机主板的PCIE插槽中,同时,由于可从这些主板取电,无需从外部供给电力,为产品一体化的设计带来便利。 [0017] 5, the present invention employs a configuration having a hot swap card PCIE characteristics on physical appearance, can be flexibly inserted into the computer's motherboard PCIE various current slot, and since these can take power from the main board, from the outside without power supply, integrated product design convenience.

附图说明 BRIEF DESCRIPTION

[0018] 图1为本发明的基于PCIE协议的数据采集装置的结构示意图;[0019] 图2为反馈式增强型锁相环的原理框图; [0018] FIG. 1 structure based on the data collection device PCIE protocol of the present invention; and FIG schematic block diagram of a phase-locked loop feedback reinforcement [0019] Figure 2;

[0020] 图3为各通道数据暂存与合路的原理框图。 [0020] FIG. 3 is a schematic block diagram of the channel data temporarily stored in the combiner.

具体实施方式 detailed description

[0021 ] 首先,对本发明采用的PCIE接口进行说明。 [0021] First, the PCIE interface employed in the invention will be described. PCIE接口能够实现高速数据传输,是当前个人电脑主板中流行的数据接口。 PCIE interface enables high-speed data transmission, a current popular PC motherboards data interface. PCIE接口全称为PCI Express,采用了目前业内流行的点对点串行连接方式,与PCI接口以及更早期的计算机总线的共享并行架构相比,每个设备都有自己的专用连接,不需要向整个总线请求带宽,可以把数据传输率提高到一个很高的速率,达到PCI接口所不能提供的高带宽。 Full PCIE interface called PCI Express, using the industry's popular point to point serial connection, compared with the earlier PCI interface and a shared parallel computer bus architecture, each device has its own dedicated connection, does not require the entire bus requested bandwidth, the data transfer rate can increase to a very high rate, to achieve high bandwidth PCI interface can not provide. 而且,相对于传统PCI总线在单一时间周期内只能实现单向传输,PCIE的双单工连接能提供更高的传输速率和质量。 Further, with respect to the conventional PCI bus within a single period of time only one-way transmission, the PCIE dual simplex connection can provide higher transmission rates and quality. PCIE的接口根据总线位宽不同而有所差异,包括XI、X4、X8以及X16模式,其中X2模式将用于内部接口而非插槽模式。 PCIE bus interface depending on the bit width vary, including XI, X4, X8 and X16 mode, the mode in which X2 rather than for the internal interface slot mode. PCIE的规格从1条通道连接到32条通道连接,有非常强的伸缩性,以满足不同系统设备对数据传输带宽不同的需求。 PCIE specifications connected to the channel from a 32 channel connection, a very strong flexibility to meet different systems different devices for data transfer bandwidth requirements. 此外,较短的PCIE卡可以插入较长的PCIE插槽中使用,PCIE接口还能够支持热拔插,这也是个不小的飞跃。 In addition, the shorter PCIE card can be inserted in the use of longer PCIE slot, PCIE interface also supports hot-swappable, which is no small leap. PCIE Xl的250MB/秒传输速度,而PCIE接口位宽为X16,能够提供5GB/s的带宽,即使有编码上的损耗,但仍能够提供约为4GB/s左右的实际带宽。 250MB / sec speeds Xl PCIE, and the bit width X16 PCIE interface, capable of providing the bandwidth 5GB / s, even in the lossy encoding, but still provide the actual bandwidth of approximately 4GB / s approximately. 在兼容性方面,PCIE在软件层面上兼容目前的PCI技术和设备,支持PCI设备和内存模组的初始化,即过去的驱动程序、操作系统都可以支持PCIE设备。 In terms of compatibility, PCIE compatible on the software level with existing PCI technology and equipment to support the PCI devices and memory modules for initialization, that is, the last driver, the operating system can support PCIE devices. 这为产品的升级和PC端程序界面的开发都带来了极大的方便。 This upgrade product development and PC-side program interface have brought great convenience.

[0022] 为使本发明的目的、特征更明显易懂,下面结合附图对本发明的具体实施方式作进一步的说明。 [0022] For purposes of the present invention, features more fully understood in conjunction with the following drawings of specific embodiments of the present invention will be further described.

[0023] 如图1所示,本发明的基于PCIE协议的多通道数据采集装置包括模数转换模块1、 微处理器模块2、PCIE协议接口模块3、微处理器辅助工作模块4、以及通道状态设置模块5。 [0023] As shown, multi-channel data acquisition device based on the present invention PCIE protocol comprises an analog to digital converter module, microprocessor module 2, 3 PCIE protocol interface module, a microprocessor module auxiliary work 4, and the channel 1 state setting module 5.

[0024] 模数转换模块1包括多个模数转换通道,每一模数转换通道实现一路模拟信号的模数转换。 [0024] The analog to digital conversion module 1 comprises a plurality of analog to digital conversion channels, each channel ADC way to achieve analog to digital conversion of the analog signal. 在本实施例中,举出四个模数转换通道的示例进行说明:第一模数转换通道11、 第二模数转换通道12、第三模数转换通道13、第四模数转换通道14。 In the present embodiment, examples thereof include four channel analog to digital conversion will be described: a first analog to digital converter channel 11, second channel ADC 12, ADC channel 13 third, fourth channel analog to digital converter 14 . 以第一模数转换通道11为例说明其构成。 A first analog to digital converter channels 11 which constitutes an example. 第一模数转换通道11包括AD转换接插件111、AD转换变压器电路子单元112、AD转换电路子单元113。 A first analog to digital converter 11 comprises an AD converter channel connector 111, AD conversion sub-unit transformer circuit 112, AD conversion circuits 113 subunit. 其中,AD转换接插件111可以为SMA同轴电缆接插件, 负责将模拟信号沿同轴电缆接入,通过Pcb走线传给后续的AD转换变压器电路子单元112。 Wherein, the AD conversion SMA connector 111 may be a coaxial cable connector, is responsible for access to the analog signal in a coaxial cable, to pass through the line away Pcb subsequent AD conversion sub-unit transformer circuit 112. AD转换变压器电路子单元112核心为一变压器,在此有两个作用:一是阻抗匹配,将输入阻抗调整为50欧姆,这样可以减少输入信号反射,维护输入信号完整性;二是隔直,将上游设备输入信号直流偏置与本发明设备隔离,减少两级设备间直流耦合之间的影响。 AD conversion sub-unit transformer circuit 112 is a transformer core, this has two effects: first impedance, the input impedance is adjusted to 50 ohms, thus reducing the input signal is reflected, input to maintain signal integrity; Second blocking, the upstream device input signal and the DC bias isolation apparatus of the present invention to reduce the impact between the DC coupling between the two devices. 输入信号经过AD转换变压器电路子单元112后传给后续的AD转换电路子单元113,在此实现模拟信号到数字信号的转换。 Input signal through the AD conversion sub-unit transformer circuit to pass subsequent AD conversion circuit 113 after sub-unit 112, this analog signal into a digital signal. 需要注意的是,整个模数转换过程是依据微处理器模块2发送给第一模数转换通道11的采样时钟信号cl来进行模数转换的。 Note that the entire analog to digital conversion process is performed based on analog to digital conversion a sampling clock signal cl microprocessor module 2 transmits to the first analog to digital converter channels 11. 在此,模数转换的最高采样率可以达到300MHz,输入的模拟信号峰值为lv,被量化成12bit的数字信号,通过后续的数字总线si〜s4传给微处理器模块2。 In this case, analog to digital conversion sampling rate can reach up to 300MHz, is the analog input signal peak LV, 12bit quantized into a digital signal through a digital bus si~s4 subsequent pass 2 the microprocessor module. 在本实施例中,数据总线si〜s4采用源同步总线标准。 In the present embodiment, the data bus using source synchronous bus standard si~s4. 其他三个通道的组成、配置以及模数转换机理与第一模数转换通道11相同。 The composition of the other three channels, and the same configuration of the first analog to digital conversion mechanism D conversion channels 11.

[0025] 通道状态设置模块5与微处理器模块2相连,根据用户的要求设置每一模数转换通道的接入状态。 [0025] channel status setting module 5 is connected to the microprocessor module 2, setting the access channel state of each analog to digital conversion according to the user's requirements. 例如,通道状态设置模块5可以包括与上述四个模数转换通道对应的四通道的拨码开关52,每一通道的拨码开关用于设置对应的模数转换通道的接入或断开。 For example, channel status setting module 5 may comprise the above-described four channel analog to digital converter corresponding to four channels of 52 DIP switch, the DIP switch of each channel analog to digital conversion for the access channel corresponding to the setting on or off. 每一通道的拨码开关用“ON”和“OFF”状态分别代表对应的模数转换通道的接入或断开,例如四通道的拨码开关52的状态为“0N0FF ON OFF”,则表示第一、第三模数转换通道接入准备使用,同时第二、第四模数转换通道断开不使用。 DIP switch with each channel "ON" and "OFF" represent the state of the corresponding access channel analog to digital conversion on or off, for example, the state of the DIP switch 52 is a four-channel "0N0FF ON OFF", it indicates The first, third ADC channel access ready for use, while the second, fourth channel analog to digital converter disconnect is not used. 此外,通道状态设置模块5还包括拨码开关52外围的电阻51,该电阻51用于限流。 In addition, the channel status setting module 5 further comprising a peripheral DIP switch 52 the resistor 51, the resistor 51 for current limiting. 从电路角度来说,某一通道的拨码开关拨至“ON” 状态,电源3. 3v通过电阻51传给微处理器模块2,微处理模块2识别该有效信号为高电平使能信号。 From the circuit perspective, the DIP switch of a channel allocated to the "ON" state, the power transmitted to the microprocessor 3. 3v resistor module 512, microprocessor module 2 identifies the valid signal is high enable signal . 反之,若拨至“OFF”状态,电源3. 3v通过电阻51接地,接地信号传给微处理器模块2,微处理模块2识别该信号为低电平禁止信号。 Conversely, if the dial to the "OFF" state, the power supply 51 via the resistor 3. 3v grounding signal to the microprocessor module 2, the microprocessor 2 identifies the signal module disable signal is low.

[0026] 微处理器模块2根据通道状态设置模块5的设置,通过反馈式增强型锁相环为多个模数转换通道提供采样时钟,并且,利用乒乓buffer结构对多个模数转换通道输出的数据进行实时接收和暂存,数据经合路复接、PCIE协议层处理及PCIE物理层处理后发送给PCIE协议接口模块3。 [0026] The microprocessor module 2 setting module 5 is provided in accordance with the channel state, a sampling clock to provide a plurality of analog to digital conversion through a feedback channel reinforcement phase-locked loop, and, using a ping-pong buffer structure of a plurality of channel converting module output the receiving and temporarily storing data in real time, the data multiplexed by the combiner, post-treatment and PCIE PCIE protocol layer to a physical layer processing module 3 PCIE protocol interface. 具体而言,微处理器模块2可以为一高性能的可编程门阵列(FPGA), 如Altera 公司的Stratix-II 系列FPGA 或Xilinx 公司的Virtex-4 系列FPGA0 FPGA 因其分布式并行处理架构和丰富的DSP硬件和块RAM资源,成为高速数字信号处理的首选。 Specifically, the microprocessor module 2 may be a high performance programmable gate array (FPGA), such as Altera's Stratix-II or Series FPGA from Xilinx Virtex-4 family FPGA0 FPGA architecture and its distributed parallel processing rich and block RAM DSP hardware resources, the preferred high-speed digital signal processing. 而且,高性能FPGA还集成有基于LVDS电平标准的高速串行收发器,可以配置成源同步接口或PCIE接口,为高速数据传输带来极大的便利。 Moreover, high-speed performance FPGA integrated transceiver serial LVDS level based on a standard, a source synchronous interface may be configured or PCIE interface, a great convenience for high speed data transmission. 微处理器模块2上电后,用于实现数据的实时传输和PCIE协议处理,其被配置成具有:通道状态控制单元、模数转换接口单元、各通道数据暂存单元、数据合路复接单元、PCIE协议层处理单元、以及PCIE物理层处理单元(均未图示)。 2 after the power module microprocessor for real-time transmission protocol PCIE and processing data, which is configured to have: a channel state control unit, an interface unit analog-digital conversion, the channel data temporary storing unit, the data combiner multiplexer means PCIE protocol layer processing unit, and PCIE physical layer processing unit (not shown).

[0027] 通道状态控制单元得到通道状态设置模块5发送来的各模数转换通道的接入状态,“翻译“成各模数转换通道的使能控制信号。 [0027] The channel state control unit to give access to the status of each molding channel status setting module 5 to the transmitted channel number conversion, "translated" into each ADC channel enable control signal. 根据该使能控制信号可以决定模数转换接口单元向对应的模数转换通道提供采样时钟、各通道数据暂存单元的读使能信号以及数据合路复接单元中的时隙控制。 According to this control signal may enable analog-digital conversion determines the channel interface unit to a corresponding conversion module to provide a sampling clock, temporarily storing the read data of each channel time slot control units enable signal combiner and a data multiplexing unit.

[0028] 模数转换接口单元向四个模数转换通道提供采样时钟Cl〜c4,采样时钟Cl〜c4 的同步性是利用反馈式增强型锁相环来实现的。 [0028] The interface unit provides analog to digital conversion a sampling clock to the four-channel analog to digital conversion Cl~c4, Cl~c4 sampling clock synchronization is to use a phase locked loop feedback to achieve enhanced. 而且,在各模数转换通道完成模数转换处理后,模数转换接口单元按照源同步总线标准对四个模数转换通道的数据总线si〜s4进行源同步接口物理层、协议层处理,恢复得到各通道的采样数据信号,送给后续的各通道数据暂存单元。 Further, after the completion of each of the analog to digital converter channel analog-digital conversion processing, analog to digital conversion interface means for source-synchronous interfaces a physical layer according to the source synchronous bus standard four channel analog to digital conversion of the data bus si~s4, protocol layer processing, recovery to obtain sample data of each channel signal, the channel data subsequent to the temporary storage unit. 源同步接口为数据、时钟并行的同步收发接口,通过时钟的相位来恢复得到原始数据。 Source synchronous data interface, a clock synchronous parallel interface to the transceiver, to recover the original data by the phase clocks. 下面结合图2说明反馈式增强型锁相环的基本实现原理。 Described below in connection with FIG. 2 the basic principle of feedback to achieve enhanced PLL.

[0029] 反馈式增强型锁相环的具体配置如下:微处理器内部集成一个锁相环,其主时钟输出管脚η通过反馈输入路径F(PCB走线)从其反馈输入引脚B输入,由于时钟输入路径延时I和反馈输入延时k相等,所以可以保证时钟输入管脚A和反馈输入管脚B锁定成等相位。 [0029] The specific configuration of the phase-locked loop feedback reinforcement as follows: a phase locked loop integrated inside the microprocessor, the main clock output pins η feedback input from an input pin through the feedback input path B F (PCB traces) Since the clock input path delay and the feedback input delay equal to I k, and the like can be secured to lock the phase of clock input pins A and a feedback input pin B. 如果时钟输出走线0和反馈输入路径F等长,则下游模块时钟输入管脚E和反馈输入管脚B等相位,而且和时钟输入管脚A也同相位,可以使上下游模块构成一个同步系统。 If the phase of the output clock traces and the feedback input path F 0 equal length, the downstream module feedback clock input pins E and B input pins and the like, and a clock input pins but also with the phase A, the downstream module can constitute a synchronous system. 若微处理器模块2的时钟输出均采用这样的技术,则四个模数转换通道的采样时钟均能同步于输入时钟(管脚A处),各个通道的采样时钟cl〜c4间的偏斜(skew)相差仅为20ps。 If the microprocessor 2 clock output module such techniques are used, the four channel analog to digital conversion a sampling clock can synchronize to a clock input (pin at A), the respective channels between the sampling clock skew cl~c4 (skew) a difference of only 20ps.

[0030] 各通道数据暂存单元被设计成读写分离的乒乓buffer结构,即各通道新接收数据和待发送数据不在同一个存储器中,这样读写操作分离,新接收数据和待发送数据不会冲突,从而确保各通道数据的传输无帧丢失。 [0030] Each channel data temporary storage unit is designed to separate read and write ping-pong buffer structure, i.e., the newly received data of each channel and the data to be transmitted not in the same memory, thus separating read and write operations, and newly received data is not data to be sent conflict, so as to ensure the transmission data of each channel with no frame loss. 下面结合图3来说明多通道的数据实时并行传输的基本原理。 Here will be described a multi-channel data transmission of real-time parallel basic principle in conjunction with FIG.

[0031] 微处理器模块2具有丰富的块RAM资源,可配置成实现各通道数据暂存的乒乓buffer结构(包括写操作的新接收数据存储器和读操作的待发送数据存储器)。 [0031] The microprocessor module RAM block 2 has a rich resource, each channel may be configured to implement a ping-pong buffer temporary data structure (including the newly received data to be transmitted the memory data read operation and write memory operations). 具体而言,在某时刻t,各通道数据均以时钟速率fl写入各自新接收数据存储器,但在各通道的使能控制信号作用下,此时刻只有一个通道待发送数据存储器能读出数据,送往后续的数据合路复接单元。 Specifically, at a time t, the channel data are written into the respective clock rate fl newly received data memory, but in each channel enable control signal under the action of only one channel in this time data memory read data to be transmitted , sent to the subsequent data combiner multiplexing unit. 而且,读写时序满足以下规律:以写满每个通道的新接收数据存储器的时间计为T1,则每个通道待发送数据存储器读的时间T2为T1的1/4(若有N个模数转换通道,则为1/N),即读频率f2比写的频率fl快4倍,但同一通道待发送数据存储器的相邻两次读操作的时间间隔仍为T1,不同通道的待发送数据存储器的读操作的时间点不冲突。 Further, read and write timing satisfies the following rules: each time filled with the newly received channel data memory in terms of T1, the data to be transmitted for each channel of the memory read time T2 is T1 1/4 (modulo N if ADC channels, for the 1 / N), i.e., the read frequency f2 4 times faster than the write frequency fl, but the same channel data to be transmitted to two adjacent memory read operations remain time interval Tl, different channels to be transmitted read a time point the data store does not conflict. 从具体实现层次上来说,各通道的待发送数据存储器的读操作均受制于各通道的使能控制信号,各通道的使能控制信号为高电平时,顺利执行读操作。 From the specific implementation level, the read operation of memory data to be transmitted for each channel are subject to the respective channel enable control signal, each channel enable control signal is high, the read operation is performed smoothly. 因此,各通道间的使能控制信号周期为T1,占空比为25%。 Therefore, the channel can be controlled among the signal period is T1, 25% duty cycle. 若四个通道全工作时,则只用将各通道间的使能控制信号的相位差严格控制在90度即可实现上述过程。 If four full operating channel, so that only with the channel between the respective difference signal to control strictly controlled at 90 degrees to achieve the above-described process. 若某个通道没有被用户选择,则其通道使能控制信号全为低电平,即读操作被禁止。 If a channel is not selected by the user, it full channel enable control signal is low, i.e., the read operation is prohibited.

[0032] 由于通道数目可为多个,而PCIE接口只有一个,因此需要通过数据合路复接单元将被选择的通道数据复接合路,统一发给后续的PCIE协议层处理单元。 [0032] Since the number of channels may be a plurality, but only a PCIE interface, thus requiring the data combiner unit multiplexing the selected channel data to be channel bonded complex, a unified protocol layer PCIE issued subsequent processing unit. 当然在合路前,选中接入的各通道数据可以被插入通道标志,作为用户识别的依据。 Of course, prior to the combiner, each of the selected access channel data flag may be inserted into the channel, as a basis for user identification. 然后在上述各通道的使能控制信号作用下,完成用户设定通道的数据合路复接成一路信号,并送往后续的PCIE协议层处理单元。 Then in each channel enable control signal action, complete data set by the user channel combiner multiplexed into one signal, and sent to the subsequent processing unit PCIE protocol layer. 在时间周期T1内,四个模数转换通道各占一个时隙TS1〜TS4,时隙长度为T1/4。 Within the time period T1, the four-channel analog to digital converters each have one slot TS1~TS4, a slot length of T1 / 4. 在每个时隙内发送对应通道数据,当然用户选择不接入的模数转换通道数据在此不被合路,因此也不可能被发送。 In each time slot corresponding to the transmission channel data, of course, the user selects not the access channel analog to digital conversion data in this way is not engaged, and therefore can not be transmitted.

[0033] 复接合路后数据送往PCIE协议层处理单元。 After [0033] The multiplexed data is sent to the road engaging PCIE protocol layer processing unit. PCIE协议层处理单元完成PCIE协议处理,包括信号组帧、信号编码等,然后送往PCIE物理层处理单元。 PCIE PCIE protocol layer protocol processing unit performs processing, comprising a signal framing, coding signals, and then sent to physical layer processing unit PCIE.

[0034] PCIE物理层处理单元完成PCIE物理层处理,包括LVC0MS电平转为LVDS基准电平,然后通过微处理器模块2的10 口和PCB走线传给PCIE协议接口模块3。 [0034] PCIE PCIE complete physical layer processing unit processing a physical layer, comprising LVC0MS into LVDS level reference level, and then passed 3 PCIE protocol interface module 10 via the microprocessor 2 and the module PCB traces.

[0035] PCIE协议接口模块3包括PCIE接口的接插件,用于与用户数据处理装置的PCIE 插槽连接,以将数据传输给所述用户数据处理装置。 [0035] PCIE PCIE protocol interface module 3 comprises a connector interface for connection to the user PCIE slot data processing apparatus, to transmit data to the user data processing apparatus. 例如,该接插件可以为一金手指,插入到用户数据处理装置(如计算机主板等)的PCIE插槽中,完成电连接(PCIE总线)。 For example, the connector may be a finger, is inserted into the user data processing device (e.g., computer motherboards, etc.) PCIE slot, the electrical connection is completed (PCIE bus). 此外, 通过PCIE协议接口模块3,可接入用户数据处理装置的电源,为本发明提供电力供给。 Further, the PCIE protocol interface module 3, the power user can access the data processing apparatus, the present invention provides power supply. 各通道数据送给用户数据处理装置后,用户可以针对各通道标志位完成数据分离以及后续信号处理等。 After the channel data to the user data processing device, the user can complete the data separation and subsequent signal processing for each channel flags.

[0036] 此外,如图1所示,本数据采集装置还包括微处理器辅助工作模块4,其与微处理器模块2相连。 [0036] Further, as shown in Figure 1, the present data acquisition device further comprises a microprocessor auxiliary work module 4, module 2 which is connected to the microprocessor. 该微处理器辅助工作模块4包括RC电路41、固化存储器42以及晶振电路43。 The auxiliary microprocessor operating module 4 comprises an RC circuit 41, crystal oscillator circuit 42, and curing the memory 43. RC电路41为微处理模块2的稳定工作提供电源去耦,固化存储器42为微处理器模块2的配置程序提供存储空间,晶振电路43为微处理器模块2提供源时钟。 RC circuit 41 micro-processing module 2 provides stable operation of the power decoupling, the microprocessor program module configuration 2 provides a cured storage memory 42, crystal oscillator circuit 43 provides microprocessor module 2 to the source clock.

[0037] 下面说明本发明实现多通道数据采集的步骤流程。 [0037] The present invention will be described below multichannel data acquisition step process.

[0038] 步骤S1,首先根据用户需要的模数转换通道数目和选择的特定模数转换通道, 对与各模数转换通道对应的四通道的拨码开关52的状态进行设置,每通道的拨码开关的“ON”和“OFF”状态分别代表对应的模数转换通道的接入或断开。 [0038] step S1, the first user desired number of analog to digital conversion channels, and selection of a particular analog to digital conversion channels, the state of the DIP switch four channels each ADC corresponding to the channel 52 is set aside for each channel "ON" and "OFF" state of the switch codes representing the access channel corresponding to the analog to digital conversion or disconnection. [0039] 步骤S2,将PCIE协议接口模块3的PCIE接口金手指插入用户计算机主板的PCIE 插槽中,完成本发明与用户数据处理装置的电连接。 [0039] Step S2, the PCIE PCIE interface protocol interface module 3 is inserted into the user's computer golden finger board slot PCIE, electrical connection is completed with the present invention, the user data processing apparatus. 通过PCIE接口接入用户计算机主板中的电源,本发明获得电力供给,开始工作。 PCIE interface access by the user computer's motherboard power source, the present invention is to obtain a power supply, starts working.

[0040] 步骤S3,本发明上电后,微处理器辅助工作模块4中的晶振电路43开始工作并输出源时钟供给微处理器模块2,微处理器模块2进入配置模式。 [0040] Step S3, the present invention is powered on, the microprocessor auxiliary work module 4 and the crystal oscillation circuit 43 starts working microprocessor clock supply output source module 2, the microprocessor 2 enters the module configuration mode. 微处理器模块2从微处理器辅助工作模块4的固化存储器42读取已固化的配置程序,并根据配置程序对微处理器模块2的内部逻辑进行配置,具体配置成具有通道状态控制单元、模数转换接口单元、各通道数据暂存单元、数据合路复接单元、PCIE协议层处理单元、以及PCIE物理层处理单元等。 Microprocessor module 2 from the secondary microprocessor operating module 42 reads the memory 4 cured cured configuration program and configure the microprocessor internal logic module 2 according to the configuration program, specifically configured to have a channel state control unit, analog-digital conversion interface unit, the channel data temporary storing unit, the data unit multiplexing combiner, PCIE protocol layer processing unit, and the physical layer processing unit PCIE like. 各单元配置完成并进行初始化设置后,微处理器模块2的配置模式结束,进入工作模式。 After each cell is configured and arranged to initialize the microprocessor module configuration mode 2, the routine proceeds mode. [0041 ] 步骤S4,微处理器模块2在配置模式时,通道状态设置模块5根据四通道的拨码开关52的设定情况,将用户设定的各模数转换通道的接入状态,以高低电平形式送给微处理器模块2的通道状态控制单元,高电平代表接入,低电平代表断开。 [0041] step S4, each of the access channel analog to digital conversion module 2 when the state of the microprocessor configuration mode, the channel status setting module 5 depending on the settings of the DIP four-channel switch 52, set by the user, to in the form of high and low state of the channel 2 to the microprocessor module of the control unit, the access on behalf of a high level, a low level indicates Open.

[0042] 步骤S5,微处理器模块2进入工作模式后,通道状态控制单元得到通道状态设置模块5发送来的各模数转换通道的接入状态,并“翻译“成各通道的使能控制信号。 [0042] In step S5, the microprocessor module 2 into the working mode, the channel state control unit to give access channel states of the respective analog-digital conversion channel status setting module 5 to the transmission, and "translated" into each channel enabling control signal. 该使能控制信号决定模数转换接口单元向对应的模数转换通道提供采样时钟、、各通道数据暂存单元的读使能信号以及数据合路复接单元中的时隙控制。 The enable control signal determining means converts analog-digital conversion interface module to a corresponding channel provides the read sampling clock ,, temporary data storage unit, each channel time slot so that the control signal and a data combiner multiplexing unit.

[0043] 步骤S6,完成用户指定设置后,微处理器模块2中的模数转换接口单元输出模数转换时钟cl〜c4。 After [0043] Step S6, the user-specified settings is completed, the microprocessor 2 ADC module interface unit outputs analog to digital conversion clock cl~c4. 若模数转换模块1中各模数转换通道的AD转换接插件接入上游的待采样模拟信号,则模数转换模块1开始工作,将各通道的模拟待采样信号模数转换并量化成12bit的数字信号,并通过数据总线si〜s4传给微处理器模块的模数转换接口单元。 If an analog to digital conversion module converting the respective analog to digital AD conversion channel access connectors to be sampled analog signal upstream of the analog to digital conversion module 1 to work, the analog signal of each channel to be sampled and quantized analog-digital conversion into 12bit a digital signal and passed to analog to digital conversion interface unit microprocessor module via the data bus si~s4. 在本实施例中,数据总线si〜s4采用源同步总线标准。 In the present embodiment, the data bus using source synchronous bus standard si~s4.

[0044] 步骤S7,微处理器模块2中的模数转换接口单元按照源同步总线标准对数据总线si〜s4进行物理层、协议层处理,恢复得到各通道的采样数据信号,送给后续的各通道数据暂存单元。 [0044] Step S7, the microprocessor module of the interface unit 2 for analog-digital conversion according to the source synchronous bus standard data bus si~s4 physical layer, protocol layer processing, recovery, to obtain sample data of each channel signal, subsequent to the each channel data register unit.

[0045] 步骤S8,为了保证各通道数据传输的无帧丢失,微处理器模块2中的各通道数据暂存单元设计成读写分离的乒乓buffer结构,即各通道新接收数据和待发送数据不在同一个存储器中。 [0045] The step S8, in order to ensure the respective data transmission channel with no frame loss, the microprocessor module 2 temporarily storing the channel data separating unit is designed to read and write buffer of ping-pong structure, i.e., the newly received data and data to be transmitted for each channel not in the same memory. 某时刻,各通道数据均以时钟fl速率写入各自新接收数据存储器;但在步骤S5中各通道的使能控制信号作用下,此时刻只有一个通道待发送数据存储器能读出数据,送往后续的数据合路复接单元。 A certain time, the channel data are written into the respective clock rate fl newly received data memory; however in step S5 at each channel enable control signal is applied, only this time a channel data memory read data to be transmitted, sent subsequent data combiner multiplexing unit. 而且,读写时序满足以下规律:以写满每通道新接收数据存储器的时间计为T1,则每个通道待发送数据存储器读的时间T2为T1的1/4,即读频率比写频率快4倍,但同一通道的待发送数据存储器的相邻两次读操作的时间间隔仍为T1, 不同通道的待发送数据存储器的读操作的时间点不冲突。 Further, read and write timing satisfies the following rules: each filled channel to the newly received data memory in terms of the time T1, the channel of each memory read data to be sent at time T2 is T1 1/4, i.e., the read frequency is faster than the write frequency 4 times, but the two adjacent transmission data read operation time of the memory to be the same channel spacing remains Tl, the time point read operation of memory data to be transmitted in different channels do not conflict.

[0046] 步骤S9,在步骤S5中各通道的使能控制信号作用下,微处理器模块2中的数据合路复接单元将用户设定的通道信号数据合路复接成一路信号,并送往后续的PCIE协议层处理单元。 The [0046] step S9, in step S5, each channel enabling control signal is applied, the data combiner module 2 in the microprocessor unit multiplexing the signal data combiner channel set by the user multiplexed into one signal, and sent to the subsequent processing unit PCIE protocol layer. 用户选择不接入的模数转换通道数据在此不被合路,因此也不可能被发送。 The user chooses not to access channel analog to digital conversion data in this way is not engaged, and therefore can not be transmitted. 在合路前,选中接入的各通道数据可以被插入通道标志,作为用户识别的依据。 Before combiner, each of the selected access channel data flag may be inserted into the channel, as a basis for user identification.

[0047] 步骤S10,PCIE协议层处理单元完成PCIE协议处理,包括信号组帧、信号编码等, 然后送往PCIE物理层处理单元。 [0047] Step SlO, PCIE PCIE protocol layer protocol processing unit performs processing, comprising a signal framing, coding signals, and then sent to physical layer processing unit PCIE.

[0048] 步骤Sll,PCIE物理层处理单元完成PCIE接口物理层处理,包括LVC0MS电平转为LVDS基准电平,然后通过微处理器模块2的10 口和PCB走线传给PCIE协议接口模块3。 [0048] Step Sll, physical layer processing unit PCIE PCIE interface physical layer processing is completed, including LVC0MS into LVDS level reference level, and then passed through 3 PCIE protocol interface module microprocessor module 10 and the PCB traces 2 .

[0049] 步骤S12,通过PCIE协议接口模块3,各通道数据送给用户数据处理装置,用户在此完成数据分离和后续信号处理。 [0049] step S12, by 3 PCIE protocol interface module, the channel data to the user data processing means, the user data is completed in this separation and subsequent signal processing.

[0050] 根据本发明的基于PCIE协议的多通道数据采集装置,通过采用PCIE协议,传输数据吞吐量最高可达5GB/s,同时还可以提供多个模数转换通道,每通道最高采样率为300MHz (随着微电子技术进展可以选择支持更高采样速率的模数转换芯片),数据采集功能强大,能高速无失真的对模拟信号采样,可应用于高速阵列信号处理中。 [0050] The multi-channel data acquisition means based PCIE protocol according to the present invention, by using PCIE protocol, data transmission throughput of up to 5GB / s, while providing a plurality of analog to digital conversion channels, the highest sampling rate per channel 300 MHz (with the progress of microelectronics may choose to support a higher sampling rate ADC chip), the data acquisition powerful, high speed without distortion of the analog signal is sampled, the array can be applied to high-speed signal processing. 而且,通过采用反馈式增强型锁相环,各模数转换通道间的时钟偏斜在20ps以内,取得优异的通道之间的时钟同步性能。 Moreover, by using enhanced PLL feedback clock between the respective analog to digital conversion within 20ps channel skew, to obtain the clock synchronization between the superior performance of the channel. 此外,通过采用乒乓buffer结构,保证采样数据传输中的读写过程不碰撞, 从而确保无帧丢失的实时性数据传输,最大限度保护采集数据的完整性,可以使各通道数据高速无误码传输。 Further, by adopting the structure of the ping-pong buffer, reading and writing process to ensure that the sample does not collide with the data transmission, the real-time data transmission to ensure no frame loss, the maximum protection of the integrity of the collected data, each channel can be error-free high-speed data transmission.

[0051] 本发明可应用于需要高速并行的多通道模数采样场景,例如相控阵天线、智能天线中的阵列信号处理等。 [0051] The present invention is applicable to multi-channel require high speed parallel sampling modulus scene, for example, a phased array antenna, the smart antenna array signal processing.

[0052] 显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。 [0052] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. 这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。 Thus, if these modifications and variations of the present invention fall within the claims of the invention and the scope of equivalents thereof, the present invention intends to include these modifications and variations.

Claims (6)

  1. 一种基于PCIE协议的多通道数据采集装置,其特征在于,包括模数转换模块、通道状态设置模块、微处理器模块、以及PCIE协议接口模块,其中,所述模数转换模块包括多个模数转换通道,每一模数转换通道实现一路模拟信号的模数转换;所述通道状态设置模块根据用户的要求设置每一模数转换通道的接入状态;所述微处理器模块根据所述通道状态设置模块的设置,通过反馈式增强型锁相环为所述多个模数转换通道提供采样时钟,并且,利用乒乓buffer结构对所述多个模数转换通道输出的数据进行实时接收和暂存,所述数据经合路复接、PCIE协议层处理及PCIE物理层处理后发送给所述PCIE协议接口模块;所述PCIE协议接口模块包括PCIE接口的接插件,用于与用户数据处理装置的PCIE插槽连接,以将数据传输给所述用户数据处理装置。 Based on multi-channel data acquisition means PCIE protocol, characterized in that it comprises analog to digital conversion module, channel status setting module, microprocessor module and PCIE protocol interface module, wherein the analog to digital conversion module comprises a plurality of mold ADC channels, each channel ADC way to achieve analog to digital conversion of the analog signal; a channel status setting module the access channel state of each analog to digital conversion according to the user's requirements; the microprocessor module according to the state setting module setting the channel, the channel provides a plurality of analog to digital conversion a sampling clock by phase-locked loop feedback is enhanced, and the use of the ping-pong data buffer structure of the plurality of analog to digital conversion of the output channel and receiving real-time temporarily storing the data multiplexed by the combiner is sent to the protocol interface module after PCIE PCIE PCIE protocol layer and the physical layer processing process; the PCIE PCIE interface protocol interface module includes a connector for communicating with the user data processing PCIE slot connection device, to transmit data to the user data processing apparatus.
  2. 2.如权利要求1所述的基于PCIE协议的多通道数据采集装置,其特征在于,所述通道状态设置模块包括与所述多个模数转换通道对应的多通道的拨码开关,每一通道的拨码开关用于设置对应的模数转换通道的接入或断开。 2. The multi-channel data acquisition means based on said protocol PCIE claimed in claim 1, wherein the channel status setting module comprises a DIP switch and the plurality of multi-channel analog to digital conversion corresponding to the channels, each analog-digital conversion channel DIP switch for setting the channel corresponding to the access on or off.
  3. 3.如权利要求1所述的基于PCIE协议的多通道数据采集装置,其特征在于,所述微处理器模块配置成具有通道状态控制单元、模数转换接口单元、各通道数据暂存单元、数据合路复接单元、PCIE协议层处理单元、以及PCIE物理层处理单元,其中,所述通道状态控制单元根据所述通道状态设置模块发送来的各模数转换通道的接入状态,形成各模数转换通道的使能控制信号,决定所述模数转换接口单元向对应的模数转换通道提供采样时钟、所述各通道数据暂存单元的读使能信号以及所述数据合路复接单元中的时隙控制;所述模数转换接口单元利用反馈式增强型锁相环向对应的模数转换通道提供采样时钟,并且,在各模数转换通道完成模数转换处理后,对各模数转换通道通过数字总线发送来的数据进行对应的物理层和协议层处理;所述各通道数据暂存单元利用 3. The multi-channel data acquisition device based on the protocol PCIE 1 D conversion interface unit the channel data temporary storing unit as claimed in claim, characterized in that the microprocessor module is configured to have a channel state control unit,,, multiplexing data combiner unit PCIE protocol layer processing unit, and PCIE physical layer processing unit, wherein the channel state control unit according to the channel status setting module sent by the access states of the respective analog to digital conversion channels, each formed analog to digital conversion channel enable control signal, determines the analog-digital conversion unit provides an interface to the analog to digital conversion a sampling clock corresponding to the channels, each channel reading the temporary data storage unit and the data enable signal combiner multiplexer slot control unit; digital conversion interface unit using a feedback phase-locked loop provides reinforcement to the analog to digital conversion a sampling clock corresponding to the channels, and the analog to digital conversion process in the analog to digital conversion channels, the respective ADC channels and the physical layer protocol processing layer corresponding to the digital bus via the data transmitted; the respective channels using the temporary data storage unit 乓buffer结构对所述模数转换接口单元输出的数据进行暂存;所述数据合路复接单元将所述各通道数据暂存单元输出的数据合路复接成一路信号;所述PCIE协议层处理单元对所述数据合路复接单元输出的数据进行PCIE协议层处理;所述PCIE物理层处理单元对所述PCIE协议层处理单元输出的数据进行PCIE物理层处理。 Pong data buffer structure of the analog-digital conversion of the output interface unit storing temporarily; the data combiner unit multiplexing the data temporary storage unit outputs the channel data multiplexed into one channel combiner signal; said protocol PCIE layer processing unit connected to the data multiplexing means for outputting the combined data processing PCIE protocol layer; PCIE the physical layer processing unit of the data processing unit outputs PCIE protocol layer for physical layer processing PCIE.
  4. 4.如权利要求3所述的基于PCIE协议的多通道数据采集装置,其特征在于,所述多个模数转换通道输出的数据通过采用源同步总线标准的数字总线传输给所述模数转换接口单元。 4. The multi-channel data acquisition means based PCIE protocol according to claim 3, wherein said plurality of data output from the analog to digital conversion channel by using a source synchronous bus standard digital bus transmission to the analog to digital conversion The interface unit.
  5. 5.如权利要求1所述的基于PCIE协议的多通道数据采集装置,其特征在于,还包括微处理器辅助工作模块,所述微处理器辅助工作模块与所述微处理器模块相连,其包括RC电路、固化存储器以及晶振电路,所述RC电路为所述微处理模块提供电源去耦,所述固化存储器为所述微处理器模块的配置程序提供存储空间,所述晶振电路为所述微处理器模块提供源时钟。 The multi-channel data acquisition means based on said protocol PCIE claimed in claim 1, wherein the microprocessor further comprises an auxiliary operating module, the operating module is connected to the auxiliary microprocessor with the microprocessor module comprises an RC circuit, a memory and a crystal oscillator circuit curing, the RC circuit of the micro-processing module provides power decoupling, the cured module microprocessor program memory is configured to provide space for the storage of the crystal oscillator circuit is the The microprocessor module source clock.
  6. 6.如权利要求1所述的基于PCIE协议的多通道数据采集装置,其特征在于,通过所述PCIE协议接口模块接入所述用户数据处理装置的电源,实现电力供给。 The multi-channel data acquisition means based on said protocol PCIE claimed in claim 1, characterized in that, through the protocol interface module PCIE user access to the data processing apparatus power supply, the power supply to achieve.
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CN103399214A (en) * 2013-08-16 2013-11-20 中国科学院上海微系统与信息技术研究所 Satellite-borne phased-array receiving antenna testing system
CN103532807A (en) * 2013-10-12 2014-01-22 江苏华丽网络工程有限公司 Technology for PCIE (Peripheral Component Interface Express) data service quality management
CN103532807B (en) * 2013-10-12 2017-10-03 丁贤根 A method for pcie data service quality management
CN104408009A (en) * 2014-11-27 2015-03-11 成都龙腾中远信息技术有限公司 System and method for acquiring, processing and verifying method multi-channel interference signal

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