CN101915025A - Lock and clutch state acquisition circuit and radio frequency identification electronic tag integrating the circuit - Google Patents
Lock and clutch state acquisition circuit and radio frequency identification electronic tag integrating the circuit Download PDFInfo
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Abstract
The invention relates to a lock clutch state acquisition circuit and a radio frequency identification electronic tag integrating the same. The lock clutch state acquisition circuit comprises a switch (S1), a first NMOS tube (MR1), a second NMOS tube (MR2), a third NMOS tube (MR3), a fourth NMOS tube (MR4), a PMOS tube (T1), a triode (T2), a fifth NMOS tube (T3), a power supply battery (B1), a trigger (D1) and a direct current-direct current voltage conversion circuit. The invention has the advantages that: the lock clutch state acquisition circuit has the advantages of low power consumption and interference resistance and can be integrated into the electronic tag, so the lock clutch state acquisition circuit can easily combined with the electronic tag to be used as a node for monitoring Internet of things with flowing containers and safety boxes in the logistics industry, can timely monitor the lock clutch state of the containers and safety boxes, and ensures the flowing safety of the containers and safety boxes.
Description
Technical field
The invention belongs to the electronic circuit technology field, relate in particular to the lock clutch state acquisition circuit of lockset and adopt the radio frequency recognizing electronic label of this circuit.
Background technology
Radio frequency identification (RFID, Radio Frequency Identification) technology is to utilize the RF-wise purposes such as identification, tracking, location and management of communication to reach article at a distance.REID is in industrial automation, business automation, and the communications and transportation control and management, various fields such as false proof, even military use is with a wide range of applications, and caused at present widely and paid close attention to.
The electronic tag and the reader that utilize REID to make are used widely, particularly as the electronic tag of the node of Internet of Things, can effectively store accompanying article various information and by with these information of communications of reader.In logistic industries such as containerized traffic management, strongbox, people wish and can effectively monitor lock clutch (opening and closing) status information by the mode of adhering to electronic tag on container that the behavior of container or strongbox is opened in monitoring.
The function that most electronic lock of the prior art only possesses is antitheft, report to the police, have only the small part electronic lock to possess the lock clutch state acquisition function, and these locksets with lock clutch state acquisition circuit generally adopt magnetic device to cooperate the collection of the method realization of relay to lock clutch state.But, the lock clutch state acquisition circuit of this lockset has following shortcoming: 1. because relay consumption power consumption is big, if use external power source to have the big shortcoming of small product size, if use battery, then exist battery power consumption too fast, product continues short shortcoming service time.2. owing to adopted magnetic device, lockset is subjected to the interference of external environment easily under the environment of strong magnetic and forceful electric power, thus the clutch state of wrong judgement lock.
Because there is above-mentioned shortcoming in existing lockset with lock clutch state acquisition circuit, the node that therefore is not suitable for combining as Internet of Things with electronic tag uses.
Summary of the invention
The objective of the invention is to exist power consumption excessive and be subject to the shortcoming of outside electromagnetic interference, proposed a kind of lock clutch state acquisition circuit in order to overcome existing lock clutch state acquisition circuit.
To achieve these goals, a kind of lock clutch state acquisition circuit is provided, the lock clutch state acquisition circuit, comprise that switch (S1), NMOS pipe (MR1), the 2nd NMOS pipe (MR2), the 3rd NMOS pipe (MR3), the 4th NMOS pipe (MR4), PMOS pipe (T1), triode (T2), the 5th NMOS manage (T3), power-supply battery (B1), trigger (D1) and DC-to-dc voltage conversion circuit, described power-supply battery (B1) is to insert integrated circuit from the outside; After a described NMOS manages (MR1) grid and drain electrode is connected, link to each other with battery (B1) is anodal again; Described NMOS pipe (MR1) source electrode is connected with first end (a) of switch (S1); After described the 2nd NMOS manages (MR2) grid and drain electrode is connected, be connected with second end (b) of switch (S1) again; Described the 2nd NMOS pipe (MR2) source electrode is connected to ground; After described the 3rd NMOS manages (MR3) grid and drain electrode is connected, be connected with PMOS pipe (T1) drain electrode again; Described the 3rd NMOS pipe (MR3) source electrode is connected with triode (T2) base stage; After described the 4th NMOS manages (MR4) grid and drain electrode is connected, be connected with battery (B1) positive pole again; Described the 4th NMOS pipe (MR4) source electrode is connected with triode (T2) colelctor electrode; Second end (b) of described triode (T2) base stage and switch (S1) is connected; Described triode (T2) colelctor electrode is connected with PMOS pipe (T1) grid; Described triode (T2) base stage is managed (T3) drain electrode with the 5th NMOS and is connected; The source electrode of described PMOS pipe (T1) is connected with drain electrode with the grid that the 4th NMOS manages (MR4); Described PMOS pipe (T1) drain electrode is connected with the power end (I) of DC-to-dc voltage conversion circuit; Described the 5th NMOS pipe (T3) source electrode is connected to ground; Described the 5th NMOS pipe (T3) grid is connected with the data output end (Q) of trigger (D1); The data input pin (D) of described trigger (D1) is connected with second end (b) of switch (S1); The voltage control signal (power_control) of the digital baseband processor of input end of clock (CP) the input radio frequency identification electronic tag of described trigger (D1); The power end (VDD) of described trigger (D1) is connected with second end (b) of lock clutch signaling switch (S1); Described DC-to-dc (DC-DC) voltage conversion circuit voltage input end (I) is connected to PMOS pipe (T1) drain electrode; Described DC-to-dc (DC-DC) voltage conversion circuit ground connection input (J) is connected to ground; Described DC-to-dc (DC-DC) voltage conversion circuit to the rf analog front-end output low level operating voltage and the high level operating voltage of radio frequency recognizing electronic label, is locked clutch signal (key_opened) to the digital baseband processor output first lock clutch signal (switch_on) and second of radio frequency recognizing electronic label respectively.
Another object of the present invention is in order to solve the difficulty of electronic tag to the lock clutch state monitoring, to have proposed a kind of radio frequency recognizing electronic label of integrated lock clutch state acquisition circuit, can being easy to the lock clutch state information gathering to radio frequency recognizing electronic label.
To achieve these goals, a kind of radio frequency recognizing electronic label of integrated above-mentioned lock clutch state acquisition circuit is provided, described electronic tag comprises antenna, rf analog front-end and digital baseband processor, described rf analog front-end comprises the said reference mu balanced circuit, described digital baseband processor comprises state controller module, it is characterized in that, described rf analog front-end also comprises above-mentioned lock clutch state acquisition circuit, described lock clutch state acquisition circuit is connected with the state controller module of digital baseband processor and exports the first lock clutch state signal and the second lock clutch state signal to state controller module, the voltage control signal (power_control) of while accepting state controller module input, described lock clutch state acquisition circuit is connected with the reference voltage-stabilizing circuit of rf analog front-end and provides high level operating voltage and low level operating voltage to reference voltage-stabilizing circuit.
Beneficial effect of the present invention: the existing relatively lock clutch state acquisition circuit of lock clutch state acquisition circuit of the present invention has low-power consumption and jamproof advantage, and can be integrated in electronic tag inside, therefore the lock clutch state acquisition circuit can be relatively easy to and the Internet of Things monitor node of electronic tag combination as container, strongbox circulation in the logistic industry, the lock clutch state of monitoring containers, strongbox has guaranteed the safety that container, strongbox circulate timely.Adopt the radio frequency recognizing electronic label of lock clutch state acquisition circuit to take into account the function of ordinary passive ultrahigh frequency electronic tag in the radiofrequency field simultaneously, simultaneously no matter extraneous the radiofrequency field that has or not all can finish record for unlocking times.Because what the present invention adopted is passive ultrahigh frequency electronic tag, can also effectively reduce the consumption and the volume in kind of power consumption, reduced dependence for external power source, strengthened practicality for various particular application.
Description of drawings
Fig. 1 is that the present invention locks clutch Acquisition Circuit schematic diagram.
Fig. 2 is the radio frequency recognizing electronic label schematic diagram of integrated lock clutch Acquisition Circuit of the present invention.
Description of reference numerals: switch S 1, a NMOS pipe MR1, the 2nd NMOS pipe MR2, the 3rd NMOS pipe MR3, the 4th NMOS pipe MR4, PMOS pipe T1, triode T2, the 5th NMOS pipe T3, power-supply battery B1, trigger D1.Decoder module 101, cyclic check module 102, input pretreatment module 103, state controller module 104, output pretreatment module 105, coder module 106, memory access control module 107, pseudorandom number generator module 108, collision counter module 109, timer conter module 110, clock generating module 111, reset generation module 112, MTP memory 113.Rectification circuit 201, reference voltage-stabilizing circuit 202, modulation circuit 203, demodulator circuit 204, reset circuit 205, clock circuit 206.
The specific embodiment
The present invention is described further below in conjunction with accompanying drawing and concrete specific embodiment:
As shown in Figure 1, the circuit structure of lock clutch state acquisition circuit is as follows: the on off state Acquisition Circuit comprises that switch S 1, a NMOS pipe MR1, the 2nd NMOS pipe MR2, the 3rd NMOS pipe MR3, the 4th NMOS pipe MR4, PMOS pipe T1, triode T2, the 5th NMOS manage T3, power-supply battery B1, trigger D1 and DC-to-dc voltage conversion circuit.
In conjunction with Fig. 1, the connected mode of each device and port is as follows: described power-supply battery B1 inserts integrated circuit from the outside; After a described NMOS manages the MR1 grid and drain electrode is connected, link to each other with battery B1 is anodal again; Described NMOS pipe MR1 source electrode is connected with the first end a of switch S 1; After described the 2nd NMOS manages the MR2 grid and drain electrode is connected, be connected with the second end b of switch S 1 again; Described the 2nd NMOS pipe MR2 source electrode is connected to ground; After described the 3rd NMOS manages the MR3 grid and drain electrode is connected, be connected with PMOS pipe T1 drain electrode again; Described the 3rd NMOS pipe MR3 source electrode is connected with triode T2 base stage; After described the 4th NMOS manages the MR4 grid and drain electrode is connected, be connected with battery B1 positive pole again; Described the 4th NMOS pipe MR4 source electrode is connected with triode T2 colelctor electrode; The second end b of described triode T2 base stage and switch S 1 is connected; Described triode T2 colelctor electrode is connected with PMOS pipe T1 grid; Drain electrode is connected described triode T2 base stage with the 5th NMOS pipe T3; The source electrode of described PMOS pipe T1 is connected with drain electrode with the grid of the 4th NMOS pipe MR4; Described PMOS pipe T1 drain electrode is connected with the power end I of DC-to-dc voltage conversion circuit; Described the 5th NMOS pipe T3 source electrode is connected to ground; Described the 5th NMOS pipe T3 grid is connected with the data output end Q of trigger D1; The data input pin D of described trigger D1 is connected with the second end b of switch S 1; The voltage control signal (power_control) of the digital baseband processor of the CP clock input radio frequency identification electronic tag of described trigger D1; The power end VDD of described trigger D1 is connected with the second end b of lock clutch signaling switch S1; Described DC-to-dc (DC-DC) voltage conversion circuit voltage input end I is connected to PMOS pipe T1 drain electrode; Described DC-to-dc (DC-DC) voltage conversion circuit ground connection input J is connected to ground; Described DC-to-dc (DC-DC) voltage conversion circuit to the rf analog front-end output low level operating voltage (1V) and the high level operating voltage (1.8V) of radio frequency recognizing electronic label, is locked clutch signal (key_opened) to the digital baseband processor output first lock clutch signal (switch_on) and second of radio frequency recognizing electronic label respectively; Described battery B1 negative pole is connected to ground.In conjunction with Fig. 1, lock clutch state acquisition circuit working process is as follows:
When lock is opened, switch S 1 closure, the power end VDD of trigger D1 and data input pin D connect high voltage, trigger D1 starts working, triode T2 base stage is carried out dividing potential drop by NMOS pipe MR1 and the 2nd NMOS pipe MR2, the conducting of triode T2 collector and emitter, PMOS pipe T1 grid is conducting to ground by triode T2, PMOS pipe T1 pipe source electrode and drain electrode conducting, battery B1 powers to the DC-to-dc voltage conversion circuit by PMOS pipe T1, simultaneously, PMOS pipe T1 source voltage feeds back to triode T2 base stage through the 3rd NMOS pipe MR3.DC-to-dc (DC-DC) voltage conversion circuit carries out the direct current conversion to the voltage by voltage input end I input, (the low level value is 1V herein to the rf analog front-end output low level operating voltage of radio frequency recognizing electronic label and high level operating voltage, the high level value is 1.8V), simultaneously to the radio frequency baseband processor output first lock clutch signal (switch_on) of radio frequency recognizing electronic label and the lock clutch state of the current lockset of second lock clutch signal (key_opened) indication, (the high level value was 1V herein when the clutch signal was high level when the first lock clutch signal and second is locked, the low level value is 0V), the lock clutch state of promptly representing lockset is unlatching, otherwise lock clutch state is for closing.
When lockset keeps opening, the digital baseband processor of radio frequency recognizing electronic label is drawn high the voltage control signal power_control of the input end of clock CP of the trigger D1 of lock clutch state acquisition circuit input and is high level, trigger D1 detects the rising edge of voltage control signal power_control, the data output end Q output high level of trigger D1 is given the 5th NMOS pipe T3 source electrode and drain electrode conducting, triode T2 base stage is conducting to ground, PMOS pipe T1 source electrode and drain electrode end, power-supply battery B1 stops DC-to-dc (DC-DC) voltage conversion circuit is powered, DC-to-dc (DC-DC) voltage conversion circuit quits work, thereby radio frequency recognizing electronic label is quit work, automatically voltage control signal power_control is dragged down after the BBP of radio frequency recognizing electronic label quits work and be low level, but this moment, the data output end Q of trigger D1 still kept exporting high level, and DC-to-dc (DC-DC) voltage conversion circuit still is in the state of quitting work.When lockset cut out, lock clutch signaling switch S1 disconnected, and the lock clutch state acquisition circuit quits work.When lock is in open mode, to voltage control signal power_control input port input high level, trigger D1 clock port samples power_control output port signal rising edge, the data output end Q output high level of trigger D1 is to NMOS pipe T3 source electrode and drain electrode conducting, triode T2 base stage is conducting to ground, PMOS pipe T1 source electrode and drain electrode end, battery B1 stops the DC-to-dc voltage conversion circuit is powered, 1V and 1.8V power supply are output as 0, the radio frequency recognizing electronic label chip quits work, voltage control signal power_control output port output low level, but this moment, the data output end Q of trigger D1 kept the output high level, and the DC-to-dc voltage conversion circuit still is in the state of quitting work.When lock cut out, switch S 1 disconnected, and entire circuit quits work.
Because the main components and parts of above-mentioned lock clutch state acquisition circuit adopt metal-oxide-semiconductor, so can be integrated in the radio frequency recognizing electronic label, therefore the lock clutch state acquisition circuit be constituted the radio frequency recognizing electronic label that adopts the lock clutch state acquisition circuit with built-in mode and radio frequency recognizing electronic label.
As shown in Figure 2, a kind of radio frequency recognizing electronic label of integrated above-mentioned lock clutch state acquisition circuit, described electronic tag comprises antenna, rf analog front-end and digital baseband processor, described rf analog front-end comprises the said reference mu balanced circuit, described digital baseband processor comprises state controller module, it is characterized in that, described rf analog front-end also comprises the lock clutch state acquisition circuit, described lock clutch state acquisition circuit is connected with the state controller module of digital baseband processor and exports the first lock clutch state signal and the second lock clutch state signal to state controller module, the voltage control signal (power_control) of while accepting state controller module input, described lock clutch state acquisition circuit is connected with the reference voltage-stabilizing circuit of rf analog front-end and provides high level operating voltage and low level operating voltage to reference voltage-stabilizing circuit.
Above-mentioned rf analog front-end concrete structure comprises rectification circuit 201, reference voltage-stabilizing circuit 202, modulation circuit 203, demodulator circuit 204, reset circuit 205, clock circuit 206 and lock clutch state acquisition circuit, described antenna is by interface PAD and the rectification circuit 201 of ESD (anti-static protection circuit), modulation circuit 203 directly is connected with demodulator circuit 204, the radiofrequency signal that rectification circuit 201 receives antenna is converted into that dc source is divided into the rectification low-voltage and the rectification high voltage offers reference voltage-stabilizing circuit 202,202 pairs of power supplys of reference voltage-stabilizing circuit carry out voltage stabilizing, for the radio frequency recognizing electronic label digital baseband part provides low supply voltage 1V and high power supply voltage 1.8V, for modulation circuit 203 provides 1.8V operating voltage, be demodulator circuit 204, clock circuit 206 and reset circuit 205 provide 1V operating voltage, also the low level operating voltage and the low high level operating voltage of DC-to-dc (DC-DC) voltage conversion circuit by the lock clutch state acquisition circuit are attached thereto simultaneously for reference voltage-stabilizing circuit 202, when lockset is opened, if rectification circuit 201 is not then powered to reference voltage-stabilizing circuit 202 by DC-to-dc (DC-DC) voltage conversion circuit when reference voltage-stabilizing circuit 202 power supplies; Demodulator circuit 204 recovers the required demodulating data of digital baseband processor of radio frequency identification from radiofrequency signal; Modulation circuit 203 adopts the method for backscattered modulation that the modulating data of radio frequency recognizing electronic label digital baseband processor output is modulated, and realizes the transfer of data of radio frequency recognizing electronic label to reader; Clock circuit 206 provides stable clock signal of system for digital baseband processor, and reset circuit 205 provides required reset signal for digital baseband processor.
The BBP concrete structure of above-mentioned radio frequency recognizing electronic label comprises that digital baseband part comprises state controller module 104, decoder module 101, coder module 106, cyclic check module 102, memory access control module 107, input pretreatment module 103, output pretreatment module 105, pseudorandom number generator module 108, collision counter module 109, timer conter module 110, clock generating module 111, reset generation module 112 and MTP memory 113.Described decoder module 101 is imported pretreatment module 103 respectively and is connected with cyclic check module 102; Described cyclic check module 103 is connected with output pretreatment module 105, coder module 106; Described memory access control module 107 is connected with output pretreatment module 105; Behind the demodulating data that the demodulator circuit 204 of described decoder module 101 received RF AFE(analog front end)s provides, through decoder module 101 decodings, export decoded data, decoded data divides two-way, one the road to importing pretreatment module 103, a road to cyclic check module 102; Described input pretreatment module 103 is finished the input preliminary treatment of decoded data, generates pending data and pending order and outputs to state controller module 104; After simultaneously cyclic check module 103 is finished cyclic check to decoded data, generate the cyclic check result and output to state controller module 104; State controller module 104 detects the first lock clutch signal switch_on, the result of the second lock clutch signal key_opened and 102 inputs of cyclic check module, and carry out the lock clutch according to situation about checking and write down or receive pending data and pending order, if the first lock clutch signal switch_on, the second lock clutch signal key_opened is high level, and (the high level value is 1V herein, the low level value is 0V), the lock clutch state of expression lockset is for opening, then carry out the record of unblanking, after 104 analyses place of state controller module, the calculated address signal is to memory access control module 107, the related memory cell that storage is unblanked to write down carries out read-write operation, and after being finished, the voltage control signal power_control of the trigger D1 of lock clutch state acquisition circuit drawn high and be high level, if carry out data and command process, then after state controller module 104 is analyzed and is handled, generate five tunnel control signal branches and be clipped to pseudorandom number generator module 108, collision counter module 109, timer conter module 110, clock generating module 111 and reset generation module 112, the calculated address signal arrives memory access control module 107, and exports pseudo random number to be sent to output pretreatment module 105; Memory access control module 107 is visited MTP memory 113 by MTP memory input/output interface and is exported memory data to be sent to the output pretreatment module according to address signal; Described output pretreatment module 105 receives pseudo random number to be sent and memory data to be sent, generates data to be sent to cyclic check module 102 through the output pretreatment module; Cyclic check module 102 is finished the cyclic code coding to data to be sent, generates data to be encoded and outputs to coder module 106; Described coder module 106 is finished the coding of data to be encoded, generates and treats that modulating data outputs to the modulation circuit 203 of rf analog front-end; The clock signal of system of clock circuit 206 inputs of 111 pairs of rf analog front-ends of described clock generating module carries out frequency division and produces the required clock signal of each module, and the reset signal of reset circuit 205 inputs of 112 pairs of rf analog front-ends of reset generation module is handled synchronously and produced the required reset signal of each module in the digital baseband processor.Digital baseband processor provides 1.8V high level and the low level working power voltage of 1V by the reference voltage-stabilizing circuit 202 of rf analog front-end.
Control method to the radio frequency recognizing electronic label of integrated lock clutch state acquisition circuit is described in detail below:
In conjunction with Fig. 2, when the radio frequency recognizing electronic label (hereinafter to be referred as radio frequency recognizing electronic label) that adopts the lock clutch state acquisition circuit was in the radio frequency identification field, its control method comprised step:
Step (a): radio frequency recognizing electronic label enters the radio frequency identification field, the rf analog front-end of radio frequency recognizing electronic label works on power, benchmark Voltage stabilizing module 202 provides low level operating voltage and high level operating voltage (present embodiment low level and high level be value 1V, 1.8V respectively) for digital baseband processor, 112 pairs of state controllers of reset generation module module 104 resets, the radiofrequency signal that demodulator circuit 204 beginning demodulation antennas receive, the lock clutch state acquisition circuit is gathered the lock clutch state of lockset;
Step (b): state controller module 104 detects the lock clutch state acquisition circuit, (the high level value was 1V herein when the clutch signal was high level when the first lock clutch signal and second is locked, the low level value is 0V), the lock clutch state of promptly representing lockset changes step (c) over to for opening; Otherwise lock clutch state changes step (d) over to for closing;
Step (c): state controller control module 104 calculated address signals are to memory access control module 107, the related memory cell that storage is unblanked to write down carries out read-write operation, new recorded data more, and the voltage control signal power_control of the trigger D1 of lock clutch state acquisition circuit drawn high be high level, if the power supply power supply finishes to change step (m) over to otherwise changes step (d) over to;
Step (d): 104 pairs of decoder module 101 of state controller module, cyclic check module 102, coder module 106, input pretreatment module 103, output pretreatment module 105, memory access control module 107, pseudorandom number generator module 108, collision counter module 109, timer conter module 110, clock generating module 111 resets, and reads the data in the MTP memory 113, cyclic check (the CRC result of calculated data;
Step (e): state controller module 104 detects the lock clutch state acquisition circuit, and when the first lock clutch signal and the second lock clutch signal were high level, the lock clutch state of promptly representing lockset changed step (c) over to, otherwise changes step (f) over to for opening;
Step (f): state controller module 104 is opened decoder module 101, off state controller module 104 self clock then, and state controller module 104 is in resting state;
Step (g): decoder module 101 begins to detect from the demodulating data of demodulator circuit 204 inputs of rf analog front-end, when detect available frame count according to the time, decoder module 101 wake-up states controller modules 104;
Step (h): state controller module 104 is opened input pretreatment module 103 and cyclic check module 102, decoder module 101 receives demodulating data, decode through decoder module, export decoded data, decoded data divides two-way, one the road to importing pretreatment module 103, a road to cyclic check module 102; Input pretreatment module 103 is finished the input preliminary treatment of decoded data, generates pending data and pending order and outputs to state controller module 104; The module of cyclic check simultaneously 102 is finished the cyclic check of decoded data, generates the cyclic check result and outputs to state controller module 104;
Step (i): when state controller module 104 detects 102 pairs of cyclic check modules the cyclic check of decoded data has been finished, state controller module 104 is turn-offed decoder module 101, input pretreatment module 103 and cyclic check module 102, state controller module 104 receives pending data and pending order simultaneously, generate control signal through state controller module analysis with after handling, according to the control signal unlatching and to pseudorandom number generator module 108, collision counter module 109 and timer conter module operate 110, and close pseudorandom number generator module 108 after operation is finished, collision counter module 109 and timer conter module 110;
Step (j): state controller module 104 is opened output pretreatment module 105 and memory access control module 107, state controller module 104 OPADD signals arrive memory access control module 107, and export pseudo random number to be sent to output pretreatment module 105; The memory access control module by MTP memory 113 input/output ports visit MTP memory, is exported memory data to be sent to output pretreatment module 105 according to address signal;
Step (k): state controller module 104 ON cycle check code module 102 and coder module 106, output pretreatment module 105 receives pseudo random number to be sent and memory data to be sent, generates data to be sent to cyclic check module 102 through output pretreatment module 105; Cyclic check module 102 is finished the cyclic code coding to data to be sent, and the data to be encoded behind the cyclic code coding are outputed to coder module 106; Coder module 106 is finished the coding to the data to be encoded behind the cyclic code coding, and the modulation circuit of modulating data to rf analog front-end treated in output; After the rf analog front-end modulation circuit is modulated data, by the communication between antenna realization and the read write line.
Step (l): after coder module 106 codings are finished, state controller module 104 is closed output pretreatment module 105, cyclic check module 102, memory access control module 107 and coder module 106, state controller module 104 is checked whether power down of power supplys, power down changes step (m) over to, otherwise changes step (e) over to;
Step (m): power supply power-fail, all modules quit work.
When the radio frequency recognizing electronic label of integrated lock clutch state acquisition circuit is in radio frequency identification outside the venue the time, its control method comprises step:
Step (A): when lockset is opened, the lock clutch state acquisition circuit is started working, the DC-to-dc voltage conversion circuit of lock clutch state acquisition circuit provides low level operating voltage and high level operating voltage (present embodiment low level and high level be value 1V, 1.8V respectively) to the reference voltage-stabilizing circuit 202 of rf analog front-end, rf analog front-end works on power, 112 pairs of state controllers of reset generation module module 104 of BBP resets, and the lock clutch state acquisition circuit is gathered the lock clutch state of lockset;
Step (B): state controller module 104 detects the lock clutch state acquisition circuit, (the high level value was 1V herein when the clutch signal was high level when the first lock clutch signal and second is locked, the low level value is 0V), the lock clutch state of promptly representing lockset changes step (C) over to for opening; Otherwise lock clutch state changes step (D) over to for closing;
Step (C): state controller control module 104 calculated address signals are to memory access control module 107, the related memory cell that storage is unblanked to write down carries out read-write operation, new recorded data more, and the voltage control signal power_control of the trigger D1 of lock clutch state acquisition circuit drawn high be high level;
Step (D): the power supply power-fail of lock clutch state acquisition circuit, the DC-to-dc voltage conversion circuit of lock clutch state acquisition circuit stop reference voltage-stabilizing circuit 202 power supplies to rf analog front-end, and rfid device quits work.
In sum, because the existing relatively lock clutch state acquisition circuit of lock clutch state acquisition circuit of the present invention has low-power consumption and jamproof advantage, and provide the concrete grammar that is integrated in radio frequency recognizing electronic label inside, therefore the lock clutch state acquisition circuit can be relatively easy to and the Internet of Things monitor node of electronic tag combination as container, strongbox circulation in the logistic industry, the lock clutch state of monitoring containers, strongbox has guaranteed the safety that container, strongbox circulate timely.Adopt the RFID tag of lock clutch state acquisition circuit to take into account the function of ordinary passive ultrahigh frequency electronic tag in the radiofrequency field, no matter extraneous the simultaneously radiofrequency field that has or not all can finish record for unlocking times.Because what the present invention adopted is radio frequency recognizing electronic label, can also effectively reduce the consumption and the volume in kind of power consumption, reduced dependence for external power source, strengthened practicality for various particular application.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.
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| CN2010102468412A CN101915025B (en) | 2010-08-06 | 2010-08-06 | Lock clutch state acquisition circuit and radio frequency identification electronic tag integrating same |
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| CN2010102468412A CN101915025B (en) | 2010-08-06 | 2010-08-06 | Lock clutch state acquisition circuit and radio frequency identification electronic tag integrating same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916353A (en) * | 2010-08-06 | 2010-12-15 | 电子科技大学 | Lock and clutch state acquisition circuit and radio frequency identification device using the circuit |
| CN102142100A (en) * | 2011-04-08 | 2011-08-03 | 华中科技大学 | High-frequency passive RFID (Radio Frequency Identification) analog front end circuit |
| CN102637261A (en) * | 2012-04-11 | 2012-08-15 | 东莞市巨细信息科技有限公司 | An RFID electronic tag integrated with an electrocardiographic signal acquisition circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0140028A2 (en) * | 1983-10-24 | 1985-05-08 | Klaus Dr. Meister | Safety locking installation with a biaxial clutch device, locking magnet, driver and reserve circuit |
| CN200992861Y (en) * | 2006-12-18 | 2007-12-19 | 汉王科技股份有限公司 | Alarm anti-theft door lock |
| CN101205772A (en) * | 2006-12-18 | 2008-06-25 | 汉王科技股份有限公司 | Face recognition without keyhole alarm anti-theft door lock |
| CN101519928A (en) * | 2009-04-07 | 2009-09-02 | 温州市创力电子有限公司 | Reinforced electronic control safety-protection lock |
-
2010
- 2010-08-06 CN CN2010102468412A patent/CN101915025B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0140028A2 (en) * | 1983-10-24 | 1985-05-08 | Klaus Dr. Meister | Safety locking installation with a biaxial clutch device, locking magnet, driver and reserve circuit |
| CN200992861Y (en) * | 2006-12-18 | 2007-12-19 | 汉王科技股份有限公司 | Alarm anti-theft door lock |
| CN101205772A (en) * | 2006-12-18 | 2008-06-25 | 汉王科技股份有限公司 | Face recognition without keyhole alarm anti-theft door lock |
| CN101519928A (en) * | 2009-04-07 | 2009-09-02 | 温州市创力电子有限公司 | Reinforced electronic control safety-protection lock |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916353A (en) * | 2010-08-06 | 2010-12-15 | 电子科技大学 | Lock and clutch state acquisition circuit and radio frequency identification device using the circuit |
| CN102142100A (en) * | 2011-04-08 | 2011-08-03 | 华中科技大学 | High-frequency passive RFID (Radio Frequency Identification) analog front end circuit |
| CN102637261A (en) * | 2012-04-11 | 2012-08-15 | 东莞市巨细信息科技有限公司 | An RFID electronic tag integrated with an electrocardiographic signal acquisition circuit |
| CN102637261B (en) * | 2012-04-11 | 2015-02-18 | 东莞市巨细信息科技有限公司 | RFID electronic tag integrated with electrocardiosignal acquisition circuit |
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| Publication number | Publication date |
|---|---|
| CN101915025B (en) | 2012-11-07 |
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