CN101911507B - Data processing device and data processing method - Google Patents

Abstract

A data processing device and method in which resistance to an error of data can be improved. A demultiplexer (25) rearranges mb bits of code bits and defines the rearranged code bits as b pieces of symbols of symbol bits according to an assignment rule to assign the code bits of an LDPC code to symbol bits representing symbols. The assignment rule defines groups grouped into the code bits and thesymbol bits according to error probability as a code bit group and a symbol bit group, respectively, a combination of the code bit group and the symbol bit group of symbol bits to assign the code bits of the code bit group, and the number of bits of code bits and symbol bits. The data processing device and method can be applied to, e.g., a transmission system or the like to transmit an LDPC code.

Description

Data processing equipment and data processing method

Technical field

The present invention relates to data processing equipment and data processing method, particularly, relate to data processing equipment and the data processing method that for example can improve the tolerance limit of data error.

Background technology

The LDPC code has high error correcting capability, and in recent years, the LDPC code begins to be widely used in the transmission system that comprises the satellite digital broadcasting system, such as DVB (the Digital Video Broadcasting that uses in Europe, digital video broadcasting)-S.2 system etc. (for example, with reference to non-patent document 1).In addition, studying and in received terrestrial digital broadcasting of future generation, also using the LDPC code.

Find by recent research, be added to when similar to Turbo code etc. in code length, can realize performance near shannon limit by the LDPC code.In addition, because the LDPC code has the characteristic that minimum range increases pro rata with code length, therefore, its characteristics are to have good piece probability of error performance.In addition, it also has advantages of so-called error floor (error floor) phenomenon of observing in the decoding characteristics that can appear at hardly Turbo code etc.

Hereinafter specifically describe aforesaid this LDPC code.It should be noted that the LDPC code is linear code, in addition, although LDPC code two-dimension code not necessarily, following description be in the situation that hypothesis its provide for two-dimension code.

The most important characteristics of LDPC code are that the parity matrix that limits this LDPC code is sparse matrix.Here, sparse matrix is the quantity considerably less matrix (nearly all element be 0 matrix) of value for the element of " 1 ".

Fig. 1 shows an example of the parity check matrix H of LDPC code.

In the parity matrix of Fig. 1, the weight of each row (row weight) (quantity of " 1 ") (weight) is " 3 ", and the weight of every delegation (row weight) is " 6 ".

When encoding (LDPC coding) with the LDPC code, for example, produce generator matrix G based on parity check matrix H, and this generator matrix G and two-dimensional signal bit multiply each other, with generated codeword (LDPC code).

Particularly, the encoding device of execution LDPC coding at first calculates and satisfies expression formula GH ^T=0 generator matrix G and the transposed matrix H of parity check matrix H ^THere, if generator matrix G is K * N matrix, then encoding device multiply by generator matrix G the Bit String (vector u) of K information bit, with the code word c that generates N bit (=uG).The code word (LDPC code) that is generated by encoding device is received by predetermined communication port by receiver side.

The algorithm as probabilistic decoding (Probabilistic Decoding) that can use Gallager to propose, namely at the message pass-algorithm (Message Passing Algorithm) of the so-called Tan Natu that comprises variable node (being also referred to as information node) and check-node (Tanner Graph) by belief propagation, come the decoding to the LDPC code.In the following description, each in variable node and the check-node all suitably is called node for short.

Fig. 2 shows the process that the LDPC code is decoded.

Should be noted that in the following description, the value of n code bit in the LDPC node (code word) that is received by the recipient is that the real number value that the likelihood of " 0 " is represented as log-likelihood ratio suitably is called reception value u _OiIn addition, from the message of check-node output by u _jExpression, and from the message of variable node output by v _iExpression.

At first, as shown in Figure 2, in the decoding to the LDPC code, at step S11, receive the LDPC code, with message (check-node message) u _jBe initialized as " 0 ", and will adopt integer, be initialized as 0 with the variable k as the counter of repetitive process; This reprocessing proceeds to step S12.At step S12, based on the reception value u that obtains by receiving the LDPC code _OiCarry out the mathematical operation (variable node mathematical operation) by expression formula (1) expression, to determine message (variable node message) v _iIn addition, based on message v _iCarry out the mathematical operation (check-node mathematical operation) by expression formula (2) expression, to determine message u _j

[expression formula 1] $v_i=u_{0i}+\underset{j=1}{\overset{d_v-1}{\mathrm{\Σ}}}{u}_j---\left(1\right)$

[expression formula 2] $\tanh \left(\frac{u_j}{2}\right)=\underset{i=1}{\overset{d_c-1}{\mathrm{\Π}}}\tanh \left(\frac{v_i}{2}\right)---\left(2\right)$

Here, the d in expression formula (1) and (2) _vAnd d _cBe optional parameter, and the quantity of " 1 " in the expression vertical direction (row) of parity check matrix H and the horizontal direction (OK).For example, in the situation of (3,6) code, d _v=3 and d _c=6.

Should be noted that in the check-node mathematical operation of the variable node mathematical operation of expression formula (1) and expression formula (2), the scope of mathematical operation is 1 to d _v-1 or 1 to d _c-1, this is because be not used as the object of mathematical operation from the message of edge (with the line of variable node and check-node interconnection) input that will output message.Simultaneously, by producing in advance the function R (v by expression formula (3) expression ₁, v ₂) table and continuously (recursively) use as the table of expression formula (4) expression comes the check-node mathematical operation of executable expressions (2), wherein, expression formula (3) is by inputting v with respect to two ₁And v ₂Output define.

[expression formula 3] x=2tanh ^-1{ tanh (v ₁/ 2) tanh (v ₂/ 2) }=R (v ₁, v ₂) (3)

[expression formula 4] $u_j=R(v_1,R(v_2,R(v_3,...R(v_{d_c-2},v_{d_c-1}))))---\left(4\right)$

In addition, at step S12, variable k increases 1, and processing proceeds to step S13.At step S13, determine that whether variable k is greater than predetermined repeat decoding number of times C.Be not more than C if in step S13, determined variable k, then process being back to step S12, and the after this processing of duplication similarity.

On the other hand, if determined variable k greater than C at step S13, then process and proceed to step S14, in step S14, determine and output message v _i, carry out the decoded result of finally being exported by the mathematical operation of expression formula (5) expression as passing through, thereby end is to the decode procedure of LDPC code.

[expression formula 5] $v_i=u_{0i}+\underset{j=1}{\overset{d_v}{\mathrm{\Σ}}}{u}_j---\left(5\right)$

Here, different from the variable node mathematical operation of expression formula (1) is to use from the marginate message u that is connected to variable node _jCome the mathematical operation of executable expressions (5).

Fig. 3 shows an example of the parity check matrix H of (3,6) LDPC code (encoding rate is 1/2, and code length is 12).

In the parity matrix of Fig. 3, with identical among Fig. 1 be, the row weight be 3 and the row weight be 6.

Fig. 4 shows the Tan Natu of the parity check matrix H of Fig. 3.

Here, in Fig. 4, by "+" expression check-node and by "=" expression variable node.Check-node and variable node correspond respectively to the row and column of parity check matrix H.Connection between check-node and the variable node is the edge, and corresponding to the element " 1 " of parity matrix.

Particularly, the element in the j of the i of parity matrix row is capable is that i the variable node (node "=") that begins from the top links to each other by the edge with j the check-node (node "+") that begins from the top in 1 the situation.The edge represents that the code bit corresponding with variable node has the constraints corresponding with check-node.

As the coding/decoding method of LDPC code and product calculation (Sum Product Algorithm) in, the mathematical operation of variable node and the mathematical operation of check-node are carried out repeatedly.

Fig. 5 shows the variable node mathematical operation of carrying out with respect to certain variable node.

With respect to this variable node, the message v corresponding with certain edge that will calculate _iThe message u that uses from the remaining edge that is connected to this variable node ₁And u ₂And reception value u _Oi, determine by the variable node mathematical operation of expression formula (1).In addition, adopt similar method to determine the message corresponding with any other edge.

Fig. 6 shows the check-node mathematical operation of carrying out at certain check node.

Here, can by utilize expression formula a * b=exp{ln (| a|)+ln (| b|) } * relation of sign (a) * sign (b) is rewritten as expression formula (6) with expression formula (2), comes the check-node mathematical operation of executable expressions (2).Should be noted that sign (x) is 1 when x 〉=0, and sign (x) is-1 when x＜0.

[expression formula 6]

$u_j=2{\tanh }^{-1}\left(\underset{i=1}{\overset{d_c-1}{\mathrm{\Π}}}\tanh \left(\frac{v_i}{2}\right)\right)$

${=2\tanh }^{-1}\left[\exp \right\{\underset{i=1}{\overset{d_c-1}{\mathrm{\Σ}}}\ln \left(\right|\tanh \left(\frac{v_i}{2}\right)\left|\right)\}\×\underset{i=1}{\overset{d_c-1}{\mathrm{\Π}}}\mathrm{sign}\left(\tanh \left(\frac{v_i}{2}\right)\right)]$

$={2\tanh }^{-1}\left[\exp \right\{-(\underset{i=1}{\overset{d_c-1}{\mathrm{\Σ}}}-\ln \left(\tanh \left(\frac{\left|v_i\right|}{2}\right)\right))\left\}\right]\×\underset{i=1}{\overset{d_c-1}{\mathrm{\Π}}}\mathrm{sign}\left(v_i\right)---\left(6\right)$

In addition, if when x 〉=0 function

Be defined as expression formula

Then owing to satisfying expression formula Expression formula (6) can be converted into expression formula (7).

[expression formula 7] $u_j={\mathrm{\φ}}^{-1}\left(\underset{i=1}{\overset{d_c-1}{\mathrm{\Σ}}}\mathrm{\φ}\left(\right|v_i\left|\right)\right)\×\underset{i=1}{\overset{d_c-1}{\mathrm{\Π}}}\mathrm{sign}\left(v_i\right)---\left(7\right)$

At this check node, come the check-node mathematical operation of executable expressions (2) according to expression formula (7).

Particularly, at this check node, the message u corresponding with certain edge that will calculate _jThe message v that is used to from being connected to the remaining edge of this check-node ₁, v ₂, v ₃, v ₄And v ₅, determine by the check-node mathematical operation of expression formula (7).In addition, adopt similar method to determine the message corresponding with any other edge.

Should be noted that the function of expression formula (7)

Can also be expressed as

X＞0 wherein,

Work as function With

When being incorporated in the hardware, in the situation that sometimes use LUT (look-up table) to come in conjunction with them, these LUT become identical LUT.

Non-patent document 1:DVB-S.2:ETSI EN 302 307 V1.1.2 (in June, 2006)

Summary of the invention

Technical problem

Adopting the LDPC code as the DVB-S.2 of satellite digital broadcasting standard with in as the DVB-T.2 of received terrestrial digital broadcasting standard of future generation.In addition, plan in as the DVB-C.2 of CATV of future generation (cable TV) standards for digital broadcasting, to adopt the LDPC code.

In the digital broadcasting that meets such as the DVB standard of DVB-S.2 etc., the LDPC code is converted (symbolism) and is the symbol such as the quadrature modulation (Digital Modulation) of QPSK (quaternary PSK), and this symbol is mapped as signaling point and sends.

In the semiosis of LDPC code, carry out the displacement to the code bit of LDPC code take two bits or more bit as unit, and will be defined as sign bit through yard bit after this displacement.

Several different methods has been proposed, as the method that is used for the permutation code bit of LDPC code sign.Yet, a kind of new method that has for the tolerance limit of the improvement of error need to be proposed.

The present invention has considered above-mentioned situation, and can improve the data of LDPC code etc. to the tolerance limit of error.

according to an aspect of the present invention, a kind of data processing equipment or a kind of data processing method are provided, wherein, code length be code bit in low-density checksum (LDPC) code of N bit be written into (described storage device follows direction and described column direction is stored described code bit) along the column direction of storage device and the code bit of the described LDPC code read along described line direction in m bit be set to a symbol, and represent with b in the situation of the positive integer of being scheduled to, described storage device is at mb bit of storage on described line direction and store the individual bit of N/ (mb) on described column direction, the code bit of described LDPC code is written into and along described line direction, is read out along the described column direction of described storage device, wherein, mb the code bit of reading along the described line direction of described storage device is set in the situation of b symbol, according to being used for the allocation rule of the code Bit Allocation in Discrete of described LDPC code to the sign bit for representing described symbol, described data processing equipment or described data processing method comprise displacement apparatus or displacement step, this displacement apparatus or displacement step are used for replacing described mb code bit, make a displacement code bit afterwards form described sign bit, described allocation rule is the rule of the following content of regulation: in the situation that the group that described code bit groupings is formed in response to the probability of error of described code bit is set to yard bit group and in response to the probability of error of described sign bit, the group that described sign bit grouping forms is set to the sign bit group, and the group collection of the combination of the sign bit group of the sign bit that is assigned to as the code bit of any yard bit group in the described code bit group of described code bit and this yard bit group, and yard bit group and yard bit in the sign bit group and each bit number of sign bit of described group of collection.

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into four code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule provides as follows content: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 3rd, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 3rd, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 4th, and a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 5th.

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein, the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 2/3 LDPC code; M bit is 10 bits, and integer b is 1; The code bit of 10 bits is mapped to several in 1024 signaling points stipulating among the 1024QAM as a symbol; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 16,200/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₆, with bit b ₇Be assigned to bit y ₅, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein, m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into four code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 3rd, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 3rd, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 4th, and a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 5th.

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 2/3 LDPC code; M bit is 10 bits, and integer b is 1; Several in 1024 signaling points that the code bit of 10 bits is stipulated in the 1024QAM as a sign map; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 64,800/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₆, with bit b ₇Be assigned to bit y ₅, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into four code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 4th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the second-best sign bit group of the probability of error, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 4th, and a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 5th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 3/4 LDPC code; M bit is 10 bits, and integer b is 1; Several in 1024 signaling points that the code bit of 10 bits is stipulated in 1024 QAM as a sign map; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 16,200/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₆, with bit b ₁Be assigned to bit y ₄, with bit b ₂Be assigned to bit y ₈, with bit b ₃Be assigned to bit y ₅, with bit b ₄Be assigned to bit y ₀, with bit b ₅Be assigned to bit y ₂, with bit b ₆Be assigned to bit y ₁, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into four code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 4th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the second-best sign bit group of the probability of error, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 4th, and a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 5th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 3/4 LDPC code; M bit is 10 bits, and integer b is 1; Several in 1024 signaling points that the code bit of 10 bits is stipulated in the 1024QAM as a sign map; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 64,800/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₆, with bit b ₁Be assigned to bit y ₄, with bit b ₂Be assigned to bit y ₈, with bit b ₃Be assigned to bit y ₅, with bit b ₄Be assigned to bit y ₀, with bit b ₅Be assigned to bit y ₂, with bit b ₆Be assigned to bit y ₁, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into three code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule regulation: two code bits in the best code bit group of the probability of error are assigned to two sign bits in the best sign bit group of the probability of error, a code bit in the best code bit group of the probability of error is assigned to a sign bit in the second-best sign bit group of the probability of error, two code bits in the best code bit group of the probability of error are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the second-best sign bit group of the probability of error, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th, and a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 4/5 LDPC code; M bit is 10 bits, and integer b is 1; Several in 1024 signaling points that the code bit of 10 bits is stipulated in the 1024QAM as a sign map; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 16,200/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₆, with bit b ₁Be assigned to bit y ₄, with bit b ₂Be assigned to bit y ₈, with bit b ₃Be assigned to bit y ₅, with bit b ₄Be assigned to bit y ₀, with bit b ₅Be assigned to bit y ₂, with bit b ₆Be assigned to bit y ₁, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into three code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 4th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th, and a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 4/5 LDPC code; M bit is 10 bits, and integer b is 1; Several in 1024 signaling points that the code bit of 10 bits is stipulated in the 1024QAM as a sign map; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 64,800/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₆, with bit b ₁Be assigned to bit y ₄, with bit b ₂Be assigned to bit y ₈, with bit b ₃Be assigned to bit y ₅, with bit b ₄Be assigned to bit y ₀, with bit b ₅Be assigned to bit y ₂, with bit b ₆Be assigned to bit y ₁, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into four code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 4th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 4th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 5/6 LDPC code; M bit is 10 bits, and integer b is 1; Several in 1024 signaling points that the code bit of 10 bits is stipulated in the 1024QAM as a sign map; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 16,200/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₆, with bit b ₁Be assigned to bit y ₄, with bit b ₂Be assigned to bit y ₈, with bit b ₃Be assigned to bit y ₅, with bit b ₄Be assigned to bit y ₀, with bit b ₅Be assigned to bit y ₂, with bit b ₆Be assigned to bit y ₁, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into four code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 4th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 4th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 5/6 LDPC code; M bit is 10 bits, and integer b is 1; Several in 1024 signaling points that the code bit of 10 bits is stipulated in the 1024QAM as a sign map; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 64,800/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₆, with bit b ₁Be assigned to bit y ₄, with bit b ₂Be assigned to bit y ₈, with bit b ₃Be assigned to bit y ₅, with bit b ₄Be assigned to bit y ₀, with bit b ₅Be assigned to bit y ₂, with bit b ₆Be assigned to bit y ₁, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into five code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the best sign bit group of the probability of error, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 5th is assigned to a sign bit in the good sign bit group of the probability of error the 4th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 8/9 LDPC code; M bit is 10 bits, and integer b is 1; Several in 1024 signaling points that the code bit of 10 bits is stipulated in the 1024QAM as a sign map; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 16,200/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₆, with bit b ₇Be assigned to bit y ₅, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into five code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the best sign bit group of the probability of error, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 5th is assigned to a sign bit in the good sign bit group of the probability of error the 4th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 8/9 LDPC code; M bit is 10 bits, and integer b is 1; Several in 1024 signaling points that the code bit of 10 bits is stipulated in the 1024QAM as a sign map; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 64,800/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₆, with bit b ₇Be assigned to bit y ₅, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into three code bit groups, and 10 * 1 sign bits are grouped into five sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 9/10 LDPC code; M bit is 10 bits, and integer b is 1; With the code bit of 10 bits as several in 1024 signaling points in 1024QAM, stipulating of a sign map; Storage device has ten row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 64,800/ (10 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₆, with bit b ₇Be assigned to bit y ₅, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 12 bits and integer b be 1 and with 12 code bits as a sign map to 2 ¹²Namely in the situation of 4096 signaling points, 12 * 1 code bits are grouped into three code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 6th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 6th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 2/3 LDPC code; M bit is 12 bits, and integer b is 1; With several in 4096 signaling points in 4096QAM, stipulating of the code bit mapping of 12 bits; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 16,200/ (12 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₁₀, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₅, with bit b ₇Be assigned to bit y ₆, with bit b ₈Be assigned to bit y ₈, with bit b ₉Be assigned to bit y ₇, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: be that 12 bits and integer b are 1 and with 12 code bits at m bit,, as a sign map to 2 ¹²Namely in the situation of 4096 signaling points, 12 * 1 code bits are grouped into three code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 6th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 6th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 2/3 LDPC code; M bit is 12 bits, and integer b is 1; With several in 4096 signaling points in 4096QAM, stipulating of the code bit mapping of 12 bits; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 64,800/ (12 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₁₀, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₅, with bit b ₇Be assigned to bit y ₆, with bit b ₈Be assigned to bit y ₈, with bit b ₉Be assigned to bit y ₇, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 12 bits and integer b be 1 and with 12 code bits as a sign map to 2 ¹²Namely in the situation of 4096 signaling points, 12 * 1 code bits are grouped into four code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and two code bits in the good code bit group of the probability of error the 4th are assigned to two sign bits in the good sign bit group of the probability of error the 6th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 3/4 LDPC code; M bit is 12 bits, and integer b is 1; With several in 4096 signaling points in 4096QAM, stipulating of the code bit mapping of 12 bits; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 16,200/ (12 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₆, with bit b ₃Be assigned to bit y ₁, with bit b ₄Be assigned to bit y ₄, with bit b ₅Be assigned to bit y ₅, with bit b ₆Be assigned to bit y ₂, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₇, with bit b ₉Be assigned to bit y ₁₀, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 12 bits and integer b be 1 and with 12 code bits as a sign map to 2 ¹²Namely in the situation of 4096 signaling points, 12 * 1 code bits are grouped into three code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 6th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 3/4 LDPC code; M bit is 12 bits, and integer b is 1; With several in 4096 signaling points in 4096QAM, stipulating of the code bit mapping of 12 bits; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 64,800/ (12 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₆, with bit b ₃Be assigned to bit y ₁, with bit b ₄Be assigned to bit y ₄, with bit b ₅Be assigned to bit y ₅, with bit b ₆Be assigned to bit y ₂, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₇, with bit b ₉Be assigned to bit y ₁₀, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 12 bits and integer b be 1 and with 12 code bits as a sign map to 2 ¹²Namely in the situation of 4096 signaling points, 12 * 1 code bits are grouped into three code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: two code bits in the best code bit group of the probability of error are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the best code bit group of the probability of error are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the best code bit group of the probability of error are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, two code bits in the best code bit group of the probability of error are assigned to two sign bits in the good sign bit group of the probability of error the 4th, a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 6th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 6th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 4/5 LDPC code; M bit is 12 bits, and integer b is 1; With several in 4096 signaling points in 4096QAM, stipulating of the code bit mapping of 12 bits; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 16,200/ (12 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₆, with bit b ₃Be assigned to bit y ₁, with bit b ₄Be assigned to bit y ₄, with bit b ₅Be assigned to bit y ₅, with bit b ₆Be assigned to bit y ₂, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₇, with bit b ₉Be assigned to bit y ₁₀, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 12 bits and integer b be 1 and with 12 code bits as a sign map to 2 ¹²Namely in the situation of 4096 signaling points, 12 * 1 code bits are grouped into five code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the best sign bit group of the probability of error, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 6th, a code bit in the good code bit group of the probability of error the 5th is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 5th is assigned to a sign bit in the good sign bit group of the probability of error the 6th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 4/5 LDPC code; M bit is 12 bits, and integer b is 1; With several in 4096 signaling points in 4096QAM, stipulating of the code bit mapping of 12 bits; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 64,800/ (12 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₆, with bit b ₃Be assigned to bit y ₁, with bit b ₄Be assigned to bit y ₄, with bit b ₅Be assigned to bit y ₅, with bit b ₆Be assigned to bit y ₂, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₇, with bit b ₉Be assigned to bit y ₁₀, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 12 bits and integer b be 1 and with 12 code bits as a sign map to 2 ¹²Namely in the situation of 4096 signaling points, 12 * 1 code bits are grouped into four code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 6th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 6th.

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 5/6 LDPC code; M bit is 12 bits, and integer b is 1; Several in 4096 signaling points that the code bit mapping of 12 bits is stipulated in the 4096QAM; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 16,200/ (12 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₆, with bit b ₃Be assigned to bit y ₁, with bit b ₄Be assigned to bit y ₄, with bit b ₅Be assigned to bit y ₅, with bit b ₆Be assigned to bit y ₂, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₇, with bit b ₉Be assigned to bit y ₁₀, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

In addition, according to an aspect of the present invention, a kind of data processing equipment or data processing method are provided, wherein: in the situation that m bit is 12 bits and integer b be 1 and with 12 code bits as i.e. 4096 signaling points of a sign map to 212,12 * 1 code bits are grouped into three code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 4th, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 6th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 6th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 5/6 LDPC code; M bit is 12 bits, and integer b is 1; Several in 4096 signaling points that the code bit mapping of 12 bits is stipulated in the 4096QAM; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 64,800/ (12 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₆, with bit b ₃Be assigned to bit y ₁, with bit b ₄Be assigned to bit y ₄, with bit b ₅Be assigned to bit y ₅, with bit b ₆Be assigned to bit y ₂, with bit b ₇Be assigned to bit y ₃, with bit b ₈Be assigned to bit y ₇, with bit b ₉Be assigned to bit y ₁₀, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 12 bits and integer b be 1 and with 12 code bits as a sign map to 2 ¹²Namely in the situation of 4096 signaling points, 12 * 1 code bits are grouped into five code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 6th, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the best sign bit group of the probability of error, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 6th, and a code bit in the good code bit group of the probability of error the 5th is assigned to a sign bit in the good sign bit group of the probability of error the 5th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 8/9 LDPC code; M bit is 12 bits, and integer b is 1; With several in 4096 signaling points in 4096QAM, stipulating of the code bit mapping of 12 bits; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 16,200/ (12 * 1) at column direction; The i+1 bit that begins at the highest significant bit of 12 * 1 code bits reading with the line direction of storage device is represented as bit b _iAnd be represented as bit y since the i+1 bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₁₀, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₅, with bit b ₇Be assigned to bit y ₆, with bit b ₈Be assigned to bit y ₈, with bit b ₉Be assigned to bit y ₇, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 12 bits and integer b be 1 and with 12 code bits as a sign map to 2 ¹²Namely in the situation of 4096 signaling points, 12 * 1 code bits are grouped into five code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 6th, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the best sign bit group of the probability of error, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 6th, and a code bit in the good code bit group of the probability of error the 5th is assigned to a sign bit in the good sign bit group of the probability of error the 5th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 8/9 LDPC code; M bit is 12 bits, and integer b is 1; With several in 4096 signaling points in 4096QAM, stipulating of the code bit mapping of 12 bits; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 64,800/ (12 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₁₀, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₅, with bit b ₇Be assigned to bit y ₆, with bit b ₈Be assigned to bit y ₈, with bit b ₉Be assigned to bit y ₇, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

In addition, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: m bit be 12 bits and integer b be 1 and with 12 code bits as a sign map to 2 ¹²Namely in the situation of 4096 signaling points, 12 * 1 code bits are grouped into five code bit groups, and 12 * 1 sign bits are grouped into six sign bit groups; Allocation rule regulation: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 6th, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the best sign bit group of the probability of error, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the second-best sign bit group of the probability of error, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 3rd, two code bits in the good code bit group of the probability of error the 3rd are assigned to two sign bits in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 6th, and a code bit in the good code bit group of the probability of error the 5th is assigned to a sign bit in the good sign bit group of the probability of error the 5th.

Further, according to an aspect of the present invention, provide a kind of data processing equipment or data processing method, wherein: the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 9/10 LDPC code; M bit is 12 bits, and integer b is 1; With several in 4096 signaling points in 4096QAM, stipulating of the code bit mapping of 12 bits; Storage device has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 64,800/ (12 * 1) at column direction; I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, displacement apparatus or displacement step are replaced according to allocation rule, with bit b ₀Be assigned to bit y ₁₀, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₅, with bit b ₇Be assigned to bit y ₆, with bit b ₈Be assigned to bit y ₈, with bit b ₉Be assigned to bit y ₇, with bit b ₁₀Be assigned to bit y ₁₁, and with bit b ₁₁Be assigned to bit y ₉

According to an above-mentioned aspect of the present invention, code length is that the code bit in the LDPC code of N bit is written into (described storage device follows direction and described column direction is stored described code bit) along the column direction of storage device, and m bit in the code bit of the described LDPC code of reading along described line direction is set to a symbol, and represent the positive integer of being scheduled to b, described storage device is stored the individual bit of N/ (mb) at described mb bit of line direction storage and at described column direction; The code bit of described LDPC code is written into and is read out along described line direction along the described column direction of described storage device; Mb the code bit of reading along the described line direction of described storage device is set to b symbol.In this case, according to for the allocation rule of the code Bit Allocation in Discrete of described LDPC code being given for the sign bit that represents described symbol, replace mb code bit of described LDPC code, so that a displacement code bit afterwards forms described sign bit.Described allocation rule is the rule of the following content of regulation: in the situation that the group that described code bit groupings is formed in response to the probability of error of described code bit is set to yard bit group and in response to the probability of error of described sign bit, the group that described sign bit grouping forms is set to the sign bit group, and the group collection of the combination of the sign bit group of the sign bit that is assigned to as the code bit of any yard bit group in the described code bit group of described code bit and this yard bit group, and yard bit group and yard bit in the sign bit group and each bit number of sign bit of described group of collection.

For example, m bit be 10 bits and integer b be 1 and with 10 code bits as a sign map to 2 ¹⁰Namely in the situation of 1024 signaling points, 10 * 1 code bits are grouped into for example four code bit groups, and 10 * 1 sign bits are grouped into for example five sign bit groups.Further, in this case, allocation rule regulation is following content for example: a code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error, two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error, a code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 3rd, a code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 4th, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 3rd, a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 4th, and a code bit in the good code bit group of the probability of error the 4th is assigned to a sign bit in the good sign bit group of the probability of error the 5th.

Particularly, for example, wherein, the LDPC code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 16,200 bits and encoding rate are 2/3 LDPC code, m bit is 10 bits, and integer b is 1, and with the code bit of 10 bits as several in 1024 signaling points in 1024QAM, stipulating of a sign map, storage device has ten row, be used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 16,200/ (10 * 1) at column direction.After this, i+1 the bit that begins at the highest significant bit of 10 * 1 code bits reading along the line direction of storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 10 * 1 sign bits of a symbol _iSituation under, displacement apparatus is replaced according to allocation rule, with for example with bit b ₀Be assigned to bit y ₈, with bit b ₁Be assigned to bit y ₀, with bit b ₂Be assigned to bit y ₁, with bit b ₃Be assigned to bit y ₂, with bit b ₄Be assigned to bit y ₃, with bit b ₅Be assigned to bit y ₄, with bit b ₆Be assigned to bit y ₆, with bit b ₇Be assigned to bit y ₅, with bit b ₈Be assigned to bit y ₉, and with bit b ₉Be assigned to bit y ₇

Should be noted that data processing equipment can be equipment independently, perhaps can be the internal module that consists of an equipment.

Beneficial effect

According to the present invention, can improve the tolerance limit to error.

Description of drawings

Fig. 1 shows the view of the parity check matrix H of LDPC code.

Fig. 2 shows the flow chart to the decode procedure of LDPC code.

Fig. 3 shows the view of an example of the parity matrix of LDPC code.

Fig. 4 is the view of Tan Natu (Tanner Graph) that parity matrix is shown.

Fig. 5 is the view that variable node (Variable Node) is shown.

Fig. 6 is the view that check-node (Check Node) is shown.

Fig. 7 is the view that the profile instance of the embodiment that has used transmission system of the present invention is shown.

Fig. 8 is the block diagram that the profile instance of transmitting apparatus 11 is shown.

Fig. 9 is the view that parity matrix is shown.

Figure 10 is the view that parity matrix is shown.

Figure 11 shows the parity matrix of LDPC code and the view of the row weight stipulated in the DVB-S.2 standard.

Figure 12 shows the view of the signaling point layout of 16QAM.

Figure 13 shows the view of the signaling point layout of 64QAM.

Figure 14 shows the view of the signaling point layout of 64QAM.

Figure 15 shows the view of the signaling point layout of 64QAM.

Figure 16 shows the view of the processing of demodulation multiplexer 25.

Figure 17 shows the view of the processing of demodulation multiplexer 25.

Figure 18 shows the view of the Tan Natu relevant with the decoding of LDPC code.

Figure 19 shows the parity matrix H with step structure _TAnd with this parity matrix H _TThe view of corresponding Tan Natu.

Figure 20 shows the parity matrix H of the parity check matrix H corresponding with odd-even LDPC code afterwards _TView.

Figure 21 shows the view of conversion parity matrix (Conversion parity check matrix).

Figure 22 shows the view that row reverse the processing of interleaver 24.

Figure 23 shows the view that row reverse the columns of the required memory 31 that interweaves and write the address of original position.

Figure 24 shows the view that row reverse the columns of the required memory 31 that interweaves and write the address of original position.

Figure 25 shows the flow chart of process of transmitting.

Figure 26 shows the view of the model of the communication path that adopts in the emulation.

Figure 27 shows at the error rate that obtains by emulation and the Doppler frequency f of flutter (flutter) _dBetween the view of relation.

Figure 28 shows at the error rate that obtains by emulation and the Doppler frequency f of flutter _dBetween the view of relation.

Figure 29 shows the block diagram of the profile instance of LDPC coding section 21.

Figure 30 shows the flow chart of the processing of LDPC coding section.

Figure 31 show encoding rate be 2/3 and code length be the view of 16,200 parity matrix initial value table.

Figure 32 show encoding rate be 2/3 and code length be the view of 64,800 parity matrix initial value table.

Figure 33 show encoding rate be 2/3 and code length be the view of 64,800 parity matrix initial value table.

Figure 34 show encoding rate be 2/3 and code length be the view of 64,800 parity matrix initial value table.

Figure 35 show encoding rate be 3/4 and code length be the view of 16,200 parity matrix initial value table.

Figure 36 show encoding rate be 3/4 and code length be the view of 64,800 parity matrix initial value table.

Figure 37 show encoding rate be 3/4 and code length be the view of 64,800 parity matrix initial value table.

Figure 38 show encoding rate be 3/4 and code length be the view of 64,800 parity matrix initial value table.

Figure 39 show encoding rate be 3/4 and code length be the view of 64,800 parity matrix initial value table.

Figure 40 show encoding rate be 4/5 and code length be the view of 16,200 parity matrix initial value table.

Figure 41 show encoding rate be 4/5 and code length be the view of 64,800 parity matrix initial value table.

Figure 42 show encoding rate be 4/5 and code length be the view of 64,800 parity matrix initial value table.

Figure 43 show encoding rate be 4/5 and code length be the view of 64,800 parity matrix initial value table.

Figure 44 show encoding rate be 4/5 and code length be the view of 64,800 parity matrix initial value table.

Figure 45 show encoding rate be 5/6 and code length be the view of 16,200 parity matrix initial value table.

Figure 46 show encoding rate be 5/6 and code length be the view of 64,800 parity matrix initial value table.

Figure 47 show encoding rate be 5/6 and code length be the view of 64,800 parity matrix initial value table.

Figure 48 show encoding rate be 5/6 and code length be the view of 64,800 parity matrix initial value table.

Figure 49 show encoding rate be 5/6 and code length be the view of 64,800 parity matrix initial value table.

Figure 50 show encoding rate be 8/9 and code length be the view of 16,200 parity matrix initial value table.

Figure 51 show encoding rate be 8/9 and code length be the view of 64,800 parity matrix initial value table.

Figure 52 show encoding rate be 8/9 and code length be the view of 64,800 parity matrix initial value table.

Figure 53 show encoding rate be 8/9 and code length be the view of 64,800 parity matrix initial value table.

Figure 54 show encoding rate be 8/9 and code length be the view of 64,800 parity matrix initial value table.

Figure 55 show encoding rate be 9/10 and code length be the view of 64,800 parity matrix initial value table.

Figure 56 show encoding rate be 9/10 and code length be the view of 64,800 parity matrix initial value table.

Figure 57 show encoding rate be 9/10 and code length be the view of 64,800 parity matrix initial value table.

Figure 58 show encoding rate be 9/10 and code length be the view of 64,800 parity matrix initial value table.

Figure 59 shows the view of determining the method for parity check matrix H according to the parity matrix initial table.

Figure 60 shows the view according to the replacement process of existing method.

Figure 61 shows the view according to the replacement process of existing method.

Figure 62 shows code bit group in the situation that the LDPC code of the encoding rate with 16,200 code length and 2/3 is modulated by 1024QAM and the view of sign bit group.

Figure 63 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 2/3 is modulated by 1024QAM.

Figure 64 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 2/3 is modulated by 1024QAM.

Figure 65 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 2/3 is modulated by 1024QAM and the view of sign bit group.

Figure 66 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 2/3 is modulated by 1024QAM.

Figure 67 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 2/3 is modulated by 1024QAM.

Figure 68 shows code bit group in the situation that the LDPC code of the encoding rate with 16,200 code length and 3/4 is modulated by 1024QAM and the view of sign bit group.

Figure 69 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 3/4 is modulated by 1024QAM.

Figure 70 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 3/4 is modulated by 1024QAM.

Figure 71 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 3/4 is modulated by 1024QAM and the view of sign bit group.

Figure 72 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 3/4 is modulated by 1024QAM.

Figure 73 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 3/4 is modulated by 1024QAM.

Figure 74 shows code bit group in the situation that the LDPC code of the encoding rate with 16,200 code length and 4/5 is modulated by 1024QAM and the view of sign bit group.

Figure 75 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 4/5 is modulated by 1024QAM.

Figure 76 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 4/5 is modulated by 1024QAM.

Figure 77 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 4/5 is modulated by 1024QAM and the view of sign bit group.

Figure 78 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 4/5 is modulated by 1024QAM.

Figure 79 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 4/5 is modulated by 1024QAM.

Figure 80 shows code bit group in the situation that the LDPC code of the encoding rate with 16,200 code length and 5/6 is modulated by 1024QAM and the view of sign bit group.

Figure 81 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 5/6 is modulated by 1024QAM.

Figure 82 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 5/6 is modulated by 1024QAM.

Figure 83 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 5/6 is modulated by 1024QAM and the view of sign bit group.

Figure 84 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 5/6 is modulated by 1024QAM.

Figure 85 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 5/6 is modulated by 1024QAM.

Figure 86 shows code bit group in the situation that the LDPC code of the encoding rate with 16,200 code length and 8/9 is modulated by 1024QAM and the view of sign bit group.

Figure 87 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 8/9 is modulated by 1024QAM.

Figure 88 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 8/9 is modulated by 1024QAM.

Figure 89 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 8/9 is modulated by 1024QAM and the view of sign bit group.

Figure 90 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 8/9 is modulated by 1024QAM.

Figure 91 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 8/9 is modulated by 1024QAM.

Figure 92 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 9/10 is modulated by 1024QAM and the view of sign bit group.

Figure 93 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 9/10 is modulated by 1024QAM.

Figure 94 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 9/10 is modulated by 1024QAM.

Figure 95 shows code bit group in the situation that the LDPC code of the encoding rate with 16,200 code length and 2/3 is modulated by 4096QAM and the view of sign bit group.

Figure 96 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 2/3 is modulated by 4096QAM.

Figure 97 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 2/3 is modulated by 4096QAM.

Figure 98 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 2/3 is modulated by 4096QAM and the view of sign bit group.

Figure 99 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 2/3 is modulated by 4096QAM.

Figure 100 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 2/3 is modulated by 4096QAM.

Figure 101 shows code bit group in the situation that the LDPC code of the encoding rate with 16,200 code length and 3/4 is modulated by 4096QAM and the view of sign bit group.

Figure 102 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 3/4 is modulated by 4096QAM.

Figure 103 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 3/4 is modulated by 4096QAM.

Figure 104 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 3/4 is modulated by 4096QAM and the view of sign bit group.

Figure 105 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 3/4 is modulated by 4096QAM.

Figure 106 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 3/4 is modulated by 4096QAM.

Figure 107 shows code bit group in the situation that the LDPC code of the encoding rate with 16,200 code length and 4/5 is modulated by 4096QAM and the view of sign bit group.

Figure 108 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 4/5 is modulated by 4096QAM.

Figure 109 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 4/5 is modulated by 4096QAM.

Figure 110 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 4/5 is modulated by 4096QAM and the view of sign bit group.

Figure 111 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 4/5 is modulated by 4096QAM.

Figure 112 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 4/5 is modulated by 4096QAM.

Figure 113 shows code bit group in the situation that the LDPC code of the encoding rate with 16,200 code length and 5/6 is modulated by 4096QAM and the view of sign bit group.

Figure 114 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 5/6 is modulated by 4096QAM.

Figure 115 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 5/6 is modulated by 4096QAM.

Figure 116 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 5/6 is modulated by 4096QAM and the view of sign bit group.

Figure 117 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 5/6 is modulated by 4096QAM.

Figure 118 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 5/6 is modulated by 4096QAM.

Figure 119 shows code bit group in the situation that the LDPC code of the encoding rate with 16,200 code length and 8/9 is modulated by 4096QAM and the view of sign bit group.

Figure 120 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 8/9 is modulated by 4096QAM.

Figure 121 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 16,200 code length and 8/9 is modulated by 4096QAM.

Figure 122 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 8/9 is modulated by 4096QAM and the view of sign bit group.

Figure 123 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 8/9 is modulated by 4096QAM.

Figure 124 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 8/9 is modulated by 4096QAM.

Figure 125 shows code bit group in the situation that the LDPC code of the encoding rate with 64,800 code length and 9/10 is modulated by 4096QAM and the view of sign bit group.

Figure 126 shows the view of the allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 9/10 is modulated by 4096QAM.

Figure 127 shows the view of the displacement of the code bit that carries out according to allocation rule in the situation that the LDPC code of the encoding rate with 64,800 code length and 9/10 is modulated by 4096QAM.

Figure 128 shows in the situation that carry out the view of the layout of 1024QAM signaling point.

Figure 129 shows in the situation that carry out the view of the layout of 4096QAM signaling point.

Figure 130 shows the view of the BER in the situation of the replacement process of carrying out new method of replacing and in the situation of the replacement process of not carrying out new method of replacing.

Figure 131 shows the view of the BER in the situation of the replacement process of carrying out new method of replacing and in the situation of the replacement process of not carrying out new method of replacing.

Figure 132 shows the view of the BER in the situation of the replacement process of carrying out new method of replacing and in the situation of the replacement process of not carrying out new method of replacing.

Figure 133 shows the view of the BER in the situation of the replacement process of carrying out new method of replacing and in the situation of the replacement process of not carrying out new method of replacing.

Figure 134 shows the block diagram of the profile instance of receiving equipment 12.

Figure 135 shows the flow chart of receiving course.

Figure 136 shows the view of example of the parity matrix of LDPC code.

Figure 137 shows by line replacement and column permutation being applied to the view of the matrix (conversion parity matrix) that parity matrix obtains.

Figure 138 shows the view of the conversion parity matrix of dividing take 5 * 5 bits as unit.

Figure 139 shows wherein to the P node together block diagram of the profile instance of the decoding device of XM mathematical operation.

Figure 140 shows the block diagram of the example of LDPC lsb decoder 56.

Figure 141 shows the block diagram of the profile instance of the embodiment that has used computer of the present invention.

Figure 142 show encoding rate be 2/3 and code length be the view of the example of 16,200 parity matrix initial value table.

Figure 143 show encoding rate be 2/3 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 144 show encoding rate be 2/3 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 145 show encoding rate be 2/3 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 146 show encoding rate be 3/4 and code length be the view of the example of 16,200 parity matrix initial value table.

Figure 147 show encoding rate be 3/4 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 148 show encoding rate be 3/4 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 149 show encoding rate be 3/4 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 150 show encoding rate be 3/4 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 151 show encoding rate be 4/5 and code length be the view of the example of 16,200 parity matrix initial value table.

Figure 152 show encoding rate be 4/5 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 153 show encoding rate be 4/5 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 154 show encoding rate be 4/5 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 155 show encoding rate be 4/5 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 156 show encoding rate be 5/6 and code length be the view of the example of 16,200 parity matrix initial value table.

Figure 157 show encoding rate be 5/6 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 158 show encoding rate be 5/6 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 159 show encoding rate be 5/6 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 160 show encoding rate be 5/6 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 161 show encoding rate be 8/9 and code length be the view of the example of 16,200 parity matrix initial value table.

Figure 162 show encoding rate be 8/9 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 163 show encoding rate be 8/9 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 164 show encoding rate be 8/9 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 165 show encoding rate be 8/9 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 166 show encoding rate be 9/10 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 167 show encoding rate be 9/10 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 168 show encoding rate be 9/10 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 169 show encoding rate be 9/10 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 170 show encoding rate be 1/4 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 171 show encoding rate be 1/4 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 172 show encoding rate be 1/3 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 173 show encoding rate be 1/3 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 174 show encoding rate be 2/5 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 175 show encoding rate be 2/5 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 176 show encoding rate be 1/2 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 177 show encoding rate be 1/2 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 178 show encoding rate be 1/2 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 179 show encoding rate be 3/5 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 180 show encoding rate be 3/5 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 181 show encoding rate be 3/5 and code length be the view of the example of 64,800 parity matrix initial value table.

Figure 182 show encoding rate be 1/4 and code length be the view of the example of 16,200 parity matrix initial value table.

Figure 183 show encoding rate be 1/3 and code length be the view of the example of 16,200 parity matrix initial value table.

Figure 184 show encoding rate be 2/5 and code length be the view of the example of 16,200 parity matrix initial value table.

Figure 185 show encoding rate be 1/2 and code length be the view of the example of 16,200 parity matrix initial value table.

Figure 186 show encoding rate be 3/5 and code length be the view of the example of 16,200 parity matrix initial value table.

Figure 187 show encoding rate be 3/5 and code length be the view of another example of 16,200 parity matrix initial value table.

Figure 188 shows the view of determining the method for parity check matrix H according to the parity matrix initial table.

Figure 189 shows the view of an example of the displacement of yard bit.

Figure 190 shows the view of another example of the displacement of yard bit.

Figure 191 shows the view of another example of the displacement of yard bit.

Figure 192 shows the again view of an example of the displacement of yard bit.

Figure 193 shows the view of the simulation result of BER.

Figure 194 shows the view of another simulation result of BER.

Figure 195 shows the view of the another simulation result of BER.

Figure 196 shows the again view of a simulation result of BER.

Figure 197 shows the view of an example of the displacement of yard bit.

Figure 198 shows the view of another example of the displacement of yard bit.

Figure 199 shows the view of another example of the displacement of yard bit.

Figure 200 shows the again view of an example of the displacement of yard bit.

Figure 20 1 shows the again view of an example of the displacement of yard bit.

Figure 20 2 shows the again view of an example of the displacement of yard bit.

Figure 20 3 shows the again view of an example of the displacement of yard bit.

Figure 20 4 shows the again view of an example of the displacement of yard bit.

Figure 20 5 shows the again view of an example of the displacement of yard bit.

Figure 20 6 shows the again view of an example of the displacement of yard bit.

Figure 20 7 shows the again view of an example of the displacement of yard bit.

Figure 20 8 shows the again view of an example of the displacement of yard bit.

Figure 20 9 shows the view of the processing of the multiplexer 54 that consists of deinterleaver 53.

Figure 21 0 shows the view that row reverse the processing of deinterleaver 55.

Figure 21 1 shows the block diagram of another profile instance of receiving equipment 12.

Figure 21 2 shows the block diagram of the first profile instance of the receiving system that can be applicable to receiving equipment 12.

Figure 21 3 shows the block diagram of the second profile instance of the receiving system that can be applicable to receiving equipment 12.

Figure 21 4 shows the block diagram of the 3rd profile instance of the receiving system that can be applicable to receiving equipment 12.

Description of reference numerals

11 transmitting apparatus, 12 receiving equipments, 21LDPC coding section, 22 bit interleavers, 23 odd-even devices, 24 row reverse interleaver, 25 demodulation multiplexers, 26 mapping sections, 27 quadrature modulation sections, 31 memories, 32 replacement sections, 51 quadrature demodulation sections, 52 separate mapping section, 53 deinterleavers, 54 multiplexers, 55 row reverse deinterleaver, 56LDPC lsb decoder, 300 marginal date memories, 301 selectors, 302 check node calculation sections, 303 cyclic shift circuits, 304 marginal date memories, 305 selectors, 306 receive data memories, 307 variable node calculating parts, 308 cyclic shift circuits, 309 decoded word calculating parts, 310 receive data rearrangement sections, 311 decoded data rearrangement sections, 601 coding processing blocks, 602 memory blocks, 611 encoding rates arrange part, 612 initial value tables are read part, 613 parity matrix generating portions, and 614 information bits are read part, 615 coding odd even mathematical operation parts, 616 control sections, 701 buses, 702CPU, 703ROM, 704RAM, 705 hard disks, 706 efferents, 707 input parts, 708 Department of Communication Forces, 709 drivers, 710 input/output interfaces, 711 detachable recording mediums, 1001 inverse permutation units, 1002 memories, 1011 odd even deinterleavers, the 1021LDPC lsb decoder, 1101 acquisition units, 1102 transmission lines decoding handling part, 1103 information sources decoding handling part, 1111 efferents, 1121 record sections.

Embodiment

Fig. 7 illustrate the configuration of the execution mode of having used transmission system of the present invention example (the term system represent a plurality of equipment logical collection and no matter various component devices whether be included in the identical cabinet).

With reference to Fig. 7, transmission system comprises transmitting apparatus 11 and receiving equipment 12.

Transmitting apparatus 11 for example carries out the transmission (broadcasting) (transmission) of television program.Namely, transmitting apparatus 11 be such as will being encoded to LDPC (low density parity check code) code as the object data of transmission object (such as the view data of television program, voice data etc.), and by transmitting result data such as communication path 13 (such as satellite channel, surface wave and CATV (cable TV) network etc.).

Receiving equipment 12 for example is tuner, television receiver or the STB (set-top box) for receiving television broadcasting program, it is decoded as the LDPC code object data and exports this object data by the LDPC code that communication path 13 receives from transmitting apparatus 11 to its transmission.

At this, the LDPC code that uses in the known transmission system in Fig. 7 presents very high capacity in AWGN (additive white Gaussian noise) communication path.

Yet, in communication path 13 (such as surface wave), burst error occur sometimes or wipe.For example, in OFDM (OFDM) system, at D/U (Desired to Undesired Ratio, signal to noise ratio) be under the multi-path environment of 0dB (power of the signal (=main path) that the power of the signal of not expecting (=echo) equals to expect), in response to the delay in echo (path that is different from main path), the power vanishing (wiping) of concrete symbol.

In addition, in being the flutter of 0dB, D/U (added that to postpone be the communication path of zero echo, and to described echo application Doppler (doppler) frequency), the power that whole OFDM symbol has occured is reduced to the situation of zero (wiping) by Doppler frequency at particular point in time.

In addition, based on from be used for receiving acceptance division from the signal of transmitting apparatus 11 (such as antenna etc.) (not shown) to the wire of receiving equipment 12 state receiving equipment 12 sides, based on the power supply instability to receiving equipment 12, burst error occurs sometimes perhaps.

Simultaneously, when the LDPC code is decoded because in the variable node mathematical operation of expression formula (1) as above-mentioned LDPC code seen in fig. 5 the code bit (reception value u _OiTherefore) addition is to carry out in the variable node corresponding with the code bit of LDPC code in the row of parity check matrix H and, therefore, if be used for the code bit generation error of variable node mathematical operation, the accuracy of the message that then will determine descends.

So, because the message of determining at the variable node that is connected to check-node when the LDPC code is decoded is used to carry out at check-node the check-node mathematical operation of expression formula (7), therefore if connected a plurality of variable nodes (corresponding to the code bit of LDPC code) quantity that the check-node of error (comprise and wiping) occurs simultaneously becomes often the degradation of then decoding.

For example, wiped simultaneously if be connected to two or more variable nodes of check-node, then check-node returns the message that its intermediate value may may be equal to each other for 1 probability for 0 probability and value to all variable nodes.In this case, the check-node that returns the message of equal probability does not play a role the circulation (combination of variable node mathematical operation and check-node mathematical operation) of processing of decoding, and the result need to increase the number of repetition that decoding is processed.Therefore, the degradation of decoding.In addition, also strengthened the power consumption of the receiving equipment 12 of the decoding of carrying out the LDPC code.

Therefore, the transmission system shown in Fig. 7 is configured such that in the performance of keeping the AWGN communication path and improves burst error or the tolerance limit of wiping.

Fig. 8 illustrates the example of configuration of the transmitting apparatus 11 of Fig. 7.

With reference to Fig. 8, transmitting apparatus 11 comprises LDPC coding section 21, bit interleaver 22, mapping section 26 and quadrature modulation section 27.

Provide object data to LDPC coding section 21.

LDPC coding section 21 carries out the LDPC coding according to parity matrix to the object data that offers it, parity matrix is corresponding to the part of the parity bits of LDPC code and has step structure and output LDPC code in described parity matrix, and described object data is information bit.

Particularly, LDPC coding section 21 carries out object data is encoded to the LDPC coding of the LDPC code of for example stipulating in DVB-S.2 or DVB-T.2 standard, and the LDPC code that obtains is exported the result who encodes as LDPC.

At this, in the DVB-T.2 standard, the LDPC code of stipulating in the DVB-S.2 standard is adopted in plan.The LDPC code of stipulating in the DVB-S.2 standard is IRA (Irregular Repeat Accumulate, the irregular repetition accumulated) code, and the parity matrix in the parity matrix of LDPC code has step structure.Parity matrix and step structure are described hereinafter.In addition, for example at H.Jin., A.Khandekar and R.J.McEliece " Irregular Repeat-Accumulate Codes " (in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp.1-8, Sept.2000) in the IRA code has been described.

Be provided for bit interleaver 22 from the LDPC code of LDPC coding section 21 outputs.

Bit interleaver 22 is the data processing equipments for interleaving data, and comprises that odd-even device 23, row reverse interleaver 24 and demodulation multiplexer (DEMUX) 25.

Odd-even device 23 carries out the parity bits from the LDPC code of LDPC coding section 21 is interweaved to the odd-even of the position of other parity bits, and the LDPC code after the odd-even is offered row reverses interleaver 24.

Row reverse 24 pairs of LDPC codes from odd-even device 23 of interleaver and are listed as to reverse and interweave, and the LDPC code that row are reversed after interweaving offers demodulation multiplexer 25.

Particularly, LDPC code transmission two or more code bit are mapped to the signaling point of a symbol of expression quadrature modulation by mapping described below section 26 after.

Row reverse interleaver 24 and carry out row for example as mentioned below and reverse and interweave, process from the pre-layout of the code bit of the LDPC code of parity checker 23 as pre-layout, so that a plurality of yards bits of the LDPC code corresponding with value 1 are not included in the symbol, described value 1 is included in any delegation of the parity matrix that uses in the LDPC coding section 21.

Demodulation multiplexer 25 is carried out the replacement Treatment that the position of two or more yards bit of the LDPC code that reverses interleaver 24 from row (will as symbol) is replaced, the LDPC code that has improved to obtain tolerance limit to AWGN.Then, two or more yards bit of the demodulation multiplexer 25 LDPC code that will obtain by replacement Treatment offers mapping section 26 as symbol.

Mapping section 26 will arrive from the sign map of demodulation multiplexer 25 signaling point of determining by the modulator approach of the quadrature modulation (many-valued modulation) of being carried out by quadrature modulation section 27.

Particularly, mapping section 26 will be mapped to from the LDPC code of demodulation multiplexer 25 determined by modulating system, be positioned at the signaling point on the IQ plane (IQ constellation), described IQ plane is definite by the Q axle of the Q component of the I axle of expression and the I component of carrier wave homophase and expression and carrier wave quadrature.

At this, comprise the modulator approach that defines in the DVB-T standard for example as the modulator approach of the modulator approach of the quadrature modulation of being carried out by quadrature modulation section 27, that is, can example such as QPSK (orthogonal PSK), 16QAM (quadrature amplitude modulation), 64QAM, 256QAM, 1025QAM, 4096QAM etc.For example according to the operator operation of transmitting apparatus 11 is set in advance any modulator approach and should be used for the quadrature modulation that quadrature modulation section 27 will carry out.Should notice that quadrature modulation section 27 can carry out some other quadrature modulation, such as 4PAM (pulse amplitude modulation).

The symbol that mapping section 26 is mapped to signaling point offers quadrature modulation section 27.

Quadrature modulation section 27 carries out quadrature modulation according to the signaling point (being mapped to the symbol of signaling point) from mapping section 26 to carrier wave, and transmits the modulation signal that obtains by quadrature modulation by communication path 13 (Fig. 7).

Referring now to Fig. 9, Fig. 9 illustrates the parity check matrix H of using in the LDPC coding that the LDPC coding section 21 by Fig. 8 carries out.

Parity check matrix H has LDGM (low-density generated matrix) structure, and can be with being derived from the information matrix H corresponding with information bit _APart and the parity matrix H corresponding with the parity bits of code in the bit of LDPC code _TExpression formula H=[H _A| H _T] expression (in this matrix, information matrix H _AElement be the element that is positioned at the left side, and parity matrix H _TElement be positioned at the right element).

At this, the amount of bits of the parity bits of code in the bit of the amount of bits of information bit and a LDPC code (code word) is called as respectively message length K and odd even length M, and the amount of bits of the code bit of a LDPD code be called as code length N (=K+M).

Message length K and odd even length M about LDPC code with certain code length N depend on encoding rate.Simultaneously, parity check matrix H is go * to classify the matrix of M * N as.So, information matrix H _AM * K matrix, and parity matrix H _TIt is M * Metzler matrix.

Figure 10 illustrates the parity matrix H of the parity check matrix H of the LDPC code of stipulating in DVB-S.2 (and DVB-T.2) standard _T

The parity matrix H of the parity check matrix H of the LDPC code of stipulating in the DVB-S.2 standard _THave step structure, its intermediate value is that 1 element is as seen in Figure 10 with stepped arrangement.Parity matrix H _TCapable weight about the first row is 1, and is 2 about all the other all row.Simultaneously, be 1 about the row weight of last row, and be 2 for all the other all row.

As mentioned above, use parity check matrix H can generate rapidly wherein parity matrix H _TLDPC code with parity check matrix H of step structure.

Particularly, LDPC code (code word) represents with the vectorial c of row, and the column vector c that obtains by this row of transposition vector ^TExpression.In addition, partly represent with the vectorial A of row as the information bit among the vectorial c of the row of LDPC code, and parity bits partly represents with the row vector T.

At this, in this case, the vectorial c of row can be with being derived from as the vectorial A of the row of information bit with as the expression formula c=[A|T of the capable vector T of parity bits] represent (in this row vector, the element of the vectorial A of row is the element that is positioned at the left side, and the element of row vector T is the element that is positioned at the right).

Parity check matrix H and as the vectorial c=[A|T of the row of LDPC code] must satisfy expression formula Hc ^T=0, parity check matrix H=[H wherein _A| H _T] parity matrix H _THas step structure as shown in Figure 10, by from expression formula Hc ^TColumn vector Hc in=0 ^TThe first row in element begin the element in the row is set to 0 in succession, can sequentially determine to form the vectorial c=[A|T of row] (satisfy expression formula Hc ^T=0) the capable vector T as parity bits.

Figure 11 illustrates the row weight stipulated in DVB-S.2 (and DVB-T.2) standard and the parity check matrix H of LDPC code.

Particularly, Figure 11 A illustrates the parity check matrix H of the LDPC code of stipulating in the DVB-S.2 standard.

For the KX from the first row of parity check matrix H row, the row weight is X; For K3 row subsequently, the row weight is 3; For M-1 row subsequently, the row weight is 2; For last row, the row weight is 1.

At this, KX+K3+M-1+1 equals code length N.

In the DVB-S.2 standard, number of columns KX, K3 and M (odd even length) and row weight X stipulate in the mode seen in Figure 11 B.

Particularly, Figure 11 B illustrates number of columns KX, K3 and M and the row weight X for the different coding rate of LDPC code that stipulates in the DVB-S.2 standard.

In the DVB-S.2 standard, stipulated that code length N is the LDPC code of 64800 bits and 16200 bits.

Seen in Figure 11 B, be the LDPC code of 64800 bits for code length N, having stipulated 1/4,1/3,2/5,1/2,3/5,2/3,3/4,4/5,5/6,8/9 and 9/10 these 11 kinds of encoding rates (specified encoding rate), is that the LDPC code of 16200 bits has then been stipulated 1/4,1/3,2/5,1/2,3/5,2/3,3/4,4/5,5/6 and 8/9 these 10 kinds of encoding rates for code length N.

For the LDPC code, the error rate that the code bit that the row of the parity check matrix H that known and row weight are higher are corresponding presents is lower.

Parity check matrix H that stipulate and that illustrate in Figure 11 has following trend in the DVB-S.2 standard: the row weight from the row of stem (left side) close to more is higher.Therefore, have following trend corresponding to the LDPC code of parity check matrix H: from the tolerance limit higher (have higher error margin) of the code bit of stem close to more to error, and lower to the tolerance limit of error from the code bit of afterbody close to more.

The layout of 16 symbols (corresponding with signaling point) in the situation of the 27 execution 16QAM of quadrature modulation section that Figure 12 illustrates at Fig. 8 on the IQ plane.

Particularly, Figure 12 A illustrates the symbol of 16QAM.

In 16QAM, 4 bits of a symbolic representation, and have 16 (=2 ⁴) individual symbol.So, 16 symbols are positioned to and make it form centered by the initial point on IQ plane the square shape of 4 * 4 symbols on I direction * Q direction.

Now, if from the highest effective ratio of the represented Bit String of symbol i+1 the bit bit y that rise abruptly _iExpression, then 16QAM 4 represented bit of symbol can be expressed as bit y according to the order that begins from the highest significant bit ₀, y ₁, y ₂And y ₃In the situation that modulator approach is 16QAM, 4 code bits of LDPC code are set up (symbolism) and are y ₀To y ₃The symbol of these 4 bits (value of symbol).

Figure 12 B illustrates about the represented y of 16QAM symbol ₀To y ₃The bit boundaries of these 4 bits (hereinafter this bit is also referred to as sign bit).

At this, about sign bit y _iThe bit boundaries of (in Figure 12, i=0,1,2,3) represents bit y _iBe 0 symbol and bit y _iIt is the border between another symbol of 1.

Seen in Figure 12 B, for 4 represented sign bit y of 16QAM symbol ₀To y ₃In the highest significant character bit y ₀, only position of the Q axle on the IQ plane becomes bit boundaries, and for second symbol bit y ₁Only position of (rising abruptly second from the highest effective ratio) I axle on the IQ plane becomes bit boundaries.

In addition, for the 3rd sign bit y ₂, between first and second row from the left side of 4 * 4 symbols and each position these two positions between the 3rd and the 4th row becomes the border.

In addition, for the 4th sign bit y ₃, between first and second row of 4 * 4 symbols and the 3rd and fourth line between each of this two positions become the border.

Along with the quantity away from the symbol of bit boundaries increases the sign bit y that symbol is represented _iRelatively be not easy to make mistakes thereby the probability of error diminishes, but along with the quantity near the symbol of bit boundaries increases the sign bit y that symbol is represented _iRelatively more may make mistakes thereby the probability of error becomes large.

The bit of (admissible error) is called as " strong bit " if relatively be not easy to make mistakes, and the bit of relatively more may make mistakes (relatively being difficult to tolerable error) is called as " weak bit ", then about the represented y of the symbol of 16QAM ₀To y ₃These 4 sign bits, the highest significant character bit y ₀With second symbol bit y ₁The strong bit of f, and the 3rd sign bit y ₂With the 4th sign bit y ₃It is weak bit.

Figure 13 illustrates in the situation that quadrature modulation section 27 at Fig. 8 carries out 64QAM 64 symbols (corresponding to signaling point) on the IQ plane to Figure 15 and arranges.

In 64QAM, 6 bits of a symbolic representation, and have 64 (=2 ⁶) individual symbol.So, 64 symbols are positioned to and make it form centered by the initial point on IQ plane the square shape of 8 * 8 symbols on I direction * Q direction.

The represented sign bit of a symbol of 64QAM can be shown bit y according to the sequence list that begins from the highest significant bit ₀, y ₁, y ₂, y ₃, y ₄And y ₅In the situation that modulator approach is 64QAM, 6 code bits of LDPC code are set up (symbolism) and are y ₀To y ₅The symbol of these 6 bits (value of symbol).

At this, Figure 13 illustrates the sign bit y about the 64QAM symbol ₀To y ₅In the highest significant character bit y ₀With second symbol bit y ₁Bit boundaries; Figure 14 illustrates about the 3rd sign bit y ₂With the 4th sign bit y ₃Bit boundaries; And Figure 15 illustrates about the 5th sign bit y ₄With the 6th sign bit y ₅Bit boundaries.

As seen in Figure 13, about the highest significant character bit y ₀With second symbol bit y ₁In each the quantity of bit boundaries be 1.Simultaneously, as seen in Figure 14, about the 3rd sign bit y ₂With the 4th sign bit y ₃In each the quantity of bit boundaries be 2, and as seen in Figure 15, about the 5th sign bit y ₄With the 6th sign bit y ₅In each the quantity of bit boundaries be 4.

Therefore, at the sign bit y of 64QAM symbol ₀To y ₅In, the highest significant character bit y ₀With second symbol bit y ₁The strongest bit, and the 3rd sign bit y ₂With the 4th sign bit y ₃It is the last the second bit.So, the 5th sign bit y ₄With the 6th sign bit y ₅It is weak bit.

From Figure 12 and further from Figure 13 to Figure 15, as seen there is following trend in the sign bit for the quadrature modulation symbol: higher order bits is strong bit, and low step bit is weak bit.

At this, described with reference to Figure 11 in as mentioned, comprise code bit and the relative yard bit that is difficult to tolerable error of admissible error from the LDPC code of LDPC coding section 21 (Fig. 8) output.

Simultaneously, described with reference to Figure 12 to 15 in as mentioned, the sign bit of the quadrature modulation symbol that quadrature modulation section 27 carries out comprises strong bit and weak bit.

Therefore, if the code bit of the lower LDPC code of the tolerance limit of error is assigned to the weak sign bit of quadrature modulation symbol, then the tolerance limit of error reduced on the whole.

Therefore, proposed to interweave, wherein the code bit of LDPC code interweaved, so that the code bit of the lower LDPC code of the tolerance limit of error is assigned to the strong bit (sign bit) of quadrature modulation symbol.

The demodulation multiplexer 25 of Fig. 8 is carried out the processing of interleaver.

Figure 16 is the figure of processing that the demodulation multiplexer 25 of Fig. 8 is shown.

Particularly, Figure 16 A illustrates the example of the functional configuration of demodulation multiplexer 25.

Demodulation multiplexer 25 comprises memory 31 and replacement section 32.

LDPC code from LDPC coding section 21 is provided for memory 31.

Memory 31 has be used to the memory capacity of storing mb bit on (level) direction of being expert at and storing the individual bit of N/ (mb) in row (vertically) direction.The code bit that memory 31 will offer its LDPC code writes column direction, and goes up in the row direction the sense code bit, then the code bit of reading is offered replacement section 32.

At this, as indicated above, the code length of N (=message length K+ odd even length M) expression LDPC code.

In addition, m indicates as the amount of bits of the code bit of the LDPC code of a symbol, and b is the positive integer of being scheduled to and is to be used for the multiplier that m multiply by integer.Demodulation multiplexer 25 is aforesaid symbol with the code bits switch (symbolism) of LDPC code, and multiplier b represents the quantity of the symbol that obtains by the performed single symbolism of demodulation multiplexer 25.

Figure 16 A illustrates the example of the configuration of demodulation multiplexer 25, and wherein modulating system is 64QAM, and the amount of bits m of code bit that therefore will become the LDPC code of a symbol is 6 bits.

In addition, in Figure 16 A, multiplier b is 1, so memory 31 has in the memory capacity of column direction * line direction for N/ (6 * 1) * (6 * 1) bit.

At this, extend and comprise that in the row direction the storage area of the memory 31 of a bit suitably is called row hereinafter at column direction.In Figure 16 A, memory 31 comprises the individual row in 6 (=6 * 1).

Demodulation multiplexer 25 (on column direction) on down direction above the row that form memory 31 begins to carry out towards right-hand column the writing of code bit of LDPC code from left-hand line.

Then, if the code bit write the bit bottom that finishes at rightmost side row, then begin to go up in the row direction take 6 bits (mb bit) as unit from the first row of all row of forming memory 31 replacement section 32 is read and offered to the code bit.

Replacement section 32 is carried out replacement Treatment: the position from 6 bits of memory 31 is replaced, and 6 bits outputs that will obtain by displacement are as 6 sign bit y of the symbol of expression 64QAM ₀, y ₁, y ₂, y ₃, y ₄And y ₅

Particularly, although mb code bit (be 6 bits at this) read from memory 31 in the row direction, if in the mb that from memory 31, a reads bit from the highest effective ratio rise abruptly i bit (i=0,1 ..., mb-1) use bit b _iExpression, 6 code bits then reading in the row direction from memory 31 can be shown bit b by the sequence list that rises abruptly from the highest effective ratio ₀, b ₁, b ₂, b ₃, b ₄And b ₅

The relation of the row weight of above describing with reference to Figure 11 is so that at bit b ₀Direction on the code bit arranged be the higher code bit of tolerance limit to error, and at bit b ₅Direction on the code bit be the lower code bit of tolerance limit to error.

Permutated bit 32 is carried out replacement Treatment: to the b from memory 31 ₀To b ₅Replace the position of these 6 code bits, so that from the b of memory 31 ₀To b ₅Can be assigned to the sign bit y of the symbol of 64QAM in these 6 code bits to the lower code bit of the tolerance limit of error ₀To y ₅In tolerance limit higher bit.

At this, to being used for the b from memory 31 ₀To b ₅6 sign bit y with a symbol it being distributed to expression 64QAM are replaced in the position of these 6 code bits ₀To y ₅Method of replacing, multiple systems has been proposed.

Figure 16 B illustrates the first method of replacing; Figure 16 C illustrates the second method of replacing; And Figure 16 D illustrates the 3rd method of replacing.

Figure 16 B (also similar among the Figure 17 that describes hereinafter) in Figure 16 D, connect bit b _iAnd y _jLine segment mean a yard bit b _iBe assigned to the sign bit y of symbol _j(be displaced to sign bit y _jThe position).

As the first method of replacing of Figure 16 B, one of three kinds of method of replacing are adopted in suggestion, and as the method for replacing of Figure 16 C, one of two kinds of method of replacing are adopted in suggestion.

As the 3rd method of replacing of Figure 16 D, advise in order six kinds of method of replacing of choice and operation.

It is that 64QAM (therefore, with similar among Figure 16, the amount of bits m of code bit that is mapped to the LDPC code of a symbol is 6) and multiplier b are example and the 4th method of replacing of the configuration of the demodulation multiplexer 25 in 2 the situation that Figure 17 illustrates in modulator approach.

When multiplier b was 2, the capacity of memory 31 storages was N/ (6 * 2) * (6 * 2) bit at column direction * line direction, and comprises the individual row in 12 (=6 * 2).

Figure 17 A illustrates the write sequence with LDPC code write memory 31.

Described with reference to Figure 16 as mentioned, demodulation multiplexer 25 (on column direction) on down direction above the row that form memory 31 begins to carry out towards right-hand column the writing of code bit of LDPC code from left-hand line.

Then, if the code bit write the bit bottom that finishes at rightmost side row, then begin to go up in the row direction take 12 bits (mb bit) as unit from the first row of all row of forming memory 31 replacement section 32 is read and offered to the code bit.

Replacement section 32 is carried out replacement Treatment: according to the 4th method of replacing the position from 12 bits of memory 31 is replaced, and will represent by 12 bit output conducts that displacement obtains 12 bits of 2 symbols (b symbol) of 64QAM, be specially 6 sign bit y of the symbol of expression 64QAM ₀, y ₁, y ₂, y ₃, y ₄And y ₅6 sign bit y with the next symbol that represents 64QAM ₀, y ₁, y ₂, y ₃, y ₄And y ₅

At this, Figure 17 B illustrates the 4th method of replacing of the replacement Treatment of being undertaken by the replacement section 32 of Figure 17 A.

It should be noted that when multiplier b is 2 (also similar when multiplier is equal to or greater than 3), in replacement Treatment, mb code bit is assigned to mb sign bit of b continuous symbol.In the description subsequently that comprises with reference to the description of Figure 17, for convenience of description, i+1 the bit that rise abruptly of the highest effective ratio from mb sign bit of b continuous symbol is represented as bit (sign bit) y _i

In addition, which kind of method of replacing is optimum, and namely which kind of method of replacing provides improved error rate and not equal with encoding rate, code length and the modulator approach of LDPC code in the AWGN communication path.

To Figure 20 the odd-even that the odd-even device 23 by Fig. 8 carries out is described referring now to Figure 18.

Figure 18 illustrates Tan Na (Tanner) figure (a part) of the parity matrix of LDPC code.

Suffer simultaneously such as the error of wiping if be connected to as shown in figure 18 a plurality of variable nodes (corresponding to the code bit) (such as 2 variable nodes) of check-node, then to return the expression value to all variable nodes that are connected to this check-node may be that 0 probability and value may be the message of the equal probability that is equal to each other of 1 probability to check-node.Therefore, be set to simultaneously erase status etc. if be connected to a plurality of variable nodes of same parity node, then the degradation of decoding.

For example, be the IRA code from LDPC coding section 21 outputs of Fig. 8 and by the LDPC code of stipulating the DVB-S.2 standard, and the parity matrix H of parity check matrix H _THas step structure as shown in figure 10.

Figure 19 illustrates the parity matrix H with step structure _TWith corresponding to this parity matrix H _TTanner figure.

Particularly, Figure 19 A illustrates the parity matrix H with step structure _T, and Figure 19 B illustrates the parity matrix H corresponding to Figure 19 A _TTanner figure.

As parity matrix H _TWhen having step structure, at this parity matrix H _TTanner figure in, the variable node of LDPC code is connected to the same parity node, described variable node and value are 1 parity matrix H _TCorresponding and its message of element column be to use an adjacent code bit (parity bits) to determine.

Therefore, if the error that above-mentioned adjacent parity bits is happened suddenly, wipe etc. is set to error state, then because the check-node that is connected to a plurality of variable nodes corresponding with a plurality of parity bits of having made mistakes (variable node that its message will be determined with parity bits) returns the message of the equal probability that the expression value may may may be equal to each other for 1 probability for 0 probability and value, the degradation of therefore decoding to the variable node that is connected to this check-node.So, when burst length (because quantity of the bit that burst makes mistakes) is very large, the further variation of the performance of decoding.

Therefore, in order to prevent the variation of above-mentioned decoding performance, odd-even device 23 (Fig. 8) carries out the parity bits from the LDPC code of LDPC coding section 21 is interweaved interweaving to the position of other parity bits.

Figure 20 illustrates after the odd-even device 23 of Fig. 8 interweaves the parity matrix H corresponding to the parity check matrix H of LDPC code _T

At this, corresponding to regulation in the DVB-S.2 standard and from the information matrix H of the parity check matrix H of the LDPC code of LDPC coding section 21 output _AHas loop structure.

Loop structure refers to the structure of closing with other column weight under certain state that is listed in cycling, and for example comprise following structure: in this structure, for every P row, the position of the value 1 in the row of P row with the first row in this P the row is shifted certain value and the position that arrives overlaps in the column direction cocycle, described certain value and increase pro rata by the value q divided by the acquisition of odd even length M.Hereinafter, the quantity of P row suitably is called the unit number of columns of loop structure hereinafter in the loop structure.

As regulation in the DVB-S.2 standard and from the LDPC code of LDPC coding section 21 output, can use in comprising as mentioned with reference to the described code length N of Figure 11 is two kinds of LDPC codes of 64800 bits and 16200 bits.

Now, code length N is the LDPC code of 64800 bits in two kinds of different LDPC codes that code length N is 64800 bits and 16200 bits if pay close attention to, and then can be used as the encoding rate that code length N is the LDPC code of 64800 bits with reference to described 11 the different encoding rates of Figure 11 in as mentioned.

Be 64800 bits and the LDPC code with 11 different encoding rates for code length N, in the DVB-S.2 standard, stipulate: the number of columns P of loop structure be defined as be the odd even length M a divisor (except 1 and M) 360.

In addition, be 64800 and LDPC code with 11 different coding rates for code length N, the odd even length M has the value that is not prime number and the expression formula M=q by using the different value q with encoding rate * P=q * 360 expressions.Therefore, be similar to the number of columns P of loop structure, value q be equally the odd even length M except 1 and M a divisor, and be (be odd even length M as the P of the divisor of odd even length M and the product of q) that obtains divided by the number of columns P of loop structure by the odd even length M.

When message length represents with K, and greater than 0 but represent with x and when representing with y greater than 0 but less than the integer of q less than the integer of P, odd-even device 23 with K+qx+y+1 in parity bits code Bit Interleave to the position of K+Py+x+1 code bit as odd-even, described parity bits is individual to the individual bit of K+M (K+M=N) from the K+1 of the LDPC code of LDPC coding section 21.

According to this odd-even, owing to being connected to the distance of the spaced number of columns P corresponding to loop structure of the variable node (corresponding to parity bits) of same parity node, at this, can prevent from being connected to the situation that a plurality of variable nodes of same parity node are made mistakes simultaneously by burst length less than 360 bits of 360 bits.As a result, can improve tolerance limit to burst error.

Should note by the LDPC code of K+qx+y+1 code Bit Interleave after the odd-even of position of K+Py+x+1 code bit overlapped with the LDPC code of parity matrix (be also referred to as hereinafter and change parity matrix) by column permutation acquisition that the K+qx+y+1 column permutation of original parity check matrix H is listed as to K+Py+x+1.

In addition, in the parity matrix of conversion parity matrix, as seen in Figure 20, unit having occurred is the quasi-cyclic of P row (being 360 row among Figure 20).

At this, the part that quasi-cyclic refers to except a part has the structure of loop structure.By using in the conversion parity matrix that the column permutation corresponding with the parity matrix of the LDPC code the stipulated odd-even of carrying out among the DVB-S.2 obtain, it is 1 element (being that its value is 0) that the part (shift matrix described below) that 360 row * 360 are listed as partly lacks one in right corner.Therefore, the conversion parity matrix does not have (complete) loop structure and has quasi-cyclic.

The conversion parity matrix that should note Figure 20 is following matrix: wherein except the column permutation corresponding to odd-even, also original parity check matrix H is used the displacement (line replacement) of row, described line replacement is used for from configuring matrix configuration transitions parity matrix described below.

Describe as reversed row that rearrangement that interleaver 24 carries out processes by the row of Fig. 8 to Figure 24 now with reference to Figure 21 and to reverse and interweave.

In the transmitting apparatus 11 of Fig. 8, as indicated above, two or more yards bit of LDPC code is used as a symbol and transmits to put forward high-frequency utilization ratio.Particularly, for example, when 2 bits that use the code bit form a symbol, for example adopt QPSK as modulator approach, but when using 4 bits to form a symbol, for example adopt 16QAM as modulator approach.

When in this way two or more yards bit being transmitted as symbol, if certain symbol has occurred wiping etc., all yards bit of this symbol all make mistakes (wiping) then.

Therefore, in order to reduce probability that a plurality of variable nodes (corresponding to the code bit) of being connected to the same parity node may be wiped simultaneously to improve decoding performance, need to avoid being connected to the same parity node corresponding to the variable node of the code bit of a symbol.

Simultaneously, regulation and from the parity check matrix H of the LDPC code of LDPC coding section 21 output in pressing the DVB-S.2 standard, as indicated above, information matrix H _AHas loop structure, parity matrix H _THas hierarchic structure.So, in conversion parity matrix (parity matrix of the LDPC code after being odd-even), loop structure (saying exactly, is quasi-cyclic as indicated above) also occurs in parity matrix as shown in Figure 20.

Figure 21 illustrates the conversion parity matrix.

Particularly, to illustrate code length N be that 64800 bits and encoding rate are the conversion parity matrix of 3/4 parity check matrix H to Figure 21 A.

In Figure 21 A, indicate the position that conversion parity matrix intermediate value is 1 element with point ().

In Figure 21 B, demodulation multiplexer 25 (Fig. 8) is processed the LDPC code (being odd-even LDPC code afterwards) of the conversion parity matrix of Figure 21 A.

In Figure 21 B, the code bit of the LDPC code after the odd-even is write 4 row at column direction, described 4 row form and use 16QAM as the memory 31 of the demodulation multiplexer 25 of modulator approach.

To read in the row direction take 4 bits that form a symbol as unit at the code bit that column direction writes in 4 row that form memory 31.

In this case, form 4 bit B of a symbol ₀, B ₁, B ₂And B ₃Sometimes form corresponding to the code bit in any delegation of the parity matrix after 1 and the conversion that be included in Figure 21 A, in kind of situation, corresponding to code bit B ₀, B ₁, B ₂And B ₃Variable node be connected to the same parity node.

Therefore, as 4 code bit B of a symbol ₀, B ₁, B ₂And B ₃Become corresponding to 1 and be included in code in any delegation during bit, if symbol wipe, then corresponding to code bit B ₀, B ₁, B ₂And B ₃The same parity node that is connected to of variable node can not determine suitable message.As a result, decoding performance variation.

Similarly, for the encoding rate that is different from encoding rate 3/4, sometimes form similarly the symbol of 16QAM corresponding to a plurality of yards bits of a plurality of variable nodes that are connected to the same parity node.

Therefore, row reverse interleaver 24 and are listed as to reverse and interweave, wherein, the code bit from the LPDC code after the odd-even of odd-even device 23 is interweaved so that corresponding to 1 and be included in any delegation of conversion parity matrix a plurality of yards bits be not included in the symbol.

Figure 22 illustrates to fall out to reverse the figure that interweaves.

Particularly, Figure 22 illustrates the memory 31 (Figure 16 and 17) of demodulation multiplexer 25.

As shown in Figure 16, memory 31 has in row (vertically) direction stores the individual bit of N/ (mb) and the memory capacity of mb the bit of (level) direction storage of being expert at, and comprises mb row.So, when the code bit was read in the row direction, row reversed interleaver 24 and on column direction code bit write memory 31 and the control of LDPC code are write the starting position, interweave to be listed as to reverse.

Particularly, row reverse interleaver 24 suitably change in a plurality of row each write starting position (writing the starting position is the position that will begin to write yard bit), so that read in the row direction and be used for forming a plurality of yards bits of a symbol can not become corresponding to 1 and be included in code bit in any delegation of conversion parity matrix (the code bit of rearrangement LDPC code so that corresponding to 1 and a plurality of yards bits being included in any delegation of parity matrix can not be included in the prosign).

At this, Figure 22 illustrates the example of the configuration of memory 31, and wherein, modulator approach is 16QAM, and the multiplier b that describes with reference to Figure 16 hereinbefore in addition is 1.Therefore, the amount of bits m of code bit that will become the LDPC code of a symbol is 4 bits, and memory 31 by 4 (=mb) individual row form.

Row reverse interleaver 24 (rather than demodulation multiplexer shown in Figure 16 25) carry out the upper code bit with the LDPC code of from the top down direction (column direction) write form memory 31 begin 4 row towards right-hand column from left-hand line.

Then, when writing of code ended at the row of the rightmost side, row reverse interleaver 24 from the first row of all row of forming memory 31, go up in the row direction, read bit code take 4 bits (mb bit) as unit, and the output code bit reverses the replacement section 32 (Figure 16 and Figure 17) of LDPC code afterwards to demodulation multiplexer 25 that interweave as row.

Yet, if the address of the stem of each row (topmost) position represents with 0 and the address of the position on column direction with the integer representation of ascending order, row reverse the starting position that writes of interleaver 24 leftmost column, and to be set to the address be 0 position; To be set to the address be 2 position in the starting position that writes of secondary series (from left to right); Tertially write the starting position to be set to the address be 4 position; And to be set to the address be 7 position in the starting position that writes of the 4th row.

Should note, for writing the row that the starting position is any other position except the address is 0 position, after the code bit was written into lowest positions, writing position mortgage originator (address is 0 position) also carried out writing the last position that and then writes the starting position.Then, carry out writing next (its right side) row.

Reverse and interweave by carrying out above-mentioned this row, it is the LDPC code of all encoding rates of 64800 for the code length N that stipulates in the DVB-S.2 standard, can prevent from forming corresponding to a plurality of yards bits of a plurality of variable nodes that are connected to the same parity node situation of the symbol (being included in the prosign) of 16QAM, as a result, can improve the decoding performance that can produce in the communication path of wiping.

Figure 23 illustrates: be the LDPC code of 11 kinds of different coding rates of 64800 about the code length N that stipulates in the DVB-S.2 standard, for every kind of modulator approach, row reverse the quantity of row of the essential memory 31 that interweaves and the address that writes the starting position.

When multiplier b is 1, in addition owing to for example adopting QPSK as modulator approach, therefore the amount of bits m of a symbol is 2 bits, according to Figure 23, memory 31 has two row, is used in the row direction upper storage 2 * 1 (=mb) individual bit and at the individual bit in column direction storage 64800/ (2 * 1).

So, to be set to the address be 0 position in the starting position that writes of the first row in two row of memory 31, and to be set to the address be 2 position in the starting position that writes of secondary series.

When for example it should be noted that one of first to the 3rd method of replacing in adopting Figure 16 as the method for replacing of the replacement Treatment of demodulation multiplexer 25 (Fig. 8) or under analogue, multiplier b is 1.

When multiplier b is 2, owing to for example adopting QPSK as modulator approach, therefore the amount of bits m of a symbol is 2 bits, according to Figure 23 in addition, memory 31 has 4 row, is used for upward storing in the row direction 2 * 2 bits and storing the individual bit in 64800/ (2 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 4 row of memory 31, to be set to the address be 2 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 4 position, and to be set to the address be 7 position in the starting position that writes of the 4th row.

For example it should be noted that multiplier b is 2 when the 4th method of replacing that adopts Figure 17 during as the method for replacing of the replacement Treatment of demodulation multiplexer 25 (Fig. 8).

When multiplier b is 1, in addition owing to for example adopting 16QAM as modulator approach, therefore the amount of bits m of a symbol is 4 bits, according to Figure 23, memory 31 has 4 row, is used for upward storing in the row direction 4 * 1 bits and storing the individual bit in 64800/ (4 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 4 row of memory 31, to be set to the address be 2 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 4 position, and to be set to the address be 7 position in the starting position that writes of the 4th row.

When multiplier b is 2, in addition owing to for example adopting 16QAM as modulator approach, therefore the amount of bits m of a symbol is 4 bits, according to Figure 23, memory 31 has 8 row, is used for upward storing in the row direction 4 * 2 bits and storing the individual bit in 64800/ (4 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 8 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 2 position, to be set to the address be 4 position in the starting position that writes of the 4th row, to be set to the address be 4 position in the starting position that writes of the 5th row, to be set to the address be 5 position in the starting position that writes of the 6th row, to be set to the address be 7 position in the starting position that writes of the 7th row, and to be set to the address be 7 position in the starting position that writes of the 8th row.

When multiplier b is 1, in addition owing to for example adopting 64QAM as modulator approach, therefore the amount of bits m of a symbol is 6 bits, according to Figure 23, memory 31 has 6 row, is used for upward storing in the row direction 6 * 1 bits and storing the individual bit in 64800/ (6 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 6 row of memory 31, to be set to the address be 2 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 5 position, to be set to the address be 9 position in the starting position that writes of the 4th row, to be set to the address be 10 position in the starting position that writes of the 5th row, and to be set to the address be 13 position in the starting position that writes of the 6th row.

When multiplier b is 2, in addition owing to for example adopting 64QAM as modulator approach, therefore the amount of bits m of a symbol is 6 bits, according to Figure 23, memory 31 has 12 row, is used for upward storing in the row direction 6 * 2 bits and storing the individual bit in 64800/ (6 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 12 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 2 position, to be set to the address be 2 position in the starting position that writes of the 4th row, to be set to the address be 3 position in the starting position that writes of the 5th row, to be set to the address be 4 position in the starting position that writes of the 6th row, to be set to the address be 4 position in the starting position that writes of the 7th row, to be set to the address be 5 position in the starting position that writes of the 8th row, to be set to the address be 5 position in the starting position that writes of the 9th row, to be set to the address be 7 position in the starting position that writes of the tenth row, to be set to the address be 8 position in the starting position that writes of the 11 row, and to be set to the address be 9 position in the starting position that writes of the 12 row.

When multiplier b is 1, in addition owing to for example adopting 256QAM as modulator approach, therefore the amount of bits m of a symbol is 8 bits, according to Figure 23, memory 31 has 8 row, is used for upward storing in the row direction 8 * 1 bits and storing the individual bit in 64800/ (8 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 8 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 2 position, to be set to the address be 4 position in the starting position that writes of the 4th row, to be set to the address be 4 position in the starting position that writes of the 5th row, to be set to the address be 5 position in the starting position that writes of the 6th row, to be set to the address be 7 position in the starting position that writes of the 7th row, and to be set to the address be 7 position in the starting position that writes of the 8th row.

When multiplier b is 2, in addition owing to for example adopting 256QAM as modulator approach, therefore the amount of bits m of a symbol is 8 bits, according to Figure 23, memory 31 has 16 row, is used for upward storing in the row direction 8 * 2 bits and storing the individual bit in 64800/ (8 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 16 row of memory 31, to be set to the address be 2 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 2 position, to be set to the address be 2 position in the starting position that writes of the 4th row, to be set to the address be 2 position in the starting position that writes of the 5th row, to be set to the address be 3 position in the starting position that writes of the 6th row, to be set to the address be 7 position in the starting position that writes of the 7th row, to be set to the address be 15 position in the starting position that writes of the 8th row, to be set to the address be 16 position in the starting position that writes of the 9th row, to be set to the address be 20 position in the starting position that writes of the tenth row, to be set to the address be 22 position in the starting position that writes of the 11 row, and to be set to the address be 22 position in the starting position that writes of the 12 row, to be set to the address be 27 position in the starting position that writes of the 13 row, to be set to the address be 27 position in the starting position that writes of the 14 row, to be set to the address be 28 position in the starting position that writes of the 15 row, and to be set to the address be 32 position in the starting position that writes of the 16 row.

When multiplier b is 1, in addition owing to for example adopting 1024QAM as modulator approach, therefore the amount of bits m of a symbol is 10 bits, according to Figure 23, memory 31 has 10 row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 64800/ (10 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 10 row of memory 31, to be set to the address be 3 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 6 position, to be set to the address be 8 position in the starting position that writes of the 4th row, to be set to the address be 11 position in the starting position that writes of the 5th row, to be set to the address be 13 position in the starting position that writes of the 6th row, to be set to the address be 15 position in the starting position that writes of the 7th row, to be set to the address be 17 position in the starting position that writes of the 8th row, to be set to the address be 18 position in the starting position that writes of the 9th row, and to be set to the address be 20 position in the starting position that writes of the tenth row.

When multiplier b is 2, in addition owing to for example adopting 1024QAM as modulator approach, therefore the amount of bits m of a symbol is 10 bits, according to Figure 23, memory 31 has 20 row, is used for upward storing in the row direction 10 * 2 bits and storing the individual bit in 64800/ (10 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 20 row of memory 31, to be set to the address be 1 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 3 position, to be set to the address be 4 position in the starting position that writes of the 4th row, to be set to the address be 5 position in the starting position that writes of the 5th row, to be set to the address be 6 position in the starting position that writes of the 6th row, to be set to the address be 6 position in the starting position that writes of the 7th row, to be set to the address be 9 position in the starting position that writes of the 8th row, to be set to the address be 13 position in the starting position that writes of the 9th row, to be set to the address be 14 position in the starting position that writes of the tenth row, to be set to the address be 14 position in the starting position that writes of the 11 row, to be set to the address be 16 position in the starting position that writes of the 12 row, to be set to the address be 21 position in the starting position that writes of the 13 row, to be set to the address be 21 position in the starting position that writes of the 14 row, to be set to the address be 23 position in the starting position that writes of the 15 row, to be set to the address be 25 position in the starting position that writes of the 16 row, to be set to the address be 25 position in the starting position that writes of the 17 row, to be set to the address be 26 position in the starting position that writes of the 18 row, to be set to the address be 28 position in the starting position that writes of the 19 row, and to be set to the address be 30 position in the starting position that writes of the 20 row.

When multiplier b is 1, in addition owing to for example adopting 4096QAM as modulator approach, therefore the amount of bits m of a symbol is 12 bits, according to Figure 23, memory 31 has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 64800/ (12 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 12 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 2 position, to be set to the address be 2 position in the starting position that writes of the 4th row, to be set to the address be 3 position in the starting position that writes of the 5th row, to be set to the address be 4 position in the starting position that writes of the 6th row, to be set to the address be 4 position in the starting position that writes of the 7th row, to be set to the address be 5 position in the starting position that writes of the 8th row, to be set to the address be 5 position in the starting position that writes of the 9th row, to be set to the address be 7 position in the starting position that writes of the tenth row, the 11 row write the position that the starting position is set to address 8, and to be set to the address be 9 position in the starting position that writes of the 12 row.

When multiplier b is 2, in addition owing to for example adopting 4096QAM as modulator approach, therefore the amount of bits m of a symbol is 12 bits, according to Figure 23, memory 31 has 24 row, is used for upward storing in the row direction 12 * 2 bits and storing the individual bit in 64800/ (12 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 24 row of memory 31, to be set to the address be 5 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 8 position, to be set to the address be 8 position in the starting position that writes of the 4th row, to be set to the address be 8 position in the starting position that writes of the 5th row, to be set to the address be 8 position in the starting position that writes of the 6th row, to be set to the address be 10 position in the starting position that writes of the 7th row, to be set to the address be 10 position in the starting position that writes of the 8th row, to be set to the address be 10 position in the starting position that writes of the 9th row, to be set to the address be 12 position in the starting position that writes of the tenth row, to be set to the address be 13 position in the starting position that writes of the 11 row, to be set to the address be 16 position in the starting position that writes of the 12 row, to be set to the address be 17 position in the starting position that writes of the 13 row, to be set to the address be 19 position in the starting position that writes of the 14 row, to be set to the address be 21 position in the starting position that writes of the 15 row, to be set to the address be 22 position in the starting position that writes of the 16 row, to be set to the address be 23 position in the starting position that writes of the 17 row, to be set to the address be 26 position in the starting position that writes of the 18 row, to be set to the address be 37 position in the starting position that writes of the 19 row, to be set to the address be 39 position in the starting position that writes of the 20 row, to be set to the address be 40 position in the starting position that writes of the 21 row, to be set to the address be 41 position in the starting position that writes of the 22 row, to be set to the address be 41 position in the starting position that writes of the 23 row, and to be set to the address be 41 position in the starting position that writes of the 24 row.

Figure 24 illustrates: be the LDPC code of 10 kinds of different coding rates of 16200 about the code length N that stipulates in the DVB-S.2 standard, for every kind of modulator approach, row reverse the quantity of row of the essential memory 31 that interweaves and the address that writes the starting position.

When multiplier b is 1, owing to for example adopting QPSK as modulator approach, therefore the amount of bits m of a symbol is 2 bits, according to Figure 24 in addition, memory 31 has 2 row, is used for upward storing in the row direction 2 * 1 bits and storing the individual bit in 16200/ (2 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in two row of memory 31, and to be set to the address be 0 position in the starting position that writes of secondary series.

When multiplier b is 2, owing to for example adopting QPSK as modulator approach, therefore the amount of bits m of a symbol is 2 bits, according to Figure 24 in addition, memory 31 has 4 row, is used for upward storing in the row direction 2 * 2 bits and storing the individual bit in 16200/ (2 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 4 row of memory 31, to be set to the address be 2 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 3 position, and to be set to the address be 3 position in the starting position that writes of the 4th row.

When multiplier b is 1, in addition owing to for example adopting 16QAM as modulator approach, therefore the amount of bits m of a symbol is 4 bits, according to Figure 24, memory 31 has 4 row, is used for upward storing in the row direction 4 * 1 bits and storing the individual bit in 16200/ (4 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 4 row of memory 31, to be set to the address be 2 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 3 position, and to be set to the address be 3 position in the starting position that writes of the 4th row.

When multiplier b is 2, in addition owing to for example adopting 16QAM as modulator approach, therefore the amount of bits m of a symbol is 4 bits, according to Figure 24, memory 31 has 8 row, is used for upward storing in the row direction 4 * 2 bits and storing the individual bit in 16200/ (4 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 8 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 0 position, to be set to the address be 1 position in the starting position that writes of the 4th row, to be set to the address be 7 position in the starting position that writes of the 5th row, to be set to the address be 20 position in the starting position that writes of the 6th row, to be set to the address be 20 position in the starting position that writes of the 7th row, and to be set to the address be 21 position in the starting position that writes of the 8th row.

When multiplier b is 1, in addition owing to for example adopting 64QAM as modulator approach, therefore the amount of bits m of a symbol is 6 bits, according to Figure 24, memory 31 has 6 row, is used for upward storing in the row direction 6 * 1 bits and storing the individual bit in 16200/ (6 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 6 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 2 position, to be set to the address be 3 position in the starting position that writes of the 4th row, to be set to the address be 7 position in the starting position that writes of the 5th row, and to be set to the address be 7 position in the starting position that writes of the 6th row.

When multiplier b is 2, in addition owing to for example adopting 64QAM as modulator approach, therefore the amount of bits m of a symbol is 6 bits, according to Figure 24, memory 31 has 12 row, is used for upward storing in the row direction 6 * 2 bits and storing the individual bit in 16200/ (6 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 12 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 0 position, to be set to the address be 2 position in the starting position that writes of the 4th row, to be set to the address be 2 position in the starting position that writes of the 5th row, to be set to the address be 2 position in the starting position that writes of the 6th row, to be set to the address be 3 position in the starting position that writes of the 7th row, to be set to the address be 3 position in the starting position that writes of the 8th row, to be set to the address be 3 position in the starting position that writes of the 9th row, to be set to the address be 6 position in the starting position that writes of the tenth row, to be set to the address be 7 position in the starting position that writes of the 11 row, and to be set to the address be 7 position in the starting position that writes of the 12 row.

When multiplier b is 1, in addition owing to for example adopting 256QAM as modulator approach, therefore the amount of bits m of a symbol is 8 bits, according to Figure 24, memory 31 has 8 row, is used for upward storing in the row direction 8 * 1 bits and storing the individual bit in 16200/ (8 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 8 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 0 position, to be set to the address be 1 position in the starting position that writes of the 4th row, to be set to the address be 7 position in the starting position that writes of the 5th row, to be set to the address be 20 position in the starting position that writes of the 6th row, to be set to the address be 20 position in the starting position that writes of the 7th row, and to be set to the address be 21 position in the starting position that writes of the 8th row.

When multiplier b is 1, in addition owing to for example adopting 1024QAM as modulator approach, therefore the amount of bits m of a symbol is 10 bits, according to Figure 24, memory 31 has 10 row, is used for upward storing in the row direction 10 * 1 bits and storing the individual bit in 16200/ (10 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 10 row of memory 31, to be set to the address be 1 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 2 position, to be set to the address be 2 position in the starting position that writes of the 4th row, to be set to the address be 3 position in the starting position that writes of the 5th row, to be set to the address be 3 position in the starting position that writes of the 6th row, to be set to the address be 4 position in the starting position that writes of the 7th row, to be set to the address be 4 position in the starting position that writes of the 8th row, to be set to the address be 5 position in the starting position that writes of the 9th row, and to be set to the address be 7 position in the starting position that writes of the tenth row.

When multiplier b is 2, in addition owing to for example adopting 1024QAM as modulator approach, therefore the amount of bits m of a symbol is 10 bits, according to Figure 24, memory 31 has 20 row, is used for upward storing in the row direction 10 * 2 bits and storing the individual bit in 16200/ (10 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 20 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 0 position, to be set to the address be 2 position in the starting position that writes of the 4th row, to be set to the address be 2 position in the starting position that writes of the 5th row, to be set to the address be 2 position in the starting position that writes of the 6th row, to be set to the address be 2 position in the starting position that writes of the 7th row, to be set to the address be 2 position in the starting position that writes of the 8th row, to be set to the address be 5 position in the starting position that writes of the 9th row, to be set to the address be 5 position in the starting position that writes of the tenth row, to be set to the address be 5 position in the starting position that writes of the 11 row, to be set to the address be 5 position in the starting position that writes of the 12 row, to be set to the address be 5 position in the starting position that writes of the 13 row, to be set to the address be 7 position in the starting position that writes of the 14 row, to be set to the address be 7 position in the starting position that writes of the 15 row, to be set to the address be 7 position in the starting position that writes of the 16 row, to be set to the address be 7 position in the starting position that writes of the 17 row, to be set to the address be 8 position in the starting position that writes of the 18 row, to be set to the address be 8 position in the starting position that writes of the 19 row, and to be set to the address be 10 position in the starting position that writes of the 20 row.

When multiplier b is 1, in addition owing to for example adopting 4096QAM as modulator approach, therefore the amount of bits m of a symbol is 12 bits, according to Figure 24, memory 31 has 12 row, is used for upward storing in the row direction 12 * 1 bits and storing the individual bit in 16200/ (12 * 1) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 12 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 0 position, to be set to the address be 2 position in the starting position that writes of the 4th row, to be set to the address be 2 position in the starting position that writes of the 5th row, to be set to the address be 2 position in the starting position that writes of the 6th row, to be set to the address be 3 position in the starting position that writes of the 7th row, to be set to the address be 3 position in the starting position that writes of the 8th row, to be set to the address be 3 position in the starting position that writes of the 9th row, to be set to the address be 6 position in the starting position that writes of the tenth row, the 11 row write the position that the starting position is set to address 7, and to be set to the address be 7 position in the starting position that writes of the 12 row.

When multiplier b is 2, in addition owing to for example adopting 4096QAM as modulator approach, therefore the amount of bits m of a symbol is 12 bits, according to Figure 24, memory 31 has 24 row, is used for upward storing in the row direction 12 * 2 bits and storing the individual bit in 16200/ (12 * 2) at column direction.

So, to be set to the address be 0 position in the starting position that writes of the first row in 24 row of memory 31, to be set to the address be 0 position in the starting position that writes of secondary series, tertially write the starting position to be set to the address be 0 position, to be set to the address be 0 position in the starting position that writes of the 4th row, to be set to the address be 0 position in the starting position that writes of the 5th row, to be set to the address be 0 position in the starting position that writes of the 6th row, to be set to the address be 0 position in the starting position that writes of the 7th row, to be set to the address be 1 position in the starting position that writes of the 8th row, to be set to the address be 1 position in the starting position that writes of the 9th row, to be set to the address be 1 position in the starting position that writes of the tenth row, to be set to the address be 2 position in the starting position that writes of the 11 row, to be set to the address be 2 position in the starting position that writes of the 12 row, to be set to the address be 2 position in the starting position that writes of the 13 row, to be set to the address be 3 position in the starting position that writes of the 14 row, to be set to the address be 7 position in the starting position that writes of the 15 row, to be set to the address be 9 position in the starting position that writes of the 16 row, to be set to the address be 9 position in the starting position that writes of the 17 row, to be set to the address be 9 position in the starting position that writes of the 18 row, to be set to the address be 10 position in the starting position that writes of the 19 row, to be set to the address be 10 position in the starting position that writes of the 20 row, to be set to the address be 10 position in the starting position that writes of the 21 row, to be set to the address be 10 position in the starting position that writes of the 22 row, to be set to the address be 10 position in the starting position that writes of the 23 row, and to be set to the address be 11 position in the starting position that writes of the 24 row.

Now, the transmission of carrying out with reference to the transmitting apparatus 11 of flow chart description Fig. 8 of Figure 25 is processed.

LDPC coding section 21 waits for and offers its object data, and this object data is encoded to the LDPC code in step S101 and provides this LDPC code to bit interleaver 22.Afterwards, processing enters step S102.

At step S102,22 pairs of LDPC codes from LDPC coding section 21 of bit interleaver carry out Bit Interleave, and provide symbol to the LDPC code sign after interweaving to mapping section 26.Afterwards, processing enters step S103.

Particularly, at step S102,23 pairs of LDPC codes from LDPC coding section 21 of the odd-even device in the bit interleaver 22 carry out odd-even, and the LDPC code after the odd-even is offered row reverse interleaver 24.

Row reverse 24 pairs of LDPC codes from odd-even device 23 of interleaver and are listed as to reverse and interweave, and the result who provides row to reverse to interweave is to demodulation multiplexer 25.

Demodulation multiplexer 25 carries out being listed as reverse interleaver 24 by row the replacement Treatment that the code bit of the LDPC code that reverses after interweaving is replaced, and the code bits switch after will replace is the sign bit (bit that represents symbol) of symbol.

At this, the replacement Treatment of being undertaken by demodulation multiplexer 25 can be carried out according to the first to the 4th method of replacing of describing with reference to Figure 16 and Figure 17 hereinbefore, and can also carry out according to allocation rule in addition.Allocation rule is for the code Bit Allocation in Discrete of the LDPC code rule to the sign bit of expression symbol, and the details of allocation rule will be described below.

The symbol that obtains by the replacement Treatment of being undertaken by demodulation multiplexer 25 is offered mapping section 26 from demodulation multiplexer 25.

At step S103, the signaling point that mapping section 26 will limit to the modulator approach of the quadrature modulation of being undertaken by quadrature modulation section 27 from the sign map of demodulation multiplexer 25, and the symbol of mapping offered quadrature modulation section 27.Then, processing enters step S104.

At step S104, quadrature modulation section 27 is according to the quadrature modulation of carrying out carrier wave from the signaling point of mapping section 26.Then, process entering step S105, at the modulation signal of step S105 transmission as the result's of quadrature modulation acquisition, afterwards processing finishes.

Should notice that the transmission approach repeatedly carries out the transmission processing of Figure 25.

Reverse and interweave by carrying out aforesaid odd-even and row, in the time of can improving a plurality of yards bits at the LDPC code and be used as a symbol and transmit to wiping or the tolerance limit of burst error.

At this, although in Fig. 8, for convenience of description, reverse piece that the row that interweave reverse interleaver 24 and be configured to separated from one anotherly as the odd-even device 23 of the piece that is used for carrying out odd-even with as being used for being listed as, can also be configured to be integrated with each other but odd-even device 23 and row reverse interleaver 24.

Particularly, odd-even and row reverse that interweave can both be by carrying out with code bit write memory with from memory sense code bit, and can the matrix of the address of sense code bit (reading the address) represents by being used for being converted to therefrom to its address (writing address) that writes yard bit.

Therefore, reverse the matrix that matrix was obtained that interweaves if pre-determined the Matrix Multiplication of expression odd-even with the expression row, if this matrix is used for the hand over word bit so, then can obtain to follow the LDPC code after the odd-even is listed as the result who reverses when interweaving when carrying out odd-even.

In addition, except odd-even device 23 and row reverse the interleaver 24, demodulation multiplexer 25 also can be configured to integrated.

Particularly, demodulation multiplexer 25 replacement Treatment of carrying out also can be converted to the matrix notation of reading the address by the writing address of the memory 31 that is used for storing the LDPC code.

Therefore, if pre-determined the matrix that matrix multiple that matrix, another expression row by the expression odd-even reverse the matrix that interweaves and another expression replacement Treatment obtains, then odd-even, row reverse and interweave and replacement Treatment can be carried out together by determined matrix.

Should note only carrying out odd-even and row reverses a kind of in interweaving or two kinds and does not carry out.

Now, with reference to Figure 26 to Figure 28 describe for measure error rate (bit error rate) to the transmitting apparatus 11 of Fig. 8 carry out emulation.

Emulation is to adopt the communication path with flutter that D/U is 0dB (flutter) to carry out.

Figure 26 illustrates the model of the communication path that adopts in the emulation.

Particularly, Figure 26 A illustrates the model of the flutter of adopting in the emulation.

Simultaneously, Figure 26 B illustrates the model that has by the communication path of the flutter of the model representation of Figure 26 A.

It should be noted that in Figure 26 B the model of the flutter of H presentation graphs 26A.In addition, in Figure 26 B, N represents ICI (inter-carrier interference), and in emulation, the desired value E[N of power ²] be similar to AWGN.

Figure 27 and Figure 28 illustrate by the error rate of emulation acquisition and the Doppler frequency f of flutter _dBetween relation.

Should notice that it is 16QAM that Figure 27 illustrates in modulator approach, encoding rate (r) is (3/4), and method of replacing is error rate and Doppler frequency f in the situation of the first method of replacing in addition _dBetween relation.Simultaneously, it is 64QAM that Figure 28 illustrates in modulator approach, and encoding rate (r) is (5/6), and method of replacing is error rate and Doppler frequency f in the situation of the first method of replacing in addition _dBetween relation.

In addition, in Figure 27 and Figure 28, bold curve be illustrated in odd-even, row reverse interweave and situation that replacement Treatment all is performed under error rate and Doppler frequency f _dBetween relation, and thin curve table be shown in odd-even, row reverse interweave and replacement Treatment in only have error rate and Doppler frequency f in the situation that replacement Treatment is performed _dBetween relation.

In Figure 27 and 28, can find out in the situation that odd-even, row reverse interweave the error rate that all is carried out with replacement Treatment with compare be improved (reduction) in the situation that only carry out the error rate of replacement Treatment.

To further describe now the LDPC coding section 21 of Fig. 8.

As described in reference Figure 11, in the DVB-S.2 standard, stipulated the LDPC coding of 64800 bits and these two kinds of different code length N of 16200 bits.

In addition, be the LDPC code of 64800 bits for code length N, 11 kinds of encoding rates 1/4,1/3,2/5,1/2,3/5,2/3,3/4,4/5,5/6,8/9 and 9/10 have been stipulated, and be the LDPC code of 16200 bits for code length N, stipulated 10 kinds of encoding rates 1/4,1/3,2/5,1/2,3/5,2/3,3/4,4/5,5/6 and 8/9 (Figure 11 B).

LDPC coding section 21 is according to obtaining the coding (error correction code) of LDPC code that code length N is the different coding rate of 64800 bits or 16200 bits for every kind of code length N with for the parity check matrix H of every kind of encoding rate preparation.

Figure 29 illustrates the example of configuration of the LDPC coding section 21 of Fig. 8.

LDPC coding section 21 comprises coding processing block 601 and memory block 602.

Coding processing block 601 comprises that encoding rate arranges part 611, initial value table and reads part 612, parity matrix generating portion 613, information bit and read part 614, coding odd even mathematical operation part 615, control section 616, and the object data that offers LDPC coding section 21 is carried out the LDPC coding, and the LDPC code that obtains is offered bit interleaver 22 (Fig. 8) as the result that LDPC encodes.

Particularly, for example in response to operator's operation, encoding rate arranges part 611 and for the LDPC code code length N and encoding rate is set.

The initial value table is read part 612 and is read corresponding to encoding rate from memory block 602 code length N that part 611 arranges and the parity matrix initial value table described below of encoding rate are set.

Read the parity matrix initial value table that part 612 is read based on the initial value table, parity matrix generating portion 613 is listed as (the number of columns P of unit of loop structure) as the periodic arrangement information matrix H corresponding with the message length K (=code length N-odd even length M) of the code length N that part 611 settings are set corresponding to encoding rate and encoding rate take 360 on column direction _AValue be 1 element, producing parity check matrix H, and store this parity check matrix H into memory block 602.

Information bit is read part 614 and read (extraction) for the information bit of message length K from the object data that offers LDPC coding section 21.

Coding odd even mathematical operation part 615 is read the parity check matrix H that is produced by parity matrix generating portion 613 from memory block 602, and calculates corresponding to the parity bits of being read the information bit that part 614 reads by information bit to produce code word (LDPC code) according to predetermined expression formula.

The piece of control section 616 controlling compositions coding processing block 601.

A plurality of parity check initial value tables of the every kind of relevant Multi-encoding rate shown in Figure 11 that corresponds respectively in memory block 602 among storage and 64800 bits and two kinds of code length N of 16200 bits etc.In addition, the essential data of processing of memory block 602 temporary transient memory encoding processing blocks 601.

Figure 30 is the flow chart that illustrates the reception ﹠ disposal that the receiving equipment by Figure 29 carries out.

At step S201, encoding rate arranges part 611 and determines that (setting) is used for carrying out code length N and the encoding rate r of LDPC coding.

At step S202, the initial value table is read part 612 and is read corresponding to encoding rate from memory block 602 code length N that part 611 determines and the predetermined parity matrix initial value table of encoding rate r are set.

At step S203, parity matrix generating portion 613 usefulness initial value tables are read parity matrix initial value table that part 612 reads from memory block 602 and are determined that (generation) is used for having the parity check matrix H that the LDPC code of code length N that part 611 determines and encoding rate r is set by encoding rate, and provide parity check matrix H to memory block 602 with its storage.

At step S204, information bit is read part 614 and is read from the object data that offers LDPC coding section 21 and have the message length K (information bit of=N * r) that code length N that part 611 determines and encoding rate r are set corresponding to encoding rate, and read the parity check matrix H that parity matrix generating portion 613 is determined from memory block 602, and provide information bit and parity check matrix H to coding odd even mathematical operation part 615.

At step S205, coding odd even mathematical operation part 615 performs mathematical calculations to the parity bits of code word c in succession, and it satisfies expression formula (8).

Hc ^T＝0 ...(8)

In expression formula (8), c represents the row vector as code word (LDPC code), and c ^TThe inversion (inversion) of the vectorial c of expression row.

At this, as mentioned above, wherein, part corresponding to information bit in as the vectorial c of the row of LDPC code represents with the vectorial A of row, and represent with the row vector T corresponding to the part of parity bits, the vectorial c of row is with being derived from as the vectorial A of the row of information bit with as the expression formula c=[A|T of the capable vector T of parity bits] represent.

Parity check matrix H and as the vectorial c=[A|T of the row of LDPC code] must satisfy expression formula Hc ^T=0, parity check matrix H=[H wherein _A| H _T] parity matrix H _THas step structure as shown in Figure 10, by from expression formula Hc ^TColumn vector Hc in=0 ^TThe first row in element begin the element in every delegation is set to 0 in succession, can sequentially determine configuration line vector c=[A|T] (satisfy expression formula Hc ^T=0) capable vector T as parity bits.

If the parity bits T that coding odd even mathematical operation part 615 is determined for information bit A, then it exports the code word c=[A|T that is represented by information bit A and parity bits T] as the LDPC coding result to information bit A.

Should notice that code word c has 64800 bits or 16200 bits.

Then, at step S206, control section 616 determines whether the LDPC coding should finish.If determine that at step S206 the LDPC coding should not finish, that is, if for example will carry out to it in addition the object data of LDPC coding, then process and return step S201, repeating step S201 is to the processing of S206 afterwards.

On the other hand, if determine that at step S206 the LDPC coding should finish, that is, for example, there is not to carry out it object data of LDPC coding, then LDPC coding section 21 end process.

As mentioned above, preparation is corresponding to the parity matrix initial value table of code length N and encoding rate r, and the parity check matrix H that 21 uses of LDPC coding section produce from the parity matrix initial value table corresponding to code length N and encoding rate r carries out encoding for the LDPC of predetermined code length N and predictive encoding rate r.

Each parity matrix initial value table be per 360 row (the number of columns P of unit of periodic structure) of expression with corresponding to information matrix H corresponding to the message length K of the code length N of the LDPC code of parity check matrix H (the LDPC code that is limited by parity check matrix H) and encoding rate r _AValue be the table of the position of 1 element, and generate in advance the parity matrix initial value table for the parity matrix of every kind of code length N and every kind of encoding rate r.

Figure 31 illustrates some parity matrix initial value tables of stipulating in the DVB-S.2 standard to Figure 58.

Particularly, to illustrate for the code length N that stipulates in the DVB-S.2 standard be that 16200 bits and encoding rate r are the parity matrix initial value table of 2/3 parity check matrix H to Figure 31.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 2/3 parity check matrix H that Figure 32 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 34.

Should notice that Figure 33 is the figure of continued access Figure 32, and Figure 34 is the figure of continued access Figure 33.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 3/4 parity check matrix H that Figure 35 illustrates for the code length N that stipulates in the DVB-S.2 standard.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 3/4 parity check matrix H that Figure 36 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 39.

Should notice that Figure 37 is the figure of continued access Figure 36, and Figure 38 is the figure of continued access Figure 37.In addition, Figure 39 is the figure of continued access Figure 38.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 4/5 parity check matrix H that Figure 40 illustrates for the code length N that stipulates in the DVB-S.2 standard.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 4/5 parity check matrix H that Figure 41 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 44.

Should notice that Figure 42 is the figure of continued access Figure 41, and Figure 43 is the figure of continued access Figure 42.In addition, Figure 44 is the figure of continued access Figure 43.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 5/6 parity check matrix H that Figure 45 illustrates for the code length N that stipulates in the DVB-S.2 standard.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 5/6 parity check matrix H that Figure 46 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 49.

Should notice that Figure 47 is the figure of continued access Figure 46, and Figure 48 is the figure of continued access Figure 47.In addition, Figure 49 is the figure of continued access Figure 48.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 8/9 parity check matrix H that Figure 50 illustrates for the code length N that stipulates in the DVB-S.2 standard.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 8/9 parity check matrix H that Figure 51 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 54.

Should notice that Figure 52 is the figure of continued access Figure 51, and Figure 53 is the figure of continued access Figure 52.In addition, Figure 54 is the figure of continued access Figure 53.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 9/10 parity check matrix H that Figure 55 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 58.

Should notice that Figure 56 is the figure of continued access Figure 55, and Figure 57 is the figure of continued access Figure 56.In addition, Figure 58 is the figure of continued access Figure 57.

Parity matrix generating portion 613 (Figure 29) comes to determine parity check matrix H in the following manner with parity matrix initial value table.

Particularly, Figure 59 illustrates the method for determining parity check matrix H from parity matrix initial value table.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 2/3 parity check matrix H for the code length N that stipulates in the DVB-S.2 standard that the parity matrix initial value that should note Figure 59 is expressed shown in Figure 31.

As mentioned above, parity matrix initial value table represent per 360 row (the number of columns P of unit of loop structure) with corresponding to information matrix H corresponding to the message length K of the code length N of LDPC code and encoding rate r _AValue (Fig. 9) is the table of the position of 1 element, and in the first row of parity matrix initial value table, the value in the row of the 1+360 of parity check matrix H * (i-1) is the numerical value that the quantity of the line number (line number of the first row of parity check matrix H is 0 in line number) of 1 element equals the row weight that the row of 1+360 * (i-1) have.

At this, because the parity matrix H corresponding to the odd even length M of parity check matrix H _T(Fig. 9) determine as illustrated in fig. 19, therefore according to parity matrix initial value table, the information matrix H corresponding to message length K of parity check matrix H _A(Fig. 9) be determined.

The line number amount k+1 of parity matrix initial value table is different according to message length K.

The message length K of parity matrix initial value table and line number amount k+1 satisfy the relation that expression formula (9) provides.

K＝(k+1)×360 ...(9)

At this, 360 in the expression formula (9) is the number of columns P of unit with reference to the loop structure of Figure 20 description.

In the parity matrix initial value table of Figure 59, first lists 13 numerical value to the third line, and lists 3 numerical value among the 4th to k+1 capable (in Figure 59, the 30th row).

Therefore, the numerical value of the row weight from the parity check matrix H that the parity matrix initial value table of Figure 59 is determined is 13 in the first to 1+360 * (3-1)-1 row, but is 3 in the row of 1+360 * (3-1) is capable to K.

The first row of the parity matrix initial value table of Figure 59 comprises 0,2084,1613,1548,1286,1460,3196,4297,2481,3369,3451,4620 and 2622, this is illustrated in the first row of parity check matrix H, and line number is that the value of the element in 0,2084,1613,1548,1286,1460,3196,4297,2481,3369,3451,4620 and 2622 the row is 1 (value of other element is value 0 in addition).

Simultaneously, the second row of the parity matrix initial value table of Figure 59 comprises 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358 and 3108, this is illustrated in the 361st (the=the 1+360 * (the 2-1)) row of parity check matrix H, and line number is that the element value in 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358 and 3108 the row is 1 (other element value is 0 in addition).

As previously discussed, parity matrix initial value table represents the information matrix H of per 360 row parity check matrix H _AValue be the position of 1 element.

Each row that is different from the row of 1+360 * (i-1) of parity check matrix H (i.e. each row from 2+360 * (i-1) to the 360th * i), comprise by being that the be shifted value that obtains of 1 element is 1 element to the value of row (periodically depending on parity matrix initial value table) of 1+360 * (i-1) circularly according to the odd even length M, in (on the downward direction of row) on the downward direction.

Particularly, for example, the row of 2+360 * (i-1) be by circularly the row of 1+360 * (i-1) are moved down M/360 (the row of=q) row that obtain of position, and the 3+360 that follows * (i-1) be by circularly the row of 1+360 * (i-1) are moved down 2 * M/360 (=2 * q) s, and then circularly the row after the cyclic shift (2+360 * (i-1) row) are moved down M/360 (=q) row that obtain.

Now, if the j row of supposition parity matrix initial value table (from left to right j row) i capable (from i capable) numerical value b _{I, j}Expression, and the w column mean of parity check matrix H is the line number H of 1 j element _W-jExpression then can determine to be different from the line number H that the w column mean of row of 1+360 * (i-1) is 1 element according to expression formula (10) in parity check matrix H _W-j

H _w-j＝mod{h _i，j+mod((w-1)，P)×q，M} ...(10)

Wherein, mod (x, y) expression x is divided by the remainder of y.

Simultaneously, P is the Board Lot of the row of above-described loop structure, for example, as mentioned above, is 360 in the DVB-S.2 standard.In addition, q is the value M/360 that the odd even length M obtains divided by the number of columns P of unit (=360) of loop structure.

It is the line number of 1 element that parity matrix generating portion 613 (Figure 29) is specified value the row of the 1+360 of parity check matrix H * (i-1) from parity matrix initial value table.

In addition, parity matrix generating portion 613 (Figure 29) determines that according to expression formula (10) w row (the w row are to be different from the row of row of 1+360 * (the i-1)) intermediate value of parity check matrix H is the line number H of 1 element _W-j, and producing parity check matrix H, line number is 1 for the value of the element of the line number by above-mentioned acquisition in this parity check matrix H.

Incidentally, estimate that standard DVB-C.2 as CATV digital broadcasting of future generation will adopt than high code-rate (such as 2/3 to 9/10) and the modulator approach (such as 1024QAM or 4096QAM) of more signaling point is arranged.

In the modulator approach that has than high code-rate or more signaling point, generally because the tolerance limit to error of communication path 13 (Fig. 7) is lower, so expectation employing measure improves the tolerance limit to error.

As the measure that improves the tolerance limit of error, for example can use the replacement Treatment of being undertaken by demodulation multiplexer 25 (Fig. 8).

In replacement Treatment, the method for replacing as being used for the code bit of LDPC code is replaced for example can use above-described the first to the 4th method of replacing.Yet, the method that the tolerance limit that needs proposition and the method that comprises the first to the 4th method of replacing that has proposed to compare error is further improved.

Thus, demodulation multiplexer (Fig. 8) is configured such that it can carry out replacement Treatment with reference to the allocation rule of Figure 25 description in as mentioned.

Hereinafter, before the replacement Treatment of describing according to allocation rule, the replacement Treatment of carrying out according to the method for replacing (hereinafter being called existing method) that has proposed is described first.

Being described in the supposition replacement Treatment with reference to Figure 60 and Figure 61 is replacement Treatment in the situation of being carried out according to existing method by demodulation multiplexer 25.

It is that code length N is that 64800 bits and encoding rate are according to the example of existing methodical replacement Treatment in the situation of 3/5 LDPC code that Figure 60 is illustrated in the LDPC code.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 3/5 LDPC code, modulator approach is that 16QAM and multiplier b are according to the example of existing methodical method of replacing in 2 the situation in addition to Figure 60 A.

When modulator approach is 16QAM, code 4 in the bit (=m) individual bit is used as a sign map some signaling points in 16 signaling points of 16QAM regulation.

In addition, when code length N is that 64800 bits and multiplier b are when being 2, the memory 31 of demodulation multiplexer 25 (Figure 16 and Figure 17) has 8 row, is used in the row direction upper storage 4 * 2 (=mb) individual bit and store the individual bit in 64800/ (4 * 2) at column direction.

In demodulation multiplexer 25, when the code bit of LDPC code is write by the column direction at memory 31 and the writing when finishing of 64800 code bits (code word), with the code bit in the write memory 31 take 4 * 2 (=mb) replacement section 32 (Figure 16 and Figure 17) is read and offered to bit in the row direction as unit.

4 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀, b ₁, b ₂, b ₃, b ₄, b ₅, b ₆And b ₇Replace, so that this 4 * 2 (=mb) individual code bit b ₀To b ₇Be assigned to continuous 2 (=b) 4 * 2 (=mb) individual sign bit y of individual symbol ₀, y ₁, y ₂, y ₃, y ₄, y ₅, y ₆And y ₇

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₄,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₃,

Code bit b ₆Give sign bit y ₆, and

Code bit b ₇Give sign bit y ₀

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 3/5 LDPC code, modulator approach is that 64QAM and multiplier b are according to the example of existing methodical method of replacing in 2 the situation in addition to Figure 60 B.

When modulator approach is 64QAM, code 6 in the bit (=m) individual bit is used as a sign map some signaling points in 64 signaling points of 64QAM regulation.

In addition, when code length N is that 64800 bits and multiplier b are when being 2, the memory 31 of demodulation multiplexer 25 (Figure 16 and Figure 17) has 12 row, is used in the row direction upper storage 6 * 2 (=mb) individual bit and store the individual bit in 64800/ (6 * 2) at column direction.

In demodulation multiplexer 25, when the code bit of LDPC code is write by the column direction at memory 31 and the writing when finishing of 64800 code bits (code word), with the code bit in the write memory 31 take 6 * 2 (=mb) replacement section 32 (Figure 16 and Figure 17) is read and offered to bit in the row direction as unit.

6 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀, b ₁, b ₂, b ₃, b ₄, b ₅, b ₆, b ₇, b ₈, b ₉, b ₁₀And b ₁₁Replace, so that this 6 * 2 (=mb) individual code bit b ₀To b ₁₁Be assigned to continuous 2 (=b) 6 * 2 (=mb) individual sign bit y of individual symbol ₀, y ₁, y ₂, y ₃, y ₄, y ₅, y ₆, y ₇, y ₈, y ₉, y ₁₀And y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₁₁,

Code bit b ₁Give sign bit y ₇,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₁₀,

Code bit b ₄Give sign bit y ₆,

Code bit b ₅Give sign bit y ₂,

Code bit b ₆Give sign bit y ₉,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₁,

Code bit b ₉Give sign bit y ₈,

Code bit b ₁₀Give sign bit y ₄, and

Code bit b ₁₁Give sign bit y ₀

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 3/5 LDPC code, modulator approach is that 256QAM and multiplier b are according to the example of existing methodical method of replacing in 2 the situation in addition to Figure 60 C.

When modulator approach is 256QAM, code 8 in the bit (=m) individual bit is used as a sign map some signaling points in 256 signaling points of 256QAM regulation.

In addition, when code length N is that 64800 bits and multiplier b are when being 2, the memory 31 of demodulation multiplexer 25 (Figure 16 and Figure 17) has 16 row, is used in the row direction upper storage 8 * 2 (=mb) individual bit and store the individual bit in 64800/ (8 * 2) at column direction.

In demodulation multiplexer 25, when the code bit of LDPC code is write by the column direction at memory 31 and the writing when finishing of 64800 code bits (code word), with the code bit in the write memory 31 take 8 * 2 (=mb) replacement section 32 (Figure 16 and Figure 17) is read and offered to bit in the row direction as unit.

8 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀, b ₁, b ₂, b ₃, b ₄, b ₅, b ₆, b ₇, b ₈, b ₉, b ₁₀, b ₁₁, b ₁₂, b ₁₃, b ₁₄And b ₁₅Replace, so that this 8 * 2 (=mb) individual code bit b ₀To b ₁₅Be assigned to continuous 2 (=b) 8 * 2 (=mb) individual sign bit y of individual symbol ₀, y ₁, y ₂, y ₃, y ₄, y ₅, y ₆, y ₇, y ₈, y ₉, y ₁₀, y ₁₁, y ₁₂, y ₁₃, y ₁₄And y ₁₅

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₁₅,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₁₃,

Code bit b ₃Give sign bit y ₃,

Code bit b ₄Give sign bit y ₈,

Code bit b ₅Give sign bit y ₁₁,

Code bit b ₆Give sign bit y ₉,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₁₀,

Code bit b ₉Give sign bit y ₆,

Code bit b ₁₀Give sign bit y ₄,

Code bit b ₁₁Give sign bit y ₇,

Code bit b ₁₂Give sign bit y ₁₂,

Code bit b ₁₃Give sign bit y ₂,

Code bit b ₁₄Give sign bit y ₁₄, and

Code bit b ₁₅Give sign bit y ₀

It is that code length N is that 16200 bits and encoding rate are according to the example of existing methodical replacement Treatment in the situation of 3/5 LDPC code that Figure 61 is illustrated in the LDPC code.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 3/5 LDPC code, modulator approach is that 16QAM and multiplier b are according to the example of existing methodical method of replacing in 2 the situation in addition to Figure 61 A.

When modulator approach is 16QAM, code 4 in the bit (=m) individual bit is used as a sign map some signaling points in 16 signaling points of 16QAM regulation.

In addition, when code length N is that 16200 bits and multiplier b are when being 2, the memory 31 of demodulation multiplexer 25 (Figure 16 and Figure 17) has 8 row, is used in the row direction upper storage 4 * 2 (=mb) individual bit and store the individual bit in 16200/ (4 * 2) at column direction.

In demodulation multiplexer 25, when the code bit of LDPC code is write by the column direction at memory 31 and the writing when finishing of 16200 code bits (code word), with the code bit in the write memory 31 take 4 * 2 (=mb) replacement section 32 (Figure 16 and Figure 17) is read and offered to bit in the row direction as unit.

4 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀, b ₁, b ₂, b ₃, b ₄, b ₅, b ₆And b ₇Replace, so that this 4 * 2 (=mb) individual code bit b ₀To b ₇Be assigned to continuous 2 (=b) 4 * 2 (=mb) individual sign bit y of individual symbol ₀, y ₁, y ₂, y ₃, y ₄, y ₅, y ₆And y ₇

Particularly, replacement section 32 is replaced, so that the situation of Figure 60 A is equally with code bit b as described above ₀To b ₇Distribute to sign bit y ₀To y ₇

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 3/5 LDPC code, modulator approach is that 64QAM and multiplier b are according to the example of existing methodical method of replacing in 2 the situation in addition to Figure 61 B.

When modulator approach is 64QAM, code 6 in the bit (=m) individual bit is used as a sign map some signaling points in 64 signaling points of 64QAM regulation.

In addition, when code length N is that 16200 bits and multiplier b are when being 2, the memory 31 of demodulation multiplexer 25 (Figure 16 and Figure 17) has 12 row, is used in the row direction upper storage 6 * 2 (=mb) individual bit and store the individual bit in 16200/ (6 * 2) at column direction.

In demodulation multiplexer 25, when the code bit of LDPC code is write by the column direction at memory 31 and the writing when finishing of 16200 code bits (code word), with the code bit in the write memory 31 take 6 * 2 (=mb) replacement section 32 (Figure 16 and Figure 17) is read and offered to bit in the row direction as unit.

6 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀, b ₁, b ₂, b ₃, b ₄, b ₅, b ₆, b ₇, b ₈, b ₉, b ₁₀And b ₁₁Replace, so that this 6 * 2 (=mb) individual code bit b ₀To b ₁₁Be assigned to continuous 2 (=b) 6 * 2 (=mb) individual sign bit y of individual symbol ₀, y ₁, y ₂, y ₃, y ₄, y ₅, y ₆, y ₇, y ₈, y ₉, y ₁₀And y ₁₁

Particularly, replacement section 32 is replaced, so that the situation of Figure 60 B is equally with code bit b as described above ₀To b ₁₁Distribute to sign bit y ₀To y ₁₁

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 3/5 LDPC code, modulator approach is that 256QAM and multiplier b are according to the example of existing methodical method of replacing in 1 the situation in addition to Figure 61 C.

When modulator approach is 256QAM, code 8 in the bit (=m) individual bit is used as a sign map some signaling points in 256 signaling points of 256QAM regulation.

In addition, when code length N is that 16200 bits and multiplier b are when being 1, the memory 31 of demodulation multiplexer 25 (Figure 16 and Figure 17) has 8 row, is used in the row direction upper storage 8 * 1 (=mb) individual bit and store the individual bit in 16200/ (8 * 1) at column direction.

In demodulation multiplexer 25, when the code bit of LDPC code is write by the column direction at memory 31 and the writing when finishing of 16200 code bits (code word), with the code bit in the write memory 31 take 8 * 1 (=mb) replacement section 32 (Figure 16 and Figure 17) is read and offered to bit in the row direction as unit.

8 * 1 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀, b ₁, b ₂, b ₃, b ₄, b ₅, b ₆And b ₇Replace, so that this 8 * 1 (=mb) individual code bit b ₀To b ₇Be assigned to continuous 1 (=b) 8 * 1 (=mb) individual sign bit y of individual symbol ₀, y ₁, y ₂, y ₃, y ₄, y ₅, y ₆And y ₇

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₃,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₅,

Code bit b ₄Give sign bit y ₂,

Code bit b ₅Give sign bit y ₆,

Code bit b ₆Give sign bit y ₄, and

Code bit b ₇Give sign bit y ₀

Replacement Treatment (also being called hereinafter the replacement Treatment according to new method of replacing) according to allocation rule will be described now.

Figure 62 to 64 is the figure that illustrate the method for replacing that makes new advances.

In new method of replacing, the replacement section 32 of demodulation multiplexer 25 is replaced mb code bit according to predetermined allocation rule.

Allocation rule is for the code Bit Allocation in Discrete of the LDPC code rule to sign bit.In allocation rule, the group collection that the code bit group of having stipulated the code bit and the sign bit group of sign bit (it has been distributed the code bit of code bit group) are combined, and stipulated code bit group and the code bit of sign bit group and the amount of bits (hereinafter be also referred to as and organize amount of bits) of sign bit of group collection.

At this, as mentioned above, the code bit is different on the probability of error each other, and sign bit is also different on the probability of error each other.Code bit group is the group that yard bit forms according to the probability of error, and the group that sign bit group is-symbol bit forms according to the probability of error.

It is that code length N is that 16200 bits and encoding rate are 2/3 LDPC code, modulator approach is 1024QAM and multiplier b is code bit group and the sign bit group in 1 situation in addition that Figure 62 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 62 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 4 code bit group Gb ₁, Gb ₂, Gb ₃And Gb ₄

At this, code bit group Gb _iLess this yard bit group Gb that then belongs to of its subscript i _iThe group of the probability of error better (lower) of code bit.

In Figure 62 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁, b ₂, b ₃, b ₄And b ₅Belong to a yard bit group Gb ₂Code bit b ₆Belong to a yard bit group Gb ₃And code bit b ₇, b ₈And b ₉Belong to a yard bit group Gb ₄

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 62 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

At this, with code bit category seemingly, sign bit group Gy _iLess this sign bit group Gy that then belongs to of its subscript i _iThe better group of the probability of error of sign bit.

In Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 16200 bits and encoding rate are 2/3 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 63 illustrates at the LDPC code.

In the allocation rule of Figure 63, code bit group Gb ₁With sign bit group Gy ₅Combination be restricted to a group collection.In addition, stipulated that the group amount of bits that this group collects is 1 bit.

In the following description, the group amount of bits of group collection and group collection is called as group collection information together.For example, code bit group Gb ₁With sign bit group Gy ₅The group collection and be described to organize collection information (Gb as 1 bit of the group amount of bits of group collection ₁, Gy ₅, 1).

In the allocation rule of Figure 63, except group collection information (Gb ₁, Gy ₅, 1) in addition, also stipulated group collection information (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 1), (Gb ₃, Gy ₄, 1), (Gb ₄, Gy ₃, 1), (Gb ₄, Gy ₄, 1) and (Gb ₄, Gy ₅, 1).

For example, group collection information (Gb ₁, Gy ₅, 1) and mean that belonging to group collects Gb ₁A code bit be assigned to and belong to sign bit group Gy ₅A sign bit.

Therefore, according to the allocation rule of Figure 63, regulation:

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the sign bit group Gy of the probability of error the 5th good (the poorest) ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ³, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 3rd ₃A sign bit,

According to group collection information (Gb ₃, Gy ₄, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₄, Gy ₃, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 3rd ₃A sign bit,

According to group collection information (Gb ₄, Gy ₄, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit, and

According to group collection information (Gb ₄, Gy ₅, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit.

As mentioned above, code bit group is with the group of code bit according to probability of error grouping, and the sign bit group is with the group of sign bit according to probability of error grouping.Therefore, also can think the combination of the probability of error of the probability of error of allocation rule regulation code bit and sign bit (having distributed the code bit to it).

Mode thus, the allocation rule of the combination of the probability of error of the probability of error of regulation code bit and sign bit (having distributed the code bit to it) is determined, so that such as the emulation by wherein measuring BER (bit error rate (BER)) etc., make the tolerance limit (to the tolerance limit of noise) to error better.

Change between the bit of prosign bit group even it should be noted that the distribution destination of the code bit of a certain code bit group, the tolerance limit of error also can't therefore be affected (hardly can).

Therefore, in order to improve the tolerance limit to error, minimized group of collection information of BER (bit error rate (BER)) (i.e. the combination (group collection) of the sign bit group of code bit group and the sign bit of code bit (it has been distributed the code bit of code bit group) and yard bit group that this group is concentrated and yard bit of sign bit group and the amount of bits (group amount of bits) of sign bit) allocation rule should be defined as, and the displacement of yard bit should be carried out so that a yard bit is distributed to sign bit according to allocation rule.

Yet the concrete distribution method that should distribute to which symbol according to allocation rule about each yard bit need to pre-determine between transmitting apparatus 11 and receiving equipment 12 (Fig. 7).

Figure 64 illustrates the example according to the code bit permutation of the allocation rule of Figure 63.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 2/3 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 63 in 1 the situation in addition to Figure 64 A.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 2/3 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of (16200/ (10 * 1)) * (10 * 1) bit on column direction * line direction take 10 * 1 ((=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 63 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 64 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₆,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 16200 bits and encoding rate are 2/3 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 63 in 1 the situation in addition that Figure 64 B illustrates at the LDPC code.

According to Figure 64 B, replacement section 32 is replaced, with according to the allocation rule of Figure 63 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₉,

Code bit b ₁Give sign bit y ₂,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₇,

Code bit b ₇Give sign bit y ₄,

Code bit b ₈Give sign bit y ₈, and

Code bit b ₉Give sign bit y ₆

At this, the code bit b that Figure 64 A and Figure 64 B illustrate _iDistribute to sign bit y _iDistribution method follow the allocation rule (according to allocation rule) of Figure 63.

It is that code length N is that 64800 bits and encoding rate are 2/3 LDPC code, modulator approach is that 1024QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 65 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 65 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 4 code bit group Gb ₁, Gb ₂, Gb ₃And Gb ₄

In Figure 65 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₅Belong to a yard bit group Gb ₂Code bit b ₆Belong to a yard bit group Gb ₃And code bit b ₇To b ₉Belong to a yard bit group Gb ₄

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 65 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

In Figure 65 B, as Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 64800 bits and encoding rate are 2/3 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 66 illustrates at the LDPC code.

In the allocation rule of Figure 66, regulation group collection information (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 1), (Gb ₃, Gy ₄, 1), (Gb ₄, Gy ₃, 1), (Gb ₄, Gy ₄, 1) and (Gb ₄, Gy ₅, 1).

Therefore, according to the allocation rule of Figure 66, regulation:

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the sign bit group Gy of the probability of error the 5th good (the poorest) ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 3rd ₃A sign bit,

According to group collection information (Gb ₃, Gy ₄, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₄, Gy ₃, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 3rd ₃A sign bit,

According to group collection information (Gb ₄, Gy ₄, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit, and

According to group collection information (Gb ₄, Gy ₅, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit.

Figure 67 illustrates the example according to the code bit permutation of the allocation rule of Figure 66.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 2/3 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 66 in 1 the situation in addition to Figure 67 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 2/3 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of (64800/ (10 * 1)) * (10 * 1) bit on column direction * line direction by take 10 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 66 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 67 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₆,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 64800 bits and encoding rate are 2/3 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 66 in 1 the situation in addition that Figure 67 B illustrates at the LDPC code.

According to Figure 67 B, replacement section 32 is replaced, with according to the allocation rule of Figure 66 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₉,

Code bit b ₁Give sign bit y ₂,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₇,

Code bit b ₇Give sign bit y ₄,

Code bit b ₈Give sign bit y ₈, and

Code bit b ₉Give sign bit y ₆

It is that code length N is that 16200 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 68 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 68 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 4 code bit group Gb ₁, Gb ₂, Gb ₃And Gb ₄

In Figure 68 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₆Belong to a yard bit group Gb ₂Code bit b ₇Belong to a yard bit group Gb ₃And code bit b ₈And b ₉Belong to a yard bit group Gb ₄

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 68 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

In Figure 68 B, as Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 16200 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 69 illustrates at the LDPC code.

In the allocation rule of Figure 69, regulation group collection information (Gb ₁, Gy ₄, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 1), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₅, 1), (Gb ₃, Gy ₂, 1), (Gb ₄, Gy ₄, 1) and (Gb ₄, Gy ₅, 1).

Therefore, according to the allocation rule of Figure 69, regulation:

According to group collection information (Gb ₁, Gy ₄, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the second-best sign bit group of probability of error Gy ₂A sign bit,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₅, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₃, Gy ₂, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the second-best sign bit group of probability of error Gy ₂A sign bit,

According to group collection information (Gb ₄, Gy ₄, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit, and

According to group collection information (Gb ₄, Gy ₅, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit.

Figure 70 illustrates the example according to the code bit permutation of the allocation rule of Figure 69.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 69 in 1 the situation in addition to Figure 70 A.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of (16200/ (10 * 1)) * (10 * 1) bit on column direction * line direction by take 10 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 69 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 70 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₆,

Code bit b ₁Give sign bit y ₄,

Code bit b ₂Give sign bit y ₈,

Code bit b ₃Give sign bit y ₅,

Code bit b ₄Give sign bit y ₀,

Code bit b ₅Give sign bit y ₂,

Code bit b ₆Give sign bit y ₁,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 16200 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 69 in 1 the situation in addition that Figure 70 B illustrates at the LDPC code.

According to Figure 70 B, replacement section 32 is replaced, with according to the allocation rule of Figure 69 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₉,

Code bit b ₂Give sign bit y ₄,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₈, and

Code bit b ₉Give sign bit y ₆

It is that code length N is that 64800 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 71 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 71 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 4 code bit group Gb ₁, Gb ₂, Gb ₃And Gb ₄

In Figure 71 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₆Belong to a yard bit group Gb ₂Code bit b ₇Belong to a yard bit group Gb ₃And code bit b ₈And b ₉Belong to a yard bit group Gb ₄

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 71 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

In Figure 71 B, as Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 64800 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 72 illustrates at the LDPC code.

In the allocation rule of Figure 72, regulation group collection information (Gb ₁, Gy ₄, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 1), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₅, 1), (Gb ₃, Gy ₂, 1), (Gb ₄, Gy ₄, 1) and (Gb ₄, Gy ₅, 1).

Therefore, according to the allocation rule of Figure 72, regulation:

According to group collection information (Gb ₁, Gy ₄, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the second-best sign bit group of probability of error Gy ₂A sign bit,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₅, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₃, Gy ₂, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the second-best sign bit group of probability of error Gy ₂A sign bit,

According to group collection information (Gb ₄, Gy ₄, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit, and

According to group collection information (Gb ₄, Gy ₅, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit.

Figure 73 illustrates the example according to the code bit permutation of the allocation rule of Figure 72.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 72 in 1 the situation in addition to Figure 73 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of (64800/ (10 * 1)) * (10 * 1) bit on column direction * line direction by take 10 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 72 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 73 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₆,

Code bit b ₁Give sign bit y ₄,

Code bit b ₂Give sign bit y ₈,

Code bit b ₃Give sign bit y ₅,

Code bit b ₄Give sign bit y ₀,

Code bit b ₅Give sign bit y ₂,

Code bit b ₆Give sign bit y ₁,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 64800 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 72 in 1 the situation in addition that Figure 73 B illustrates at the LDPC code.

According to Figure 73 B, replacement section 32 is replaced, with according to the allocation rule of Figure 72 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₉,

Code bit b ₂Give sign bit y ₄,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₈, and

Code bit b ₉Give sign bit y ₆

It is that code length N is that 16200 bits and encoding rate are 4/5 LDPC code, modulator approach is that 1024QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 74 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 74 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 3 code bit group Gb ₁, Gb ₂And Gb ₃

In Figure 74 A, code bit b ₀To b ₆Belong to a yard bit group Gb ₁Code bit b ₇Belong to a yard bit group Gb ₂And code bit b ₈And b ₉Belong to a yard bit group Gb ₃

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 74 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

In Figure 74 B, as Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 16200 bits and encoding rate are 4/5 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 75 illustrates at the LDPC code.

In the allocation rule of Figure 75, regulation group collection information (Gb ₁, Gy ₁, 2), (Gb ₁, Gy ₂, 1), (Gb ₁, Gy ₃, 2), (Gb ₁, Gy ₄, 1), (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₂, 1), (Gb ₃, Gy ₄, 1) and (Gb ₃, Gy ₅, 1).

Therefore, according to the allocation rule of Figure 75, regulation:

According to group collection information (Gb ₁, Gy ₁, 2), the code bit group Gb that the probability of error is best ₁Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₁, Gy ₂, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the second-best sign bit group of probability of error Gy ₂A sign bit,

According to group collection information (Gb ₁, Gy ₃, 2), the code bit group Gb that the probability of error is best ₁Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₁, Gy ₄, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₂, 1), the code bit of the second-best code of probability of error bit group Gb2 is assigned to the second-best sign bit group of probability of error Gy ₂A sign bit,

According to group collection information (Gb ₃, Gy ₄, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit, and

According to group collection information (Gb ₃, Gy ₅, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit.

Figure 76 illustrates the example according to the code bit permutation of the allocation rule of Figure 75.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 4/5 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 75 in 1 the situation in addition to Figure 76 A.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 4/5 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (16200/ (10 * 1)) * (10 * 1) bit by take 10 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 75 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 76 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₆,

Code bit b ₁Give sign bit y ₄,

Code bit b ₂Give sign bit y ₈,

Code bit b ₃Give sign bit y ₅,

Code bit b ₄Give sign bit y ₀,

Code bit b ₅Give sign bit y ₂,

Code bit b ₆Give sign bit y ₁,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 16200 bits and encoding rate are 4/5 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 75 in 1 the situation in addition that Figure 76 B illustrates at the LDPC code.

According to Figure 76 B, replacement section 32 is replaced, with according to the allocation rule of Figure 75 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₉,

Code bit b ₁Give sign bit y ₇,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₄,

Code bit b ₇Give sign bit y ₂,

Code bit b ₈Give sign bit y ₈, and

Code bit b ₉Give sign bit y ₆

It is that code length N is that 64800 bits and encoding rate are 4/5 LDPC code, modulator approach is that 1024QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 77 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 77 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 3 code bit group Gb ₁, Gb ₂And Gb ₃

In Figure 77 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₇Belong to a yard bit group Gb ₂And code bit b ₈And b ₉Belong to a yard bit group Gb ₃

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 77 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

In Figure 77 B, as Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 64800 bits and encoding rate are 4/5 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 78 illustrates at the LDPC code.

In the allocation rule of Figure 78, regulation group collection information (Gb ₁, Gy ₄, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₅, 1), (Gb ₃, Gy ₄, 1) and (Gb ₃, Gy ₅, 1).

Therefore, according to the allocation rule of Figure 78, regulation:

According to group collection information (Gb ₁, Gy ₄, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₅, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₃, Gy ₄, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit, and

According to group collection information (Gb ₃, Gy ₅, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit.

Figure 79 illustrates the example according to the code bit permutation of the allocation rule of Figure 78.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 4/5 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 78 in 1 the situation in addition to Figure 79 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 4/5 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (64800/ (10 * 1)) * (10 * 1) bit by take 10 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 78 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 79 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₆,

Code bit b ₁Give sign bit y ₄,

Code bit b ₂Give sign bit y ₈,

Code bit b ₃Give sign bit y ₅,

Code bit b ₄Give sign bit y ₀,

Code bit b ₅Give sign bit y ₂,

Code bit b ₆Give sign bit y ₁,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 64800 bits and encoding rate are 4/5 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 78 in 1 the situation in addition that Figure 79 B illustrates at the LDPC code.

According to Figure 79 B, replacement section 32 is replaced, with according to the allocation rule of Figure 78 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₉

Code bit b ₈Give sign bit y ₈, and

Code bit b ₉Give sign bit y ₆

It is that code length N is that 16200 bits of encoded rates are 5/6 LDPC code, modulator approach is that 1024QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 80 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 80 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 4 code bit group Gb ₁, Gb ₂, Gb ₃And Gb ₄

In Figure 80 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₇Belong to a yard bit group Gb ₂Code bit b ₈Belong to a yard bit group Gb ₃And code bit b ₉Belong to a yard bit group Gb ₄

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 80 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

In Figure 80 B, as Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 16200 bits and encoding rate are 5/6 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 81 illustrates at the LDPC code.

In the allocation rule of Figure 81, regulation group collection information (Gb ₁, Gy ₄, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₅, 1), (Gb ₃, Gy ₅, 1) and (Gb ₄, Gy ₄, 1).

Therefore, according to the allocation rule of Figure 81, regulation:

According to group collection information (Gb ₁, Gy ₄, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₅, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₃, Gy ₅, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₄, Gy ₄, 1), the code bit group Gb that the probability of error the 4th is good ₅A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₅A sign bit.

Figure 82 illustrates the example according to the code bit permutation of the allocation rule of Figure 81.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 5/6 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 81 in 1 the situation in addition to Figure 82 A.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 5/6 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (16200/ (10 * 1)) * (10 * 1) bit by take 10 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 81 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 82 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₆,

Code bit b ₁Give sign bit y ₄,

Code bit b ₂Give sign bit y ₈,

Code bit b ₃Give sign bit y ₅,

Code bit b ₄Give sign bit y ₀,

Code bit b ₅Give sign bit y ₂,

Code bit b ₆Give sign bit y ₁,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 16200 bits and encoding rate are 5/6 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 81 in 1 the situation in addition that Figure 82 B illustrates at the LDPC code.

According to Figure 82 B, replacement section 32 is replaced, with according to the allocation rule of Figure 81 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₈,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₁,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₆

It is that code length N is that 68400 encoding rates are 5/6 LDPC code, modulator approach is that 1024QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 83 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 83 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 4 code bit group Gb ₁, Gb ₂, Gb ₃And Gb ₄

In Figure 83 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₇Belong to a yard bit group Gb ₂Code bit b ₈Belong to a yard bit group Gb ₃And code bit b ₉Belong to a yard bit group Gb ₄

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 83 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

In Figure 83 B, as Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 84 illustrates at the LDPC code.

In the allocation rule of Figure 84, regulation group collection information (Gb ₁, Gy ₄, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₅, 2), (Gb ₂, Gy ₅, 1), (Gb ₃, Gy ₅, 1) and (Gb ₄, Gy ₄, 1).

Therefore, according to the allocation rule of Figure 84, regulation:

According to group collection information (Gb ₁, Gy ₄, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₅, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₃, Gy ₅, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₄, Gy ₄, 1), the code bit group Gb that the probability of error the 4th is good ₅A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₅A sign bit.

Figure 85 illustrates the example according to the code bit permutation of the allocation rule of Figure 84.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 84 in 1 the situation in addition to Figure 85 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (64800/ (10 * 1)) * (10 * 1) bit by take 10 * 1 ((=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 84 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 85 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₆,

Code bit b ₁Give sign bit y ₄,

Code bit b ₂Give sign bit y ₈,

Code bit b ₃Give sign bit y ₅,

Code bit b ₄Give sign bit y ₀,

Code bit b ₅Give sign bit y ₂,

Code bit b ₆Give sign bit y ₁,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 84 in 1 the situation in addition that Figure 85 B illustrates at the LDPC code.

According to Figure 85 B, replacement section 32 is replaced, with according to the allocation rule of Figure 84 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₈,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₁,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₆

It is that code length N is that 16200 encoding rates are 8/9 LDPC code, modulator approach is that 1024QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 86 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 86 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 5 code bit group Gb ₁, Gb ₂, Gb ₃And Gb ₄, and Gb ₅

In Figure 86 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁Belong to a yard bit group Gb ₂Code bit b ₂To b ₇Belong to a yard bit group Gb ₃Code bit b ₈Belong to a yard bit group Gb ₄And code bit b ₉Belong to a yard bit group Gb ₅

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 86 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

In Figure 86 B, as Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 16200 bits and encoding rate are 8/9 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 87 illustrates at the LDPC code.

In the allocation rule of Figure 87, regulation group collection information (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₁, 1), (Gb ₃, Gy ₁, 1), (Gb ₃, Gy ₂, 2), (Gb ₃, Gy ₃, 2), (Gb ₃, Gy ₄, 1), (Gb ₄, Gy ₅, 1) and (Gb ₅, Gy ₄, 1).

Therefore, according to the allocation rule of Figure 87, regulation:

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₁, 1),, the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₂, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₃, Gy ₃, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₃, Gy ₄, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₄, Gy ₅, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₅, Gy ₄, 1), the code bit group Gb that the probability of error the 5th is good ₅A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit.

Figure 88 illustrates the example according to the code bit permutation of the allocation rule of Figure 87.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 8/9 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 87 in 1 the situation in addition to Figure 88 A.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 8/9 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (16200/ (10 * 1)) * (10 * 1) bit by take 10 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 87 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 88 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₆,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 16200 bits and encoding rate are 8/9 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 87 in 1 the situation in addition that Figure 88 B illustrates at the LDPC code.

According to Figure 88 B, replacement section 32 is replaced, with according to the allocation rule of Figure 87 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₉,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇

Code bit b ₈Give sign bit y ₈, and

Code bit b ₉Give sign bit y ₆

It is that code length N is that 64800 encoding rates are 8/9 LDPC code, modulator approach is that 1024QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 89 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 89 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 5 code bit group Gb ₁, Gb ₂, Gb ₃, Gb ₄And Gb ₅

In Figure 89 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁Belong to a yard bit group Gb ₂Code bit b ₂To b ₇Belong to a yard bit group Gb ₃Code bit b ₈Belong to a yard bit group Gb ₄And code bit b ₉Belong to a yard bit group Gb ₅

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 89 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

In Figure 89 B, as Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 64800 bits and encoding rate are 8/9 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 90 illustrates at the LDPC code.

In the allocation rule of Figure 90, regulation group collection information (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₁, 1), (Gb ₃, Gy ₁, 1), (Gb ₃, Gy ₂, 2), (Gb ₃, Gy ₅, 2), (Gb ₃, Gy ₄, 1), (Gb ₄, Gy ₅, 1) and (Gb ₅, Gy ₄, 1).

Therefore, according to the allocation rule of Figure 90, regulation:

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₁, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₂, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₃, Gy ₃, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₃, Gy ₄, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₄, Gy ₅, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₅, Gy ₄, 1), the code bit group Gb that the probability of error the 5th is good ₅A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit.

Figure 91 illustrates the example according to the code bit permutation of the allocation rule of Figure 90.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 8/9 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 90 in 1 the situation in addition to Figure 91 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 8/9 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (64800/ (10 * 1)) * (10 * 1) bit by take 10 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 90 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 91 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₆,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 64800 bits and encoding rate are 8/9 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 90 in 1 the situation in addition that Figure 91 B illustrates at the LDPC code.

According to Figure 91 B, replacement section 32 is replaced, with according to the allocation rule of Figure 90 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₉,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇

Code bit b ₈Give sign bit y ₈, and

Code bit b ₉Give sign bit y ₆

It is that code length N is that 64800 bits and encoding rate are 9/10 LDPC code, modulator approach is that 1024QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 92 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 92 A, from memory 31 read 10 * 1 (=mb) individual code bit can be divided into 3 code bit group Gb ₁, Gb ₂And Gb ₃

In Figure 92 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₈Belong to a yard bit group Gb ₂And code bit b ₉Belong to a yard bit group Gb ₃

When modulator approach is 1024QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 92 B, 10 * 1 (=mb) individual sign bit can be divided into 5 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄And Gy ₅

In Figure 92 B, as Figure 62 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

It is that code length N is that 64800 bits and encoding rate are 9/10 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 93 illustrates at the LDPC code.

In the allocation rule of Figure 93, regulation group collection information (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₄, 1), (Gb ₂, Gy ₅, 1) and (Gb ₃, Gy ₄, 1).

Therefore, according to the allocation rule of Figure 93, regulation:

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₄, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₂, Gy ₅, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₃, Gy ₄, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit.

Figure 94 illustrates the example according to the code bit permutation of the allocation rule of Figure 93.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 9/10 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 93 in 1 the situation in addition to Figure 94 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 9/10 LDPC code, modulator approach is that 1024QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (64800/ (10 * 1)) * (10 * 1) bit by take 10 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 93 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Replace, so that such as these 10 * 1 code bit b seen in Figure 94 A ₀To b ₉(=b) 10 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₉

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₆,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 64800 bits and encoding rate are 9/10 LDPC code, modulator approach is that 1024QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 93 in 1 the situation in addition that Figure 94 B illustrates at the LDPC code.

According to Figure 94 B, replacement section 32 is replaced, with according to the allocation rule of Figure 93 10 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₉Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₆,

Code bit b ₂Give sign bit y ₉,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₁,

Code bit b ₈Give sign bit y ₃, and

Code bit b ₉Give sign bit y ₇

It is that code length N is that 16200 bits and encoding rate are 2/3 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 95 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 95 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 3 code bit group Gb ₁, Gb ₂And Gb ₃

In Figure 95 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₇Belong to a yard bit group Gb ₂Code bit b ₈To b ₁₁Belong to a yard bit group Gb ₃

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 95 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄Sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 16200 bits and encoding rate are 2/3 LDPC code, modulator approach is that 4096QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 96 illustrates at the LDPC code.

In the allocation rule of Figure 96, regulation group collection information (Gb ₁, Gy ₆, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₄, 1), (Gb ₃, Gy ₄, 1), (Gb ₃, Gy ₅, 2) and (Gb ₃, Gy ₆, 1).

Therefore, according to the allocation rule of Figure 96, regulation:

According to group collection information (Gb ₁, Gy ₆, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₄, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₃, Gy ₄, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₃, Gy ₅, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 5th ₅Two sign bits, and

According to group collection information (Gb ₃, Gy ₆, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit.

Figure 97 illustrates the example according to the code bit permutation of the allocation rule of Figure 96.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 2/3 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 96 in 1 the situation in addition to Figure 97 A.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 2/3 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (16200/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 96 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as these 12 * 1 code bit b seen in Figure 97 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₁₀,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₅,

Code bit b ₇Give sign bit y ₆,

Code bit b ₈Give sign bit y ₈,

Code bit b ₉Give sign bit y ₇,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 16200 bits and encoding rate are 2/3 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 96 in 1 the situation in addition that Figure 97 B illustrates at the LDPC code.

According to Figure 97 B, replacement section 32 is replaced, with according to the allocation rule of Figure 96 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₁₁,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₉,

Code bit b ₉Give sign bit y ₆,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

It is that code length N is that 64800 bits and encoding rate are 2/3 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 98 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 98 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 3 code bit group Gb ₁, Gb ₂And Gb ₃

In Figure 98 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₇Belong to a yard bit group Gb ₂And code bit b ₈To b ₁₁Belong to a yard bit group Gb ₃

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 98 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 98 B, as Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄Sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 64800 bits and encoding rate are 2/3 LDPC code, modulator approach is that 4096QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 99 illustrates at the LDPC code.

In the allocation rule of Figure 99, regulation group collection information (Gb ₁, Gy ₆, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₄, 1), (Gb ₃, Gy ₄, 1), (Gb ₃, Gy ₅, 2) and (Gb ₃, Gy ₆, 1).

Therefore, according to the allocation rule of Figure 99, regulation:

According to group collection information (Gb ₁, Gy ₆, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₄, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₃, Gy ₄, 1), the code bit group Gb that the probability of error the 3rd is good ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₃, Gy ₅, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 5th ₅Two sign bits, and

According to group collection information (Gb ₃, Gy ₆, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit.

Figure 100 illustrates the example according to the code bit permutation of the allocation rule of Figure 99.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 2/3 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 99 in 1 the situation in addition to Figure 100 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (64800/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 99 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as 12 * 1 code bit b seen in Figure 100 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₁₀,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₅,

Code bit b ₇Give sign bit y ₆,

Code bit b ₈Give sign bit y ₈,

Code bit b ₉Give sign bit y ₇,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 64800 bits and encoding rate are 2/3 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 99 in 1 the situation in addition that Figure 100 B illustrates at the LDPC code.

According to Figure 100 B, replacement section 32 is replaced, with according to the allocation rule of Figure 99 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₁₁,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₉,

Code bit b ₉Give sign bit y ₆,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

It is that code length N is that 16200 bits and encoding rate are 3/4 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 101 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 101 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 4 code bit group Gb ₁, Gb ₂, Gb ₃And Gb ₄

In Figure 101 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₇Belong to a yard bit group Gb ₂Code bit b ₈Belong to a yard bit group Gb ₃And code bit b ₉To b ₁₁Belong to a yard bit group Gb ₄

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 101 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 101 B, as Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄Sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 16200 bits and encoding rate are 3/4 LDPC code, modulator approach is that 4096QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 102 illustrates at the LDPC code.

In the allocation rule of Figure 102, regulation group collection information (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₄, 1), (Gb ₃, Gy ₄, 1), (Gb ₄, Gy ₅, 1) and (Gb ₄, Gy ₆, 2).

Therefore, according to the allocation rule of Figure 102, regulation:

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₄, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₃, Gy ₄, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 4th ₄A sign bit,

According to group collection information (Gb ₄, Gy ₅, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₄, Gy ₆, 2), the code bit group Gb that the probability of error the 4th is good ₄Two code bits be assigned to the good sign bit group Gy of the probability of error the 6th ₆Two sign bits.

Figure 103 illustrates the example according to the code bit permutation of the allocation rule of Figure 102.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 3/4 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 102 in 1 the situation in addition to Figure 103 A.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 3/4 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (16200/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 102 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as these 12 * 1 code bit b seen in Figure 103 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₆,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₄,

Code bit b ₅Give sign bit y ₅,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₇,

Code bit b ₉Give sign bit y ₁₀,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 16200 bits and encoding rate are 3/4 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 102 in 1 the situation in addition that Figure 103 B illustrates at the LDPC code.

According to Figure 103 B, replacement section 32 is replaced, with according to the allocation rule of Figure 102 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₉,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₆,

Code bit b ₉Give sign bit y ₁₁,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

It is that code length N is that 64800 bits and encoding rate are 3/4 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 104 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 104 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 3 code bit group Gb ₁, Gb ₂And Gb ₃

In Figure 104 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₈Belong to a yard bit group Gb ₂And code bit b ₉To b ₁₁Belong to a yard bit group Gb ₃

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 104 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 104 B, as Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 64800 bits and encoding rate are 3/4 LDPC code, modulator approach is that 1024QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 105 illustrates at the LDPC code.

In the allocation rule of Figure 105, regulation group collection information (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₄, 2), (Gb ₃, Gy ₅, 1) and (Gb ₃, Gy ₆, 2).

Therefore, according to the allocation rule of Figure 105, regulation:

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₄, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 4th ₄Two sign bits,

According to group collection information (Gb ₃, Gy ₅, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₃, Gy ₆, 2), the code bit group Gb that the probability of error the 3rd is good ₅Two code bits be assigned to the good sign bit group Gy of the probability of error the 6th ₆Two sign bits.

Figure 106 illustrates the example according to the code bit permutation of the allocation rule of Figure 105.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 3/4 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 105 in 1 the situation in addition to Figure 106 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 3/4 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (64800/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 105 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as these 12 * 1 code bit b seen in Figure 106 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₆,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₄,

Code bit b ₅Give sign bit y ₅,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₇,

Code bit b ₉Give sign bit y ₁₀,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 64800 bits and encoding rate are 3/4 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 105 in 1 the situation in addition that Figure 106 B illustrates at the LDPC code.

According to Figure 106 B, replacement section 32 is replaced, with according to the allocation rule of Figure 105 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₂Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₉,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₆,

Code bit b ₉Give sign bit y ₁₁,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

It is that code length N is that 16200 bits and encoding rate are 4/5 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 107 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 107 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 3 code bit group Gb ₁, Gb ₂And Gb ₃

In Figure 107 A, code bit b ₀To b ₈Belong to a yard bit group Gb ₁Code bit b ₉Belong to a yard bit group Gb ₂And code bit b ₁₀And b ₁₁Belong to a yard bit group Gb ₃

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 107 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 107 B, as Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 16200 bits and encoding rate are 4/5 LDPC code, modulator approach is that 4096QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 108 illustrates at the LDPC code.

In the allocation rule of Figure 108, regulation group collection information (Gb ₁, Gy ₁, 2), (Gb ₁, Gy ₂, 2), (Gb ₁, Gy ₃, 2), (Gb ₁, Gy ₄, 2), (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₆, 1), (Gb ₃, Gy ₅, 1) and (Gb ₃, Gy ₆, 1).

Therefore, according to the allocation rule of Figure 108, regulation:

According to group collection information (Gb ₁, Gy ₁, 2), the code bit group Gb that the probability of error is best ₁Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₁, Gy ₂, 2), the code bit group Gb that the probability of error is best ₁Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₁, Gy ₃, 2), the code bit group Gb that the probability of error is best ₁Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₁, Gy ₄, 2), the code bit group Gb that the probability of error is best ₁Two code bits be assigned to the good sign bit group Gy of the probability of error the 4th ₄Two sign bits,

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₆, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit, and

According to group collection information (Gb ₃, Gy ₅, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₃, Gy ₆, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit.

Figure 109 illustrates the example according to the code bit permutation of the allocation rule of Figure 108.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 4/5 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 108 in 1 the situation in addition to Figure 109 A.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 4/5 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (16200/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 108 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as 12 * 1 code bit b seen in Figure 109 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₆,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₄,

Code bit b ₅Give sign bit y ₅,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₇,

Code bit b ₉Give sign bit y ₁₀,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 16200 bits and encoding rate are 4/5 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 108 in 1 the situation in addition that Figure 109 B illustrates at the LDPC code.

According to Figure 109 B, replacement section 32 is replaced, with according to the allocation rule of Figure 108 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₆,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₉,

Code bit b ₉Give sign bit y ₁₁,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

It is that code length N is that 64800 bits and encoding rate are 4/5 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 110 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 110 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 5 code bit group Gb ₁, Gb ₂, Gb ₃, Gb ₄And Gb ₅

In Figure 110 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁Belong to a yard bit group Gb ₂Code bit b ₂To b ₈Belong to a yard bit group Gb ₃Code bit b ₉Belong to a yard bit group Gb ₄And code bit b ₁₀And b ₁₁Belong to a yard bit group Gb ₅

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 110 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 110 B, as Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 64800 bits and encoding rate are 4/5 LDPC code, modulator approach is that 4096QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 111 illustrates at the LDPC code.

In the allocation rule of Figure 111, regulation group collection information (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₁, 1), (Gb ₃, Gy ₁, 1), (Gb ₃, Gy ₂, 2), (Gb ₃, Gy ₃, 2), (Gb ₃, Gy ₄, 2), (Gb ₄, Gy ₆, 1), (Gb ₅, Gy ₅, 1) and (Gb ₅, Gy ₆, 1).

Therefore, according to the allocation rule of Figure 111, regulation:

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₁, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₂, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₃, Gy ₃, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₃, Gy ₄, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 4th ₄Two sign bits,

According to group collection information (Gb ₄, Gy ₆, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit,

According to group collection information (Gb ₅, Gy ₅, 1), the code bit group Gb that the probability of error the 5th is good ₅A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₅, Gy ₆, 1), the code bit group Gb that the probability of error the 5th is good ₅A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit.

Figure 112 illustrates the example according to the code bit permutation of the allocation rule of Figure 111.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 4/5 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 111 in 1 the situation in addition to Figure 112 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (64800/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 111 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as 12 * 1 code bit b seen in Figure 112 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₆,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₄,

Code bit b ₅Give sign bit y ₅,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₇,

Code bit b ₉Give sign bit y ₁₀,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 64800 bits and encoding rate are 4/5 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 111 in 1 the situation in addition that Figure 112 B illustrates at the LDPC code.

According to Figure 112 B, replacement section 32 is replaced, with according to the allocation rule of Figure 111 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₉,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₆,

Code bit b ₉Give sign bit y ₁₁,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

It is that code length N is that 16200 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 113 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 113 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 4 code bit group Gb ₁, Gb ₂, Gb ₃And Gb ₄

In Figure 113 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₈Belong to a yard bit group Gb ₂Code bit b ₉Belong to a yard bit group Gb ₃And code bit b ₁₀And b ₁₁Belong to a yard bit group Gb ₄

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 113 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 113 B, as Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄Sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 16200 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 111 illustrates at the LDPC code.

In the allocation rule of Figure 111, regulation group collection information (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₄, 2), (Gb ₃, Gy ₆, 1), (Gb ₄, Gy ₅, 1) and (Gb ₄, Gy ₆, 1).

Therefore, according to the allocation rule of Figure 111, regulation:

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₄, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 4th ₄Two sign bits,

According to group collection information (Gb ₃, Gy ₆, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit,

According to group collection information (Gb ₄, Gy ₅, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₄, Gy ₆, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit.

Figure 115 illustrates the example according to the code bit permutation of the allocation rule of Figure 114.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 114 in 1 the situation in addition to Figure 115 A.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (16200/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 114 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as these 12 * 1 code bit b seen in Figure 115 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₆,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₄,

Code bit b ₅Give sign bit y ₅,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₇,

Code bit b ₉Give sign bit y ₁₀,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 16200 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 114 in 1 the situation in addition that Figure 115 B illustrates at the LDPC code.

According to Figure 115 B, replacement section 32 is replaced, with according to the allocation rule of Figure 114 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₉,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₆,

Code bit b ₉Give sign bit y ₁₁,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

It is that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 116 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 116 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 3 code bit group Gb ₁, Gb ₂And Gb ₃

In Figure 116 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁To b ₉Belong to a yard bit group Gb ₂And code bit b ₁₀And b ₁₁Belong to a yard bit group Gb ₃

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 116 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 116 B, as Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄Sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 117 illustrates at the LDPC code.

In the allocation rule of Figure 117, regulation group collection information (Gb ₁, Gy ₅, 1), (Gb ₂, Gy ₁, 2), (Gb ₂, Gy ₂, 2), (Gb ₂, Gy ₃, 2), (Gb ₂, Gy ₄, 2), (Gb ₂, Gy ₆, 1), (Gb ₃, Gy ₅, 1) and (Gb ₃, Gy ₆, 1).

Therefore, according to the allocation rule of Figure 117, regulation:

According to group collection information (Gb ₁, Gy ₅, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₂, Gy ₁, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the best sign bit group Gy of the probability of error ₁Two sign bits,

According to group collection information (Gb ₂, Gy ₂, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₂, Gy ₃, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₂, Gy ₄, 2), the second-best code of probability of error bit group Gb ₂Two code bits be assigned to the good sign bit group Gy of the probability of error the 4th ₄Two sign bits,

According to group collection information (Gb ₂, Gy ₆, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit,

According to group collection information (Gb ₃, Gy ₅, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit, and

According to group collection information (Gb ₃, Gy ₆, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit.

Figure 118 illustrates the example according to the code bit permutation of the allocation rule of Figure 117.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 117 in 1 the situation in addition to Figure 118 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (64800/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 117 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as these 12 * 1 code bit b seen in Figure 118 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₆,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₄,

Code bit b ₅Give sign bit y ₅,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₇,

Code bit b ₉Give sign bit y ₁₀,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 64800 bits and encoding rate are 5/6 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 117 in 1 the situation in addition that Figure 118 B illustrates at the LDPC code.

According to Figure 118 B, replacement section 32 is replaced, with according to the allocation rule of Figure 117 12 * 1 ((=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₉,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₁₁,

Code bit b ₉Give sign bit y ₆,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

It is that code length N is that 16200 bits and encoding rate are 8/9 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 119 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 119 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 5 code bit group Gb ₁, Gb ₂, Gb ₃, Gb ₄And Gb ₅

In Figure 119 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁Belong to a yard bit group Gb ₂Code bit b ₂To b ₉Belong to a yard bit group Gb ₃Code bit b ₁₀Belong to a yard bit group Gb ₄And code bit b ₁₁Belong to a yard bit group Gb ₅

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 119 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 119 B, as Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄Sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 16200 bits and encoding rate are 8/9 LDPC code, modulator approach is that 4096QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 120 illustrates at the LDPC code.

In the allocation rule of Figure 120, regulation group collection information (Gb ₁, Gy ₆, 1), (Gb ₂, Gy ₁, 1), (Gb ₃, Gy ₁, 1), (Gb ₃, Gy ₂, 2), (Gb ₃, Gy ₃, 2), (Gb ₃, Gy ₄, 2), (Gb ₃, Gy ₅, 1), (Gb ₄, Gy ₆, 1) and (Gb ₅, Gy ₅, 1).

Therefore, according to the allocation rule of Figure 120, regulation:

According to group collection information (Gb ₁, Gy ₆, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit,

According to group collection information (Gb ₂, Gy ₁, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₁, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₂, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₃, Gy ₃, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₃, Gy ₄, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 4th ₄Two sign bits,

According to group collection information (Gb ₃, Gy ₅, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₄, Gy ₆, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit, and

According to group collection information (Gb ₅, Gy ₅, 1), the code bit group Gb that the probability of error the 5th is good ₅A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit.

Figure 121 illustrates the example according to the code bit permutation of the allocation rule of Figure 120.

Particularly, to illustrate at the LDPC code be that code length N is that 16200 bits and encoding rate are 8/9 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 120 in 1 the situation in addition to Figure 121 A.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 8/9 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (16200/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 120 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as these 12 * 1 code bit b seen in Figure 121 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₁₀,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₅,

Code bit b ₇Give sign bit y ₆,

Code bit b ₈Give sign bit y ₈,

Code bit b ₉Give sign bit y ₇,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 16200 bits and encoding rate are 8/9 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 120 in 1 the situation in addition that Figure 121 B illustrates at the LDPC code.

According to Figure 121 B, replacement section 32 is replaced, with according to the allocation rule of Figure 120 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₁₁,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₉,

Code bit b ₉Give sign bit y ₆,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

It is that code length N is that 64800 bits and encoding rate are 8/9 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 122 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 122 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 5 code bit group Gb ₁, Gb ₂, Gb ₃, Gb ₄And Gb ₅

In Figure 122 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁Belong to a yard bit group Gb ₂Code bit b ₂To b ₉Belong to a yard bit group Gb ₃Code bit b ₁₀Belong to a yard bit group Gb ₄And code bit b ₁₁Belong to a yard bit group Gb ₅

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 122 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 122 B, as Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄Sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 64800 bits and encoding rate are 8/9 LDPC code, modulator approach is that 4096QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 123 illustrates at the LDPC code.

In the allocation rule of Figure 123, regulation group collection information (Gb ₁, Gy ₆, 1), (Gb ₂, Gy ₁, 1), (Gb ₃, Gy ₁, 1), (Gb ₃, Gy ₂, 2), (Gb ₃, Gy ₃, 2), (Gb ₃, Gy ₄, 2), (Gb ₃, Gy ₅, 1), (Gb ₄, Gy ₆, 1) and (Gb ₅, Gy ₅, 1).

Therefore, according to the allocation rule of Figure 123, regulation:

According to group collection information (Gb ₁, Gy ₆, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit,

According to group collection information (Gb ₂, Gy ₁, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₁, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₂, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₃, Gy ₃, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₃, Gy ₄, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 4th ₄Two sign bits,

According to group collection information (Gb ₃, Gy ₅, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₄, Gy ₆, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit, and

According to group collection information (Gb ₅, Gy ₅, 1), the code bit group Gb that the probability of error the 5th is good ₅A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit.

Figure 124 illustrates the example according to the code bit permutation of the allocation rule of Figure 123.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 8/9 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 123 in 1 the situation in addition to Figure 124 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 8/9 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (64800/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 123 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as these 12 * 1 code bit b seen in Figure 124 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₁₀,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₅,

Code bit b ₇Give sign bit y ₆,

Code bit b ₈Give sign bit y ₈,

Code bit b ₉Give sign bit y ₇,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 64800 bits and encoding rate are 8/9 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 123 in 1 the situation in addition that Figure 124 B illustrates at the LDPC code.

According to Figure 124 B, replacement section 32 is replaced, with according to the allocation rule of Figure 123 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₁₁,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₉,

Code bit b ₉Give sign bit y ₆,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

It is that code length N is that 64800 bits and encoding rate are 9/10 LDPC code, modulator approach is that 4096QAM and multiplier b are code bit group and the sign bit groups in 1 the situation in addition that Figure 125 illustrates at the LDPC code.

In this case, according to the difference on the probability of error, seen in Figure 125 A, from memory 31 read 12 * 1 (=mb) individual code bit can be divided into 5 code bit group Gb ₁, Gb ₂, Gb ₃, Gb ₄And Gb ₅

In Figure 125 A, code bit b ₀Belong to a yard bit group Gb ₁Code bit b ₁Belong to a yard bit group Gb ₂Code bit b ₂To b ₉Belong to a yard bit group Gb ₃Code bit b ₁₀Belong to a yard bit group Gb ₄And code bit b ₁₁Belong to a yard bit group Gb ₄

When modulator approach is 4096QAM and multiplier when being 1, according to the difference on the probability of error, seen in Figure 125 B, 12 * 1 (=mb) individual sign bit can be divided into 6 sign bit group Gy ₁, Gy ₂, Gy ₃, Gy ₄, Gy ₅And Gy ₆

In Figure 125 B, as Figure 95 B, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄Sign bit y ₈And y ₉Belong to sign bit group Gy ₅And sign bit y ₁₀And y ₁₁Belong to sign bit group Gy ₆

It is that code length N is that 64800 bits and encoding rate are 9/10 LDPC code, modulator approach is that 4096QAM and multiplier b are the allocation rule in 1 the situation in addition that Figure 126 illustrates at the LDPC code.

In the allocation rule of Figure 126, regulation group collection information (Gb ₁, Gy ₆, 1), (Gb ₂, Gy ₁, 1), (Gb ₃, Gy ₁, 1), (Gb ₃, Gy ₂, 2), (Gb ₃, Gy ₃, 2), (Gb ₃, Gy ₄, 2), (Gb ₃, Gy ₅, 1), (Gb ₄, Gy ₆, 1) and (Gb ₅, Gy ₅, 1).

Therefore, according to the allocation rule of Figure 126, regulation:

According to group collection information (Gb ₁, Gy ₆, 1), the code bit group Gb that the probability of error is best ₁A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit,

According to group collection information (Gb ₂, Gy ₁, 1), the second-best code of probability of error bit group Gb ₂A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₁, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the best sign bit group Gy of the probability of error ₁A sign bit,

According to group collection information (Gb ₃, Gy ₂, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the second-best sign bit group of probability of error Gy ₂Two sign bits,

According to group collection information (Gb ₃, Gy ₃, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 3rd ₃Two sign bits,

According to group collection information (Gb ₃, Gy ₄, 2), the code bit group Gb that the probability of error the 3rd is good ₃Two code bits be assigned to the good sign bit group Gy of the probability of error the 4th ₄Two sign bits,

According to group collection information (Gb ₃, Gy ₅, 1), the code bit group Gb that the probability of error the 3rd is good ₃A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit,

According to group collection information (Gb ₄, Gy ₆, 1), the code bit group Gb that the probability of error the 4th is good ₄A code bit be assigned to the good sign bit group Gy of the probability of error the 6th ₆A sign bit, and

According to group collection information (Gb ₅, Gy ₅, 1), the code bit group Gb that the probability of error the 5th is good ₅A code bit be assigned to the good sign bit group Gy of the probability of error the 5th ₅A sign bit.

Figure 127 illustrates the example according to the code bit permutation of the allocation rule of Figure 126.

Particularly, to illustrate at the LDPC code be that code length N is that 64800 bits and encoding rate are 9/10 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the first example of the code bit permutation of the allocation rule of Figure 126 in 1 the situation in addition to Figure 127 A.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 9/10 LDPC code, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for column direction * line direction for the code bit of the memory 31 of (64800/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32 (Figure 16 and Figure 17).

Replacement section 32 is according to the allocation rule of Figure 126 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Replace, so that such as these 12 * 1 code bit b seen in Figure 127 A ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that for example are assigned to 1 ₀To y ₁₁

Particularly, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₁₀,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₅,

Code bit b ₇Give sign bit y ₆,

Code bit b ₈Give sign bit y ₈,

Code bit b ₉Give sign bit y ₇,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

It is that code length N is that 64800 bits and encoding rate are 9/10 LDPC code, modulator approach is that 4096QAM and multiplier b are according to the second example of the code bit permutation of the allocation rule of Figure 126 in 1 the situation in addition that Figure 127 B illustrates at the LDPC code.

According to Figure 127 B, replacement section 32 is replaced, with according to the allocation rule of Figure 126 12 * 1 (=mb) individual code bit b to reading from memory 31 ₀To b ₁₁Carry out following distribution: distribute

Code bit b ₀Give sign bit y ₁₁,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₀,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₇,

Code bit b ₈Give sign bit y ₉,

Code bit b ₉Give sign bit y ₆,

Code bit b ₁₀Give sign bit y ₁₀, and

Code bit b ₁₁Give sign bit y ₈

Although altogether having described 22 kinds of different replacement Treatment (comprises with 1024QAM and 4096QAM these 2 kinds of modulator approaches code length N with 64800 bits and different encoding rates 2/3,3/4,4/5,5/6,8/9 12 kinds of different replacement Treatment of modulating with 6 kinds of 9/10 different LDPC codes, and with these 2 kinds of modulator approaches of 1024QAM and 4096QAM to code length N with 16200 bits and different encoding rates 2/3,3/4,4/5,5/6 10 kinds of different replacement Treatment of modulating with 5 kinds of 8/9 different LDPC codes) as the replacement Treatment according to new method of replacing, for example, for example 4 kinds of different method of replacing are as the method for replacing that is used for the code bit is replaced in employing, and these 22 kinds of different replacement Treatment can be undertaken by one of these 4 kinds of method of replacing.

Particularly, when code length N is that 64800 bits or 16200 bits and encoding rate are 3/4,4/5 or 5/6 LPDC code when modulating with 1024QAM, replacement Treatment can be undertaken by the method for replacing that for example Figure 70 A illustrates, its distribution

Code bit b ₀Give sign bit y ₆,

Code bit b ₁Give sign bit y ₄,

Code bit b ₂Give sign bit y ₈,

Code bit b ₃Give sign bit y ₅,

Code bit b ₄Give sign bit y ₀,

Code bit b ₅Give sign bit y ₂,

Code bit b ₆Give sign bit y ₁,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

In addition, when code length N is that 64800 bits or 16200 bits and encoding rate are 3/4,4/5 or 5/6 LPDC code when modulating with 4096QAM, replacement Treatment can be undertaken by the method for replacing that for example Figure 103 A illustrates, its distribution

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₆,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₄,

Code bit b ₅Give sign bit y ₅,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₇,

Code bit b ₉Give sign bit y ₁₀,

Code bit b ₉Give sign bit y ₁₁, and

Code bit b ₉Give sign bit y ₉

In addition, when code length N is that 64800 bits or 16200 bits and encoding rate are that 2/3 or 8/9 LPDC code and code length N are that 64800 bits and encoding rate are that 9/10 LPDC code is when modulating with 1024QAM, replacement Treatment can be carried out its distribution by the method for replacing that for example Figure 64 A illustrates

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₆,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₉, and

Code bit b ₉Give sign bit y ₇

In addition, when code length N is that 64800 bits or 16200 bits and encoding rate are that 2/3 or 8/9 LPDC code and code length N are that 64800 bits and encoding rate are that 9/10 LPDC code is when modulating with 4096QAM, replacement Treatment can be undertaken by the method for replacing that for example Figure 97 A illustrates, its distribution

Code bit b ₀Give sign bit y ₁₀,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₃,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₅,

Code bit b ₇Give sign bit y ₆,

Code bit b ₈Give sign bit y ₈,

Code bit b ₉Give sign bit y ₇,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

Above is that the situation of 1024QAM and situation that modulator approach is 4096QAM have been described new method of replacing about modulator approach, and hereinafter describes the layout of the symbol (corresponding to signaling point) of each modulator approach.

Figure 128 illustrates the layout of 1024 symbols (corresponding to signaling point) on the IQ plane in the situation that quadrature modulation section 27 at Fig. 8 carries out 1024QAM.

Particularly, Figure 128 illustrates from the symbol of the 256QAM of DVB-T.2 and arranges the method that the symbol of recursively determining 1024QAM is arranged.

It should be noted that in Figure 128 the coordinate (I coordinate and Q coordinate) of (i, q) expression symbol on the IQ plane.

Simultaneously, C ₂₅₆(i, q) is illustrated in for designated symbols the symbol number that is positioned at the symbol of coordinate (i, q) position in the numbering (hereinafter being called symbol number) of 256 symbols that sequentially impose on 256QAM (imposing on symbol).Hereinafter, the symbol that is positioned at the 256QAM of coordinate (i, q) position is also referred to as C ₂₅₆(i, q) individual symbol.

In addition, C ₁₀₂₄(i, q) is illustrated in the symbol number that is positioned at the symbol of coordinate (i, q) position in 1024 symbols of 1024QAM.Hereinafter, the symbol that is positioned at the 1024QAM of coordinate (i, q) position is also referred to as C ₁₀₂₄(i, q) individual symbol.

Now, if in the parallel first quartile of transferring on the IQ plane of all 256 symbols with 256QAM, the C of the 256QAM after the parallel transfer then ₂₅₆(i, q) individual symbol becomes the C of 1024QAM ₁₀₂₄(i, q) individual=C ₂₅₆(i, q) individual symbol.

In addition, if parallel 256 symbols transferring to the 256QAM in the first quartile are moved axisymmetrically the C of the 256QAM after then symmetry moves about I ₂₅₆(i, q) individual symbol becomes the C of 1024QAM ₁₀₂₄(i ,-q) individual=(C ₂₅₆(i, q)+256) individual symbol.

In addition, if parallel 256 symbols transferring to the 256QAM in the first quartile are moved axisymmetrically the C of the 256QAM after then symmetry moves about Q ₂₅₆(i, q) individual symbol becomes the C of 1024QAM ₁₀₂₄(-i, q) individual=(C ₂₅₆(i, q)+256 * 2) individual symbol.

In addition, if parallel 256 symbols transferring to the 256QAM in the first quartile are moved the C of the 256QAM after then symmetry moves about origin symmetry ground ₂₅₆(i, q) individual symbol becomes the C of 1024QAM ₁₀₂₄(i ,-q) individual=(C ₂₅₆(i, q)+256 * 3) individual symbol.

It should be noted that for above-mentioned X symbol the value of its value representation symbol when X represents with binary scale (signaling point that sign map arrives).

For example, work as C ₂₅₆(i, q)=25 o'clock, C ₂₅₆The value of symbol of (i, q) individual symbol is 00011001B (B represents that the value of above numeral represents with binary scale).In addition, for example, work as C ₁₀₂₄(i, q)=823, the C ₁₀₂₄The value of symbol of (i, q) individual symbol is 1100110111B.

In addition, the C in the second quadrant (i＜0, q＞0) ₁₀₂₄(-i, q) individual=(C ₂₅₆(i, q)+256 * 2) individual symbol is arranged in parallel to the C of 256 symbols of the 256QAM of first quartile ₂₅₆(i, q) individual symbol is by the position that moves to symmetrically about the Q axis, and C ₁₀₂₄(-i, q) individual=(C ₂₅₆(i, q)+256 * 2) value of symbol of individual symbol adopts by will be as the 10B of the binary representation of 2 in 256 * 2 and the C of usefulness binary number representation ₂₅₆Two higher order bits additions of the value of (i, q) and the result's that obtains value.

In 1024QAM, the amount of bits m of a symbol is 10, thereby the sign bit of a symbol begins to be expressed as (y from the highest significant bit ₀, y ₁..., y _M-1)=(y ₀, y ₁, y ₂, y ₃, y ₄, y ₅, y ₆, y ₇, y ₈, y ₉).

For example, work as C ₁₀₂₄(i, q)=823, the C ₁₀₂₄The value of symbol of (i, q) individual symbol (i.e. 10 sign bit (y ₀, y ₁, y ₂, y ₃, y ₄, y ₅, y ₆, y ₇, y ₈, y ₉)) be (1,1,0,0,1,1,0,1,1,1).

Like this, as mentioned in reference to Figure 62 to Figure 94 described, sign bit y ₀And y ₁Belong to sign bit group Gy ₁Sign bit y ₂And y ₃Belong to sign bit group Gy ₂Sign bit y ₄And y ₅Belong to sign bit group Gy ₃Sign bit y ₆And y ₇Belong to sign bit group Gy ₄And sign bit y ₈And y ₉Belong to sign bit group Gy ₅

In addition, the sign bit group Gy of subscript j less _jSign bit present the relatively preferably probability of error (presenting the relatively high tolerance limit to error).

Figure 129 illustrates the layout of 4096 symbols (corresponding to signaling point) on the IQ plane in the situation that quadrature modulation section 27 at Fig. 8 carries out 4096QAM.

It should be noted that in Figure 129 C ₄₀₉₆Be positioned at the symbol number of the symbol of coordinate (i, q) position in 4096 symbols of (i, q) expression 4096QAM.Hereinafter, the symbol that is positioned at the 4096QAM of coordinate (i, q) position is also referred to as C ₄₀₉₆(i, q) individual symbol.

Now, if with in the first quartile on all 1024 the parallel IQ of transferring to of symbol planes of the 1024QAM that describes among Figure 128, the C of the 1024QAM after the parallel transfer then ₁₀₂₄(i, q) individual symbol becomes the C of 4096QAM ₄₀₉₆(i, q) individual=C ₁₀₂₄(i, q) individual symbol.

In addition, if parallel 1024 symbols transferring to the 1024QAM in the first quartile are moved axisymmetrically the C of the 1024QAM after then symmetry moves about I ₁₀₂₄(i, q) individual symbol becomes the C of 4096QAM ₄₀₉₆(i ,-q) individual=(C ₄₀₉₆(i, q)+1024) individual symbol.

In addition, if parallel 1024 symbols transferring to the 1024QAM in the first quartile are moved axisymmetrically the C of the 1024QAM after then symmetry moves about Q ₁₀₂₄(i, q) individual symbol becomes the C of 4096QAM ₄₀₉₆(-i, q) individual=(C ₄₀₉₆(i, q)+1024 * 2) individual symbol.

In addition, if parallel 1024 symbols transferring to the 1024QAM in the first quartile are moved the C of the 1024QAM after then symmetry moves about origin symmetry ground ₁₀₂₄(i, q) individual symbol becomes the C of 4096QAM ₄₀₉₆(i ,-q) individual=(C ₄₀₉₆(i, q)+1024 * 3) individual symbol.

For the sign bit of the symbol of the sign bit of the symbol of 1024QAM (Figure 128) and 4096QAM (Figure 129), same strong bit and the weak bit that is similar to description in Figure 12 etc. that exist.

Figure 130 is illustrated in to Figure 133 and carries out according in the situation of the replacement Treatment of new method of replacing and at the simulation result that does not carry out according to the BER (bit error rate (BER)) in the situation of the replacement Treatment of new method of replacing.

Particularly, Figure 130 illustrate length N be 16200 and encoding rate to be 2/3,3/4,3/5,5/6 and 8/9 LDPC code be confirmed as object and adopt 1024QAM as the BER in the situation of modulator approach.

Figure 131 illustrate length N be 64800 and encoding rate to be 2/3,3/4,3/5,5/6,8/9 and 9/10 LDPC code be confirmed as object and adopt 1024QAM as the BER in the situation of modulator approach.

Figure 132 illustrate length N be 16200 and encoding rate to be 2/3,3/4,3/5,5/6 and 8/9 LDPC code be confirmed as object and adopt 4096QAM as the BER in the situation of modulator approach.

Figure 133 illustrate length N be 64800 and encoding rate to be 2/3,3/4,3/5,5/6,8/9 and 9/10 LDPC code be confirmed as object and adopt 4096QAM as the BER in the situation of modulator approach.

It should be noted that at Figure 130 multiplier b in Figure 133 be 1.

In addition, in Figure 133, transverse axis represents E at Figure 130 _s/ N ₀(noise power of each symbol is to the ratio of signal power), the longitudinal axis represents BER.In addition, solid line is illustrated in the BER that carries out according in the situation of the replacement Treatment of new method of replacing, and dotted line is illustrated in the BER in the situation of not carrying out replacement Treatment.

From Figure 130 to Figure 133, can find out with another situation of not carrying out according to the replacement Treatment of new method of replacing and compare, show improve BER and improved tolerance limit to error according to the replacement Treatment of new method of replacing.

Should note, although in the present embodiment, for convenience of description, the code bits that 32 pairs of replacement sections in the demodulation multiplexer 25 are read from memory 31 carry out replacement Treatment, but can be by the sense code bit controls to carry out replacement Treatment to writing yard bit in memory 31 or from memory 31.

Particularly, can for example carry out by the following method replacement Treatment: therefrom the address of sense code bit (reading the address) controlled, so that reading according to the order of the code bit after the displacement of sense code bit carried out from memory 31.

Figure 134 is the block diagram of ios dhcp sample configuration IOS DHCP of the receiving equipment 12 of Fig. 7.

With reference to Figure 134, receiving equipment 12 is for the data processing equipment that receives modulation signal from transmitting apparatus 11 (Fig. 7), and it comprises quadrature demodulation section 51, separates mapping section 52, deinterleaver 53 and LDPC lsb decoder 56.

Quadrature demodulation section 51 receives modulation signal from transmitting apparatus 11, and carry out quadrature demodulation system, then, the symbol that obtains is offered the mapping section 52 that separates as quadrature demodulation result processed (value on I axle and the Q axle).

Separate mapping section 52 and separate mapping, be about to code bit that signaling point from quadrature demodulation section 51 is converted to the LDPC code so that its symbol is turned to symbol, and the code bit is offered deinterleaver 53.

Deinterleaver 53 comprises that multiplexer (MUX) 54 and row reverse deinterleaver 55, and the symbol of the sign bit of explaining mapping section 52 by oneself is carried out deinterleaving.

Particularly, the symbol that 54 pairs of multiplexers are explained the sign bit of mapping section 52 by oneself carries out the inverse permutation corresponding with the replacement Treatment of the demodulation multiplexer 25 of Fig. 8 and processes (the contrary of replacement Treatment processed), that is the location restore of the code bit (sign bit) of the LDPC code of, replaced processing being replaced is processed to the inverse permutation of origin-location.Then, multiplexer 54 result that the LDPC code that obtains is processed as inverse permutation offers row and reverses deinterleaver 55.

Row reverse deinterleaver 55 carries out with the row of Fig. 8 reverse that interleaver carries out row of processing as rearrangement and reverse the corresponding row that interweave and reverse deinterleaving (row reverse the contrary processing that interweaves), namely, for example reverse deinterleaving as what contrary rearrangement was processed as following: to the LDPC code from multiplexer 54, the layout that is used as row that rearrangement processes and reverses the code bit of the LDPC code that changes of interweaving is returned to original layout.

Particularly, row reverse deinterleaver 55 and write for the memory of deinterleaving and read a code bit that writes from this deinterleaving memory by the code bit with the LDPC code and be listed as and reverse deinterleaving, and the memory 31 shown in this memory is configured to wait with Figure 22 is similar.

It should be noted that at row and reverse in the deinterleaver 55, writing of code bit is to use the address of reading when from memory 31 sense code to carry out at the line direction of deinterleaving memory as writing address.And reading of code bit is to carry out at the column direction of deinterleaving memory as reading the address with the writing address when with code bit write memory 31.

The LDPC code that obtains reverses the result of deinterleaving as row and is reversed deinterleaver 55 from row and offers LDPC lsb decoder 56.

At this, although be to interweave and in sequence odd-even, the row of replacement Treatment reverse and interweave and replacement Treatment obtains by reversing by odd-even, row from separating LDPC code that mapping section 52 offers deinterleaver 53,53 of deinterleavers carry out processing and reversing the row that interweave corresponding to row and reverse deinterleaving corresponding to the inverse permutation of replacement Treatment.Therefore, do not carry out the odd even deinterleaving (the contrary of odd-even processed) corresponding to odd-even, be about to be returned to by the layout of the code bit of the altered LDPC code of odd-even the odd even deinterleaving of original layout.

Therefore, carried out that inverse permutation is processed and row reverse deinterleaving but the LDPC code that do not carry out the odd even deinterleaving is offered LDPC lsb decoder 56 from deinterleaver 53 (row of deinterleaver 53 reverse deinterleaver 55).

LDPC lsb decoder 56 usefulness conversion parity matrixs come the LDPC code from deinterleaver 53 is carried out the LDPC decoding, and will be as the data output of the acquisition of the LDPC decoded result decoded result as object data, described conversion parity matrix is to obtain by parity check matrix H (being used for the LDPC coding that the LDPC coding section 21 by Fig. 8 carries out) is carried out column permutation (corresponding to odd-even) at least.

Figure 135 is the flow chart that illustrates the reception ﹠ disposal that the receiving equipment 12 by Figure 134 carries out.

In step 111, quadrature demodulation section 51 receives modulation signal from transmitting apparatus 11.Then, process entering step S112,51 pairs of modulation signals of quadrature demodulation section carry out quadrature demodulation systems in arranging S112.Quadrature demodulation section 51 will offer as the signaling point of the result's of quadrature demodulation system acquisition and separate mapping section 52, process afterwards from step S112 and enter step S113.

At step S113, separate the solution mapping that mapping section 52 carries out the signaling point from quadrature demodulation section 51 is converted to symbol, and the code bit is offered deinterleaver 53, process afterwards entering step S114.

At step S114, the symbol that 53 pairs of deinterleavers are explained the sign bit of mapping section 52 by oneself carries out deinterleaving, processes afterwards entering step S115.

Particularly, at step S114, the symbol that 54 pairs of the multiplexers in the deinterleaver 53 are explained the sign bit of mapping section 52 by oneself carries out inverse permutation to be processed, and will offer row as the LDPC code of the acquisition of inverse permutation result and reverse deinterleaver 55.

Row reverse 55 pairs of LDPC codes from multiplexer 54 of deinterleaver and are listed as and reverse deinterleaving, and will offer LDPC lsb decoder 56 as the LDPC code that row reverse deinterleaving result's acquisition.

At step S115, LDPC lsb decoder 56 uses the conversion parity matrixs that the LDPC code that reverses deinterleaver 55 from row is carried out the LDPC decoding, and the data that obtain by the LDPC decoding of output are as the decoded result of object data.Afterwards processing finishes.Described conversion parity matrix is to obtain by parity check matrix H (LDPC that carries out for the LDPC coding section 21 by Fig. 8 encodes) is carried out column permutation (corresponding to odd-even) at least.

The reception ﹠ disposal that it should be noted that Figure 135 repeats.

Similarly, similar with situation among Fig. 8 in Figure 134, for convenience of description, be used for carrying out the multiplexer 54 that inverse permutation processes and be used for being listed as the row that reverse deinterleaving reversing deinterleaver 55 and being configured to separated from one another.But multiplexer 54 and row reverse deinterleaver 55 and can also be configured to be integrated with each other.

In addition, do not reverse when interweaving when the transmitting apparatus 11 of Fig. 8 is not listed as, row then need to be set in the receiving equipment 12 of Figure 134 reverse deinterleaver 55.

Now, the LDPC decoding of the LDPC lsb decoder 56 that further describes by Figure 134 being carried out.

The LDPC lsb decoder 56 of Figure 134 use the conversion parity matrixs to as mentioned above from row reverse deinterleaver 55 carrying out inverse permutation process and row reverse deinterleaving but the LDPC code that do not carry out the odd even deinterleaving carries out the LDPC decoding, described conversion parity matrix is to obtain by parity check matrix H (being used for the LDPC coding that the LDPC coding section 21 by Fig. 8 carries out) is carried out column permutation (corresponding to odd-even) at least.

At this, decode to suppress the LDPC decoding (for example referring to the open No.2004-343170 of Japanese Patent Laid) of circuit scale by the LDPC that uses the conversion parity matrix when having proposed in the past in operating frequency can being suppressed at enough enforceable scopes.

The LDPC decoding of previously presented use conversion parity matrix is at first described to Figure 139 with reference to Figure 136 thus.

It is 90 and encoding rate is the example of the parity check matrix H of 2/3 LDPC code that Figure 136 illustrates code length N.

It should be noted that in Figure 136 0 usefulness point (.) expression (this also is applicable to Figure 137 described below and Figure 138 similarly).

In the parity check matrix H of Figure 136, parity matrix has step structure.

Figure 137 illustrate by the line replacement of the parity check matrix H of Figure 136 being used expression formula (11) and expression formula (12) and parity check matrix H that column permutation obtains '.

Line replacement: 6s+t+1 is capable → and 5t+s+1 is capable ... (11)

Column permutation: 6x+y+61 row the → the 5y+x+61 row ... (12)

Yet in expression formula (11) and (12), s, t, x and y are respectively the integers in 0≤s＜5,0≤t＜6,0≤x＜5 and 0≤t＜6 scopes.

Line replacement according to expression formula (11), replace as follows: will number divided by 6 rear remainders is 1 the 1st, 7,13,19 and 25 line replacements to the 1,2,3,4 and 5 row, and will to number divided by 6 rear remainders be 2 the 2nd, 8,14,20 and 26 line replacements to the 6,7,8,9 and 10 row.

On the other hand, column permutation according to expression formula (12), the 61st row and its row (parity matrix) are subsequently replaced, make call number divided by 6 rear remainders be 1 the 61st, 67,73,79 and 85 row be displaced to the 61st, 62,63,64 and 65 row, and the numbering divided by 6 rear remainders be 2 the 62nd, 68,74,80 and 86 row be displaced to the 66th, 67,68,69 and 70 row.

The parity check matrix H of Figure 137 by the parity check matrix H of Figure 136 being carried out the matrix that line replacement and column permutation obtain '.

At this, even parity check matrix H is carried out line replacement, its layout to the code bit of LDPC code can not exert an influence yet.

At this moment, when with the divisor q of the number of columns P of unit of the message length K of K+qx+y+1 code Bit Interleave in the odd-even of the position of K+Py+x+1 yard bit, loop structure and odd even length M (be 30 at this) (=when M/P) being set to respectively 60,5 and 6, the column permutation of expression formula (12) is corresponding to odd-even.

If the parity check matrix H with Figure 137 ' (suitably be called hereinafter displacement parity matrix) multiply by the result who carries out the displacement identical with expression formula (12) with LDPC code to parity check matrix H (suitably being called hereinafter original parity matrix), then exports 0 vector.Particularly, use in the situation of c ' expression at the row vector that obtains by the column permutation that the vectorial c of row as the LDPC code (code word) of original parity matrix is applied according to expression formula (12), owing to the characteristic Hc based on parity matrix ^TBecome 0 vector, naturally H ' c ' ^TAlso become 0 vector.

From the foregoing, the conversion parity check matrix H of Figure 137 ' become the parity matrix that carries out the LDPC code c ' that the column permutation of expression formula (12) obtains by the LDPC code c to original parity check matrix H.

Therefore, by the LDPC code c of original parity check matrix H being carried out the column permutation of expression formula (12), use the parity check matrix H of Figure 137 ' to the LDPC code c ' behind the column permutation decode (LDPC decoding), and then decoded result is carried out the inverse permutation of the column permutation of expression formula (12), can obtain and the similar decoded result that in the situation of using parity check matrix H that the LDPC code of original parity check matrix H is decoded, obtains.

Figure 138 illustrates the conversion parity check matrix H of Figure 137 ', wherein between 5 * 5 matrix units, be provided with blank.

In Figure 138, conversion parity check matrix H ' be expressed as the combination of matrix: the unit matrix of 5 * 5 elements; Be changed to the another kind of matrix (suitably being called hereinafter accurate unit matrix) of the unit matrix of element 0 corresponding to its element 1; Corresponding to the unit matrix of displacement (cyclic shift) or another matrix (suitably being called hereinafter shift matrix) of accurate unit matrix with being recycled; Comprise two or more another matrix (suitably being called hereinafter and matrix) in unit matrix, accurate unit matrix and the shift matrix; And 0 matrix of 5 * 5 elements.

The conversion parity check matrix H that can regard Figure 138 as ' formed by the matrix of following 5 * 5 elements: unit matrix, accurate unit matrix, shift matrix and matrix and 0 matrix.Therefore, form the conversion parity check matrix H ' 5 * 5 matrix of elements be called as into hereinafter sub matrix.

Decode for the LDPC code that the parity matrix by the matrix notation of P * P element is represented, can use simultaneously to P check-node and P the framework that variable node carries out check-node mathematical operation and variable node mathematical operation.

Figure 139 is the block diagram that the ios dhcp sample configuration IOS DHCP of the decoding device that carries out aforesaid decoding is shown.

Particularly, Figure 139 illustrates the conversion parity check matrix H of using Figure 138 the ios dhcp sample configuration IOS DHCP of the decoding device that the LDPC code of the original parity check matrix H of Figure 136 is decoded ', described conversion parity check matrix H ' is to obtain by the column permutation that carries out at least expression formula (12).

The decoding device of Figure 139 comprises: comprise 6 FIFO (push-up storage) 300 ₁To 300 ₆ Marginal date memory 300, be used for to select FIFO 300 ₁To 300 ₆ Selector 301, check node calculation section 302,2 cyclic shift circuits 303 and 308, comprise 18 FIFO304 ₁To 304 ₁₈ Marginal date memory 304, be used for to select 18 FIFO 304 ₁To 304 ₁₈ Selector 305, be used for receive data memory 306, variable node calculating part 307, decoded word calculating part 309, receive data rearrangement section 310 and the decoded data rearrangement section 311 of storing received information.

At first, describe and to store data in marginal date memory 300 and 304 method.

Marginal date memory 300 comprises 6 FIFO 300 ₁To 300 ₆, its quantity equals the conversion parity check matrix H of Figure 138 ' line number amount 30 divided by the merchant of the line number amount 5 that becomes sub matrix.Each FIFO 300 _y(y=1,2 ..., 6) all have multistage storage area, make it possible to simultaneously in the storage area of each grade, to read or write 5 message that the edge is corresponding with the line number amount that quantitatively equals into sub matrix and number of columns.In addition, each FIFO 300 _yThe quantity of level of storage area be 9, i.e. 1 the maximum quantity (Hamming weight) (Hamming weight) gone up in the row direction of the conversion parity matrix of Figure 138.

At FIFO 300 ₁In, with the conversion parity check matrix H of Figure 138 ' data corresponding to first the position of value 1 in the fifth line (from the message of variable node _Vi) be stored in the horizontal direction in each row (with 0 form that is omitted wherein) with closed form.Particularly, if the element of the j of i row in capable is expressed as (j, i), then at FIFO 300 ₁The storage area of the first order in storage with from the conversion parity check matrix H ' the unit matrix of 5 * 5 elements of (1,1) to (5,5) in data corresponding to the position of value 1.In the storage area of the second level storage with from the conversion parity check matrix H ' (1,21) data corresponding to position of the value 1 in the shift matrix of (5,25) (circulate to the right move 3 shift matrixes that obtain by the unit matrix with 5 * 5 elements).Similarly, in the 3rd to the 8th grade storage area, according to the conversion parity check matrix H ' relation store data.Like this, in the 9th grade storage area the storage with the conversion parity check matrix H ' (1,86) to the shift matrix of (5,90) (by with the value 1 in the first row of the unit matrix of 5 * 5 elements of value 0 displacement, and then will replace after unit matrix 1 shift matrix that obtains of loopy moving left) the data corresponding to position of value 1.

At FIFO 300 ₂In, storage and the conversion parity check matrix H of Figure 138 ' the 6th to the tenth row in the data corresponding to position of value 1.Particularly, at FIFO 300 ₂The storage area of the first order in the data corresponding to position of value 1 in storage and the first shift matrix, described the first shift matrix forms from the conversion parity check matrix H ' (6,1) to (10,5) and matrix (with matrix be unit matrix with 5 * 5 elements move right the second shift matrix sum of 2 acquisitions of the first shift matrix of 1 acquisition and unit matrix with 5 * 5 elements that moves right).In addition, in the storage area of the second level, the data that storage is corresponding with the position of value 1 in the second shift matrix, described the second shift matrix forms from the conversion parity check matrix H ' (6,1) arrive (10,5) and matrix.

Particularly, 2 or larger one-tenth sub matrix for weight, being represented as the form of a plurality of matrix sums in the following matrix at this one-tenth sub matrix---weight is the unit matrix of 1 P * P element, be that 1 element is by the accurate unit matrix of the unit matrix of 0 displacement corresponding to one or more values, and in the situation of the shift matrix that obtains by cyclic shift unit matrix or accurate unit matrix, with weight be 1 unit matrix, data corresponding to the position of the value 1 of accurate unit matrix or shift matrix are (corresponding to belonging to unit matrix, the message at the edge of accurate unit matrix or shift matrix) be stored in that (FIFO 300 in the identical address ₁To 300 ₆In same FIFO).

Similarly, in the 3rd to the 9th grade storage area, according to the conversion parity check matrix H ' relation store data.

Similarly, FIFO 300 ₃To 300 ₆According to the conversion parity check matrix H ' relation store data.

Marginal date memory 304 comprises 18 FIFO 304 ₁To 304 ₁₈, its quantity equals to change parity check matrix H ' number of columns 90 divided by the merchant of composition matrix column quantity 5.Each marginal date memory 304 _x( _x=1,2 ..., 18) all have multistage storage area, make it possible to simultaneously in the storage area of each grade, to read or write 5 message that the edge is corresponding with the line number amount that quantitatively equals into sub matrix and number of columns.

At FIFO 304 ₁In, with the conversion parity check matrix H from Figure 138 ' first row to the five row in data corresponding to the position of value 1 (from the message u of check-node _j) be stored in the independent row (with 0 form that is omitted wherein) with the closed form in the vertical direction.Particularly, at FIFO 304 ₁The storage area of the first order in storage with from the conversion parity check matrix H ' the unit matrix of 5 * 5 elements of (1,1) to (5,5) in data corresponding to the position of value 1.The storage data corresponding with the position of value 1 in the first shift matrix in the storage area of the second level, described the first shift matrix forms from the conversion parity check matrix H ' (6,1) to (10,5) and matrix (with matrix be unit matrix with 5 * 5 elements move right the second shift matrix sum of 2 acquisitions of the first shift matrix of 1 acquisition and unit matrix with 5 * 5 elements that moves right).In addition, in the storage area of the third level, the data that storage is corresponding with the position of value 1 in the second shift matrix, described the second shift matrix forms from the conversion parity check matrix H ' (6,1) arrive (10,5) and matrix.

Particularly, 2 or larger one-tenth sub matrix for weight, being represented as the form of a plurality of matrix sums in the following matrix at this one-tenth sub matrix---weight is the unit matrix of 1 P * P element, be that 1 element is by the accurate unit matrix of the unit matrix of 0 displacement corresponding to one or more values, and in the situation of the shift matrix that obtains by cyclic shift unit matrix or accurate unit matrix, with weight be 1 unit matrix, data corresponding to the position of the value 1 of accurate unit matrix or shift matrix are (corresponding to belonging to unit matrix, the message at the edge of accurate unit matrix or shift matrix) be stored in that (FIFO 304 in the identical address ₁To 304 ₁₈In same FIFO).

Similarly, about the 4th and the storage area of level V, according to the conversion parity check matrix H ' relation store data.FIFO 304 ₁The quantity of level of storage area be 5, namely change parity check matrix H ' first row to the five be listed in the maximum quantity (Hamming weight) of 1 on the line direction.

Similarly, FIFO 304 ₂With 304 ₃Similarly with according to and the conversion parity check matrix H ' relation store data, and FIFO 304 ₂With 304 ₃Each length (number of stages) be 5.Similarly, FIFO 304 ₄To 304 ₁₂Similarly according to and the conversion parity check matrix H ' relation store data, and FIFO 304 ₄To 304 ₁₂Each length (number of stages) be 3.Similarly, FIFO 304 ₁₃To 304 ₁₈Similarly with according to and the conversion parity check matrix H ' relation store data, and FIFO 304 ₁₃To 304 ₁₈Each length (number of stages) be 2.

The operation of the decoding device of Figure 139 is described now.

Marginal date memory 300 comprises 6 FIFO 300 ₁To 300 ₆, 5 message D311 that provided by the cyclic shift circuits 308 of previous stage according to expression belong to the conversion parity check matrix H ' which information (matrix data) D312 come from FIFO 300 ₁To 300 ₆The FIFO of stored data is wanted in middle selection.Then, 5 message D311 are stored among the selected FIFO together according to priority.In addition, when data will be read out, marginal date memory 300 was in order from FIFO 300 ₁ Read 5 message D300 ₁, and with 5 message D300 ₁Offer the selector 301 of next stage.From FIFO 300 ₁Read after the end of message, marginal date memory 300 is equally from FIFO 300 ₂To FIFO 300 ₆Read in order message, and the message of reading is offered selector 301.

Selector 301 is according to selecting signal D301 to select from FIFO 300 ₁To 300 ₆In current 5 message that are read out the FIFO of data, and these 5 message are offered check node calculation section 302 as message D302.

Check node calculation section 302 comprises 5 check node calculation devices 302 ₁To 302 ₅, and use offers its message D302 (D302 by selector 301 ₁To D302 ₅) (the message of expression formula (7) _Vi) carry out the check-node mathematical operation according to expression formula (7).Then, check node calculation section 302 will be as 5 message D303 (D303 of the result's of check-node mathematical operation acquisition ₁To D303 ₅) (the message of expression formula (7) _Uj) offer cyclic shift circuits 303.

Based on about the conversion parity check matrix H ' in corresponding edge be recycled information (matrix data) D305 of how many original unit matrixes that has been shifted, 303 couples of 5 message D303 that determined by check node calculation section 302 of cyclic shift circuits ₁To D303 ₅Be shifted circularly, and the result of cyclic shift is offered marginal date memory 304 as message D304.

Marginal date memory 304 comprises 18 FIFO 304 ₁To 340 ₁₈ Marginal date memory 304 is to belong to the conversion parity check matrix H according to 5 message D304 that provide about the cyclic shift circuits 303 by previous stage ' which information D 305 come from FIFO 304 ₁To 340 ₁₈The FIFO of stored data is wanted in middle selection, and 5 message D304 are stored among the selected FIFO together according to priority.On the other hand, when data will be read out, marginal date memory 304 was in order from FIFO 304 ₁ Read 5 message D306 ₁, and with message D306 ₁Offer the selector 305 of next stage.From FIFO 304 ₁After sense data finished, marginal date memory 304 was similarly in order from FIFO 304 ₂To 340 ₁₈Read message, and message is offered selector 305.

Selector 305 is according to selecting signal D307 to select from FIFO 304 ₁To 340 ₁₈In current 5 message that are read out the FIFO of data, and selected message offered variable node calculating part 307 and decoded word calculating part 309 as message D308.

On the other hand, receive data rearrangement section 310 carries out the column permutation of expression formula (12), the LDPC code D313 that receives by communication path with rearrangement, and the LDPC code D313 that rearrangement is crossed offered receive data memory 306 as receive data D314.Receive data memory 306 calculates and stores reception LLR (the logarithmic likelihood ratio that offers its receive data D134 from receive data rearrangement section 310, log-likelihood ratio), and collect and provide 5 receive LLR as reception value D309 to variable node calculating part 307 and decoded word calculating part 309.

Variable node calculating part 307 comprises 5 variable node calculators 307 ₁To 307 ₅, and use offers its message D380 (308 by selector 305 ₁To 308 ₅) (the message u of expression formula (1) _j) and 5 reception value D309 (reception value u of expression formula (1) of offering it from receive data memory 306 _Oi) carry out the variable node mathematical operation according to expression formula (1).Then, variable node calculating part 307 will be as the message D310 (D301 of the result's of mathematical operation acquisition ₁To D310 ₅) (the message of expression formula (1) _Vi) offer cyclic shift circuits 308.

Based on about the conversion parity check matrix H ' in corresponding edge be recycled the information of how many original unit matrixes that has been shifted, the message D310 that 308 pairs of variable node calculating parts of cyclic shift circuits 307 calculate ₁To D310 ₅Be shifted circularly, and the result of cyclic shift is offered marginal date memory 300 as message D311.

By carrying out the aforesaid operations sequence, can carry out the decoding to a circulation of LDPC code.In the decoding device of Figure 139, after the decoded pre-determined number of LDPC code, final decoded result is determined by decoded word calculating part 309 and decoded data rearrangement section 311, subsequently output.

Particularly, decoded word calculating part 309 comprises 5 decoded word calculators 309 ₁To 309 ₅, and in a plurality of circulations of decoding, play final level, to use from 5 message D308 (D308 of selector 350 outputs ₁To D308 ₅) (the message u of expression formula (5) _j) and from 5 reception value D309 (reception value u of expression formula (5) of receive data memory 306 output _Oi) come to calculate decoded result (decoded word) according to expression formula (5).Then, decoded word calculating part 309 will offer decoded data rearrangement section 311 as the decoded data D315 of the acquisition of result of calculation.

The decoded data D315 that 311 pairs in decoded data rearrangement section offers it from decoded word calculating part 309 carries out the inverse permutation of column permutation of expression formula (12) with the order of rearrangement decoded data D315, and the decoded data D315 that the output rearrangement is crossed is as decoded result D316.

As mentioned above, by parity matrix (original parity matrix) being applied in line replacement and the column permutation one or both parity matrix is converted to the available aforesaid matrix (unit matrix of P * P element; Be changed to the accurate unit matrix of the unit matrix of element 0 corresponding to its element 1; Corresponding to the unit matrix after being shifted or the shift matrix of accurate unit matrix with being recycled; Two or more matrixes in unit matrix, accurate unit matrix and the shift matrix and matrix; The parity matrix (conversion parity matrix) of combinational expression and 0 matrix of P * P element), the decoding of LDPC code can be adopted P check-node and P the structure that variable node carries out check-node mathematical operation and variable node mathematical operation simultaneously.Therefore, by P node carried out the node mathematical operation simultaneously, carry out the LDPC coding in the practical range but operating frequency can be suppressed at.

56 pairs of P check-nodes of LDPC lsb decoder and P variable node of forming the receiving equipment of Figure 134 carry out check-node mathematical operation and variable node mathematical operation simultaneously, and the LDPC that carries out with the decoding device that is similar to Figure 139 decodes.

Particularly, for convenience of description, now supposition for example is that wherein parity matrix has the parity check matrix H of the step structure shown in Figure 136 from the parity matrix of the LDPC code of LDPC coding section 21 outputs of the transmitting apparatus 11 of composition diagram 8.In this case, the odd-even device 23 of transmitting apparatus 11 carries out odd-even, with with the position of K+qx+y+1 code Bit Interleave to K+Py+x+1 yard bit, wherein, message length K is set to 60, the number of columns P of unit of loop structure is set to 5, and the divisor q of odd even length M (=M/P) be set to 6.

Because odd-even is corresponding to the column permutation of expression formula (12), so LDPC lsb decoder 56 does not need to carry out the column permutation of expression formula (12).

Therefore, in the receiving equipment 12 of Figure 134, being reversed deinterleaver 55 from row does not offer LDPC lsb decoder 56 as mentioned above to its LDPC code (i.e. LDPC code under the state of the column permutation that it has been carried out expression formula (12)) that carries out the odd even deinterleaving.LDPC lsb decoder 56 is similar to the processing column permutation of expression formula (12) (but do not carry out) of the decoding device of Figure 139.

Particularly, Figure 140 illustrates the example of configuration of the LDPC lsb decoder 56 of Figure 134.

With reference to Figure 140, the configuration of LDPC lsb decoder 56 and the decoding device of Figure 139 similar (but do not have Figure 139 receive data rearrangement section 310), and be similar to the processing column permutation of expression formula (12) (but do not carry out) of the decoding device of Figure 139.Therefore, will be in the description of this omission to LDPC lsb decoder 56.

Because LPPC lsb decoder 56 can be configured to not comprise receive data rearrangement section 310 as mentioned above, therefore its scale of decoding device than Figure 139 can reduce.

Should note, although at Figure 136 in Figure 140, for convenience of description, the code length N that supposes the LDPC code is 90, message length K is 60, the number of columns P of unit (becoming line number amount and the column number of sub matrix) of loop structure be 5 and the divisor q of odd even length M (=M/P) be 6, but the number of columns P of unit of code length N, message length K, loop structure and divisor q (=M/P) all be not limited to separately the above occurrence that provides.

Particularly, code length N for example is 64800 or 16200, message length K is N-Pq although the LDPC coding section 21 in the transmitting apparatus of Fig. 8 11 exports (=N-M), the number of columns P of unit of loop structure be 360 and divisor q be the LDPC code of M/P, but decoding is by P check-node and P variable node being carried out simultaneously also can use the LDPC lsb decoder 56 of Figure 140 in the situation that check-node mathematical operation and variable node mathematical operation carry out about the LDPC of aforesaid this LDPC code.

Although processing sequence described above can be carried out by hardware, it can also be carried out by software.When series of processes was carried out by software, the program that consists of software was installed in the all-purpose computer etc.

Figure 141 illustrates the example of the configuration of the execution mode that the computer that is used for carrying out above-described processing sequence has been installed.

Program can be recorded in advance in as on the hard disk 705 of the recording medium of setting up in the computer or among the ROM (read-only memory) 703.

Perhaps, program can temporarily or for good and all be stored (record) on removable recording medium 711 (such as floppy disk, CD-ROM (read-only optical disc), MO (magneto-optic) dish, DVD (digital versatile disc), disk or semiconductor memory).This removable recording medium 711 described above can be provided as so-called software kit.

Should notice that program not only can be installed in the computer by removable recording medium 711 from the above description, and can received and pass to the situation of the hard disk 705 of setting up in the computer by Department of Communication Force 708 under, be installed in the hard disk 705 of setting up in the computer.In this case, program can be delivered to computer from the download website by radio communication via the artificial satellite that is used for digital satellite broadcasting, perhaps is delivered in the computer by wire communication via network (such as LAN (local area network (LAN)) or internet).

Computer has built-in CPU (CPU) 702.Input/output interface 7410 is connected to CPU 702 by bus 701, and, when the input part 707 based on configurations such as keyboard, mouse, microphones is operated by the user, if instruction is input to CPU702 by input/output interface 710, then CPU 702 carries out the program of storage among the ROM (read-only memory) 703.Perhaps, CPU 702 with the program of storage on the hard disk 705, from satellite or network delivery received by Department of Communication Force 708 and be installed in the program on the hard disk 705 or be loaded among the RAM (random access memory) 704 and executive program from the program that is loaded into the driver 709 and is installed in hard disk 705 that removable recording medium 711 is read.Therefore, CPU 702 carries out according to the processing of above-described flow chart or the processing of being undertaken by the configuration of above-described block diagram.Then, CPU 702 is from the efferent 706 output results based on configurations such as LCD (liquid crystal display), loud speakers, and pass through input/output interface 710 and transmit results from Department of Communication Force 708, perhaps in case of necessity result is recorded on the hard disk 705.

At this, in this manual, the treatment step that description makes computer carry out the program of various processing need to not carried out according to the time series of the described order of flow chart, but comprises the processing that will walk abreast or carry out separately (for example, parallel processing or the processing by object).

In addition, program can be processed by single computer, or can be processed by the distributed treatment of a plurality of computers.In addition, program can be delivered to long-range computer and by its processing.

The processing of now, the LDPC that further describes the LDPC coding section 21 of transmitting apparatus 11 being encoded.

For example, in the DVB-S.2 standard, stipulated the LDPC coding of 64800 bits and two kinds of 16200 bits different code length N.

And, be the LDPC code of 64800 bits for code length N, 1/4,1/3,2/5,1/2,3/5,2/3,3/4,4/5,5/6,8/9 and 9/10 totally 11 kinds of encoding rates have been stipulated, and be the LDPC code of 16200 bits for code length N, stipulated 1/4,1/3,2/5,1/2,3/5,2/3,3/4,4/5,5/6 and 8/9 totally 10 kinds of encoding rates.

LDPC coding section 21 is according to obtaining the coding (error correction code) of LDPC code that code length N is the different coding rate of 64800 bits or 16200 bits for every kind of code length N with for the parity check matrix H of every kind of encoding rate preparation.

Particularly, LDPC coding section 21 storage is described below for generation of for every kind of code length N with for the parity matrix initial value table of the parity check matrix H of every kind of encoding rate.

At this, in the DVB-S.2 standard, the LDPD coding of having stipulated 64800 bits and two kinds of 16200 bits different code length N as indicated above is that the LDPC code of 64800 bits has been stipulated 11 kinds of encoding rates for code length N, and is that the LDPC code of 16200 bits has been stipulated 10 kinds of encoding rates for code length N.

Therefore, when transmitting apparatus 11 is when carrying out the equipment of compatible with DVB-S.2 processing of standard, in LDPC coding section 21 storage separately corresponding to for code length N be 64800 bits the LDPC code 11 kinds of different coding rates parity matrix initial value table and separately corresponding to the parity matrix initial value table of 10 kinds of different coding rates that for code length N is the LDPC code of 16200 bits.

LDPC coding section 21 for example arranges code length N and encoding rate r in response to operator's the LDPC code that is operating as.The code length N that LDPC coding section 21 arranges and encoding rate r suitably are called hereinafter and code length N are set and encoding rate r is set.

Based on corresponding to code length N being set and the parity matrix initial value table of encoding rate r is set, LDPC coding section 21 on column direction take 360 row (the number of columns P of unit of loop structure) for the cycle arrange with corresponding to the code length N information matrix H corresponding with the message length K (=Nr=code length N-odd even length M) that encoding rate r is set is set _AValue be 1 element, to produce parity check matrix H.

Then, the information bit for message length K is provided from the view data that provides such as transmitting apparatus 11 as the object data of transmission object or voice data in LDPC coding section 21.In addition, parity bits corresponding to information bit is calculated based on parity check matrix H by LDPC coding section 21, with the code word (LDPC code) that produces a code length.

In other words, LDPC coding section 21 carries out the mathematical operation of the parity bits of code word c in succession, and it satisfies following expression.

Hc ^T＝0

At this, in above-mentioned expression formula, c represents the row vector as code word (LDPC code), c ^TThe counter-rotating of the vectorial c of expression row.

In the situation about in as the vectorial c of row of LDPC code (code word), representing with the row vector T corresponding to the part of parity bits corresponding to the part of information bit represents with the vectorial A of row, the vectorial c useful source of row voluntarily vectorial A as information bit and the row vector T as the expression formula c=[A|T of parity bits] represent.

Simultaneously, parity check matrix H can be enough be derived from the information matrix H corresponding to the code bit of the LDPC code of information bit _AWith the parity matrix H corresponding to the code bit of the LDPC code of parity bits _TExpression formula H=[H _A| H _T] (information matrix H in matrix H _AElement be positioned at the left side element, parity matrix H _TElement be the element that is positioned at the right side) expression.

In addition, for example in the DVB-S.2 standard, parity check matrix H=[H _A| H _T] parity matrix H _THas step structure.

Parity check matrix H and as the vectorial c=[A|T of the row of LDPC code] must satisfy expression formula Hc ^T=0, parity check matrix H=[H wherein _A| H _T] parity matrix H _THas step structure, by from expression formula Hc ^TColumn vector Hc in=0 ^TThe first row in element begin the element in every delegation is set to 0 in order, can sequentially determine configuration line vector c=[A|T] (satisfy expression formula Hc ^T=0) the capable vector T as parity bits.

If LDPC coding section 21 determines parity bits T for information bit A, the code word c=[A|T that represents by information bit A and parity bits T of its output then] as the LDPC coding result of information bit A.

As mentioned above, pre-stored parity matrix initial value table corresponding to code length N and encoding rate r in the LDPC coding section 21, and use from the parity check matrix H that the parity matrix initial value table that encoding rate r is set produces code length N and the LDPC coding that encoding rate r is set being set corresponding to code length N is set.

Each parity matrix initial value table be per 360 row of expression (the number of columns P of unit of periodic structure) with corresponding to information matrix H corresponding to the message length K of the code length N of the LDPC code of parity check matrix H (the LDPC code of parity check matrix H restriction) and encoding rate r _AValue be the table of the position of 1 element, and produce in advance the parity matrix initial value table for the parity check matrix H of every kind of code length N and every kind of encoding rate r.

Figure 142 illustrates the parity matrix initial value table for the multiple parity check matrix H of generation that comprises the parity matrix initial value table of stipulating in the DVB-S.2 standard to Figure 187.

Particularly, to illustrate for the code length N that stipulates in the DVB-S.2 standard be that 16200 bits and encoding rate r are the parity matrix initial value table of 2/3 parity check matrix H to Figure 142.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 2/3 parity check matrix H that Figure 143 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 145.

Should notice that Figure 144 is the figure of continued access Figure 143, and Figure 145 is the figure of continued access Figure 144.

Figure 146 illustrate for stipulate in the DVB-S.2 standard code length N be that 16200 bits and encoding rate r are the parity matrix initial value table of 3/4 parity check matrix H.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 3/4 parity check matrix H that Figure 147 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 150.

Should notice that Figure 148 is the figure of continued access Figure 147, and Figure 149 is the figure of continued access Figure 148.In addition, Figure 150 is the figure of continued access Figure 149.

Figure 151 illustrate for stipulate in the DVB-S.2 standard code length N be that 16200 bits and encoding rate r are the parity matrix initial value table of 4/5 parity check matrix H.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 4/5 parity check matrix H that Figure 152 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 155.

Should notice that Figure 153 is the figure of continued access Figure 152, and Figure 154 is the figure of continued access Figure 153.In addition, Figure 155 is the figure of continued access Figure 154.

Figure 156 illustrate for stipulate in the DVB-S.2 standard code length N be that 16200 bits and encoding rate r are the parity matrix initial value table of 5/6 parity check matrix H.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 5/6 parity check matrix H that Figure 157 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 160.

Should notice that Figure 158 is the figure of continued access Figure 157, and Figure 159 is the figure of continued access Figure 158.In addition, Figure 160 is the figure of continued access Figure 159.

Figure 161 illustrate for stipulate in the DVB-S.2 standard code length N be that 16200 bits and encoding rate r are the parity matrix initial value table of 8/9 parity check matrix H.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 8/9 parity check matrix H that Figure 162 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 165.

Should notice that Figure 163 is the figure of continued access Figure 162, and Figure 164 is the figure of continued access Figure 163.In addition, Figure 165 is the figure of continued access Figure 164.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 9/10 parity check matrix H that Figure 166 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 169.

Should notice that Figure 167 is the figure of continued access Figure 166, and Figure 168 is the figure of continued access Figure 167.In addition, Figure 169 is the figure of continued access Figure 168.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 1/4 parity check matrix H that Figure 170 and Figure 171 illustrate for the code length N that stipulates in the DVB-S.2 standard.

Should notice that Figure 171 is the figure of continued access Figure 170.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 1/3 parity check matrix H that Figure 172 and Figure 173 illustrate for the code length N that stipulates in the DVB-S.2 standard.

Should notice that Figure 173 is the figure of continued access Figure 172.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 2/5 parity check matrix H that Figure 174 and Figure 175 illustrate for the code length N that stipulates in the DVB-S.2 standard.

Should notice that Figure 175 is the figure of continued access Figure 174.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 1/2 parity check matrix H that Figure 176 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 178.

Should notice that Figure 177 is the figure of continued access Figure 176, and Figure 178 is the figure of continued access Figure 177.

It is that 64800 bits and encoding rate r are the parity matrix initial value table of 3/5 parity check matrix H that Figure 179 illustrates for the code length N that stipulates in the DVB-S.2 standard to Figure 181.

Should notice that Figure 180 is the figure of continued access Figure 179, and Figure 181 is the figure of continued access Figure 180.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 1/4 parity check matrix H that Figure 182 illustrates for the code length N that stipulates in the DVB-S.2 standard.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 1/3 parity check matrix H that Figure 183 illustrates for the code length N that stipulates in the DVB-S.2 standard.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 2/5 parity check matrix H that Figure 184 illustrates for the code length N that stipulates in the DVB-S.2 standard.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 1/2 parity check matrix H that Figure 185 illustrates for the code length N that stipulates in the DVB-S.2 standard.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 3/5 parity check matrix H that Figure 186 illustrates for the code length N that stipulates in the DVB-S.2 standard.

It is that 16200 bits and encoding rate r are the parity matrix initial value table of 3/5 parity check matrix H that Figure 187 illustrates for the code length N that stipulates in the DVB-S.2 standard, and it can be used to replace the parity matrix initial value table of Figure 186.

The LDPC coding section 21 of transmitting apparatus 11 determines parity check matrix H with parity matrix initial value table in the following manner.

Particularly, Figure 188 illustrates the method for determining parity check matrix H from parity matrix initial value table.

The parity matrix initial value table that it should be noted that Figure 188 represents shown in Figure 142 to be that 16200 bits and encoding rate r are the parity matrix initial value table of 2/3 parity check matrix H for the code length N that stipulates in the DVB-S.2 standard.

As mentioned above, parity matrix initial value table be per 360 row (for the per unit number of columns P of loop structure) of expression with corresponding to information matrix H corresponding to the message length K of the code length N of LDPC code and encoding rate r _AValue be the table of the position of 1 element, and in the first row of parity matrix initial value table, the column mean of the 1+360 of parity check matrix H * (i-1) is the numerical value that the quantity of the line number (line number of the first row of parity check matrix H is 0) of 1 element equals the row weight that the row of 1+360 * (i-1) have.

At this, suppose the parity matrix H corresponding to the parity check matrix H of odd even length M _THave step structure, and be determined in advance.According to parity matrix initial value table, in the parity check matrix H corresponding to the information matrix H of message length K _ABe determined.

The line number amount k+1 of parity matrix initial value table is difference with the information length K.

The line number amount k+1 of message length K and parity matrix initial value table satisfies the relation that following expression provides.

K＝(k+1)×360

At this, 360 in the above expression formula is number of columns P of unit of loop structure.

In the parity matrix initial value table of Figure 188, in the 1st row to the 3 row, list 13 numerical value, and in k+1 (being the 30th) row, list 3 numerical value at the 4th row in Figure 188.

Therefore, the numeral of the row weight in the parity check matrix H of determining based on the parity matrix initial value table of Figure 188 is 13 at the 1st row in the row of 1+360 * (3-1)-1, and is 3 in the row of 1+360 * (3-1) is capable to K.

The 1st row of the parity matrix initial value table of Figure 188 comprises 0,2084,1613,1548,1286,1460,3196,4297,2481,3369,3451,4620 and 2622, this is illustrated in the 1st row of parity check matrix H, and line number is that the value of the element in 0,2084,1613,1548,1286,1460,3196,4297,2481,3369,3451,4620 and 2622 the row is 1 (value of other element is 0 in addition).

Simultaneously, the 2nd row of the parity matrix initial value table of Figure 188 comprises 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358 and 3108, this is illustrated in the 361st (the=the 1+360 * (the 2-1)) row of parity check matrix H, and line number is that the value of the element in 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358 and 3108 the row is 1.

As mentioned above, parity matrix initial value table represents the information matrix H of per 360 row parity check matrix H _AValue be the position of 1 element.

Each row except the row of 1+360 * (i-1) of parity check matrix H (i.e. each row from 2+360 * (i-1) to the 360th * i), comprise by the value that circularly 1+360 * (i-1) is listed as (periodically depending on parity matrix initial value table) according to the odd even length M, in (on the downward direction of row) on the downward direction being that the be shifted value that obtains of 1 element is 1 element.

Particularly, for example, the row of 2+360 * (i-1) are that (=q) the row that obtain of position, the row of and the 3+360 that follows * (i-1) are by circularly the row of 1+360 * (i-1) being moved down (=2 * q) s and then will move down M/360 (=q) row that obtain through the row after the cyclic shift (2+360 * (i-1) be listed as) circularly of 2 * M/360 by circularly the row of 1+360 * (i-1) being moved down M/360.

Now, if the j row of supposition parity matrix initial value table (from left to right j row) i capable (from i capable) numerical value b _{I, j}Expression, and the w column mean of parity check matrix H is the line number H of 1 j element _W-jExpression then can determine to be different from the line number H that the w column mean of row of 1+360 * (i-1) is 1 element according to following expression in parity check matrix H _W-j

H _w-j＝mod{h _i，j+mod((w-1)，P)×q，M}

Wherein, mod (x, y) expression x is divided by the remainder of y.

At this moment, P is the Board Lot of the row of above-described loop structure, and is 360 in DVB-S.2 standard for example.In addition, q is the value M/360 that the odd even length M obtains divided by the number of columns P of unit (=360) of loop structure.

It is the line number of 1 element that LDPC coding section 21 specifies value the row of the 1+360 of parity check matrix H * (i-1) from parity matrix initial value table.

In addition, LDPC coding section 21 determines that according to expression formula (10) w row (the w row are to be different from the row of row of 1+360 * (the i-1)) intermediate value of parity check matrix H is the line number H of 1 element _W-j, and producing parity check matrix H, line number is 1 for the value of the element of the line number by above-mentioned acquisition in this parity check matrix H.

Now, the modification of the method for replacing of yard bit of LDPC code in the replacement Treatment of being undertaken by the replacement section 32 of the demodulation multiplexer 25 in the transmitting apparatus 11 will be described, i.e. the modification of the allocation model (hereinafter referred to as the Bit Allocation in Discrete pattern) of the sign bit of the code bit of LDPC code and expression symbol.

In demodulation multiplexer 25, the code bit of LDPC code writes at the column direction of memory 31, and memory 31 is at column direction * line direction storage (N/ (mb)) * (mb) individual bit.Afterwards, the code bit is read in the row direction take mb bit as unit.In addition, in demodulation multiplexer 25,32 pairs of mb bits of reading at the line direction of memory 31 of replacement section are replaced, and the code bit after will replacing is defined as mb the sign bit of (continuous) b symbol.

Particularly, i+1 the bit that rises abruptly from the highest effective ratio of mb code bit will reading at the line direction of memory 31 of replacement section 32 is defined as a yard bit b _i, i+1 the bit from highest order of mb the sign bit of b (continuous) symbol is defined as sign bit y _i, and next come mb code bit b according to predetermined Bit Allocation in Discrete pattern ₀To b _Mb-1Replace.

It is that code length N is that 64800 bits and encoding rate r are 5/6 or 9/10 LDPC codes, modulator approach is that 4096QAM and multiplier b are the examples of the Bit Allocation in Discrete pattern that can adopt in 1 the situation in addition that Figure 189 is illustrated in the LDPC code.

When the LDPC code is that code length N is that 64800 bits and encoding rate r are 5/6 or 9/10 LDPC codes, modulator approach is that 4096QAM and multiplier b are when being 1 in addition, in demodulator 25, write for the code bit of the memory 31 of column direction * line direction storage (64800/ (12 * 1)) * (12 * 1) bit by take 12 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

32 pairs 12 * 1 of replacement sections (=mb) individual code bit b ₀To b ₁₁Replace, so that 12 * 1 (=mb) individual code bit b as reading from memory 31 seen in Figure 189 ₀To b ₁₁(=b) 12 * 1 (=mb) the individual sign bit y of individual symbol that can be assigned to 1 ₀To y ₁₁

Particularly, according to Figure 189, encoding rate is that 5/6 LDPC code and encoding rate are that 9/10 LDPC code is replaced in the LDPC code that 32 couples of code length N of replacement section are 64800 bits, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₀,

Code bit b ₂Give sign bit y ₆,

Code bit b ₃Give sign bit y ₁,

Code bit b ₄Give sign bit y ₄,

Code bit b ₅Give sign bit y ₅,

Code bit b ₆Give sign bit y ₂,

Code bit b ₇Give sign bit y ₃,

Code bit b ₈Give sign bit y ₇,

Code bit b ₉Give sign bit y ₁₀,

Code bit b ₁₀Give sign bit y ₁₁, and

Code bit b ₁₁Give sign bit y ₉

Figure 190 illustrate when the LDPC code be that code length N is that 64800 bits and encoding rate r are 5/6 or 9/10 LDPC codes, modulator approach is the example of 4096QAM and multiplier b adoptable Bit Allocation in Discrete pattern when being 2 in addition.

When the LDPC code is that code length N is that 64800 bits and encoding rate r are 5/6 or 9/10 LDPC codes, modulator approach is that 4096QAM and multiplier b are when being 2 in addition, in demodulator 25, write for the code bit of the memory 31 of column direction * line direction storage (64800/ (12 * 2)) * (12 * 2) individual bit by take 12 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

32 pairs 12 * 2 of replacement sections (=mb) individual code bit b ₀To b ₂₃Replace, so that 12 * 2 (=mb) individual code bit b as reading from memory 31 seen in Figure 190 ₀To b ₂₃(=b) 12 * 2 (=mb) the individual sign bit y of individual continuous symbol that can be assigned to 2 ₀To y ₂₃

Particularly, according to Figure 190, encoding rate is that 5/6 LDPC code and encoding rate are that 9/10 LDPC code is replaced in the LDPC code that 32 couples of code length N of replacement section are 64800 bits, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₂Give sign bit y ₀,

Code bit b ₄Give sign bit y ₆,

Code bit b ₆Give sign bit y ₁,

Code bit b ₈Give sign bit y ₄,

Code bit b ₁₀Give sign bit y ₅,

Code bit b ₁₂Give sign bit y ₂,

Code bit b ₁₄Give sign bit y ₃,

Code bit b ₁₆Give sign bit y ₇,

Code bit b ₁₈Give sign bit y ₁₀,

Code bit b ₂₀Give sign bit y ₁₁,

Code bit b ₂₂Give sign bit y ₉,

Code bit b ₁Give sign bit y ₂₀,

Code bit b ₃Give sign bit y ₁₂,

Code bit b ₅Give sign bit y ₁₈,

Code bit b ₇Give sign bit y ₁₃,

Code bit b ₉Give sign bit y ₁₆,

Code bit b ₁₁Give sign bit y ₁₇,

Code bit b ₁₃Give sign bit y ₁₄,

Code bit b ₁₅Give sign bit y ₁₅,

Code bit b ₁₇Give sign bit y ₁₉,

Code bit b ₁₉Give sign bit y ₂₂,

Code bit b ₂₁Give sign bit y ₂₃, and

Code bit b ₂₃Give sign bit y ₂₁

At this, it is the Bit Allocation in Discrete pattern of Figure 189 of 1 that the Bit Allocation in Discrete pattern of Figure 190 is not utilized multiplier b wherein with not making any modification.Particularly, in Figure 190, code bit b ₀, b ₂... b ₂₂To sign bit y _iDistribution and a code bit b ₁, b ₃... b ₂₃To sign bit y _iDistribution be similar to the code bit b of Figure 189 ₀To b ₁₁To sign bit y _iDistribution.

Figure 191 illustrate when modulator approach be that 1024QAM and LDPC code are that code length N is that 16200 bits and encoding rate r are 3/4,5/6 or 8/9 the other multiplier b of LDPC code when being 2, and when modulator approach be that 1024QAM and LDPC code are that code length N is that 64800 bits and encoding rate r are the examples of 3/4,5/6 or 9/10 the other multiplier b of LDPC code adoptable Bit Allocation in Discrete pattern when being 2.

When the LDPC code is that code length N is that 16200 bits and encoding rate r are 3/4,5/6 or 8/9 LDPC codes, modulator approach is that 1024QAM and multiplier b are when being 2 in addition, in demodulator 25, write for the code bit of the memory 31 of column direction * line direction storage (16200/ (10 * 2)) * (10 * 2) individual bit by take 10 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

On the other hand, when the LDPC code is that code length N is that 64800 bits and encoding rate r are 3/4,5/6 or 9/10 LDPC codes, modulator approach is that 1024QAM and multiplier b are when being 2 in addition, in demodulator 25, write for the code bit of the memory 31 of column direction * line direction storage (64800/ (10 * 2)) * (10 * 2) individual bit by take 10 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

32 pairs 10 * 2 of replacement sections (=mb) individual code bit b ₀To b ₁₉Replace, so that 10 * 2 (=mb) individual code bit b as reading from memory 31 seen in Figure 191 ₀To b ₁₉(=b) 10 * 2 (=mb) the individual sign bit y of individual continuous symbol that can be assigned to 2 ₀To y ₁₉

Particularly, according to Figure 191, in the LDPC code that 32 couples of code length N of replacement section are 16200 bits all encoding rates be 3/4 LDPC code, encoding rate be 5/6 LDPC code and further encoding rate be 8/9 LDPC code, and code length N be in the LDPC code of 64800 bits encoding rate be 3/4 LDPC code, encoding rate be 5/6 LDPC code and further encoding rate be that 9/10 LDPC code is replaced, to distribute

Code bit b ₀Give sign bit y ₈,

Code bit b ₁Give sign bit y ₃,

Code bit b ₂Give sign bit y ₇,

Code bit b ₃Give sign bit y ₁₀,

Code bit b ₄Give sign bit y ₁₉,

Code bit b ₅Give sign bit y ₄,

Code bit b ₆Give sign bit y ₉,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₁₇,

Code bit b ₉Give sign bit y ₆,

Code bit b ₁₀Give sign bit y ₁₄,

Code bit b ₁₁Give sign bit y ₁₁,

Code bit b ₁₂Give sign bit y ₂,

Code bit b ₁₃Give sign bit y ₁₈,

Code bit b ₁₄Give sign bit y ₁₆,

Code bit b ₁₅Give sign bit y ₁₅,

Code bit b ₁₆Give sign bit y ₀,

Code bit b ₁₇Give sign bit y ₁,

Code bit b ₁₈Give sign bit y ₁₃, and

Code bit b ₁₉Give sign bit y ₁₂

Figure 192 illustrate when modulator approach be that 4096QAM and LDPC code are that code length N is that 16200 bits and encoding rate r are that 5/6 or 8/9 the other multiplier b of LDPC code is when being 2, also have when modulator approach be that 4096QAM and LDPC code are that code length N is that 64800 bits and encoding rate r are 5/6 or 9/10 the other multiplier b of LDPC code when being 2, the example of adoptable Bit Allocation in Discrete pattern.

When the LDPC code is that code length N is that 16200 bits and encoding rate r are 5/6 or 8/9 LDPC codes, modulator approach is that 4096QAM and multiplier b are when being 2 in addition, in demodulator 25, write for the code bit of the memory 31 of column direction * line direction storage (16200/ (12 * 2)) * (12 * 2) individual bit by take 12 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

On the other hand, when the LDPC code is that code length N is that 64800 bits and encoding rate r are 5/6 or 9/10 LDPC codes, modulator approach is that 4096QAM and multiplier b are when being 2 in addition, in demodulator 25, write for the code bit of the memory 31 of column direction * line direction storage (64800/ (12 * 2)) * (12 * 2) individual bit by take 12 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

32 pairs 12 * 2 of replacement sections (=mb) individual code bit b ₀To b ₂₃Replace, so that 12 * 2 (=mb) individual code bit b as reading from memory 31 seen in Figure 192 ₀To b ₂₃(=b) 12 * 2 (=mb) the individual sign bit y of individual continuous symbol that can be assigned to 2 ₀To y ₂₃

Particularly, according to Figure 192, all encoding rates are that 5/6 LDPC code and encoding rate are 8/9 LDPC code in the LDPC code that 32 couples of code length N of replacement section are 16200 bits, and code length N is that encoding rate is that 5/6 LDPC code and encoding rate are that 9/10 LDPC code is replaced in the LDPC code of 64800 bits, to distribute

Code bit b ₀Give sign bit y ₁₀,

Code bit b ₁Give sign bit y ₁₅,

Code bit b ₂Give sign bit y ₄,

Code bit b ₃Give sign bit y ₁₉,

Code bit b ₄Give sign bit y ₂₁,

Code bit b ₅Give sign bit y ₁₆,

Code bit b ₆Give sign bit y ₂₃,

Code bit b ₇Give sign bit y ₁₈,

Code bit b ₈Give sign bit y ₁₁,

Code bit b ₉Give sign bit y ₁₄,

Code bit b ₁₀Give sign bit y ₂₂,

Code bit b ₁₁Give sign bit y ₅,

Code bit b ₁₂Give sign bit y ₆,

Code bit b ₁₃Give sign bit y ₁₇,

Code bit b ₁₄Give sign bit y ₁₃,

Code bit b ₁₅Give sign bit y ₂₀,

Code bit b ₁₆Give sign bit y ₁,

Code bit b ₁₇Give sign bit y ₃,

Code bit b ₁₈Give sign bit y ₉,

Code bit b ₁₉Give sign bit y ₂,

Code bit b ₂₀Give sign bit y ₇,

Code bit b ₂₁Give sign bit y ₈,

Code bit b ₂₂Give sign bit y ₁₂, and

Code bit b ₂₃Give sign bit y ₀

To the Bit Allocation in Discrete pattern shown in Figure 192, identical Bit Allocation in Discrete pattern can be used for multiple LDPC code according to Figure 189, and in addition, the LDPC code of all kinds can both be set to the performance of expectation to the tolerance limit of error.

Particularly, Figure 193 illustrates the simulation result of BER (bit error rate (BER)) in the situation of carrying out replacement Treatment according to Figure 189 to the Bit Allocation in Discrete pattern of Figure 192 to Figure 196.

It should be noted that at Figure 193 transverse axis represents E in Figure 196 _s/ N _O(signal power of each symbol is to the ratio of noise power), the longitudinal axis represents BER.

In addition, solid-line curve is illustrated in the BER in the situation of carrying out replacement Treatment, and the dotted line that length replaces is illustrated in the BER in the situation of not carrying out replacement Treatment.

Figure 193 illustrate according to the Bit Allocation in Discrete pattern of Figure 189 to adopting 4096QAM as modulator approach and multiplier b is set is that 1 code length N is 64800 and BER in the situation of encoding rate to be 5/6 and 9/10 LDPC code carry out replacement Treatment.

Figure 194 illustrate according to the Bit Allocation in Discrete pattern of Figure 190 to adopting 4096QAM as modulator approach and multiplier b is set is that 2 code length N is 64800 and BER in the situation of encoding rate to be 5/6 and 9/10 LDPC code carry out replacement Treatment.

It should be noted that in Figure 193 and Figure 194, the graphical representation that has added triangular marker is the BER of 5/6 LDPC code about encoding rate, and the graphical representation that has added spider lable is the BER of 9/10 LDPC code about encoding rate.

Figure 195 illustrate according to the Bit Allocation in Discrete pattern of Figure 191 to adopt 1024QAM as modulator approach and arrange multiplier b be 2 code length N be 16200 and encoding rate to be 3/4,5/6 and 8/9 LDPC code and code length N be 64800 and BER in the situation of encoding rate to be 3/4,5/6 and 9/10 LDPC code carry out replacement Treatment.

Should note, in 195 figure, the graphical representation that has added spider lable is 64800 and encoding rate is the BER of 9/10 LDPC code about code length N, and the graphical representation that has added the triangular marker that makes progress is 64800 and encoding rate is the BER of 5/6 LDPC code about code length N.In addition, the figure that has added square marks represents that about code length N be 64800 and encoding rate is the BER of 3/4 LDPC code.

In addition, in Figure 195, the graphical representation that has added circular mark is 16200 and encoding rate is the BER of 8/9 LDPC code about code length N, and the graphical representation that has added downward triangular marker is 16200 and encoding rate is the BER of 5/6 LDPC code about code length N.In addition, the graphical representation that has added labelled notation is 16200 and encoding rate is the BER of 3/4 LDPC code about code length N.

Figure 196 illustrate according to the Bit Allocation in Discrete pattern of Figure 192 to adopt 4096QAM as modulator approach and arrange multiplier b be 2 code length N be 16200 and encoding rate to be 5/6 and 8/9 LDPC code and code length N be 64800 and BER in the situation of encoding rate to be 5/6 and 9/10 LDPC code carry out replacement Treatment.

Should note, in 196 figure, the graphical representation that has added spider lable is 64800 and encoding rate is the BER of 9/10 LDPC code about code length N, and the graphical representation that has added the triangular marker that makes progress is 64800 and encoding rate is the BER of 5/6 LDPC code about code length N.

In addition, in Figure 196, the graphical representation that has added circular mark is 16200 and encoding rate is the BER of 8/9 LDPC code about code length N, and the graphical representation that has added downward triangular marker is 16200 and encoding rate is the BER of 5/6 LDPC code about code length N.

To Figure 196, identical Bit Allocation in Discrete pattern can be used for multiple LDPC code according to Figure 193, and in addition, the LDPC code of all kinds can be set to the performance of expectation to the tolerance limit of error.

Particularly, when in the different multiple LDPC codes different with encoding rate to code length each all adopts the Bit Allocation in Discrete pattern of special use, can be raised to very high performance to the tolerance limit of error.Yet this need to come conversion bit allocation model in the multiple LDPC code each.

On the other hand, according to the Bit Allocation in Discrete pattern of Figure 189 to Figure 192, identical Bit Allocation in Discrete pattern can be used for the different multiple LDPC codes different with encoding rate of code length, and has eliminated in the situation of Bit Allocation in Discrete pattern that in the different multiple LDPC codes different with encoding rate to code length each all adopts special use in the multiple LDPC code each and come the necessity of conversion bit allocation model.

In addition, to the Bit Allocation in Discrete pattern of Figure 192, can be raised to higher performance to the tolerance limit of error according to Figure 189, although a shade below in the multiple LDPC code each is all adopted the situation of special-purpose Bit Allocation in Discrete pattern.

Particularly, for example, when method of adjustment was 4096QAM, it was 64800 and encoding rate is all LDPC codes of 5/6 and 9/10 that the same bits allocation model among Figure 189 or Figure 190 can be used to code length N.In this way, even adopt identical Bit Allocation in Discrete pattern, also can be raised to higher performance to the tolerance limit of error.

In addition, for example, when method of adjustment was 1024QAM, it was 16200 and encoding rate is all LDPC codes of 3/4,5/6 and 8/9 and code length N is 64800 and encoding rate is 3/4,5/6 and 9/10 LDPC code that the identical Bit Allocation in Discrete pattern of Figure 191 can be used to code length N.So, in this way, even adopt identical Bit Allocation in Discrete pattern, also can be raised to higher performance to the tolerance limit of error.

Simultaneously, for example, when method of adjustment was 4096QAM, it was 16200 and encoding rate is all LDPC codes of 5/6 and 8/9 and code length N is 64800 and encoding rate is 5/6 and 9/10 LDPC code that the identical Bit Allocation in Discrete pattern of Figure 192 can be used to code length N.So, in this way, even adopt identical Bit Allocation in Discrete pattern, also can be raised to higher performance to the tolerance limit of error.

Further describe now the modification of Bit Allocation in Discrete pattern.

Figure 197 illustrate when the LDPC code be that code length N is that 16200 or 64800 bits and encoding rate are any LDPC codes of any one encoding rate of the LDPC code that limits for the parity check matrix H that is for example produced to any parity matrix initial value table shown in Figure 187 by Figure 142 except encoding rate 3/5, modulator approach is the example of QPSK and multiplier b adoptable Bit Allocation in Discrete pattern when being 1 in addition.

When the LDPC code be code length N be 16200 or 64800 and have except 3/5 encoding rate in addition modulator approach be that QPSK and multiplier b are when being 1, demodulation multiplexer 25 take 2 * 1 (=mb) individual bit reads out in the code bit that writes for the memory 31 at column direction * line direction storage (N/ (2 * 1)) * (2 * 1) individual bit in the row direction as unit, and a code bit of reading is offered replacement section 32.

Replacement section 32 is according to (=mb) the individual code bit b with 2 * 1 seen in Figure 197 ₀And b ₁(=b) 2 * 1 (=mb) the individual sign bit y of individual symbol that distribute to 1 ₀And y ₁2 * 1 (=mb) the individual code bit bs of mode to reading from memory 31 ₀And b ₁Replace.

Particularly, according to Figure 197, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₀, and

Code bit b ₁Give sign bit y ₁

It should be noted that in this case, it is also conceivable that and do not carry out replacing and respectively with code bit b ₀And b ₁Former state fixedly is defined as sign bit y ₀And y ₁

It is that code length N is 16200 or 64800 bits and encoding rate for the LDPC code of any encoding rate except 3/5, modulator approach is that 16QAM multiplier b is the example of adoptable Bit Allocation in Discrete pattern in 2 the situation in addition that Figure 198 is illustrated in the LDPC code.

When the LDPC code is that code length N is 16200 or 64800 bits and encoding rate for the LDPC code of any encoding rate except 3/5, modulator approach is that 16QAM multiplier b is when being 2 in addition, demodulation multiplexer 25 take 4 * 2 (=mb) individual bit reads out in the code bit that writes for the memory 31 at column direction * line direction storage (N/ (4 * 2)) * (4 * 2) individual bit in the row direction as unit, and a code bit of reading is offered replacement section 32.

Replacement section 32 according to as among Figure 198 as seen with 4 * 2 (=mb) individual code Bit Allocation in Discrete (=b) 4 * 2 (=mb) individual sign bit y of individual continuous symbol that give 2 ₀And y ₇4 * 2 (=mb) the individual code bit bs of mode to reading from memory 31 ₀And b ₇Replace.

Particularly, according to Figure 198, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₄,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₃,

Code bit b ₆Give sign bit y ₆, and

Code bit b ₇Give sign bit y ₀

It is that 64QAM, LDPC code are that code length N is 16200 or 64800 bits and encoding rate for the LDPC code of any encoding rate except 3/5, multiplier b is the example of adoptable Bit Allocation in Discrete pattern in 2 the situation in addition that Figure 199 is illustrated in modulator approach.

When the LDPC code be code length N be 16200 or 64800 bits and encoding rate for LDPC code, the modulator approach of any encoding rate except 3/5 be 64QAM, when multiplier b is 2 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of column direction * line direction storage (N/ (6 * 2)) * (6 * 2) individual bit by take 6 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

6 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀And b ₁₁Replace, so that such as (=mb) individual code bit b visible 6 * 2 among Figure 199 ₀And b ₁₁(=b) 6 * 2 (=mb) the individual sign bit y of individual continuous symbol that are assigned to 2 ₀And y ₁₁

Particularly, according to Figure 199, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₁₁,

Code bit b ₁Give sign bit y ₇,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₁₀,

Code bit b ₄Give sign bit y ₆,

Code bit b ₅Give sign bit y ₂,

Code bit b ₆Give sign bit y ₉,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₁,

Code bit b ₉Give sign bit y ₈,

Code bit b ₁₀Give sign bit y ₄, and

Code bit b ₁₁Give sign bit y ₀

It is that 256QAM, LDPC code are that code length N is 64800 bits and encoding rate for the LDPC code of any encoding rate except 3/5, multiplier b is the example of adoptable Bit Allocation in Discrete pattern in 2 the situation in addition that Figure 200 is illustrated in modulator approach.

When the LDPC code is that code length N is 64800 bits and encoding rate for the LDPC code of any encoding rate except 3/5, modulator approach is that 256QAM multiplier b is when being 2 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of column direction * line direction storage (64800/ (8 * 2)) * (8 * 2) individual bit by take 8 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

8 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀And b ₁₅Replace, so that such as (=mb) individual code bit b visible 8 * 2 among Figure 200 ₀And b ₁₅(=b) 8 * 2 (=mb) the individual sign bit y of individual continuous symbol that are assigned to 2 ₀And y ₁₅

Particularly, according to Figure 200, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₁₅,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₁₃,

Code bit b ₃Give sign bit y ₃,

Code bit b ₄Give sign bit y ₈,

Code bit b ₅Give sign bit y ₁₁,

Code bit b ₆Give sign bit y ₉,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₁₀,

Code bit b ₉Give sign bit y ₆,

Code bit b ₁₀Give sign bit y ₄,

Code bit b ₁₁Give sign bit y ₇,

Code bit b ₁₂Give sign bit y ₁₂,

Code bit b ₁₃Give sign bit y ₂,

Code bit b ₁₄Give sign bit y ₁₄, and

Code bit b ₁₅Give sign bit y ₀

It is that 256QAM, LDPC code are that code length N is 16200 bits and encoding rate for the LDPC code of any encoding rate except 3/5, multiplier b is the example of adoptable Bit Allocation in Discrete pattern in 1 the situation in addition that Figure 20 1 is illustrated in modulator approach.

When the LDPC code is that code length N is 16200 bits and encoding rate for the LDPC code of any encoding rate except 3/5, modulator approach is that 256QAM multiplier b is when being 1 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of column direction * line direction storage (16200/ (8 * 1)) * (8 * 1) individual bit by take 8 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

8 * 1 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀And b ₇Replace, so that such as (=mb) individual code bit b visible 8 * 1 among Figure 20 1 ₀And b ₇(=b) 8 * 1 (=mb) the individual sign bit y of individual symbol that are assigned to 1 ₀And y ₇

Particularly, according to Figure 20 1, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₃,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₅,

Code bit b ₄Give sign bit y ₂,

Code bit b ₅Give sign bit y ₆,

Code bit b ₆Give sign bit y ₄, and

Code bit b ₇Give sign bit y ₀

It is that code length N is that 16200 or 64800 bits and encoding rate are for the LDPC code of any encoding rate except 3/5, modulator approach is that QPSK multiplier b is the example of 1 o'clock adoptable Bit Allocation in Discrete pattern in addition that Figure 20 2 illustrates the LDPC code.

When the LDPC code is that code length N is 16200 or 64800 bits and encoding rate for the LDPC code of any encoding rate except 3/5, modulator approach is that QPSK multiplier b is when being 1 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of column direction * line direction storage (N/ (2 * 1)) * (2 * 1) individual bit by take 2 * 1 (=mb) individual bit reads out in the row direction as unit, and is provided for replacement section 32.

2 * 1 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀And b ₁Replace, so that such as (=mb) individual code bit b visible 2 * 1 among Figure 20 2 ₀And b ₁(=b) 2 * 1 (=mb) the individual sign bit y of individual symbol that are assigned to 1 ₀And y ₁

Particularly, according to Figure 20 2, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₀,

Code bit b ₁Give sign bit y ₂,

It should be noted that in this case, can also consider not carry out replacing and respectively with code bit b ₀And b ₁Former state fixedly is defined as sign bit y ₀And y ₁

It is that code length N is that 64800 bits and encoding rate are 3/5 LDPC code, modulator approach is that 16QAM and multiplier b are the examples of adoptable Bit Allocation in Discrete pattern in 2 the situation in addition that Figure 20 3 is illustrated in the LDPC code.

When the LDPC code is that the LDPC code is that code length N is that 64800 bits and encoding rate are 3/5 LDPC code, modulator approach is that 16QAM and multiplier b are when being 2 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of column direction * line direction storage (64800/ (4 * 2)) * (4 * 2) individual bit by take 4 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

4 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀And b ₇Replace, so that such as (=mb) individual code bit b visible 4 * 2 among Figure 20 3 ₀And b ₇(=b) 4 * 2 (=mb) the individual sign bit y of individual continuous symbol that are assigned to 2 ₀And y ₇

Particularly, according to Figure 20 3, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₀,

Code bit b ₁Give sign bit y ₅,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₄,

Code bit b ₅Give sign bit y ₇,

Code bit b ₆Give sign bit y ₃, and

Code bit b ₇Give sign bit y ₆

It is that code length N is that 16200 bits and encoding rate are 3/5 LDPC code, modulator approach is that 16QAM and multiplier b are the examples of adoptable Bit Allocation in Discrete pattern in 2 the situation in addition that Figure 20 4 is illustrated in the LDPC code.

When the LDPC code is that the LDPC code is that code length N is that 16200 bits and encoding rate are 3/5 LDPC code, modulator approach is that 16QAM and multiplier b are when being 2 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of column direction * line direction storage (16200/ (4 * 2)) * (4 * 2) individual bit by take 4 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

4 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀And b ₇Replace, so that such as (=mb) individual code bit b visible 4 * 2 among Figure 20 4 ₀And b ₇(=b) 4 * 2 (=mb) the individual sign bit y of individual continuous symbol that are assigned to 2 ₀And y ₇

Particularly, according to Figure 20 4, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₁,

Code bit b ₂Give sign bit y ₄,

Code bit b ₃Give sign bit y ₂,

Code bit b ₄Give sign bit y ₅,

Code bit b ₅Give sign bit y ₃,

Code bit b ₆Give sign bit y ₆, and

Code bit b ₇Give sign bit y ₀

It is that code length N is that 64800 bits and encoding rate are 3/5 LDPC code, modulator approach is that 64QAM and multiplier b are the examples of adoptable Bit Allocation in Discrete pattern in 2 the situation in addition that Figure 20 5 is illustrated in the LDPC code.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 3/5 LDPC code, modulator approach is that 64QAM and multiplier b are when being 2 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of column direction * line direction storage (64800/ (6 * 2)) * (6 * 2) individual bit by take 6 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

6 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀And b ₁₁Replace, so that such as (=mb) individual code bit b visible 6 * 2 among Figure 20 5 ₀And b ₁₁(=b) 6 * 2 (=mb) the individual sign bit y of individual continuous symbol that are assigned to 2 ₀And y ₁₁

Particularly, according to Figure 20 5, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₂,

Code bit b ₁Give sign bit y ₇,

Code bit b ₂Give sign bit y ₆,

Code bit b ₃Give sign bit y ₉,

Code bit b ₄Give sign bit y ₀,

Code bit b ₅Give sign bit y ₃,

Code bit b ₆Give sign bit y ₁,

Code bit b ₇Give sign bit y ₈,

Code bit b ₈Give sign bit y ₄,

Code bit b ₉Give sign bit y ₁₁,

Code bit b ₁₀Give sign bit y ₅, and

Code bit b ₁₁Give sign bit y ₁₀

It is that 64QAM, LDPC code are that code length N is that 16200 bits and encoding rate are 3/5 LDPC code, multiplier b is the example of adoptable Bit Allocation in Discrete pattern in 2 the situation in addition that Figure 20 6 is illustrated in modulator approach.

When the LDPC code is that code length N is that 16200 bits and encoding rate are 3/5 LDPC code, modulator approach is that 64QAM and multiplier b are when being 2 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of column direction * line direction storage (16200/ (6 * 2)) * (6 * 2) individual bit by take 6 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

6 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀And b ₁₁Replace, so that such as (=mb) individual code bit b visible 6 * 2 among Figure 20 6 ₀And b ₁₁(=b) 6 * 2 (=mb) the individual sign bit y of individual continuous symbol that are assigned to 2 ₀And y ₁₁

Particularly, according to Figure 20 6, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₁₁,

Code bit b ₁Give sign bit y ₇,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₁₀,

Code bit b ₄Give sign bit y ₆,

Code bit b ₅Give sign bit y ₂,

Code bit b ₆Give sign bit y ₉,

Code bit b ₇Give sign bit y ₅,

Code bit b ₈Give sign bit y ₁,

Code bit b ₉Give sign bit y ₈,

Code bit b ₁₀Give sign bit y ₄, and

Code bit b ₁₁Give sign bit y ₀

It is that 256QAM, LDPC code are that code length N is that 64800 bits and encoding rate are 3/5 LDPC code, multiplier b is the example of adoptable Bit Allocation in Discrete pattern in 2 the situation in addition that Figure 20 7 is illustrated in modulator approach.

When the LDPC code is that code length N is that 64800 bits and encoding rate are 3/5 LDPC code, modulator approach is that 256QAM and multiplier b are when being 2 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of column direction * line direction storage (64800/ (8 * 2)) * (8 * 2) individual bit by take 8 * 2 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

8 * 2 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀And b ₁₅Replace, so that such as (=mb) individual code bit b visible 8 * 2 among Figure 20 7 ₀And b ₁₅(=b) 8 * 2 (=mb) the individual sign bit y of individual continuous symbol that are assigned to 2 ₀And y ₁₅

Particularly, according to Figure 20 7, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₂,

Code bit b ₁Give sign bit y ₁₁,

Code bit b ₂Give sign bit y ₃,

Code bit b ₃Give sign bit y ₄,

Code bit b ₄Give sign bit y ₀,

Code bit b ₅Give sign bit y ₉,

Code bit b ₆Give sign bit y ₁,

Code bit b ₇Give sign bit y ₈,

Code bit b ₈Give sign bit y ₁₀,

Code bit b ₉Give sign bit y ₁₃,

Code bit b ₁₀Give sign bit y ₇,

Code bit b ₁₁Give sign bit y ₁₄,

Code bit b ₁₂Give sign bit y ₆,

Code bit b ₁₃Give sign bit y ₁₅,

Code bit b ₁₄Give sign bit y ₅, and

Code bit b ₁₅Give sign bit y ₁₂

It is that 256QAM, LDPC code are that code length N is that 16200 bits and encoding rate are 3/5 LDPC code, multiplier b is the example of adoptable Bit Allocation in Discrete pattern in 1 the situation in addition that Figure 20 8 is illustrated in modulator approach.

When the LDPC code is that the LDPC code is that code length N is that 16200 bits and encoding rate are 3/5 LDPC code, modulator approach is that 256QAM and multiplier b are when being 1 in addition, in demodulation multiplexer 25, write for the code bit of the memory 31 of column direction * line direction storage (16200/ (8 * 1)) * (8 * 1) individual bit by take 8 * 1 (=mb) individual bit is read in the row direction as unit, and is provided for replacement section 32.

8 * 1 (=mb) the individual code bit b that 32 pairs of replacement sections are read from memory 31 ₀And b ₇Replace, so that such as (=mb) individual code bit b visible 8 * 1 among Figure 20 8 ₀And b ₇(=b) 8 * 1 (=mb) the individual sign bit y of individual symbol that are assigned to 1 ₀And y ₇

Particularly, according to Figure 20 8, replacement section 32 is replaced, to distribute

Code bit b ₀Give sign bit y ₇,

Code bit b ₁Give sign bit y ₃,

Code bit b ₂Give sign bit y ₁,

Code bit b ₃Give sign bit y ₅,

Code bit b ₄Give sign bit y ₂,

Code bit b ₅Give sign bit y ₆,

Code bit b ₆Give sign bit y ₄, and

Code bit b ₇Give sign bit y ₀

Now, will the deinterleaver 53 that form receiving equipment 12 be described.

Figure 20 9 is the figure that illustrate the processing of the multiplexer 54 that forms deinterleaver 53.

Particularly, Figure 20 9A illustrates the example of the functional configuration of multiplexer 54.

Multiplexer 54 is comprised of inverse permutation unit 1001 and memory 1002.

The sign bit of the symbol that multiplexer 54 will provide from the solution mapping section 52 of previous stage is defined as the processing object of self, carry out the inverse permutation of the replacement Treatment that the demodulation multiplexer 25 corresponding to transmitting apparatus 11 carries out and process (the contrary of replacement Treatment processed), that is, recover the inverse permutation processing of position of yard bit (sign bit) of the LDPC code of replace by replacement Treatment.Then, multiplexer 54 will obtain the row that result that the LDPC code processes as inverse permutation offers next stage and reverse deinterleaver 55.

Particularly, in multiplexer 54, with mb sign bit y of b symbol ₀, y ₁... y _Mb-1Offer inverse permutation unit 1001 take b (continuously) symbol as unit.

Inverse permutation unit 1001 is carried out mb sign bit y ₀To y _Mb-1Layout return to a yard bit b ₀, b ₁... b _Mb-1Original arrangement (the code bit b before the replacement section 32 of the demodulation multiplexer 25 that forms transmitting apparatus 11 sides is replaced ₀, b ₁... b _Mb-1Layout) inverse permutation.Inverse permutation unit 1001 output code bit b ₀To b _Mb-1Result as inverse permutation.

Similar with the memory 31 of the demodulation multiplexer 25 that forms transmitting apparatus 11 sides, memory 1002 has the memory capacity of storing mb bit on (level) direction of being expert at and storing the individual bit of N/ (mb) in row (vertically) direction.In other words, inverse permutation unit 1001 is comprised of mb row of the individual bit of each row storage N/ (mb).

Yet, in memory 1002, carry out from the direction that is written in sense code bit from the memory 31 of the demodulation multiplexer 25 of transmitting apparatus 11 of the code bit of the LDPC code of inverse permutation unit 1001 output, and reading out on the direction with code bit write memory 31 of the code bit of write memory 1002 carried out.

Particularly, seen in Figure 20 9A, carry out continuously writing from the code bit of the LDPC code of inverse permutation unit 1001 outputs on the line direction of the multiplexer 54 of receiving equipment 12 from the first row of memory 1002 to next line take mb bit as unit.

Then, when finishing for writing of the code bit of a code length, multiplexer 54 is from memory 1002 sense code bit on column direction, and the row that the code bit offers rear one-level are reversed deinterleaver 55.

At this, Figure 20 9B is the view that illustrates from memory 1002 sense code bits.

Multiplexer 54 from the leftmost row towards the reading of code bit that from the top of the row that form memory 1002 downward direction (column direction) is carried out the LDPC code that be listed on the right.

Now, the row of describing the deinterleaver 53 that forms receiving equipment 12 with reference to Figure 21 0 reverse the processing of deinterleaver 55.

Figure 21 0 illustrates the example of configuration of the memory 1002 of multiplexer 54.

Memory 1002 has for the memory capacity of storing the individual bit of N/ (mb) and mb the bit of (level) direction storage of being expert in row (vertically) direction, and is comprised of mb row.

Row reverse deinterleaver 55 and go up in the row direction in the code bit write memory 1002 with the LDPC code, and are read to be listed as at column direction at the code bit and control the position of reading beginning when reversing deinterleaving.

Particularly, row reverse deinterleaver 55 to carry out contrary rearrangement and processes: suitably change the starting position of reading that each row sense code bit to a plurality of row begins, returning to original arrangement by the layout that row reverse the code bit that the rearrangement that interweaves crosses.

At this, it is that 16QAM and multiplier b are the examples of the configuration of memory 1002 in 1 the situation that Figure 21 0 is illustrated in modulator approach.Therefore, the amount of bits m of a symbol is 4 bits, thus memory 1002 comprises 4 (=mb) individual row.

Row reverse that deinterleaver 55 (replace multiplexer 54) go up continuously in the row direction towards next line from the first row will be from yard bit write memory 1002 of the LDPC code of inverse permutation unit 1001 outputs.

Like this, if the code bit of a code length write end, then row reverse deinterleaver 55 from the leftmost row towards right-hand column from memory 1002 the top downward direction (column direction) carry out reading of yard bit.

Yet, when writing yard bit, transmitting apparatus 11 sides write the starting position of reading that the starting position is defined as yard bit by row being reversed interleaver 24, and row reverse deinterleaver 55 and carry out yard bit reading from memory 1002.

Particularly, if the address of the position at the top of each row be confirmed as 0 and column direction in each position with the integer representation of ascending order, then when modulator approach be that 16QAM and multiplier b are when being 1, row reverse the starting position of reading of deinterleaver 55 left columns, and to be set to the address be 0 position, to be set to the address be 2 position in the starting position of reading of secondary series (from left to right), tertially read the starting position to be set to the address be 4 position, and to be set to the address be 7 position in the starting position of reading of the 4th row.

Should note, each row non-zero to the address of reading the starting position, carry out yard bit read so that: after the position of reading below proceeding to, read-out position turns back to the top (address is 0 position) of row, reads and proceeds to the last position of and then reading the starting position downwards.Then, afterwards, carry out reading from next (right side) row.

Reverse deinterleaving by carrying out aforesaid this row, row reverse deinterleaving with rearrangement cross the code bit layout return to original arrangement.

Figure 21 1 is the block diagram of another example that the configuration of receiving equipment 12 is shown.

With reference to Figure 21 1, receiving equipment 12 is to receive modulation signals and comprise quadrature demodulation section 51, separate the data processing equipment of mapping section 52, deinterleaver 53 and LDPC lsb decoder 1021 from transmitting apparatus 11.

Quadrature demodulation section 51 receives modulation signals from transmitting apparatus 11, carry out quadrature demodulation system, will offer the mapping section 52 that separates as the symbol (value on I and the Q direction of principal axis) of the result's of quadrature demodulation system acquisition.

It is the solution mapping of the code bit of LDPC code that solution mapping section 52 carries out the symbol transition from quadrature demodulation section 51, and the code bit is offered deinterleaver 53.

Deinterleaver 53 comprises that multiplexing (MUX) device 54, row reverse deinterleaver 55 and odd even deinterleaver 1011, and the code bit of the LDPC code of explaining mapping section 52 by oneself is carried out deinterleaving.

Particularly, the LDPC code that multiplexer 54 is explained mapping section 52 in the future by oneself is defined as it and processes object, and (the contrary of replacement Treatment processed) processed in the inverse permutation of carrying out the replacement Treatment that the demodulation multiplexer 25 corresponding to transmitting apparatus 11 carries out, that is the location restore of the code bit of, replaced processing being replaced is processed to the inverse permutation of origin-location.Then, the LDPC code of multiplexer 54 result's that will process as inverse permutation acquisition offers row and reverses deinterleaver 55.

Row reverse deinterleaver 55 and will be defined as processing object from the LDPC code of multiplexer 54, and carry out reversing row that interleaver 24 carries out with the row by transmitting apparatus 11 of processing as rearrangement and reverse the corresponding row that interweave and reverse deinterleaving.

The LDPC code of acquisition that reverses the result of deinterleaving as row is reversed deinterleaver 55 and is offered odd even deinterleaver 1011 from row.

Odd even deinterleaver 1011 reverses deinterleaver 55 with row to have carried out row and reverses a code bit after the deinterleaving and be defined as it and process object, and carry out odd even deinterleaving corresponding to the odd-even of carrying out with the odd-even device 23 of transmitting apparatus 11 (the contrary of odd-even processed), that is, it is arranged the layout of the code bit of the LDPC code that is changed by odd-even returns to the odd even deinterleaving of original layout.

LDPC code as the result's of odd even deinterleaving acquisition is offered LDPC lsb decoder 1021 from odd even deinterleaver 1011.

Therefore, in the receiving equipment 12 of Figure 21 1, it has been carried out the inverse permutation processing, has been listed as the LDPC code that reverses deinterleaving and odd even deinterleaving, the LDPC code that namely obtains by the LDPC coding according to parity check matrix H is provided for LDPC lsb decoder 1021.

LDPC lsb decoder 1021 uses parity check matrix H itself (being used for the LDPC coding that the LDPC coding section 21 of transmitting apparatus 11 carries out) or uses by parity check matrix H being listed as at least conversion parity matrix that conversion (corresponding to odd-even) obtains to come that the LDPC code from deinterleaver 53 is carried out LDPC and decode.Then, the data that obtain by the LDPC decoding of LDPC lsb decoder 1021 output are as the decoded result of object data.

At this, in the receiving equipment 12 of Figure 21 1, because the LDPC code that obtains by the LDPC coding according to parity check matrix H is offered LDPC lsb decoder 1021 from deinterleaver 53 (the odd even deinterleaver 1011 of deinterleaver 53), using parity check matrix H self (the LDPC coding that is used for the LDPC coding section 21 of transmitting apparatus 11) to carry out in the situation of LDPC decoding of LDPC code, LDPC lsb decoder 1021 can for example configure based on following decoding device: carry out the decoding device configuration of LDPC decoding according to full serial coding/decoding method (singly node being carried out mathematical operation to message (check-node message and variable node message) in the method); Perhaps according to full parallel decoding method (in the method to all nodes simultaneously (walk abreast) carry out mathematical operation to message) carry out other decoding device that LDPC decodes.

In addition, when using the LDPC that carries out the LDPC code by parity check matrix H (being used for the LDPC coding that the LDPC coding section 21 of transmitting apparatus 11 carries out) being carried out at least conversion parity matrix that column permutation (corresponding to odd-even) obtains to decode, LDPC lsb decoder 1021 can configure based on the decoding device with following framework: P (or the divisor of the P except 1) individual check-node and P variable node are carried out check-node mathematical operation and variable node mathematical operation simultaneously; And have be used to carrying out the receive data rearrangement section 310 of column permutation (with similar for the column permutation of the conversion parity matrix of LDPC code for acquisition) with the code bit of rearrangement LDPC code.

Should note, although in Figure 21 1, for convenience of description, be used for carrying out multiplexer 54 that inverse permutation processes, be used for being listed as the odd even deinterleaver 1011 that the row that reverse deinterleaving reverse deinterleaver 55 and be used for carrying out the odd even deinterleaving and configure separated from one anotherly, but the odd-even device 23, the row that are similar to transmitting apparatus 11 reverse interleaver 24 and demodulation multiplexer 25, and multiplexer 54, row reverse in deinterleaver 55 and the odd even deinterleaver 1011 two or more and can be configured to integrate.

Figure 21 2 is block diagrams of the first example that the configuration of the receiving system that can be applied to receiving equipment 12 is shown.

With reference to Figure 21 2, receiving system comprises acquisition unit 1101, transmission line decoding handling part 1102 and information source decoding handling part 1103.

Acquisition unit 1101 is obtained and is comprised at least by the object data (such as view data and the music data of program) via transmission lines (such as terrestrial digital broadcasting, satellite digital broadcasting, catv network, internet or some other network) being carried out the signal of the LDPC code that the LDPC coding obtains.Then, acquisition unit 1101 offers transmission line decoding handling part 1102 with the signal that obtains.

At this, when the signal that is obtained by acquisition unit 1101 is such as from the broadcasting of the broadcasting platform by surface wave, satellite ripple, CATV (cable TV) etc. the time, acquisition unit 1101 can be configured to tuner, STB (set-top box) etc.On the other hand, when the signal that is obtained by acquisition unit 1101 is for example when the webserver transmits with multileaving (multicast) state as the IPTV (internet protocol TV), acquisition unit 1101 is configured to network I/F (interface), such as NIC (network interface card).

Transmission line decoding handling part 1102 carries out the transmission line decoding to be processed, this processing comprises the processing of the error that produces for the signal correction transmission line that acquisition unit 1101 is obtained by transmission line at least, and the signal of the result's that will process as the transmission line decoding acquisition offers information source decoding handling part 1103.

Particularly, the signal that acquisition unit 1101 is obtained by transmission line is the signal that obtains for the error correction of proofreading and correct the error that transmission line produces by carrying out at least, and, to described signal, transmission line decoding handling part 1102 carries out the transmission line decoding to be processed, such as correction processing.

At this, as error correction code, can example such as LDPC coding, Li De-Saloman coding (Reed-Solomon encoding) etc.At this, as error correction code, carry out at least the LDPC coding.

In addition, transmission line decoding processing comprises the demodulation of modulation signal etc. sometimes.

Information source decoding handling part 1103 carries out the information source decoding to be processed, and this processings comprises that at least the compressed information decompress(ion) that will carry out in the signal of transmission line decoding processing is condensed to raw information.

Concrete, sometimes to be processed by compressed encoding by the signal that transmission line obtains by acquisition unit 1101, described compressed encoding is used for compressed information to reduce the data volume such as information such as image, sound.In the case, information source decoding handling part 1103 carries out the information source decoding to be processed, and is condensed to the processing (decompression) of raw information such as the information decompress(ion) that will compress for the signal that has carried out transmission line decoding processing.

It should be noted that when the signal that is obtained by transmission line by acquisition unit 1101 not being carried out compressed encoding, information source decoding handling part 1103 does not carry out the compressed information decompress(ion) is condensed to the processing of raw information.

At this, as decompression, can example such as MPEG (dynamic image expert group) decoding etc.In addition, the transmission line decoding is processed and is sometimes also comprised descrambling except decompression.

In the receiving system of in the above described manner configuration, acquisition unit 1101 receives by data such as image, sound being carried out compressed encoding (such as mpeg encoded) and further compress coding data being carried out the signal that error correction code (such as the LDPC coding) obtains via transmission line.Signal is provided for transmission line decoding handling part 1102.

In transmission line decoding handling part 1102, the signal from acquisition unit 1101 is similar to the processing of for example being undertaken by quadrature demodulation section 51, solution mapping section 52, deinterleaver 53 and LDPC lsb decoder 56 (or LDPC lsb decoder 1021).The signal of the result's that then, decoding is processed as transmission line acquisition is provided for information source decoding handling part 1103.

In information source decoding handling part 1103, the signal from transmission line decoding handling part 1102 is carried out the information source decoding process (such as mpeg decode), and image or the sound of the output result's that decoding is processed as information source acquisition.

The receiving system of Figure 21 2 described above can be applied to such as be used for receiving as the TV tuner of the television broadcasting of digital broadcasting etc.

It should be noted that and in acquisition unit 1101, transmission line decoding handling part 1102 and the information source decoding handling part 1103 each can be configured to autonomous device (hardware (IC (integrated circuit) etc.) or software module).

In addition, for acquisition unit 1101, transmission line decoding handling part 1102 and information source decoding handling part 1103, the combination of the combination of acquisition unit 1101 and transmission line decoding handling part 1102, transmission line decoding handling part 1102 and information source decoding handling part 1103, or the combination of acquisition unit 1101, transmission line decoding handling part 1102 and information source decoding handling part 1103 all can be configured to single autonomous device.

Figure 21 3 is block diagrams of the second example that the configuration of the receiving system that can be applied to receiving equipment 12 is shown.

It should be noted that in Figure 21 3, represent with identical Reference numeral corresponding to the element of Figure 21 2, and suitably the descriptions thereof are omitted in the explanation hereinafter.

The something in common of the receiving system of Figure 21 3 and Figure 21 2 is to comprise acquisition unit 1101, transmission line decoding handling part 1102 and information source decoding handling part 1103, is that with the difference of Figure 21 2 it newly comprises efferent 1111.

Efferent 1111 is the loud speakers that for example be used for to show the display device of image or be used for output sound, and output image, sound etc. are as the signal from 1103 outputs of information source decoding handling part.In other words, efferent 1111 shows image or output sound.

The receiving system of aforesaid Figure 21 3 can be applied to such as be used for receiving TV (television receiver) as the television broadcasting of digital broadcasting, being used for receiving the radio receiver of radio broadcasting etc.

It should be noted that when the signal that is obtained by acquisition unit 1101 be not when not carrying out the form of compressed encoding, be provided for efferent 1111 from the signal of transmission line decoding handling part 1102 outputs.

Figure 21 4 is block diagrams of the 3rd example that the configuration of the receiving system that can be applied to receiving equipment 12 is shown.

It should be noted that in Figure 21 4, represent with identical Reference numeral corresponding to the element of Figure 21 2, and suitably the descriptions thereof are omitted in the explanation hereinafter.

The something in common of the receiving system of Figure 21 4 and Figure 21 2 is to comprise acquisition unit 1101 and transmission line decoding handling part 1102.

Yet the difference of the receiving system of Figure 21 4 and Figure 21 2 is that it does not comprise information source decoding handling part 1103 but newly comprises record section 1121.

Record section 1121 will record on (storage) medium such as CD, hard disk (disk) or flash memory etc. from decode signal (such as transport stream (TS) or the TS bag of the MPEG) record (storage) of handling part 1102 output of transmission line.

The receiving system of aforesaid Figure 21 4 can be applied to the video tape recorder of record television broadcasting etc.

Should note, in Figure 21 4, receiving system can comprise information source decoding handling part 1103, so that the signal (image or the sound that namely obtain by decoding) after information source decoding handling part 1103 has carried out information source decoding processing is recorded section's 1121 records.

One skilled in the art will understand that according to design needs and other factors, can in the scope of claims or its equivalent, carry out various modifications, combination, sub-portfolio and modification.

Claims (15)

1. data processing equipment comprises:

Follow the storage device that direction and column direction come the memory code bit, wherein, code length is that the code bit in the low density parity check code of N bit is written into along the column direction of described storage device, and m bit in the code bit of the described low density parity check code of reading along described line direction is set to a symbol, and wherein, represent the positive integer of being scheduled to b, then described storage device is stored the individual bit of N/ (mb) at described mb bit of line direction storage and at described column direction; The code bit of described low density parity check code is written into and is read out along described line direction afterwards along the described column direction of described storage device; And

Be set at read along the described line direction of described storage device mb code bit in the situation of b described symbol, according to being used for the code Bit Allocation in Discrete of described low density parity check code replaced described mb code bit so that yard bit after replacing forms the displacement apparatus of described sign bit to the allocation rule of the sign bit that is used for representing described symbol;

Wherein, described allocation rule is the rule of the following content of regulation:

The group that described code bit groupings is formed in the probability of error in response to described code bit is set to yard bit group and is set in the situation of sign bit group in response to the group that the probability of error of described sign bit forms described sign bit grouping,

The bit number of the code bit in the group collection of the combination of the sign bit group that is assigned to as the code bit of any described code bit group and this yard bit group, each described code bit group of described group of collection, reach the bit number of the sign bit in each described sign bit group of described group of collection.

2. data processing equipment comprises:

Follow the storage device that direction and column direction come the memory code bit, wherein, code length is that the code bit in the low density parity check code of N bit is written into along the column direction of described storage device, and m bit in the code bit of the described low density parity check code of reading along described line direction is set to a symbol, and wherein, represent the positive integer of being scheduled to b, then described storage device is stored the individual bit of N/ (mb) at described mb bit of line direction storage and at described column direction, and the code bit of described low density parity check code is written into and is read out along described line direction afterwards along the described column direction of described storage device; And

Be set at read along the described line direction of described storage device mb code bit in the situation of b described symbol, according to being used for the code Bit Allocation in Discrete of described low density parity check code replaced described mb code bit so that yard bit after replacing forms the displacement apparatus of described sign bit to the allocation rule of the sign bit that is used for representing described symbol;

Wherein, described low density parity check code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is the low density parity check code of 64,800 bits; And described allocation rule is the rule of the following content of regulation: the group that described code bit groupings is formed in the probability of error in response to described code bit is set to yard bit group and in response to the probability of error of described sign bit the group that described sign bit grouping forms is set in the situation of sign bit group, the group collection of the combination of the sign bit group that is assigned to as yard bit of any described code bit group and this yard bit group, the bit number of the code bit of the described code of each of described group of collection bit group, bit number with sign bit in each described sign bit group of described group of collection;

A described m bit be 12 bits and described integer b be 1 and with 12 code bits as a described sign map to 2 ¹²Namely in the situation of 4096 signaling points,

12 * 1 code bits are grouped into three code bit groups, and

12 * 1 sign bits are grouped into six sign bit groups;

Described allocation rule is stipulated following content:

A code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th,

Two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error,

Two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error,

Two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd,

Two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 4th,

A code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 6th,

A code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and

A code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 6th.

3. data processing equipment comprises:

Follow the storage device that direction and column direction come the memory code bit, wherein, code length is that the code bit in the low density parity check code of N bit is written into along the column direction of storage device, and m bit in the code bit of the described low density parity check code of reading along described line direction is set to a symbol, and wherein, represent the positive integer of being scheduled to b, then described storage device is stored the individual bit of N/ (mb) at described mb bit of line direction storage and at described column direction; The code bit of described low density parity check code is written into and is read out along described line direction afterwards along the described column direction of described storage device; And

Be set at read along the described line direction of described storage device mb code bit in the situation of b described symbol, according to being used for the code Bit Allocation in Discrete of described low density parity check code replaced described mb code bit so that yard bit after replacing forms the displacement apparatus of described sign bit to the allocation rule of the sign bit that is used for representing described symbol;

Wherein, described low density parity check code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 5/6 low density parity check code;

A described m bit is 12 bits, and described integer b is 1; With the code bit of 12 bits as several in 4096 signaling points in 4096QAM, stipulating of a described sign map;

And wherein, described storage device has 12 row, is used for storing 12 * 1 bits and storing the individual bit in 64,800/ (12 * 1) at described column direction at described line direction;

Described displacement apparatus also is represented as bit b at i+1 the bit that the highest significant bit of 12 * 1 code bits reading along the described line direction of described storage device begins _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, according to described allocation rule, replace

With with bit b ₀Be assigned to bit y ₈,

With bit b ₁Be assigned to bit y ₀,

With bit b ₂Be assigned to bit y ₆,

With bit b ₃Be assigned to bit y ₁,

With bit b ₄Be assigned to bit y ₄,

With bit b ₅Be assigned to bit y ₅,

With bit b ₆Be assigned to bit y ₂,

With bit b ₇Be assigned to bit y ₃,

With bit b ₈Be assigned to bit y ₇,

With bit b ₉Be assigned to bit y ₁₀,

With bit b ₁₀Be assigned to bit y ₁₁, and

With bit b ₁₁Be assigned to bit y ₉

4. each described data processing equipment in 3 according to claim 1, wherein:

Described low density parity check code is the low density parity check code by obtaining according to parity matrix execution low-density checksum coding, in described parity matrix, parity matrix as the part corresponding with parity bits this low density parity check code described low density parity check code has step structure

Described data processing equipment also comprises:

The odd-even device be used for to be carried out parity bits with described low density parity check code and is interweaved to the odd-even of the position of other parity bits.

5. data processing equipment according to claim 4, wherein:

The bit number M of the parity bits of described low density parity check code is the value except prime number, and

If in the factor of the bit number M of described parity bits except 1 and M and two factors that product equals the bit number M of described parity bits represented by P and q,

The bit number of the information bit of described low density parity check code represents by K,

More than or equal to 0 and represented by x less than the integer of P, and

More than or equal to 0 and represented by y less than another integer of q,

Described odd-even device will be as the position of individual K+qx+y+1 the code Bit Interleave in the parity bits of K+M code bit of the K+1 of described low density parity check code to K+Py+x+1 code bit.

6. each described data processing equipment in 3 according to claim 1 also comprises:

The rearrangement device be used for to carry out is used for the code bit rearrangement of described low density parity check code being not included in rearrangement process in the prosign so that be included in the code bit of arbitrary row of the parity matrix of described low density parity check code corresponding to a plurality of yards bits of value 1.

7. each described data processing equipment in 3 according to claim 1, wherein:

Described low density parity check code is the low density parity check code that information matrix has loop structure, and described information matrix is the part corresponding to the information bit of described low density parity check code in the parity matrix of described low density parity check code,

Described data processing equipment also comprises:

The rearrangement device, be used for to carry out be used for when the code bit of described low density parity check code will be written into along the described column direction of described storage device, change the row that write original position for every row of described storage device and reverse and interweave, as the rearrangement process of the code bit that is used for the described low density parity check code of rearrangement.

8. data processing equipment according to claim 7, wherein:

The parity matrix corresponding with parity bits described low density parity check code the parity matrix of described low density parity check code has pseudo-loop structure, wherein, except the part of having carried out column permutation, described parity matrix comprises the part with loop structure.

9. data processing equipment according to claim 8, wherein:

Described parity matrix has the step structure that is converted into pseudo-loop structure by described column permutation.

10. data processing equipment according to claim 9 also comprises:

The odd-even device be used for to carry out is used for parity bits with described low density parity check code and interweaves to the odd-even of the position of other parity bits, wherein

Described rearrangement device is carried out row to described low density parity check code and is reversed and interweave after described odd-even.

11. data processing equipment according to claim 10, wherein:

The bit number M of the parity bits of described low density parity check code is the value except prime number, and

If in the factor of the bit number M of described parity bits except 1 and M and two factors that product equals the bit number M of described parity bits represented by P and q,

The bit number of the information bit of described low density parity check code represents by K,

More than or equal to 0 and represented by x less than the integer of P, and

More than or equal to 0 and represented by y less than another integer of q,

Described odd-even device will be as the position of the K+1 of described low density parity check code K+qx+y+1 code Bit Interleave in the parity bits of K+M code bit to K+Py+x+1 yard bit.

12. data processing equipment according to claim 7, wherein,

Described low density parity check code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is the low density parity check code of 64,800 bits,

A described m bit is that 12 bits and described integer b are 1, and

With 12 the code bit mappings of code in the bit of described low density parity check code, 12 signaling points in 4096 signaling points determining with predetermined modulator approach, and

Described storage device has 12 row, is used for storing 12 * 1 bits and storing the individual bit in 64,800/ (12 * 1) at described column direction at described line direction,

Described rearrangement device is used for:

In the situation about being represented by the integer that provides in the ascending order mode by 0 expression and in the address of each position of described the above storage device of column direction in the address of the tip position of described the above storage device of column direction,

To be set to the address be 0 position to the original position that writes of the first row in 12 row of described storage device,

To be set to the address be 0 position to the original position that writes of the secondary series in 12 row of described storage device,

Tertial in 12 row of described storage device writes original position, and to be set to the address be 2 position,

To be set to the address be 2 position to the original position that writes of the 4th row in 12 row of described storage device,

To be set to the address be 3 position to the original position that writes of the 5th row in 12 row of described storage device,

To be set to the address be 4 position to the original position that writes of the 6th row in 12 row of described storage device,

To be set to the address be 4 position to the original position that writes of the 7th row in 12 row of described storage device,

To be set to the address be 5 position to the original position that writes of the 8th row in 12 row of described storage device,

To be set to the address be 5 position to the original position that writes of the 9th row in 12 row of described storage device,

To be set to the address be 7 position to the original position that writes of the tenth row in 12 row of described storage device,

To be set to the address be 8 position to the original position that writes of the 11 row in 12 row of described storage device, and

To be set to the address be 9 position to the original position that writes of the 12 row in 12 row of described storage device.

13. a data processing method, wherein:

Code length is that the code bit in the low density parity check code of N bit is written into along the column direction of storage device, described storage device follows direction and described column direction is stored described code bit, and m bit in the code bit of the described low density parity check code of reading along described line direction is set to a symbol, and

Represent the positive integer of being scheduled to b,

Described storage device is stored the individual bit of N/ (mb) at described mb bit of line direction storage and at described column direction;

The code bit of described low density parity check code is written into and is read out along described line direction afterwards along the described column direction of described storage device;

Wherein, mb the code bit of reading along the described line direction of described storage device is set in the situation of b described symbol,

According to being used for code Bit Allocation in Discrete with described low density parity check code to the allocation rule for the sign bit that represents described symbol, described data processing method comprises displacement method, this displacement method is used for replacing described mb code bit, so that the code bit after the displacement forms described sign bit;

Described allocation rule is the rule of the following content of regulation:

The group that described code bit groupings is formed in the probability of error in response to described code bit is set to yard bit group and is set in the situation of sign bit group in response to the group that the probability of error of described sign bit forms described sign bit grouping,

The group collection of the combination of the sign bit group that is assigned to as the described code bit of any described code bit group and this yard bit group reaches

The bit number of the sign bit in the bit number of the code bit in the described code of each of the described group of collection bit group and each described sign bit group of described group of collection.

14. a data processing method, wherein:

Code length is that the code bit in the low density parity check code of N bit is written into along the column direction of storage device, described storage device follows direction and described column direction is stored described code bit, and m bit in the code bit of the described low density parity check code of reading along described line direction is set to a symbol, and

Represent the positive integer of being scheduled to b,

Described storage device is stored the individual bit of N/ (mb) at described mb bit of line direction storage and at described column direction;

The code bit of described low density parity check code is written into and is read out along described line direction afterwards along the described column direction of described storage device;

Wherein, mb the code bit of reading along the described line direction of described storage device is set in the situation of b described symbol,

According to being used for code Bit Allocation in Discrete with described low density parity check code to the allocation rule for the sign bit that represents described symbol, described data processing method comprises displacement step, this displacement step is used for replacing described mb code bit, so that the code bit after the displacement forms described sign bit;

Described low density parity check code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is the low density parity check code of 64,800 bits;

Described allocation rule is the rule of the following content of regulation:

The group that described code bit groupings is formed in the probability of error in response to described code bit is set to yard bit group and is set in the situation of sign bit group in response to the group that the probability of error of described sign bit forms described sign bit grouping,

The group collection of the combination of the sign bit group that is assigned to as the code bit of any described code bit group and this yard bit group reaches

The bit number of the sign bit in the bit number of the code bit in the described code of each of the described group of collection bit group and each described sign bit group of described group of collection;

A described m bit be 12 bits and described integer b be 1 and with 12 code bits as a described sign map to 2 ¹²Namely in the situation of 4096 signaling points,

12 * 1 code bits are grouped into three code bit groups, and

12 * 1 sign bits are grouped into six sign bit groups;

Described allocation rule is stipulated following content:

A code bit in the best code bit group of the probability of error is assigned to a sign bit in the good sign bit group of the probability of error the 5th,

Two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the best sign bit group of the probability of error,

Two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the second-best sign bit group of the probability of error,

Two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 3rd,

Two code bits in the second-best code of the probability of error bit group are assigned to two sign bits in the good sign bit group of the probability of error the 4th,

A code bit in the second-best code of the probability of error bit group is assigned to a sign bit in the good sign bit group of the probability of error the 6th,

A code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 5th, and

A code bit in the good code bit group of the probability of error the 3rd is assigned to a sign bit in the good sign bit group of the probability of error the 6th.

15. a data processing method, wherein:

Code length is that the code bit in the low density parity check code of N bit is written into along the column direction of storage device, described storage device follows direction and described column direction is stored described code bit, and m bit in the code bit of the described low density parity check code of reading along described line direction is set to a symbol, and

Represent the positive integer of being scheduled to b,

Described storage device is stored the individual bit of N/ (mb) at described mb bit of line direction storage and at described column direction;

The code bit of described low density parity check code is written into and is read out along described line direction afterwards along the described column direction of described storage device;

Wherein, mb the code bit of reading along the described line direction of described storage device is set in the situation of b described symbol,

According to being used for code Bit Allocation in Discrete with described low density parity check code to the allocation rule for the sign bit that represents described symbol, described data processing method comprises displacement step, this displacement step is used for replacing described mb code bit, so that the code bit after the displacement forms described sign bit;

Described low density parity check code be stipulate in DVB-S.2 or the DVB-T.2 standard, code length N is that 64,800 bits and encoding rate are 5/6 low density parity check code;

A described m bit is 12 bits, and described integer b is 1;

Several in 4096 signaling points that the code bit of 12 bits is stipulated in the 4096QAM as a described sign map;

Described storage device has 12 row, is used for storing 12 * 1 bits and storing the individual bit in 64,800/ (12 * 1) at described column direction at described line direction;

Described displacement step is carried out following action:

I+1 the bit that begins at the highest significant bit of 12 * 1 code bits reading along the described line direction of described storage device is represented as bit b _iAnd be represented as bit y since i+1 the bit of high significant bit of 12 * 1 sign bits of a symbol _iSituation under, according to described allocation rule, replace

With with bit b ₀Be assigned to bit y ₈,

With bit b ₁Be assigned to bit y ₀,

With bit b ₂Be assigned to bit y ₆,

With bit b ₃Be assigned to bit y ₁,

With bit b ₄Be assigned to bit y ₄,

With bit b ₅Be assigned to bit y ₅,

With bit b ₆Be assigned to bit y ₂,

With bit b ₇Be assigned to bit y ₃,

With bit b ₈Be assigned to bit y ₇,

With bit b ₉Be assigned to bit y ₁₀,

With bit b ₁₀Be assigned to bit y ₁₁, and

With bit b ₁₁Be assigned to bit y ₉

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