CN101901131B - Audio coding/decoding bit level reading/writing acceleration device and acceleration reading/writing method thereof - Google Patents

Abstract

The invention discloses an audio coding/decoding bit level reading/writing acceleration device and acceleration reading/writing method thereof, belonging to the technical field of signal processing. The device comprises a bit reading/writing module, a position recording module, a reading/writing direction module and an active register mark module, wherein the reading/writing direction module is connected with the bit reading/writing module and the active register mark module respectively, and outputs reading/writing direction information; the active register mark module is connected with the position recording module and the bit reading/writing module respectively, and outputs a current reading/writing register number; and the position recording module is connected with the bit reading/writing module and outputs reading/writing position information. By adding a special hardware module into an embedded processor or DSP, the invention effectively reduces the number of instructions and the number of clock periods required by bit level reading/writing operation, thereby reducing the time required by the bit level reading/writing operation and improving the speed and the efficiency of audio coding/decoding.

Description

Audio coding/decoding bit level reading/writing acceleration device and acceleration reading/writing method thereof

Technical field

What the present invention relates to is the device in a kind of signal processing technology field, specifically is a kind of audio coding/decoding bit level reading/writing acceleration device and acceleration reading/writing method thereof.

Background technology

In existing audio code decode algorithm, in MP3 standard and AAC standard, usually need data are carried out the read-write operation of bit-level.For example, entropy is encoded to a kind of undistorted encryption algorithm that often uses in the audio coding process.In the entropy encryption algorithm, the code word of compiling out need be generally several bits, be written to destination register from several successive bits that a certain ad-hoc location begins.Similarly, in the entropy decoding algorithm in the audio decoder process, several successive bits in the code stream need be read out and write destination register from several successive bits that lowest order begins.

At present, audio code decode algorithm is realized by flush bonding processor or digital signal processor (DSP) usually.Find in general flush bonding processor or DSP, do not have special bit level reading/writing operational order through the retrieval to prior art.Therefore, read operation and the write operation of finishing bit-level need form with some the packings of orders usually.These instructions comprise displacement, logical and, logical OR and move etc.

Find through the retrieval to prior art, in " MIPS architecture and programming " book that people such as Liu Peilin write, introduced MIPS32 processor and instruction set thereof.If use this processor to carry out the bit level reading/writing operation, as data (the 2nd bit to the 0 bit of [2:0] expression register with [2:0] bit of a certain register R3, write in [9:7] bit of another register R4 down together), and the direction that writes is little-endian, and general operating process is as follows:

1. write among the temporary register R5 to R3 7 bit manipulations that move to left, and with the result.

Instruction: DSLL R5, R3, #7

2. R5 is carried out the logical and operation, making R5 all the other bits except [9:7] bit is 0.

Instruction: DADDI R6,0,0X7

DSLL R6，R6，#7

ANDI R5，R5，R6

Wherein: R6 is a temporary register, down together.

3. R4 is carried out the logical and operation, make [9:7] bit of R4 become 0, all the other bits are constant.

Instruction: XORI R6, R6,0XFFFF

ANDI R4，R4，R6

4. R4 and R5 are carried out the logical OR operation, the result is write R4.

Instruction: OR R4, R5, R4

All need computing is followed the tracks of in the bit position during each the operation, with the position of determining to write.A write operation of this example just need be used 7 instructions.In addition, when running into the border of word, general flush bonding processor or DSP need read respectively from two 32 bit registers or write some bits, splice then, the bit level reading/writing operation will become very complicated, thereby need to use more instructions to finish.

Therefore, when using general flush bonding processor or DSP to realize the bit level reading/writing operation, need more instruction number and clock periodicity.The bit level reading/writing operation has seriously reduced the speed of processor or the encoding and decoding of DSP processing audio.

Summary of the invention

The present invention is directed to the prior art above shortcomings, a kind of audio coding/decoding bit level reading/writing acceleration device and acceleration reading/writing method thereof are provided, by in flush bonding processor or DSP, increasing special hardware module, effectively reduce bit level reading/writing and operate needed instruction number and clock periodicity, operate the needed time thereby reduce bit level reading/writing, improve speed and the efficient of audio coding decoding.

The present invention is achieved by the following technical solutions:

The present invention relates to a kind of audio coding/decoding bit level reading/writing acceleration device, comprise: bit module for reading and writing, position logging modle, read-write direction module and enliven the register flag module, wherein: read-write direction module is respectively with bit module for reading and writing, position record with enliven the register flag module and link to each other and export and read and write directional information, position logging modle and bit module for reading and writing with enliven the register flag module and be connected and export read and write position information, enliven the register flag module and be connected with the bit module for reading and writing and export current read-write register number.

Described read-write direction module is bit read-write direction register (SDIR), its bit wide is 1 bit, the direction that this bit read-write direction register is used for the control bit read-write and skips, when bit read-write direction register is 1, the direction of the read-write of expression bit is to hang down bit to the higher bit position, otherwise expression read-write direction is that the higher bit position is to low bit.

Described bit module for reading and writing comprises: two bit input-output registers (BITIO1 and BITIO2), its bit wide is 32 bits, wherein: the input end of the first bit input-output register respectively at read-write direction module, enliven register flag module, position logging modle and be connected with external data bus and transmit and continue direction, current read-write register number, read and write position and read data information, the output terminal of the first bit input-output register is connected with external data bus and transmits and writes data message; The input end of the second bit input-output register respectively at read-write direction module, enliven register flag module, position logging modle and be connected with external data bus and transmit and continue direction, current read-write register number, read and write position and read data information, the output terminal of the second bit input-output register is connected with external data bus and transmits and writes data message.The first bit input-output register and the second bit input-output register are used for serving as the Data Source of bit-level read operation; When carrying out the bit-level write operation, the target that the first bit input-output register and the second bit input-output register are used for serving as the bit-level write operation.

Described position logging modle comprises: bit position register (SPOS) and position update module, wherein: the input end of bit position register links to each other with the position update module and transmission of location information, the output terminal of bit position register respectively with the position update module, enliven that the register flag module is connected with the bit module for reading and writing and transmission of location information; The input end of position update module is respectively at being connected with bit position register with read-write direction module and transmitting read-write direction and positional information, and the output terminal of position update module links to each other with bit position register and transmission of location information.Bit position register is 5 bit register, is used to refer to the position of the initial bits of bit-level read operation.After the position update module is finished the bit read-write operation, the automatic renewal of bit position register.

The described register flag module of enlivening comprises: enliven register flag (ABITIOR) and sign update module, wherein: the input end that enlivens register flag links to each other with the sign update module and transmits current read-write register information, and the output terminal that enlivens register flag is respectively at being connected with the bit module for reading and writing and transmitting current read-write register information with indicating update module; The input end of sign update module respectively with enliven register flag, read-write direction module and position record and link to each other and transmit current read-write register number, read-write direction and read and write position information, the output terminal that indicates update module with enliven register flag and be connected and transmit current read-write register information.Enlivening register flag is 1 bit register, and 0 represents the first bit input-output register for enlivening register, and 1 represents the second bit input-output register for enlivening register.After the sign update module is finished the bit read-write operation, enliven the automatic renewal of register flag.

The read-write acceleration method of the above-mentioned audio bit level reading/writing acceleration device that the present invention relates to comprises read operation stage and write operation stage, wherein:

The described read operation stage may further comprise the steps:

The first step is loaded into data the bit input-output register from external memory or other general-purpose registers.

In second step, if adopt the currency of each register, then skip this step.Otherwise, read read-write directional information, current read-write register number and read and write position information and deposit in the corresponding register.

Described read-write directional information, current read-write register number and read and write position information comprise the bit position initial value, the read-write direction.

The 3rd step, bit number (the Length that reads according to value, the value of enlivening register flag and the needs of the value of bit position register, bit read-write direction register, span is 0 to 31), from active bit input-output register, read corresponding value.If all bits that read have exceeded active bit input-output register, then read method with annular and read at inactive input-output register.

Described annular reads method and refers to: read or read to the non-low bit direction of enlivening register from the higher bit of enlivening register to the non-higher bit direction of enlivening register from the lowest bit of enlivening register.

In the 4th step, position update module and sign update module are upgraded automatically.

Wherein: the update rule of bit position register is as follows:

$\mathrm{SPOS}=\left\{\begin{array}{c}(\mathrm{SPOS}+\mathrm{Length})\%32,\mathrm{IfSDIR}=1;\\ (\mathrm{SPOS}-\mathrm{Length}+32)\%32,\mathrm{IfSDIR}=0.\end{array}\right.$

Wherein: SPOS represents the value of bit position register, the length that the Length representative is read, and SDIR is the value of bit read-write direction register, % represents modulo operation.

The update rule that enlivens register flag is as follows:

If the value of bit read-write direction register is 1,

$\mathrm{ABITIR}=\left\{\begin{array}{c}\mathrm{notABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})>31;\\ \mathrm{ABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})\≤31.\end{array}\right.$

Otherwise, if the value of bit read-write direction register is 0,

$\mathrm{ABITIR}=\left\{\begin{array}{c}\mathrm{notABITIR},\mathrm{If}(\mathrm{SPOS}-\mathrm{Length})<0;\\ \mathrm{ABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})\&GreaterEqual;0.\end{array}\right.$

Wherein: the ABITIR representative enlivens the value of register flag, and SPOS represents the value of bit position register, the length that the Length representative is read, and not represents inversion operation.

The 5th step repeated above-mentioned second step to the 4th step, needed the data that read in running through the bit input-output register.

The described write operation stage may further comprise the steps:

Step 1 if adopt the currency of each register, is then skipped this step.Otherwise, read read-write directional information, current read-write register number and read and write position information and deposit in the corresponding register.

Described read-write directional information, current read-write register number and read and write position information comprise the bit position initial value, the read-write direction.

Step 2, the bit number (Length, span is 0 to 31) according to value, the value of enlivening register flag and the needs of the value of bit position register, bit read-write direction register write writes data in the active bit input-output register.If all bits that write have exceeded the scope of active bit input-output register, then write in inactive input-output register with annular wrting method.

Described annular wrting method refers to: write or write to the non-low bit direction of enlivening register from the higher bit of enlivening register to the non-higher bit direction of enlivening register from the lowest bit of enlivening register.

Step 3, position update module and sign update module are upgraded automatically.

Wherein: the update rule of bit position register is as follows:

$\mathrm{SPOS}=\left\{\begin{array}{c}(\mathrm{SPOS}+\mathrm{Length})\%32,\mathrm{IfSDIR}=1;\\ (\mathrm{SPOS}-\mathrm{Length}+32)\%32,\mathrm{IfSDIR}=0.\end{array}\right.$

Wherein: SPOS represents the value of bit position register, the length that the Length representative writes, and SDIR is the value of bit read-write direction register, % represents modulo operation.

The update rule that enlivens register flag is as follows:

If the value of bit read-write direction register is 1,

$\mathrm{ABITIR}=\left\{\begin{array}{c}\mathrm{notABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})>31;\\ \mathrm{ABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})\&le;31.\end{array}\right.$

Otherwise, if the value of bit read-write direction register is 0,

$\mathrm{ABITIR}=\left\{\begin{array}{c}\mathrm{notABITIR},\mathrm{If}(\mathrm{SPOS}-\mathrm{Length})<0;\\ \mathrm{ABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})\&GreaterEqual;0.\end{array}\right.$

Wherein: the ABITIR representative enlivens the value of register flag, and SPOS represents the value of bit position register, the length that the Length representative is read, and not represents inversion operation.

Step 4 repeats above-mentioned steps one to step 3, up to having write the data that need write in the bit input-output register.

Step 5 writes external memory or other general-purpose registers with the value of bit input-output register.

The present invention compared with prior art has the following advantages: the invention provides a kind of audio coding/decoding bit level reading/writing acceleration device and acceleration reading/writing method thereof, by in flush bonding processor, increasing special hardware module, from the position of motion tracking bit level reading/writing, operations such as displacement, logical and, logical OR, movement and splicing have been saved.Therefore, the present invention can effectively reduce bit level reading/writing and operate needed instruction number and clock periodicity, operates the needed time thereby reduce bit level reading/writing, improves speed and the efficient of audio coding decoding.

Description of drawings

Fig. 1 is that device of the present invention is formed connection diagram.

Fig. 2 is the variation synoptic diagram that automatic update bit reads the position.

Fig. 3 is the synoptic diagram that annular reads wiring method.

Embodiment

Below embodiments of the invention are elaborated, present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed embodiment and concrete operating process, but protection scope of the present invention is not limited to following embodiment.

The operation of present embodiment is divided into two parts, first reads address A from the 16th to the 23rd data (8 bit) from external memory, and second portion writes a certain data (16 bit) 24 to 31 and the 0th to the 7th of next address (A+4) of address A.

As shown in Figure 1, present embodiment relates to a kind of audio coding/decoding bit level reading/writing acceleration device, comprising: bit module for reading and writing, position logging modle, read-write direction module and enliven the register flag module.Wherein: read-write direction module is respectively with bit module for reading and writing, position record with enliven the register flag module and link to each other and export and read and write directional information, position logging modle and bit module for reading and writing with enliven the register flag module and be connected and export read and write position information, enliven the register flag module and be connected with the bit module for reading and writing and export current read-write register number.

Described read-write direction module comprises: bit read-write direction register (SDIR), bit wide is 1 bit.Bit read-write direction register, the direction that is used for the control bit read-write and skips.When bit read-write direction register was 1, the direction of the read-write of expression bit was for hanging down bit to higher bit; When bit read-write direction register was 0, the direction of the read-write of expression bit was that higher bit is to low bit.

Described bit module for reading and writing comprises: two bit input-output registers (BITIO1 and BITIO2), its bit wide is 32 bits.Wherein: the input end of the first bit input-output register respectively at read-write direction module, enliven register flag module, position logging modle and be connected with external data bus and transmit and continue direction, current read-write register number, read and write position and read data information, the output terminal of the first bit input-output register is connected with external data bus and transmits and writes data message; The input end of the second bit input-output register respectively at read-write direction module, enliven register flag module, position logging modle and be connected with external data bus and transmit and continue direction, current read-write register number, read and write position and read data information, the output terminal of the second bit input-output register is connected with external data bus and transmits and writes data message.The first bit input-output register and the second bit input-output register are used for serving as the Data Source of bit-level read operation; When carrying out the bit-level write operation, the target that the first bit input-output register and the second bit input-output register are used for serving as the bit-level write operation.

Described position logging modle comprises: bit position register (SPOS) and automatic update module.Wherein: the input end of bit position register links to each other with the position update module and transmission of location information, the output terminal of bit position register respectively with the position update module, enliven that the register flag module is connected with the bit module for reading and writing and transmission of location information; The input end of position update module is respectively at being connected with bit position register with read-write direction module and transmitting read-write direction and positional information, and the output terminal of position update module links to each other with bit position register and transmission of location information.Bit position register is 5 bit register, is used to refer to the position of the initial bits of bit-level read operation.After the position update module is finished the bit read-write operation, the automatic renewal of bit position register.

The described register flag module of enlivening comprises: enliven register flag (ABITIOR) and automatic update module.Wherein: the input end that enlivens register flag links to each other with the sign update module and transmits current read-write register information, and the output terminal that enlivens register flag is respectively at being connected with the bit module for reading and writing and transmitting current read-write register information with indicating update module; The input end of sign update module respectively with enliven register flag, read-write direction module and position record and link to each other and transmit current read-write register number, read-write direction and read and write position information, the output terminal that indicates update module with enliven register flag and be connected and transmit current read-write register information.Enlivening register flag is 1 bit register, and 0 represents the first bit input-output register for enlivening register, and 1 represents the second bit input-output register for enlivening register.After the sign update module is finished the bit read-write operation, enliven the automatic renewal of register flag.

The read-write acceleration method of the above-mentioned audio bit level reading/writing acceleration device of present embodiment may further comprise the steps:

If currently be operating as read operation, namely from the bit input-output register, read data,

The first step is loaded into data the bit input-output register from external memory or general-purpose register.

In second step, if adopt the currency of each register, then skip this step.Otherwise, read read-write directional information, current read-write register number and read and write position information and deposit in the corresponding register.

Described read-write directional information, current read-write register number and read and write position information comprise the bit position initial value, the read-write direction.

The 3rd step, bit number (the Length that reads according to value, the value of enlivening register flag and the needs of the value of bit position register, bit read-write direction register, span is 0 to 31), from active bit input-output register, read corresponding value.If all bits that read have exceeded active bit input-output register, then read method with annular and read at inactive input-output register.

Described annular reads method and refers to: read or read to the non-low bit direction of enlivening register from the higher bit of enlivening register to the non-higher bit direction of enlivening register from the lowest bit of enlivening register.

In the 4th step, position update module and sign update module are upgraded automatically.

Wherein: the update rule of bit position register is as follows:

$\mathrm{SPOS}=\left\{\begin{array}{c}(\mathrm{SPOS}+\mathrm{Length})\%32,\mathrm{IfSDIR}=1;\\ (\mathrm{SPOS}-\mathrm{Length}+32)\%32,\mathrm{IfSDIR}=0.\end{array}\right.$

Wherein: SPOS represents the value of bit position register, the length that the Length representative is read, and SDIR is the value of bit read-write direction register, % represents modulo operation.

The update rule that enlivens register flag is as follows:

If the value of bit read-write direction register is 1,

$\mathrm{ABITIR}=\left\{\begin{array}{c}\mathrm{notABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})>31;\\ \mathrm{ABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})\&le;31.\end{array}\right.$

Otherwise, if the value of bit read-write direction register is 0,

$\mathrm{ABITIR}=\left\{\begin{array}{c}\mathrm{notABITIR},\mathrm{If}(\mathrm{SPOS}-\mathrm{Length})<0;\\ \mathrm{ABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})\&GreaterEqual;0.\end{array}\right.$

Wherein: the ABITIR representative enlivens the value of register flag, and SPOS represents the value of bit position register, the length that the Length representative is read, and not represents inversion operation.

The 5th step repeated above-mentioned second step to the 4th step, needed the data that read in running through the bit input-output register.

The first of present embodiment is read operation.Earlier the data with address A deposit current active bit-level input-output register (being assumed to be the first bit-level input-output register) in, deposit the data of address A+4 in current inactive bit-level input-output register (being assumed to be the second bit-level input-output register).As shown in Figure 2, setting the bit position initial value is 16, and the read-write direction is 1 (from hanging down bit to higher bit).Then from active bit-level input-output register, read 16 bits to 23 bits.At last bit position register is automatically updated into 24, enlivens register flag and remain unchanged.So just finished the read operation of present embodiment first.

Otherwise, if the current write operation that is operating as is about to data and writes in the bit input-output register,

The first step if adopt the currency of each register, is then skipped this step.Otherwise, read read-write directional information, current read-write register number and read and write position information and deposit in the corresponding register.

Described read-write directional information, current read-write register number and read and write position information comprise the bit position initial value, the read-write direction.

In second step, the bit number (Length, span is 0 to 31) according to value, the value of enlivening register flag and the needs of the value of bit position register, bit read-write direction register write writes data in the active bit input-output register.If all bits that write have exceeded the scope of active bit input-output register, then write in inactive input-output register with annular wrting method.

Described annular wrting method refers to: write or write to the non-low bit direction of enlivening register from the higher bit of enlivening register to the non-higher bit direction of enlivening register from the lowest bit of enlivening register.

In the 3rd step, position update module and sign update module are upgraded automatically.

Wherein: the update rule of bit position register is as follows:

$\mathrm{SPOS}=\left\{\begin{array}{c}(\mathrm{SPOS}+\mathrm{Length})\%32,\mathrm{IfSDIR}=1;\\ (\mathrm{SPOS}-\mathrm{Length}+32)\%32,\mathrm{IfSDIR}=0.\end{array}\right.$

Wherein: SPOS represents the value of bit position register, the length that the Length representative writes, and SDIR is the value of bit read-write direction register, % represents modulo operation.

The update rule that enlivens register flag is as follows:

If the value of bit read-write direction register is 1,

$\mathrm{ABITIR}=\left\{\begin{array}{c}\mathrm{notABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})>31;\\ \mathrm{ABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})\&le;31.\end{array}\right.$

Otherwise, if the value of bit read-write direction register is 0,

$\mathrm{ABITIR}=\left\{\begin{array}{c}\mathrm{notABITIR},\mathrm{If}(\mathrm{SPOS}-\mathrm{Length})<0;\\ \mathrm{ABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})\&GreaterEqual;0.\end{array}\right.$

Wherein: the ABITIR representative enlivens the value of register flag, and SPOS represents the value of bit position register, the length that the Length representative is read, and not represents inversion operation.

In the 4th step, repeat above-mentioned three steps of the first step to the, up to having write the data that need write in the bit input-output register.

In the 5th step, the value of bit input-output register is write external memory or general-purpose register.

The second portion of present embodiment is write operation.As shown in Figure 3, use the value after each register automatically upgrades, according to annular wiring method, data write active bit-level input-output register 24 bits to 32 bits and inactive bit-level input-output register 0 bit to 7 bits.Then bit position register is automatically updated into 8, enlivens register flag and be automatically updated into 1.Value with the first bit-level input-output register writes address A at last, and the value of the second bit-level input-output register is write address A+4.

When the method for the method that adopts present embodiment respectively and prior art is handled same problem, the present embodiment method is by using the audio bit level reading/writing acceleration device in processor, only need 6 instructions just can finish, and at least 21 instructions of existing Technology Need just can be finished.Therefore, the present embodiment method can significantly reduce bit level reading/writing and operate needed instruction number and clock periodicity, operates the needed time thereby reduce bit level reading/writing, improves speed and the efficient of audio coding decoding.

Claims (8)

1. audio coding/decoding bit level reading/writing acceleration device, comprise: the bit module for reading and writing, the position logging modle, read and write the direction module and enliven the register flag module, it is characterized in that: read-write direction module respectively with the bit module for reading and writing, the position logging modle with enliven the register flag module link to each other and export the read-write directional information, this directional information refer to low bit to the higher bit position or the higher bit position to the direction of low bit, position logging modle and bit module for reading and writing with enliven the register flag module and be connected and export read and write position information, this positional information refers to the position of the initial bits of read-write operation, enlivens the register flag module and is connected with the bit module for reading and writing and exports current read-write register number;

The described register flag module of enlivening comprises: enliven register flag and sign update module, wherein: the input end that enlivens register flag links to each other with the sign update module and transmits current read-write register information, and the output terminal that enlivens register flag is connected with the bit module for reading and writing and transmits current read-write register information with indicating update module respectively; The input end of sign update module respectively with enliven register flag, read-write direction module links to each other with the position logging modle and transmit current read-write register number, read-write direction and read and write position information, the output terminal that indicates update module with enliven register flag and be connected and transmit current read-write register information.

2. audio coding/decoding bit level reading/writing acceleration device according to claim 1, it is characterized in that, described read-write direction module is bit read-write direction register, its bit wide is 1 bit, the direction that this bit read-write direction register is used for the control bit read-write and skips, when bit read-write direction register was 1, the direction of the read-write of expression bit was to hang down bit to the higher bit position, otherwise expression read-write direction is that the higher bit position is to low bit.

3. audio coding/decoding bit level reading/writing acceleration device according to claim 2, it is characterized in that, described bit module for reading and writing comprises: two bit input-output registers, wherein: the input end of the first bit input-output register respectively with read-write direction module, enliven register flag module, position logging modle and be connected with external data bus and transmit and read and write direction, current read-write register number, read and write position and read data information, the output terminal of the first bit input-output register is connected with external data bus and transmits and writes data message; The input end of the second bit input-output register respectively with read-write direction module, enliven register flag module, position logging modle and be connected with external data bus and transmit and read and write direction, current read-write register number, read and write position and read data information, the output terminal of the second bit input-output register is connected with external data bus and transmits and writes data message.

4. audio coding/decoding bit level reading/writing acceleration device according to claim 3, it is characterized in that, described position logging modle comprises: bit position register and position update module, wherein: the input end of bit position register links to each other with the position update module and transmission of location information, the output terminal of bit position register respectively with the position update module, enliven that the register flag module is connected with the bit module for reading and writing and transmission of location information; The input end of position update module is connected with bit position register with read-write direction module respectively and transmits read-write direction and positional information, and the output terminal of position update module links to each other with bit position register and transmission of location information.

5. audio coding/decoding bit level reading/writing acceleration device according to claim 4 is characterized in that, described bit position register is 5 bit register, is used to refer to the position of the initial bits of bit-level read operation.

6. audio coding/decoding bit level reading/writing acceleration device according to claim 4, it is characterized in that, the described register flag of enlivening is 1 bit register, and 0 represents the first bit input-output register for enlivening register, and 1 represents the second bit input-output register for enlivening register.

7. the read-write acceleration method of an audio coding/decoding bit level reading/writing acceleration device according to claim 6 is characterized in that, comprises read operation stage and write operation stage, wherein:

The described read operation stage may further comprise the steps:

The first step is loaded into data the described bit input-output register from external memory or other general-purpose registers;

In second step, when the currency that adopts each register, then skip this step, otherwise read read-write directional information, current read-write register number and read and write position information and deposit in the corresponding register;

The 3rd step, the bit number that reads according to value, the value of enlivening register flag and the needs of the value of bit position register, bit read-write direction register, from active bit input-output register, read corresponding value, when all bits that read have exceeded active bit input-output register, then read method with annular and read at inactive bit input-output register;

In the 4th step, position update module and sign update module are upgraded automatically;

The 5th step repeated above-mentioned second step to the 4th step, needed the data that read in running through the bit input-output register;

The described write operation stage may further comprise the steps:

Step 1 when the currency that adopts each register, is then skipped this step, otherwise, read read-write directional information, current read-write register number and read and write position information and deposit in the corresponding register;

Step 2, the bit number that writes according to value, the value of enlivening register flag and the needs of the value of bit position register, bit read-write direction register, data are write in the active bit input-output register, when all bits that write have exceeded the scope of active bit input-output register, then write in inactive input-output register with annular wrting method;

Step 3, position update module and sign update module are upgraded automatically;

Step 4 repeats above-mentioned steps one to step 3, up to having write the data that need write in the bit input-output register;

Step 5 writes external memory or other general-purpose registers with the value of bit input-output register;

Described annular reads method and refers to: read or read to the non-low bit direction of enlivening register from the higher bit of enlivening register to the non-higher bit direction of enlivening register from the lowest bit of enlivening register;

Described annular wrting method refers to: write or write to the non-low bit direction of enlivening register from the higher bit of enlivening register to the non-higher bit direction of enlivening register from the lowest bit of enlivening register.

8. method according to claim 7 is characterized in that, it is as follows that described position update module and sign update module are upgraded concrete steps automatically:

1) the automatic renewal of sign update module:

The value of reading and writing the direction register when bit is 1,

$\mathrm{ABITIR}=\left\{\begin{array}{c}\mathrm{notABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})>31;\\ \mathrm{ABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})\&le;31\&CenterDot;\end{array}\right.$

Otherwise the value of reading and writing the direction register when bit is 0,

$\mathrm{ABITIR}=\left\{\begin{array}{c}\mathrm{notABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})<0;\\ \mathrm{ABITIR},\mathrm{If}(\mathrm{SPOS}+\mathrm{Length})\&GreaterEqual;0\&CenterDot;\end{array}\right.$

Wherein: the ABITIR representative enlivens the value of register flag, and SPOS represents the value of bit position register, the length that the Length representative is read, and not represents inversion operation,

2) the automatic renewal of position update module:

$\mathrm{SPOS}=\left\{\begin{array}{c}(\mathrm{SPOS}+\mathrm{Length})\%32,\mathrm{IfSDIR}=1;\\ (\mathrm{SPOS}-\mathrm{Length}+32)\%32,\mathrm{IfSDIR}=0\&CenterDot;\end{array}\right.$

Wherein: SPOS represents the value of bit position register, the length that the Length representative is read, and SDIR is the value of bit read-write direction register, % represents modulo operation.

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