CN101877346B - Static discharge protection system and static discharge protection circuit - Google Patents

Static discharge protection system and static discharge protection circuit Download PDF

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CN101877346B
CN101877346B CN 200910137261 CN200910137261A CN101877346B CN 101877346 B CN101877346 B CN 101877346B CN 200910137261 CN200910137261 CN 200910137261 CN 200910137261 A CN200910137261 A CN 200910137261A CN 101877346 B CN101877346 B CN 101877346B
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electrode
substrate
gate
formed
layer
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CN 200910137261
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CN101877346A (en )
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杨景荣
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瑞鼎科技股份有限公司
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Abstract

The invention provides a static discharge protection system and a circuit thereof. The static discharge protection system is coupled between a first power line and a second power line. The static discharge protection system comprises a substrate, a semiconductor capacitor and a transistor switch, wherein the semiconductor capacitor comprises a dielectric layer formed on the substrate and a conducting layer formed on the dielectric layer. The conducting layer is electrically connected to the first power line. The transistor switch is arranged on the substrate, and is provided with a gate, a first electrode and a second electrode, wherein the first electrode is electrically connected with the conducting layer of the semiconductor capacitor and is coupled to the first power line; and the gate is electrically connected with the second electrode and is coupled to the second power line. Thus, the static discharge protection system can prevent damage caused by static discharge phenomenon between power lines.

Description

静电放电防护系统及静电放电防护电路技术领域[0001] 本发明涉及一种静电放电(electrostatic discharge,ESD)防护系统及静电放电防护电路,特别涉及一种基体触发式(substrate-triggered)静电放电防护系统及静电放电防护电路。 Electrostatic discharge protection systems and ESD protection circuits Technical Field [0001] The present invention relates to an electrostatic discharge (electrostatic discharge, ESD) protection system and the ESD protection circuit, particularly to a trigger matrix (substrate-triggered) electrostatic discharge protection systems and ESD protection circuits. 背景技术[0002] 随着半导体技术的发展,集成电路的制作不断引进更先进的工艺技术。 [0002] With the development of semiconductor technology, the production of integrated circuits continue to introduce more advanced technology. 消费者也因此享受到更轻薄、更高效能且更低电耗的高科技产品。 Therefore, consumers enjoy more light, higher performance and lower power consumption of high-tech products. 以手持式电子产品如手机、数字相机、个人数字助理(personal digital assistant, PDA)为例,愈来愈多的电路被整合至极小尺寸的单芯片系统(System-on-Chip,SoC)中,使各种数字产品在占用最小的空间下,发挥最大的效能。 To handheld electronic products such as mobile phones, digital cameras, personal digital assistants (personal digital assistant, PDA), for example, more and more circuits are integrated extremely small size of the single-chip system (System-on-Chip, SoC), the the various digital products takes up minimal space under, to maximize performance. [0003] 现今的微电子电路,其元件大小以倍增速率不断缩小,其可以在微小的电位差下, 以微小的电流驱动,即可执行各种应用功能。 [0003] Today's microelectronic circuit element sized to doubling rate of shrinking, it may be, a slight current drive at a slight potential difference can perform various application functions. 然而,电子装置在制造、搬运甚至是正常操作的情况下,皆有可能在电子装置内部累积静电。 However, in the electronic device manufacturing, handling even under normal operation, there are static electricity may accumulate inside the electronic device. 当不可预期的静电放电现象发生时,产生的静电放电电流可能在电子装置的内部工作电路四处流窜,这些静电放电电流对电子装置的内部工作电路造成不可回复的损坏。 When the unexpected phenomenon of electrostatic discharge ESD generated current may flows around the internal circuitry of the electronic device, the ESD current irreversible damage to the internal circuitry of the electronic device. [0004] 现有技术中,电子装置为了避免静电放电电流对内部工作电路可能造成的损坏, 通常设置了静电放电防护系统。 [0004] In the prior art, the electronic device to prevent electrostatic discharge current may be caused by internal circuitry, typically electrostatic discharge protection system is provided. 静电放电防护系统可检测静电放电电流的产生,并将可能造成危害的静电放电电流导入特定的静电放电路径,避免损坏精密的内部工作电路。 The ESD protection system can detect the electrostatic discharge current and discharge current may cause static electricity hazard introducing a specific electrostatic discharge path, to avoid damage to delicate internal circuitry. [0005] 请参照图1。 [0005] Referring to FIG. 图1示出现有技术中静电放电防护系统1的示意图。 FIG 1 is a schematic of an ESD protection system illustrating the prior art. 如图1所示,静电放电防护系统1包含静电放电检测器10以及晶体管开关12。 1, the electrostatic discharge protection system 1 comprises an electrostatic discharge detector 10, and a transistor switch 12. 静电放电防护系统1耦接于正电源线Vdd以及负电源线Vss之间,用以保护内部工作电路2。 The ESD protection system is coupled to a positive power supply line Vdd and a negative power line Vss, to protect internal circuitry 2. [0006] 正常工作情况下,正电源线Vdd以及负电源线Vss提供工作电压驱动内部工作电路2,由此内部工作电路2可顺利执行应用功能。 [0006] Under normal operating conditions, the positive power supply line Vdd and a negative power supply line Vss internal operating voltage driving circuit 2 work, whereby the work of the internal circuit 2 smoothly perform application functions. 此时静电放电防护系统1不动作(disable)而晶体管开关12关闭。 At this time, the ESD protection system does not operate (disable) and the transistor switch 12 is closed. [0007] 另一方面,正电源线Vdd以及负电源线Vss间因静电放电突然产生异常信号(例如过大的瞬间电压)。 [0007] On the other hand, between the positive power supply line Vdd and a negative power supply line Vss sudden abnormality signal (e.g., excessive instantaneous voltage) due to electrostatic discharge. 在这种应用中,静电放电检测器10可为电压检测器,电压检测器根据此时的瞬间电压产生控制信号,以开启晶体管开关12并在正电源线Vdd以及负电源线Vss 形成放电路径。 In this application, the detector 10 may be an electrostatic discharge, the voltage detector generating a control signal based on the instantaneous voltage at this time is a voltage detector, to turn the transistor switch 12 and a discharge path formed positive power supply line Vdd and a negative power source line Vss. 正电源线Vdd以及负电源线Vss间的静电放电电流Iesd即可通过晶体管开关12的放电路径,避免对内部工作电路2造成损害。 Iesd ESD current between the positive power supply line Vdd and a negative power supply line Vss through the discharge path to the transistor switch 12, to avoid damage to internal circuitry 2. [0008] 如图1所示,晶体管开关12为N型金氧半场效晶体管(或N沟道金属氧化物半导体场效应晶体管,NM0SFET),静电放电检测器10(ESD detector)产生的控制信号控制晶体管开关12的闸极(或栅极,gate electrode)以切换放电路径的开关。 [0008] As shown, a control signal to the transistor switch 12 is an N-type metal oxide semiconductor field effect transistors (or N-channel metal oxide semiconductor field effect transistor, NM0SFET), the electrostatic discharge detector 10 (ESD detector) generated 1 the control gate 12 of transistor switch electrode (or gate, gate electrode) to switch the discharge path. 然而,随着现今先进半导体工艺的演进,晶体管采用了金属化硅化物扩散层(silicideddiffusion)工艺以及轻掺杂汲极(light doped drain, LDD)工艺,使这样的闸极触发式(gate-triggered)晶体管的静电放电耐受能力下降。 However, with the evolution of today's advanced semiconductor processes, a transistor with a metal diffusion layer of silicide (silicideddiffusion) processes and lightly doped drain (light doped drain, LDD) process, so that the gate trigger (gate-triggered ) decreased ESD withstand capability of the transistor. [0009] 为了达到足够的静电放电耐受能力,需要特地加大晶体管的闸极宽度,使晶体管开关需占用较大的芯片空间。 [0009] In order to achieve adequate ESD tolerance, specifically required to increase the gate width of the transistor, the transistor switch must occupy a larger chip space. 除了晶体管开关,静电放电防护系统还需要设置检测用的静电放电检测器,使整个静电放电防护系统的空间利用效率(area efficiency)下降。 In addition to the transistor switch, an electrostatic discharge protection systems also require electrostatic discharge provided with the detector, so that the entire space utilization efficiency decreased electrostatic discharge protection system (area efficiency). [0010] 本发明提出一种具有基体触发式晶体管开关的静电放电防护系统及静电放电防护电路,以解决上述问题。 [0010] The present invention proposes an electrostatic discharge protection systems and ESD protection circuit substrate having a transistor switch trigger to solve the above problems. 发明内容[0011] 本发明的一方面在于提供一种静电放电防护系统,静电放电防护系统耦接于第一电源线以及第二电源线之间,用以避免第一电源线以及第二电源线之间的静电放电现象损坏其他内部工作电路系统。 SUMMARY OF THE INVENTION [0011] In one aspect of the present invention is to provide an electrostatic discharge protection system, an electrostatic discharge protection system is coupled between the first power line and the second power line, to avoid the first power line and the second power source line electrostatic discharge between the system damage other internal circuitry. [0012] 根据一个具体实施例,静电放电防护系统包含基材(或基底,substrate)、半导体电容以及晶体管开关。 [0012] According to a particular embodiment, the ESD protection system comprises a substrate (or substrate, Substrate), a semiconductor capacitor and a transistor switch. 半导体电容包含形成于基材上的介电层以及进一步形成于介电层上的导电层。 The semiconductor capacitor comprising a dielectric layer formed on the substrate and a conductive layer is further formed on the dielectric layer. 导电层与第一电源线电性连接。 A first conductive layer connected to the electrical power supply line. 晶体管开关设置于基材。 Transistor switch disposed on a substrate. 晶体管开关具有闸极、 第一电极以及第二电极。 Transistor switch having a gate, a first electrode and a second electrode. 第一电极与半导体电容的导电层彼此电性连接并耦接至该第一电源线。 Another electrically conductive layer of the first capacitor electrode connected to the semiconductor and coupled to the first power line. 闸极与第二电极彼此电性连接并耦接至第二电源线。 And a second gate electrode electrically connected to each other and coupled to the second power line. [0013] 在该实施例中,半导体电容设置于与晶体管开关相同的基材上。 [0013] In this embodiment, the capacitance of the semiconductor transistor switch is provided on the same substrate. 由此,半导体电容可将第一电源线的电压信号耦合至晶体管开关所在的基材,用以控制晶体管开关进而形成基体触发式的静电放电防护系统。 Thus, the semiconductor substrate may be a capacitive voltage signal is coupled to a first power supply line where the transistor switch, thereby forming a transistor switch for controlling the base-triggered electrostatic discharge protection system. [0014] 根据本发明的静电放电防护系统,其中,晶体管开关进一步包含基极,基极设置于基材中,基极与闸极以及第二电极彼此电性连接,并耦接至第二电源线。 [0014] The ESD protection system of the present invention, wherein the switching transistor further comprises a base, a base electrode disposed in the substrate, the base and the second gate electrode and electrically connected to each other, and coupled to a second power supply line. [0015] 根据本发明的静电放电防护系统,其中,晶体管开关的闸极设置于基材上,第一电极与第二电极分别位于基材中且位置对应间极的两侧,晶体管开关选择性地在第一电极与第二电极间形成电通道。 [0015] The ESD protection system of the present invention, wherein the gate electrode of the transistor switch is provided on the substrate, the first and second electrodes are positioned on both sides between the substrate and the position corresponding to the electrode, the transistor switch selectively an electrical path is formed between the first electrode and the second electrode. [0016] 根据本发明的静电放电防护系统,其中,当第一电源线与第二电源线间发生静电放电电流时,半导体电容的导电层感测静电放电电流,并通过半导体电容对基材形成耦合电压,耦合电压驱使设置于基材的晶体管开关的电通道形成,并使静电放电电流通过电通道。 [0016] The ESD protection system of the present invention, wherein, when ESD current generated between the first power source line and the second power source line, a conductive layer for sensing static discharge current of the semiconductor capacitor, and the capacitor is formed on a semiconductor substrate by voltage coupling, the coupling voltage is provided to drive the switching transistor is electrically passage forming substrate, and the electrostatic discharge current through the electrical path. [0017] 根据本发明的静电放电防护系统,其中,闸极包含闸极介电层以及闸极导电层,闸极介电层形成于基材上,而闸极导电层形成于闸极介电层上,闸极通过闸极导电层与第二电极电性连接。 [0017] The ESD protection system of the present invention, wherein the gate electrode comprises a gate dielectric layer and a gate conductive layer, gate dielectric formed on the substrate, and a gate conductive layer is formed on the gate dielectric layer, a gate electrode conductive layer is electrically connected to the second electrode through the gate. [0018] 根据本发明的静电放电防护系统,其中,晶体管开关的第一电极与第二电极分别为形成于基材中的高掺杂区。 [0018] The ESD protection system of the present invention, wherein the first and second electrodes of transistor switches are formed in the substrate is highly doped region. [0019] 本发明的另一方面在于提供一种静电放电防护电路,其耦接于正电源线以及负电源线之间,用以避免正电源线以及负电源线之间的静电放电现象损坏其他内部工作电路系统。 [0019] Another aspect of the present invention is to provide an electrostatic discharge protection circuit coupled between the positive power source line and a negative power source line, to avoid electrostatic discharge phenomenon between the positive power source line and a negative power source line damage to other internal operating circuitry. [0020] 根据一个具体实施例,静电放电防护电路包含基材、介电层、导电层以及N型金氧半场效晶体管。 [0020] According to a particular embodiment, the ESD protection circuit comprising a substrate, a dielectric layer, a conductive layer and an N-type metal oxide semiconductor field effect transistor. 介电层形成于基材上,而导电层形成于介电层上。 A dielectric layer formed on the substrate, and the conductive layer is formed on the dielectric layer. 导电层与正电源线电性连接。 The conductive layer is electrically connected to the positive power supply line. N型金氧半场效晶体管具有闸极介电层、闸极导电层、汲极(或漏极,drainelectrode)、 源极以及基极。 N-type metal oxide semiconductor field effect transistor having a gate dielectric, gate conductor, a drain (or drain electrode, drainelectrode), a source electrode and a base electrode. 闸极介电层设置于基材上,闸极导电层设置于闸极介电层上,汲极与源极分别形成于基材中且位置分别对应闸极介电层的两侧,基极形成于基材中,汲极与正电源线电性连接,闸极导电层、源极、基极以及负电源线间电性连接。 Gate dielectric disposed on the substrate, a conductive gate layer disposed on the dielectric layer, the gate, drain and source electrodes are formed in the substrate and respectively correspond to positions on both sides of the gate dielectric layer, a base formed in the substrate, and a drain connected to the positive power supply line, a gate conductive layer, a source electrode, and between the base electrode connected to the negative power supply line. [0021] 在该实施例中,N型金氧半场效晶体管为闸极接地(低电压)。 [0021] In this embodiment, N-type metal oxide semiconductor field effect transistor gate to ground (low voltage). 通过该导电层可将正电源线的电压信号耦合至基材,用以控制N型金氧半场效晶体管进而形成基体触发式的静电放电防护电路。 The conductive layer through a positive voltage signal is coupled to the power supply line may be a substrate, for controlling an N-type metal oxide semiconductor field effect transistor forming substrate further trigger the ESD protection circuits. [0022] 根据本发明的静电放电防护电路,其中,介电层与闸极介电层分别为氧化层。 [0022] The ESD protection circuit of the present invention, wherein the dielectric layer and the gate dielectric oxide layer, respectively. [0023] 根据另一具体实施例,静电放电防护电路包含基材、介电层、导电层以及P型金氧半场效晶体管。 [0023] According to another embodiment, the ESD protection circuit comprising a substrate, a dielectric layer, a conductive layer, and a P-type metal oxide semiconductor field effect transistor. 介电层形成于基材上,而导电层形成于介电层上。 A dielectric layer formed on the substrate, and the conductive layer is formed on the dielectric layer. 导电层与负电源线电性连接。 The conductive layer is electrically connected to the negative power line. P型金氧半场效晶体管具有闸极介电层、闸极导电层、汲极、源极以及基极。 P-type metal oxide semiconductor field effect transistor having a gate dielectric, gate conductor, a drain, a source, and a base. 闸极介电层设置于基材上,闸极导电层设置于闸极介电层上,汲极与源极分别形成于基材中且位置分别对应闸极介电层的两侧,基极形成于基材中,汲极与负电源线电性连接,闸极导电层、 源极、基极以及正电源线间电性连接。 Gate dielectric disposed on the substrate, a conductive gate layer disposed on the dielectric layer, the gate, drain and source electrodes are formed in the substrate and respectively correspond to positions on both sides of the gate dielectric layer, a base formed in the substrate, drain and the negative power source line is electrically connected to the conductive gate layer, source electrode, and between the base electrode connected to the positive power supply line. [0024] 在该实施例中,P型金氧半场效晶体管的闸极接高电压。 [0024] In this embodiment, the gate P-type metal oxide semiconductor field effect transistor is connected to a high voltage. 通过导电层可将负电源线的电压信号耦合至基材,用以控制P型金氧半场效晶体管进而形成基体触发式的静电放电防护电路。 By the conductive layer may be a negative voltage signal is coupled to the base power supply line for controlling the P-type metal oxide semiconductor field effect transistor formed in the substrate and thus trigger the ESD protection circuits. [0025] 根据本发明的静电放电防护电路,其中,介电层与闸极介电层分别为氧化层。 [0025] The ESD protection circuit of the present invention, wherein the dielectric layer and the gate dielectric oxide layer, respectively. [0026] 与现有技术中需要设置静电放电检测器以判断并控制放电路径相比,本发明提出的静电放电防护系统及其电路,仅利用结构简单的半导体电容将电压信号耦接至晶体管开关所在的基材,并由此控制晶体管开关的开关状态。 [0026] The prior art requires an electrostatic discharge detector to determine and control the discharge path as compared to the ESD protection circuit and system proposed by the present invention, only a simple structure of the semiconductor capacitor voltage signal coupled to the transistor switch where the substrate, and thereby control the switching state of the transistor switch. 也就是说,本发明的静电放电防护系统及其电路可以较小的芯片空间完成基体触发式的静电放电防护功能。 That is, the ESD protection circuit of the present invention and the system can be smaller chip space to complete the base body triggered electrostatic discharge protection. [0027] 关于本发明的优点与精神可以通过以下的具体实施方式及附图得到进一步的了解。 [0027] The advantage and spirit of the present invention may be further understood by the following detailed description and accompanying drawings. 附图说明[0028] 图1示出现有技术中静电放电防护系统的示意图。 BRIEF DESCRIPTION [0028] FIG 1 illustrates a schematic view of a prior art electrostatic discharge protection system occurs. [0029] 图2示出根据本发明的第一具体实施例中静电放电防护系统的示意图。 [0029] Figure 2 shows a schematic view of a first embodiment of the present invention, the ESD protection system according to. [0030] 图3示出图2中静电放电防护系统的等效电路示意图。 [0030] FIG. 3 shows an equivalent circuit diagram of FIG. 2 of the electrostatic discharge protection system. [0031] 图4示出根据本发明的第二具体实施例中静电放电防护系统的示意图。 [0031] Figure 4 shows a schematic diagram of an electrostatic discharge protection system according to a second specific embodiment of the present invention. [0032] 图5示出根据本发明的第三具体实施例中静电放电防护电路的示意图。 [0032] FIG. 5 shows a schematic diagram of the ESD protection circuit according to a third specific embodiment of the present invention. [0033] 图6示出图5中静电放电防护电路的等效电路示意图。 [0033] FIG. 6 shows an equivalent circuit schematic of FIG. 5 ESD protection circuit. 具体实施方式[0034] 请参照图2。 DETAILED DESCRIPTION [0034] Referring to FIG. 图2示出根据本发明的第一具体实施例中静电放电防护系统3的示意图。 Figure 2 shows a schematic embodiment according to the ESD protection system of the first embodiment of the present invention particularly 3. 静电放电防护系统3为耦接于电路系统中第一电源线与第二电源线之间的静电放电防护电路,用以避免两电源线之间因过大的瞬间电压差产生瞬间的静电放电电流,进而保护两电源线之间耦接的内部工作电路(未示出)不致因此受损。 The ESD protection system 3 is coupled to ESD protection circuitry in the circuit between the first power line and the second power source line, to avoid electrostatic discharge is generated between the two current momentary power cord is excessively large instantaneous voltage difference , thereby protecting internal circuitry between the two power supply lines coupled (not shown) will not be adversely affected. 在该实施例中,两电源线分别以正电源线Vdd以及负电源线Vss为例,但本发明不以此为限。 In this embodiment, two power supply lines are a positive power supply line Vdd and a negative power supply line Vss as an example, but the present invention is not limited thereto. [0035] 如图2所示,在该实施例中,静电放电防护系统3包含基材30、半导体电容32以及晶体管开关;34。 [0035] As shown in FIG 2, in this embodiment, the ESD protection system 3 comprises a substrate 30, capacitor 32, and a semiconductor transistor switch; 34. 在该实施例中,晶体管开关34以N型金氧半场效晶体管为例,但不以此为限。 In this embodiment, the transistor switch 34 is an N-type metal oxide semiconductor field effect transistor as an example, but not limited thereto. [0036] 半导体电容32包含形成于基材30上的介电层320以及进一步形成于介电层320 上的导电层322。 [0036] The semiconductor capacitor 32 comprises a dielectric layer 320 is formed on the substrate 30 and a conductive layer 322 is further formed on the dielectric layer 320. 实际应用中,介电层320可为氧化层(oxide layer)。 In practical applications, the dielectric layer 320 may be an oxide layer (oxide layer). 精确地说,导电层322与基材30之间通过介电层320的介电效果形成本发明所谓的半导体电容32。 Precisely, a so-called semiconductor capacitor 32 between the conductive layer 322 of the present invention and the substrate 30 is formed by the dielectric effect of the dielectric layer 320. 导电层322与正电源线Vdd电性连接。 Conductive layer 322 is connected to the positive power source line Vdd electrically. 也就是说,半导体电容32可将正电源线Vdd的电压信号自导电层322耦合传导至基材30。 That is, the semiconductor capacitor 32 may be a positive power supply line Vdd voltage signal from the conductive layer 322 is coupled to the conductive substrate 30. [0037] 晶体管开关34设置于基材30。 [0037] The transistor switch 34 is provided on the substrate 30. 晶体管开关34具有闸极G、第一电极、第二电极以及基极B。 Switching transistor 34 having a gate G, a first electrode, a second electrode and a base electrode B. 第一电极、第二电极分别为形成于基材30中的高掺杂区。 First and second electrodes are formed in the substrate 30 is highly doped region. 在该实施例中,对应晶体管开关34为N型金氧半场效晶体管,第一电极以及第二电极分别为汲极D以及源极S。 In this embodiment, the corresponding transistor switch 34 is an N-type metal oxide semiconductor field effect transistor, the first electrode and the second electrode are a drain D and a source S. 在该实施例中,晶体管开关34另具有介电隔离块340,介电隔离块340可用以分隔掺杂极性相反的源极S与基极B (在该实施例中分别为η型掺杂与ρ型掺杂)。 In this embodiment, the transistor switch 34 further has a dielectric isolation block 340, the dielectric block 340 may be used to isolate the source S and the polarity opposite to the partition doped source group B (η-type doping in this embodiment are ρ-type doping). [0038] 闸极G设置于基材30上,闸极G包含闸极介电层Gi以及闸极导电层Ge,闸极介电层Gi形成于基材30上,而闸极导电层Gc形成于闸极介电层Gi上,闸极导电层Gc与源极S电性连接。 [0038] The gate G is provided on the substrate 30, a gate G comprises a gate dielectric and a gate conductor Gi Ge, Gi gate dielectric formed on the substrate 30, the gate conductive layer is formed Gc to gate on the dielectric layer Gi, Gc and a gate conductive layer is electrically connected to the source S. 实际应用中,闸极介电层Gi可为氧化层。 In practice, Gi gate dielectric may be an oxide layer. [0039] 汲极D与源极S分别位于基材30中且位置对应闸极G的两侧。 [0039] The drain D and source S is located on both sides of the base 30, and a position corresponding to the gate G, respectively. 汲极D与半导体电容32的导电层322彼此电性连接并耦接至正电源线Vdd。 Drain D and the conductive layer 32 of the semiconductor capacitor 322 are electrically connected and coupled to the positive power supply line Vdd. 源极S与闸极导电层Gc彼此电性连接并耦接至负电源线Vss。 The source S and the gate conductor Gc electrically connected to each other and coupled to the negative power source line Vss. 晶体管开关34选择性地在汲极D与源极S间形成电通道。 Transistor switch 34 selectively between the drain electrode D and the source S to form an electrical path. 基极B也设置于基材30中,基极B与闸极导电层Gc以及源极S彼此电性连接,并耦接至负电源线Vss。 The base B is also provided in the base 30, the base B and the gate conductor Gc, and a source S electrically connected to each other, and coupled to the negative power source line Vss. [0040] 请一并参照图3。 [0040] Referring together to FIG 3. 图3示出图2中静电放电防护系统3的等效电路示意图。 The equivalent circuit schematic diagram of an electrostatic discharge protection system 3 shown in FIG. 2 FIG. 3. 如图3所示,静电放电防护系统3中等效电容将正电源线Vdd的信号耦合至基材30。 3, the equivalent capacitance of the signal coupling 3 the positive power supply line Vdd ESD protection system 30 to the substrate. 此外晶体管开关;34等效具有寄生的NPN型双载子接面晶体管(或双极结型晶体管,BJT),寄生NPN 型双载子接面晶体管其操作状态由基材30本身的电压(即图3等效电路中的基材电压准位Vsub)控制。 Moreover transistor switch; 34 equivalents with NPN-type parasitic bipolar junction transistors (or bipolar junction transistor, BJT), a parasitic NPN type bipolar junction transistor operating state of the base material 30 which itself voltage (i.e. voltage level of the substrate 3 in the equivalent circuit of FIG Vsub) control. [0041] 当正电源线Vdd与负电源线Vss间具有瞬间的过大电压差时,即静电放电电流将发生时,半导体电容32的导电层322可感测该静电放电电流,并对基材30形成耦合电压。 [0041] When an excessive voltage between the positive power source line Vdd and the negative power supply line Vss having a difference in instantaneous, i.e., when the ESD current will occur, the conductive layer 322 of the semiconductor capacitor 32 can sense the electrostatic discharge current, and substrate 30 a coupling voltage. 耦合电压可提升基材30的基材电压准位Vsub,并使晶体管开关34形成的寄生NPN型双载子接面晶体管进入工作导通状态,进而驱使设置于基材30的晶体管开关34的电通道形成, 并使静电放电电流通过电通道。 Coupling voltage level can be improved substrate voltage Vsub of the substrate 30, and the parasitic NPN-type bipolar junction transistor switch transistor 34 into the conduction state of work, in turn drives the transistor switch is provided in the base 34 of 30 passage is formed, and the electrostatic discharge current through the electrical path. [0042] 此外,本发明的静电放电防护系统并不以上述电路结构为限。 [0042] Further, the ESD protection system of the present invention is not limited to the above-described circuit configuration. 在实际应用中,因电路设计布局的需求,正负电源线常连续交替出现,以分别对各部位的工作电路提供信号或电源供给。 In practice, because the demand of circuit design layout, the positive and negative power lines often appear alternately continuous to respectively provide a signal or power supply to each part of the operation of the circuit. 请参照图4。 Referring to FIG. 图4示出根据本发明的第二具体实施例中静电放电防护系统5的示意图。 Figure 4 shows a schematic view of embodiment 5 according to the ESD protection system of the second specific embodiment of the present invention. [0043] 与先前所述的第一具体实施例相比,主要不同之处在于本实施例的静电放电防护系统5包含晶体管开关Ma以及晶体管开关Mb。 [0043] Compared with the first embodiment previously described, the main difference is that the ESD protection system of the present embodiment 5 comprises the switching transistor Ma and the switching transistor Mb. 晶体管开关5½耦接于正电源线Vdd与负电源线Vssl间,而晶体管开关54b耦接于正电源线Vdd与负电源线Vss2间。 5½ transistor switch coupled to the positive power supply line Vdd and the negative power source line between Vssl, 54b and the transistor switch coupled to the positive power supply line Vdd and a negative power supply line Vss2 room. 当正电源线Vdd与这些负电源线之间产生瞬间的静电放电现象时,根据半导体电容52的感测可提高基材50的基材电压准位,进而使静电放电电流可流经晶体管开关5½与晶体管开关54b中分别形成的电通道。 When the electrostatic discharge is generated between the instantaneous positive power supply line Vdd and the negative power source line, according to the sensing capacitor 52 can be improved semiconductor voltage level of the base substrate 50, and thus the electrostatic discharge current through transistor switch 5½ electrical switch channel transistor 54b respectively formed. 由此,静电放电防护系统5可提供静电放电电流的放电路径以保护正电源线Vdd与负电源线VSS1、VSS2连接的其他内部工作电路(未示出)。 Thereby, the electrostatic discharge protection system 5 can provide a discharge path of the ESD current to protect the positive supply line Vdd and a negative power source line VSS1 is, connected to the other internal circuitry VSS2 (not shown). [0044] 其中两个晶体管开关与半导体电容52的详细作动关系与等效电路在第一具体实施例中大致相同,在此不再赘述。 [0044] wherein actuation detail the relationship between an equivalent circuit of two transistors of the semiconductor switching capacitor 52 is substantially the same in the first embodiment, which is not repeated herein. 需特别说明的是,由此,可利用简单的单一半导体电容结构即可作为两条放电路径的静电放电检测器,其不但具有良好的静电放电防护效果且具有高空间利用效率。 Special note is required, whereby, using a simple single semiconductor capacitor structure as an electrostatic discharge detector can be two discharge paths, which not only has good electrostatic discharge protection effect and has a high space utilization efficiency. [0045] 上述实施例中,静电放电防护电路的晶体管开关以N型金氧半场效晶体管为例, 但本发明并不以此为限。 [0045] The above-described embodiments, the switching transistor ESD protection circuit to an N-type metal oxide semiconductor field effect transistor as an example, but the present invention is not limited thereto. 实际应用中,晶体管开关可为各种晶体管形成的开关组件。 In practical applications, the transistor switch may be a switch assembly of the various transistors are formed. 请参照图5以及图6。 Referring to FIG 5 and FIG 6. 图5示出根据本发明的第三具体实施例中静电放电防护电路7的示意图。 Figure 5 shows a schematic diagram of the ESD protection circuit embodiment of the present invention, a third particular embodiment 7. 图6示出图5中静电放电防护电路7的等效电路示意图。 FIG 6 shows an equivalent circuit schematic diagram of the ESD protection circuits 7 in FIG. 5. [0046] 静电放电防护电路7包含基材70、介电层72、导电层74以及P型金氧半场效晶体管(或P沟道金属氧化物半导体场效应晶体管)76。 [0046] The ESD protection circuit 7 comprises a substrate 70, a dielectric layer 72, conductive layer 74 and a P-type metal oxide semiconductor field effect transistors (or P-channel metal oxide semiconductor field effect transistor) 76. 介电层72形成于基材70上,而导电层74形成于介电层72上。 The dielectric layer 72 is formed on the substrate 70, the conductive layer 74 is formed on the dielectric layer 72. 导电层74与负电源线Vss电性连接。 The conductive layer 74 is electrically connected to the negative power source line Vss. P型金氧半场效晶体管76 具有闸极介电层Gi、闸极导电层Ge、汲极D、源极S以及基极B。 P-type metal oxide semiconductor field effect transistor 76 having a gate dielectric Gi, gate conductor Ge, drain D, source S and the base B. 闸极介电层Gi设置于基材70上。 Gi gate dielectric 70 is provided on the substrate. 闸极导电层Gc设置于闸极介电层Gi上。 Gc gate conductor disposed on the gate dielectric layer on the Gi. 汲极D与源极S分别形成于基材70中且位置分别对应闸极介电层Gi的两侧。 Drain D and source S are formed in the substrate 70 and respectively correspond to the position of gate dielectric layer on both sides of Gi. 基极B形成于基材70中。 The base B is formed in the substrate 70. 汲极D与负电源线Vss电性连接。 Drain D electrically connected to the negative power source line Vss. 闸极导电层Ge、源极S、基极B以及正电源线Vdd间电性连接。 Gate conductor Ge, a source S, between the base B and the positive power supply line Vdd is electrically connected. [0047] 请参照图6。 [0047] Referring to FIG. 在该实施例中,通过导电层74可将负电源线Vss的电压信号耦合至基材70,用以控制P型金氧半场效晶体管76进而形成基体触发式的静电放电防护电路7。 In this embodiment, the conductive layer 74 may be coupled to the negative voltage signal to the power supply line Vss is the substrate 70, for controlling the P-type metal oxide semiconductor field effect transistor 76 forming substrate further trigger circuit 7 ESD protection. 其作动原理与第一具体实施例中大致相同,仅采用的晶体管开关类型不同,其电极的极性有相对应的替换关系,其为本领域中普通技术人员所熟知,在此不再赘述。 Which actuation principle and the first embodiment is substantially the same, only the use of different types of transistor switches, the polarity of the electrodes which have replaced corresponding relationship, known to those of ordinary skill in the art, are not repeated here . [0048] 综上所述,与现有技术中需要设置静电放电检测器以判断并控制放电路径相比, 本发明提出的静电放电防护系统及其电路,仅利用结构简单的半导体电容将电压信号耦接至晶体管开关所在的基材,并由此控制晶体管开关的开关状态。 [0048] In summary, the prior art required an electrostatic discharge detector to determine and control the discharge path as compared to the ESD protection circuit and system proposed by the present invention, a semiconductor structure using only simple capacitor voltage signal coupled to the base of the transistor switch is located, and thereby control the switching state of the transistor switch. 也就是说,本发明的静电放电防护系统及其电路可以较小的芯片空间完成基体触发式的静电放电防护功能。 That is, the ESD protection circuit of the present invention and the system can be smaller chip space to complete the base body triggered electrostatic discharge protection. [0049] 通过以上对优选具体实施例的详述,希望能更加清楚描述本发明的特征与精神, 而并非以上述所披露的优选具体实施例来对本发明的范围加以限制。 [0049] The above detailed description of embodiments of the preferred embodiment, hoping to more clearly describe the characteristics and spirit of the invention, and are not disclosed in the above-described preferred embodiments to limit the scope of the invention. 相反地,其目的是希望能涵盖各种改变及等同安排在本发明的权利要求范围内。 Conversely, its purpose is to be able to cover various modifications and equivalent arrangements as claimed in the present invention within the scope of the claims. [0050] 主要元件符号说明[0051] 1、3、5 :静电放电防护系统[0052] 10 :静电放电检测器[0053] 12、34、54a、54b :晶体管开关[0054] 30、50、70 :基材[0055] 320、72:介电层[0056] 76 =P型金氧半场效晶体管[0057] Vss、Vssl、Vss2 :负电源线[0058] G:闸极[0059] Ge:闸极导电层[0060] S :源极 B :基极[0061] Iesd :静电放电电流Vsub :基材电压准位。 [0050] Main reference numerals DESCRIPTION [0051] 1,3,5: electrostatic discharge protection system [0052] 10: the electrostatic discharge detector [0053] 12,34,54a, 54b: a transistor switch [0054] 30, 50 : substrate [0055] 320,72: a dielectric layer [0056] 76 = P-type metal oxide semiconductor field effect transistor [0057] Vss, Vssl, Vss2: negative power source line [0058] G: gate electrode [0059] Ge: gate conductive layer [0060] S: source B: base [0061] Iesd: ESD current Vsub: substrate voltage level. 7:静电放电防护电路2 :内部工作电路32,52 :半导体电容322,74 :导电层340 :介电隔离块Vdd:正电源线Gi :闸极介电层D :汲极 7: ESD protection circuits 2: internal circuitry 32, 52: semiconductor capacitor 322,74: conductive layer 340: dielectric isolation block Vdd: positive power source line Gi of: gate dielectric D: Drain

Claims (10)

  1. 1. 一种静电放电防护系统,耦接于第一电源线以及第二电源线之间,所述静电放电防护系统包含:基材;半导体电容,包含:介电层,形成于所述基材上;导电层,形成于所述介电层上,所述导电层与所述第一电源线电性连接;以及晶体管开关,设置于所述基材,其具有间极、第一电极以及第二电极,所述第一电极与所述半导体电容的所述导电层彼此电性连接并耦接至所述第一电源线,所述间极与所述第二电极彼此电性连接并耦接至所述第二电源线。 1. An electrostatic discharge protection system, coupled between the first power supply line and a second power supply line, the electrostatic discharge protection system comprising: a substrate; a semiconductor capacitor, comprising: a dielectric layer formed on the substrate on; a conductive layer formed on the dielectric layer, the conductive layer connected to the first power supply line electrically; and a transistor switch, disposed on the substrate, the inter-electrode having a first electrode and two electrodes, the first electrode electrically to each other with the conductive layer of the capacitor is connected to the semiconductor and coupled to the first power line, a source connected between the second electrode and coupled to each other properties to the second power supply line.
  2. 2.根据权利要求1所述的静电放电防护系统,其中所述晶体管开关进一步包含基极, 所述基极设置于所述基材中,所述基极与所述间极以及所述第二电极彼此电性连接,并耦接至所述第二电源线。 2. The ESD protection system as recited in claim 1, wherein the switching transistor further comprises a base, the base disposed on the substrate, between the base and the second electrode and the electrodes electrically connected to each other, and coupled to the second power line.
  3. 3.根据权利要求1所述的静电放电防护系统,其中所述晶体管开关的所述闸极设置于所述基材上,所述第一电极与所述第二电极分别位于所述基材中且位置对应所述间极的两侧,所述晶体管开关选择性地在所述第一电极与所述第二电极间形成电通道。 The ESD protection system according to claim 1, wherein the gate electrode of the transistor switch is disposed on the substrate, the first electrode and the second electrode are respectively located in the substrate and the inter-pole positions corresponding to both sides of the transistor switch selectively electrical path is formed between the first electrode and the second electrode.
  4. 4.根据权利要求3所述的静电放电防护系统,其中当所述第一电源线与所述第二电源线间发生静电放电电流时,所述半导体电容的所述导电层感测所述静电放电电流,并通过所述半导体电容对所述基材形成耦合电压,所述耦合电压驱使设置于所述基材的所述晶体管开关的所述电通道形成,并使所述静电放电电流通过所述电通道。 4. The electrostatic discharge protection system as claimed in claim 3, wherein when the ESD current generated between said first power source line and the second power supply line, the capacitance of the semiconductor layer senses the conductive electrostatic discharge current, and is formed by the coupling voltage of the semiconductor substrate capacitance, the electrical path coupling the drive voltage provided on the substrate of the transistor switch is formed, and the electrostatic discharge current through the said electrical path.
  5. 5.根据权利要求1所述的静电放电防护系统,其中所述闸极包含闸极介电层以及闸极导电层,所述闸极介电层形成于所述基材上,而所述闸极导电层形成于所述闸极介电层上, 所述闸极通过所述闸极导电层与所述第二电极电性连接。 The ESD protection system according to claim 1, wherein said gate electrode comprises a gate dielectric layer and a gate conductive layer, the gate dielectric formed on the substrate, and the gate a conductive electrode layer formed on the gate electrode on the dielectric layer, the gate electrode by the gate conductive layer is connected to the second electrode electrically.
  6. 6.根据权利要求1所述的静电放电防护系统,其中所述晶体管开关的所述第一电极与所述第二电极分别为形成于所述基材中的高掺杂区。 6. The electrostatic discharge protection system according to claim 1, wherein said transistor switch first electrode and the second electrode are formed in the highly doped region of the substrate.
  7. 7. 一种静电放电防护电路,耦接于正电源线以及负电源线之间,所述静电放电防护系统包含:基材;介电层,形成于所述基材上;导电层,形成于所述介电层上,所述导电层与所述正电源线电性连接;以及N型金氧半场效晶体管,其具有间极介电层、间极导电层、汲极、源极以及基极,所述闸极介电层设置于所述基材上,所述间极导电层设置于所述间极介电层上,所述汲极与所述源极分别形成于所述基材中且位置分别对应所述间极介电层的两侧,所述基极形成于所述基材中,所述汲极与所述导电层彼此电性连接并与所述正电源线电性连接,所述闸极导电层、所述源极、所述基极以及所述负电源线间电性连接。 An electrostatic discharge protection circuit coupled between the positive power source line and a negative power source line, the electrostatic discharge protection system comprising: a substrate; a dielectric layer formed on said substrate; a conductive layer formed on the upper dielectric layer, the conductive layer is connected electrically to the positive power source line; and N-type metal oxide semiconductor field effect transistor, having the inter-electrode dielectric layer, the conductive electrode layer, a drain, a source, and a base, a gate dielectric disposed on said substrate, said conductive layer is disposed between the electrode on the inter-electrode on the dielectric layer, the drain and the source are formed on the base material and in positions corresponding to the sides of the inter-electrode dielectric layer, the base electrode formed on said substrate, said drain electrode electrically connected to the conductive layer of each other and to the positive power supply line connection, the conductive layer of the gate electrode, the source electrode, the base and electrically connected between the negative power supply line.
  8. 8.根据权利要求7所述的静电放电防护电路,其中所述介电层与所述闸极介电层分别为氧化层。 8. The ESD protection circuit of claim 7, wherein the dielectric layer and the gate dielectric oxide layer, respectively.
  9. 9. 一种静电放电防护电路,耦接于正电源线以及负电源线之间,所述静电放电防护系统包含:基材;介电层,形成于所述基材上;导电层,形成于所述介电层上,所述导电层与所述负电源线电性连接;以及P型金氧半场效晶体管,其具有间极介电层、间极导电层、汲极、源极以及基极,所述闸极介电层设置于所述基材上,所述间极导电层设置于所述间极介电层上,所述汲极与所述源极分别形成于所述基材中且位置分别对应所述间极介电层的两侧,所述基极形成于所述基材中,所述汲极与所述导电层彼此电性连接并与所述负电源线电性连接,所述闸极导电层、所述源极、所述基极以及所述正电源线间电性连接。 An ESD protection circuits, coupled between the positive power source line and a negative power source line, the electrostatic discharge protection system comprising: a substrate; a dielectric layer formed on said substrate; a conductive layer formed on the upper dielectric layer, the conductive layer and the negative power source line is electrically connected; and a P-type metal oxide semiconductor field effect transistor, having the inter-electrode dielectric layer, the conductive electrode layer, a drain, a source, and a base, a gate dielectric disposed on said substrate, said conductive layer is disposed between the electrode on the inter-electrode on the dielectric layer, the drain and the source are formed on the base material and in positions corresponding to the sides of the inter-electrode dielectric layer, the base formed in the substrate, the drain is electrically connected to the conductive layer of each other and said negative power supply line and connection, the conductive layer of the gate electrode, the source electrode, the base electrode and is electrically connected between the positive power source line.
  10. 10.根据权利要求9所述的静电放电防护电路,其中所述介电层与所述闸极介电层分别为氧化层。 10. The ESD protection circuit according to claim 9, wherein the dielectric layer and the gate dielectric oxide layer, respectively.
CN 200910137261 2009-04-29 2009-04-29 Static discharge protection system and static discharge protection circuit CN101877346B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173755A (en) 1989-05-12 1992-12-22 Western Digital Corporation Capacitively induced electrostatic discharge protection circuit
DE19629511C2 (en) 1996-03-16 1998-09-24 Winbond Electronics Corp Protection circuitry against electrostatic discharges

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173755A (en) 1989-05-12 1992-12-22 Western Digital Corporation Capacitively induced electrostatic discharge protection circuit
DE19629511C2 (en) 1996-03-16 1998-09-24 Winbond Electronics Corp Protection circuitry against electrostatic discharges

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