CN101860467B - Special wired train bus control device - Google Patents

Special wired train bus control device Download PDF

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CN101860467B
CN101860467B CN 201010189327 CN201010189327A CN101860467B CN 101860467 B CN101860467 B CN 101860467B CN 201010189327 CN201010189327 CN 201010189327 CN 201010189327 A CN201010189327 A CN 201010189327A CN 101860467 B CN101860467 B CN 101860467B
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frame
hdlc
unit
wtb
module
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CN 201010189327
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CN101860467A (en )
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吴正平
周学勋
曹洋
曾嵘
杨卫峰
肖家博
蒋国涛
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株洲南车时代电气股份有限公司
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Abstract

The invention provides a special wired train bus control device, which is characterized in that: a link layer interface comprises a transmitting buffer and a receiving buffer; a link layer comprises an HDLC frame transmitter unit and an HDLC frame receiver unit; and a physical layer comprises a control module, a channel management module, a Manchester coding and decoding module, a timer, an interrupter and a register. The special wired train bus control device provided by the invention has high generality.

Description

一种专用绞线式列车总线控制装置 Strand one kind of device-specific control train bus

技术领域 FIELD

[0001] 本发明属于列车通信网络控制领域,尤其涉及一种专用绞线式列车总线控制装置。 [0001] The present invention belongs to the field of train control communication network, particularly to a dedicated wire train bus control apparatus.

背景技术 Background technique

[0002] 目前,用于列车通信网络控制技术中的列车通信网络总线(WTB)控制专用芯片的成本高,价格昂贵。 [0002] Currently, a train communication network control technology train communication network bus (WTB) of the control ASIC cost expensive. WTB是一种串行数据通信总线,主要用于经常连挂和解连的重连车辆。 WTB is a serial data communication bus, mainly for reconciliation often even Coupling reconnection vehicle. WTB满足IEC-61375标准的要求,支持周期性的过程数据、非周期性的消息数据以及监视数据,能够通过初运行实现列车的自动编址和自动编组。 WTB meet the requirements of IEC-61375 standard, supports cyclical process data, message data and non-periodic monitoring data, the automatic addressing and automatic train operation by incipient grouping. WTB最多可互联32个节点,传输介质为屏蔽双绞线,干线电缆最大长度为860m,工作速率为IMb/s。 WTB up to 32 nodes can be interconnected, shielded twisted pair transmission medium, the maximum length of the trunk cable 860M, at the speed of IMb / s. WTB采用了硬件冗余,数据在两条介质上同时发送,仲裁逻辑根据收发器提供的载波检测信号在两路接收信号间作出选择。 WTB using hardware redundancy, data is transmitted simultaneously on two media arbitration logic to choose between two received signals according to carrier detection signals provided by the transceiver. WTB的所有帧格式相同,遵循HDLC(High Level DataLink Control,高级数据链路控制)协议。 All WTB same frame format follows the HDLC (High Level DataLink Control, High-Level Data Link Control) protocol. 虽然目前有人开发出了基于FPGA的WTB物理层控制器IP核,但该IP核还只能实现物理层信号编解码、信号监测、线路选择以及冗余管理等物理功能,远远不能符合国际上成熟的标准,例如IEC-61375标准。 Although it was developed based on FPGA WTB physical layer controller IP core, but also the IP core can only achieve physical layer signal coding and decoding, signal monitoring, line selection and redundancy management and other physical features, it is far from consistent with international mature standard, for example, IEC-61375 standard. 要实现WTB通信,还需要借助外界器件实现HDLC协议,通用性差。 To achieve WTB communication, but also by external devices to achieve the HDLC protocol, poor versatility.

发明内容 SUMMARY

[0003] 有鉴于此,本发明的目的在于提供一种专用绞线式列车总线控制装置,通用性高。 [0003] In view of this, an object of the present invention is to provide a dedicated wire train bus control apparatus of high versatility.

[0004] 为实现上述目的,本发明提供一种专用绞线式列车总线WTB控制装置,包括链路层接口、链路层和物理层,其中所述链路层接口包括:发送缓存和接收缓存,所述链路层包括HDLC帧发送器单元和HDLC帧接收器单元,所述物理层包括物理层控制模块、通道管理模块、曼彻斯特编码解码模块、定时器、中断器和寄存器; [0004] To achieve the above object, the present invention provides a wire train bus WTB a special control device, comprising a link layer interface, a link layer and a physical layer, wherein said link-layer interface comprising: a transmission buffer and the reception buffer the link layer comprises a HDLC frame transmitter unit and a receiver unit of the HDLC frame, the physical layer control module includes a physical layer, a channel management module, Manchester encoding and decoding module, a timer, and an interrupt register;

[0005] 其中,所述发送缓存用于为待发送数据提供缓存;所述HDLC帧发送器单元用于从发送缓存中读取待发送数据,并利用该取出的数据生成循环冗余校验码及形成HDLC帧; 所述物理层控制模块用于为所述链路层和物理层之间提供接口,所述通道管理模块用于对WTB帧头和帧尾进行编码和解码,信号监测和线路选择;所述曼彻斯特编码解码模块用于对所述HDLC帧发送器单元生成的HDLC帧进行曼彻斯特编码,并将编码后的WTB帧头和WTB 帧尾与编码后的HDLC帧组成WTB帧,通过外部接口发送至传输通道中,还用于对通过外部接口接收到的WTB帧中的HDLC帧进行曼彻斯特解码;所述HDLC帧接收器单元用于接收曼彻斯特编码解码模块解码后的HDLC帧,进行解帧得到HDLC帧中的数据,发送至接收缓存中。 [0005] wherein, for providing said transmission buffer buffers data to be transmitted; the HDLC frame transmission unit from the transmission buffer for reading data to be transmitted, and uses the extracted data to generate cyclic redundancy check code and forming HDLC frame; the physical layer control module for providing an interface between the link layer and the physical layer, the channel management module for WTB header and trailer encoding and decoding, and signal monitoring circuit selection; said means for decoding the Manchester encoded HDLC frames to said HDLC frame generated by the transmitter unit Manchester encoding, the encoded WTB the header and tail frames WTB HDLC frames encoding WTB frame, external an interface to the transmission channel, also for WTB frame received through the external interface HDLC frame Manchester decoding; the HDLC frame receiving unit for receiving HDLC frames Manchester code decoding module, deframed data obtained in the HDLC frame sent to the receive buffer.

[0006] 优选地,所述HDLC帧发送器单元包括: [0006] Preferably, the HDLC frame transmitting unit comprises:

[0007] 读取单元,用于从发送缓存中读取待发送数据; [0007] The reading unit configured to read from the transmission buffer data to be transmitted;

[0008] 校验码生成单元,用于利用读取单元取出的待发送数据生成循环冗余校验码; [0008] The check code generating means for generating a cyclic redundancy check code to be read by the transmission data extracting means;

[0009] 标志位插入单元,用于构建HDLC帧的帧头和帧尾,所述HDLC帧头和帧尾为'01111110,; [0009] flag insertion unit, for constructing the header of the HDLC frame and frame end, the HDLC header and trailer to '01111110 ,;

[0010] 零比特插入单元,用于对待发送数据进行扫描,在5个'1'后插入一个'0' ; [0010] zero-bit insertion unit for scanning data to be sent, in 5 '1' is inserted after a '0';

[0011] 组帧单元,用于将构建的HDLC帧的帧头、经过零比特插入单元插零后的待发送数据、构建的HDLC帧的帧尾组成HDLC帧,将构建的HDLC帧和所述生成的循环冗余校验码发送至物理层控制模块中。 [0011] The framing unit for constructing the header of the HDLC frame of data to be sent after the zero insertion through zero bit insertion unit frame builder composition HDLC frame tail HDLC frame, the frame and the HDLC constructed generating a cyclic redundancy check code to the physical layer control module.

[0012] 优选地,所述HDLC帧接收器单元包括: [0012] Preferably, the HDLC frame receiving unit comprises:

[0013] 帧同步单元,用于检测HDLC帧的帧头; [0013] The frame synchronization unit for detecting a header of the HDLC frame;

[0014] 剔零单元,用于扫描HDLC帧中HDLC帧头后的数据,剔除5个'1'后面的'0' ; [0014] tick zero means for scanning data in the HDLC frame HDLC header, excluding the 5 '1' followed by '0';

[0015] 校验单元,用于根据剔零单元剔除后的HDLC帧数据生成循环冗余校验码,并与包括该HDLC帧的WTB帧中的循环冗余校验码进行比较,完成循环冗余校验; [0015] checking unit for HDLC frame data generating cyclic redundancy check code of zero means the tick removed, and compared with the HDLC frame comprises a frame WTB in the cyclic redundancy check code, cyclic redundancy complete I check;

[0016] 所述接收缓存用于接收从HDLC帧接收器单元中经剔零单元剔零后的HDLC帧中的数据。 [0016] The receive buffer for receiving data from an HDLC frame received via the HDLC frame unit after the unit tick tick zero or zero.

[0017] 优选地,所述通道管理模块包括: [0017] Preferably, the channel management module comprises:

[0018] 帧头帧尾编码解码单元,用于实现WTB帧的帧头和帧尾的编码和识别; [0018] encoding the end of frame header decoding unit for implementing WTB header and the trailer frame coding and identification;

[0019] 线路选择与冗余控制单元,用于实现依据线路上的有效帧和无效帧对线路进行选择; [0019] The redundancy control circuit selecting unit, for realizing the frame of the selected line based on the line valid frame and invalid;

[0020] 载波与信号品质监测单元,用于对载波和信号品质进行监测。 [0020] The carrier and the signal quality monitoring means for monitoring signal quality and a carrier.

[0021] 优选地,所述校验码生成单元在生成循环校验码时采用并行循环校验生成算法。 [0021] Preferably, the check code generating means generating a parallel cyclic redundancy check algorithm in the generation of cyclic redundancy check code.

[0022] 优选地,所述物理层还包括存储转发模块,用于对传输线路上的信号采样并进行存储转发。 [0022] Preferably, the physical layer further comprises a store and forward means for sampling the signal on the transmission line to store and forward.

[0023] 本发明实施例考虑到了WTB总线控制器的全局,在满足物理层各项功能的基础上实现链路层的帧转发功能,通用性好,不受专用的HDLC收发芯片的限制。 Embodiment [0023] The present invention takes into account the global bus controller WTB, achieve frame link layer forwarding, versatility, and not limited by the specific HDLC transceiver chip on the basis of the functions to meet the physical layer.

附图说明 BRIEF DESCRIPTION

[0024] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 [0024] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, briefly introduced hereinafter, embodiments are described below in the accompanying drawings or described in the prior art needed to be used in describing the embodiments figures some embodiments of the present invention, those of ordinary skill in the art is concerned, without creative efforts, can derive from these drawings other drawings.

[0025] 图1是IEC61375标准规定的线路上理想的WTB帧的结构示意图; [0025] FIG. 1 is a schematic view of the ideal frame structure WTB predetermined IEC61375 standard line;

[0026] 图2是理想线路上的有效WTB帧的结构示意图; [0026] FIG. 2 is a schematic view of the effective WTB frame over the line;

[0027] 图3是理想线路上的无效WTB帧的结构示意图; [0027] FIG. 3 is a schematic view of the invalid frame WTB over line;

[0028] 图4是WTB帧与HDLC帧的关系示意图; [0028] FIG. 4 is a diagram illustrating the relationship between the frame and the WTB HDLC frame;

[0029] 图5是本发明实施例提供的专用绞线式列车总线控制装置的示意图; [0029] FIG. 5 is a schematic diagram dedicated wire train bus control apparatus according to an embodiment of the present invention;

[0030] 图6是HDLC帧发送器单元的一种内部具体实现电路示意图; [0030] FIG. 6 is a circuit diagram of an internal unit of the HDLC frame transmitter embodied;

[0031] 图7是WTB总线控制器发送数据时的流程示意图; [0031] FIG. 7 is a flow diagram when transmitting data WTB bus controller;

[0032] 图8是HDLC帧接收器单元的一种内部具体实现电路示意图; [0032] FIG. 8 is a circuit diagram of a HDLC frame inside the embodied receiver unit;

[0033] 图9是WTB总线控制器接收数据时的流程示意图。 [0033] FIG. 9 is a flow diagram when the controller receives data bus WTB.

具体实施方式[0034] 为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。 DETAILED DESCRIPTION [0034] In order that the invention object of the embodiment, the technical solution and merits thereof more apparent in conjunction with the present invention in the drawings embodiments below, the technical solutions in the embodiments of the present invention will be clearly and completely described, clearly , the described embodiments are part of the embodiments of the present invention rather than all embodiments. 基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, those of ordinary skill in the art to make all other embodiments without creative work obtained by, it falls within the scope of the present invention.

[0035] 首先介绍一下WTB帧。 [0035] First, some WTB frame. IEC61375标准规定一帧信号由帧头开始,接着是帧数据,最后由终止分界符结束。 IEC61375 standard specifies a start signal from the header, followed by a data frame, and ends with a termination delimiter. 帧头由电平为“1”的起始位S开始,随后是若干个(“0”,“1”)对, 通常为7对,最后以“1”结束。 S start bit of the header by the level "1", followed by a number ( "0", "1") pair, usually seven pairs, and finally to "1" end. 帧数据的开始和结束由标志序列“01111110”进行标识。 Beginning and end of frame data identified by the flag sequence "01111110." 终止分界符为2. OBT (IBT= 1个时间单位)宽的正电平。 Termination delimiter is 2. OBT (IBT = 1 time units) wide positive level. 图1示出了线路上理想的WTB帧的结构示意图。 FIG 1 shows a schematic view of the ideal line WTB frame structure.

[0036] IEC-61375规范定义了解码器产生的两个信号:载波检测信号(CS)和信号品质错误信号(SQE),分别用于信号品质监视和冗余切换。 [0036] IEC-61375 specification defines the decoder generates two signals: carrier detection signal (CS) signal and a signal quality error (SQE), respectively, for monitoring and redundancy switching signal quality.

[0037] a)载波检测信号:在检测到图1中的规定的WTB帧头的最后一位0. 5BT内,解码器应使载波检测CS信号有效。 [0037] a) the carrier detect signal: 0. 5BT within the last detected specified in the header of FIG. 1 WTB, that the decoder should detect the carrier signal CS active. 在检测到终止分界符,非'0'、非'1'或非中值分界符的最后的0. 5BT内,解码器应使CS信号无效。 Termination delimiter is detected, a non '0', the last non 0. 5BT '1' or the value delimiters, the decoder of the CS signal to be invalid.

[0038] b)信号品质出错(SQE)信号:在检测到按图1中规定的WTB帧头的最后一位后的0.5BT内,解码器应使SQE信号无效。 [0038] b) signal quality error (SQE) signal: in 0.5BT after the last detected specified in the frame header WTB in FIG 1, the decoder should be SQE signal invalid. CS信号有效后,在检测到非'0'、非'1'或非终止符的位以后的0. 5BT内,解码器应使SQE信号有效。 After the CS signal is valid, in the non-detected '0', or non-terminator bit '1' after 0. 5BT, SQE signal decoder should be effective.

[0039] 有效帧是指包含了帧头、一定数目的帧数据以及一个终止分界符的帧,图2示出了理想线路上的有效WTB帧的格式。 [0039] The effective frame means comprising a header, data of a certain number of frames and the frame delimiter of a terminator, FIG. 2 illustrates the format of a frame on the effective WTB over the line. 当CS信号有效后,如果SQE信号有效的时间超过0. 5BT,则此帧定义为无效帧,图3示出了理想线路上的无效WTB帧的格式。 When the CS signal is active, if the signal is valid for more than SQE 0. 5BT, then this frame is defined as an invalid frame, FIG 3 shows a format of an invalid frame WTB on the ideal line. 冗余切换对信任线的切换就是依据线路上收到的有效帧和无效帧来判断的。 Redundancy switching lines is switched based on trust valid frame received on line and judged invalid frames.

[0040] WTB所有的帧都具有同样的格式,遵循HDLC规范,图4示出了WTB帧与HDLC帧的关系。 [0040] WTB all frames have the same format, following the HDLC standard, FIG. 4 shows the relationship WTB frame of the HDLC frame.

[0041] 其中,Preamble为前同步码,WTB帧的开始部分的前同步码由曼彻斯特编码器产生,并由曼彻斯特译码器去除。 [0041] wherein, a Preamble is the preamble, start portion of the frame preamble WTB is generated by the Manchester encoder, it is removed by the Manchester decoder. 它不属于HDLC帧部分。 It does not belong HDLC frame portion. 它的长度为16到32位,16位是默认值。 Its length is 16 to 32, 16 is the default value. 前同步码主要用于WTB帧的位同步。 The preamble is mainly used for bit synchronization frame WTB.

[0042] Flag是HDLC帧头标志位,HDLC帧通常以两个^Dit标志(例如01111110)作为分界符,作为帧同步标志。 [0042] Flag is a flag HDLC header, generally two HDLC frame flags ^ Dit (e.g. 01111110) as the delimiter, a frame synchronization flag.

[0043] DD(目标设备)可以是接收该帧的节点的节点地址(Node_AddreSS)或是广播地址。 [0043] DD (target device) may be the node address of the receiving node frame (node_address) or a broadcast address.

[0044] LC(链路控制字段)是链路控制的Sbit字段,可以用于标识帧类型等。 [0044] LC (Link Control field) is Sbit link control field identifies the frame type, etc. may be used.

[0045] SD (源设备)用于表示发送帧的节点地址。 [0045] SD (source device) is used to indicate the node address of the transmission frame.

[0046] SIZE用于标识以字节为单位的链路数据的长度。 [0046] SIZE for identifying the length in bytes of the data link.

[0047] FCS (帧校验序列)可以是16bit的帧校验序列,由曼彻斯特编码器产生,由译码器去除。 [0047] FCS (Frame Check Sequence) may be a 16bit frame check sequence is generated by a Manchester encoder, it is removed by the decoder.

[0048] ED (结束分界符)由曼彻斯特编码器产生,由译码器去除。 [0048] ED (end delimiter) is generated by a Manchester encoder, is removed by the decoder.

[0049] 下面详细说明本发明实施例提供的专用绞线式列车总线(WTB)控制装置的具体结构,全部是在FPGA内部实现。 [0049] A specific structural diagram of a dedicated wire train bus (WTB) of the control apparatus of the present embodiment of the invention, all implemented in FPGA detail. 该控制装置连接上层的处理器2和WTB物理通道电路3。 WTB physical channel processor circuit 2 and the control means is connected to an upper layer 3. 如图5所示,从通信协议分层的角度看,本发明提供的专用绞线式列车总线控制控制装置分成三个部分,即物理层、链路层和链路层接口。 5, from the perspective of a layered communication protocol, dedicated wire train bus control apparatus of the present invention provides divided into three parts, namely the physical layer, link layer and link-layer interfaces. 其中链路层接口主要提供与外部处理器之间的接口,为发送数据和接收数据提供缓存空间,作为与其他处理器件的数据传输通道;链路层主要实现HDLC协议;物理层主要实现WTB物理通道的控制、曼彻斯特编解码、定时、中断、FIFO转发。 Wherein the interface between the main link-layer interfaces with an external processor, to provide cache space for the transmit and receive data, as with the other member of the data transmission channel processor; link layer are as HDLC protocol; physical layer are as physical WTB the control channel, Manchester encoding and decoding, timing interrupts, forwarding the FIFO.

[0050] 具体地,在链路层接口部分包括发送缓存101和接收缓存102,其中发送缓存101 可以是发送双口RAM,接收缓存102可以是接收双口RAM。 [0050] Specifically, in the link-layer interface portion 101 includes a transmission buffer and a reception buffer 102, transmission buffer 101 which may be transmitted dual port RAM, the reception buffer 102 may be a dual-port receiver RAM. 发送缓存101用于为待发送数据提供缓存,接收缓存102用于为接收的数据提供缓存。 Transmission buffer cache 101 for providing data to be transmitted, the reception buffer 102 for providing the received data buffer.

[0051] 链路层部分包括HDLC帧发送器单元103和HDLC帧接收器单元104。 [0051] The link layer of the HDLC frame portion comprises a transmitter unit 103 and receiver unit 104 of the HDLC frame. 发送缓存101 相当于一个保存从处理器2发送过来的待发送数据的池,HDLC帧发送器单元103不断从这个池中取出待发送数据组成HDLC帧。 Transmission buffer 101 corresponds to a storage tank 2 is transmitted from the processor over the data to be transmitted, HDLC frame transmitting unit 103 transmits data to be continuously removed from this pool consisting of HDLC frame. HDLC帧发送器单元103用于从发送缓存101中读取待发送数据,并利用该取出的数据生成循环冗余校验(CRC)码,并形成HDLC帧。 HDLC frame transmission unit 103 from the transmission buffer 101 for reading the data to be transmitted, the data generated using a cyclic redundancy check (CRC) code of the extracted and formed HDLC frame. HDLC帧接收器单元104用于接收曼彻斯特编码解码模块107解码后的HDLC帧,进行解帧得到HDLC 帧中的数据,发送至接收缓存102中。 HDLC frame receiving unit 104 for receiving Manchester encoded HDLC frame after decoding module 107 decodes the deframed data obtained HDLC frame is transmitted to the reception buffer 102.

[0052] HDLC帧发送器单元103具体地可以包括读取单元1031、校验码生成单元1032、标志位插入单元1033、零比特插入单元1034、组帧单元10;35。 [0052] HDLC frame transmission unit 103 may particularly include a reading unit 1031, check code generating unit 1032, flag bit inserting unit 1033, a zero bit insertion unit 1034, framing unit 10; 35.

[0053] 其中,读取单元1031用于从发送缓存101中读取待发送数据; [0053] wherein the reading unit 1031 for reading from a transmission buffer 101, data to be transmitted;

[0054] 校验码生成单元1032用于利用读取单元1031读取的待发送数据生成循环冗余校验码。 [0054] check code generating unit 1032 for transmitting data to be read using the reading unit 1031 generates a cyclic redundancy check code. 进行循环冗余校验可以采用CRC-16校验,产生16位的CRC校验码,其生成多项式为: g(x) = x16+x、x5+l。 Cyclic redundancy check CRC-16 check may be employed, a 16-bit CRC check code generator polynomial is: g (x) = x16 + x, x5 + l. 为了进一步提高控制装置性能和处理速度,该发明采用并行CRC算法。 To further improve the performance and processing speed of the control apparatus, the invention is a parallel CRC algorithm.

[0055] 标志位插入单元1033用于构建HDLC帧的帧头和帧尾,例如,根据IS03309标准定义的一个HDLC格式,每个HDLC帧又应该由标识符'01111110'开始,同时由相同的标识符结束,此时,帧头和帧尾均为'01111110'。 [0055] flag bit inserting unit 1033 for constructing the header of the HDLC frame and the end frame, for example, according to an HDLC format defined by IS03309 standard, and each of the HDLC frame to be started by the identifier '01111110', and identified by the same break ends, at this time, header and trailer are '01111110'. 在实际HDLC帧发送的过程中,在发送数据前先插入HDLC帧头发送,当帧数据发送完毕后再插入相同的标识符作为HDLC帧尾。 In the actual transmission of the HDLC frame, is inserted before the transmission data is first transmission HDLC frame header, the frame when data transmission is completed and then insert the same identifier as the end of an HDLC frame.

[0056] 零比特插入单元1034用于对待发送数据进行扫描,对待发送数据中出现与HDLC 帧的帧头和帧尾的形式相同的位串的最后一位前插入零。 [0056] zero-bit insertion unit 1034 scans for data to be sent, treated with the form of HDLC frame header and the trailer of the same bit string appearing in the transmission data before a last zero is inserted. 如果在数据位中出现与作为HDLC 帧头和帧尾的标识符相同的数据,接收端会将该标识符识别为HDLC帧的帧头或帧尾,从而产生识别错误,为了防止这种现象的发生,对数据进行扫描,在5个'1'后插入一个'0',这个插入的'0'在接收端将被剔除以恢复数据,例如,当待发送的数据为'011101111110'时, 经过插零后实际发送的数据是'0111011111010,。 If the data bits as the identifier with the HDLC frame head and tail of the same data, the receiver will recognize the identifier of the header of the HDLC frame or a frame end, resulting in a recognition error in order to prevent this phenomenon occurs, the data is scanned, in 5 '1' after inserting a '0', this insert '0' at the receiving end will be removed to restore the data, for example, when data to be transmitted is '011101111110' when, after zero insertion data actually transmitted is "0111011111010 ,.

[0057] 组帧单元1035用于将构建的HDLC帧的帧头,经过零比特插入单元1034插零后的待发送数据、构建的HDLC帧的帧尾组成HDLC帧,并将构建的HDLC帧和生成的循环冗余校验码发送至物理层控制模块中。 HDLC frame of frame [0057] 1035 framing unit for constructing the header of the HDLC frame of data to be sent via the zero-bit insertion zero insertion unit 1034 to construct tail composition HDLC frame, and constructed and HDLC frames generating a cyclic redundancy check code to the physical layer control module.

[0058] 在实际中可以设置一个发送状态控制模块,用于采用状态机的方式对HDLC帧发送器单元进行控制,控制HDLC帧头发送、生成循环冗余校验码、实现零比特插入、数据发送、HDLC帧尾发送。 [0058] In practice, the state may be provided a transmission control module, a state machine manner HDLC frame transmission control unit controlling transmission HDLC header, cyclic redundancy check code, zero bit insertion, a data transmitting, HDLC transmission frame end. 图6示出了引入发送状态控制模块后的HDLC帧发送器单元的一种内部具体实现电路示意图。 FIG 6 illustrates an internal HDLC frame transmitter unit transmitting state after the introduction of the control module circuit diagram showing a specific implementation. 图7示出了WTB总线控制器发送数据时的流程示意图。 Figure 7 shows a schematic flow chart when the bus controller transmits data WTB.

[0059] HDLC帧接收器单元104具体地可以包括: [0059] HDLC frame receiver unit 104 may include in particular:

[0060] 帧同步单元1041,用于检测HDLC帧的帧头; [0060] The frame synchronization unit 1041, for detecting the header of the HDLC frame;

[0061] 剔零单元1042,用于扫描HDLC帧,并提出剔除连续5个'1,后的'0,;[0062] 校验单元1043,用于根据剔零单元1042剔零后的HDLC帧数据生成循环冗余校验码,并与包括该HDLC帧数据的WTB帧中的循环冗余校验码进行比较,完成循环冗余检验。 [0061] tick zero unit 1042 for scanning an HDLC frame, and make 5 consecutive reject '1, after the' 0,; [0062] checking unit 1043, a unit 1042 in accordance with the zero tick tick zero HDLC frame generating a cyclic redundancy check code data, and compared with the HDLC frame comprises WTB frame data in cyclic redundancy check, cyclic redundancy check is completed. 由上面描述可知,在发送方的HDLC帧发送器单元构建HDLC帧的过程中针对其中的数据生成循环冗余校验码,并加入到WTB帧中发送到接收方,当接收方接收到该HDLC帧后,针对接收到的HDLC帧中的数据重新生成循环冗余校验码,采用的算法与发送方相同,如果接收的数据没有出现差错,接收方再次生成的循环冗余校验码与从发送方接收的循环冗余校验码(即包括该HDLC帧数据的WTB帧中携带的循环冗余校验码)应该相同; From the above description that, in the HDLC frame constructing unit HDLC frames transmitted on the transmission side of the process for which the cyclic redundancy check code data generated and added to WTB frames sent to the receiver, when the receiving side receives the HDLC after the frame data is re-generated for the received HDLC frame in the cyclic redundancy check code, using the same algorithm as the sender, if no error occurs in the received data, the receiving side again cyclic redundancy check code generated from the sender received cyclic redundancy check code (i.e., cyclic redundancy check code comprises WTB frame of the HDLC frame carried in data) should be the same;

[0063] 解帧单元1044,用于将来自剔零单元1042的HDLC帧,去掉帧头标识符和帧尾标识符,并将处理后的数据送到校验单元1043进行CRC校验。 [0063] Solutions of the frame unit 1044, a tick from the zero-padding unit 1042 of the HDLC frame, remove the frame end identifier and the identifier header, and the processed data to the check unit 1043 performs a CRC check.

[0064] 在实际中可以设置一个接收状态控制模块,用于采用状态机的方式对HDLC帧接收器单元中的各个部分进行控制,控制HDLC帧头识别、码元同步、数据的解码、剔除被发送方填充的零比特并完成HDLC帧的校验,最后发送至接收缓存。 [0064] In practice, the reception state may be provided a control module, a mode for using the state machine controls each section of the HDLC frame receiving unit, the control HDLC header identification, symbol synchronization, decoded data, is excluded sender padding zero bits and complete HDLC frame check, and finally to the receiving buffer. 图8示出了引入接收状态控制模块后的HDLC帧接收器单元的一种内部具体实现电路示意图。 FIG 8 shows an internal HDLC frame receiving unit receiving state after the introduction of the control module circuit diagram showing a specific implementation. 图9为WTB总线控制器接收数据时的流程示意图。 FIG 9 is a schematic view of the flow controller receives the data bus WTB.

[0065] 最后详细说明物理层的构成。 [0065] Finally, the physical layer configuration described in detail.

[0066] 物理层主要实现WTB物理通道控制、曼彻斯特编码和解码、定时、中断和信号再生。 [0066] Physical layer are as WTB physical control channel, Manchester encoding and decoding, timing, interrupt and signal regeneration. 具体地,物理层可以包括WTB物理层控制模块105、通道管理模块106、曼彻斯特编码解码模块107、WTB定时器108、WTB寄存器109和WTB中断110。 Specifically, the physical layer may comprise WTB physical layer control module 105, the channel management module 106, Manchester encoding and decoding module 107, a timer 108 WTB, WTB WTB interrupt register 109 and 110.

[0067] 其中,通道管理模块106用于对WTB帧头和帧尾进行编码和解码,信号监测和线路选择;具体地,通道管理模块106可以包括:帧头帧尾编码解码单元1061、线路选择与冗余控制单元1062和载波与信号品质监测单元1063。 [0067] wherein the channel management module 106 for WTB header and trailer encoding and decoding, signal monitoring, and line selection; in particular, the channel management module 106 may include: the end of the encoding frame header decoding unit 1061, line selection and the redundancy control unit 1062 and the carrier 1063 with the signal quality monitoring unit. 其中,帧头帧尾编码解码单元1061用于实现WTB帧的帧头和帧尾的编码和识别;线路选择与冗余控制单元1062用于实现依据线路上的有效帧和无效帧对线路进行选择;载波与信号品质监测单元1063用于对载波和信号品质进行监测。 Wherein the end of frame header 1061 for realizing the codec unit WTB header and the trailer frame coding and identification; and the redundancy selection circuit 1062 for the control unit on the basis of a frame effective lines and select lines of the invalid frames ; carrier and signal quality monitoring unit 1063 and the carrier signal for quality monitoring.

[0068] 根据IEC61375规定的WTB的帧头是由起始位'1,和结束位'1,及夹在中间的7〜 15对('0,'1,)对组成,通常夹在中间('0,'1,)对总共为7对。 [0068] The header of IEC61375 WTB predetermined start bit is '1, and a stop bit' 1, and July to 15 pairs sandwiching ( '0,' 1) of the composition, typically sandwich ( '0,' 1,) for a total of 7 pairs. WTB帧尾是由一个2 个位宽的高脉冲和2个位宽的低脉冲组成,其中低脉冲不是必需的。 WTB end of the frame by a 2-bit wide bit width pulse high and low two pulses, wherein the low pulse is not required. 发送通道在发送帧数据前会根据链路控制层信号先插入WTB帧头发送,等数据发送完毕后再插入帧尾发送,接收通道通过监测到帧头和帧尾对数据进行同步。 Before transmitting the transmission channel based on the frame data link control layer header transmitted signal into first WTB, and other data transmission is completed before the end of the insertion frame transmission, the data is synchronized receiving channel by monitoring the frame head and tail.

[0069] 根据IEC61375的规定进行信号品质监测主要用于信号质量监测和冗余切换,产生载波检测信号(CS)和信号品质错误信号(SQE)反馈给上层,用于判断帧是否有效,依据线路上的有效帧和无效帧来对线路进行选择。 [0069] The predetermined signal quality monitoring IEC61375 primarily for quality monitoring and redundancy switching signal, generating a carrier detect signal (CS) signal quality and an error signal (the SQE) is fed back to the upper layer, for determining whether the frame is valid, based on the line valid frame and invalid frame of the selected line.

[0070] 根据IEC61375规定的WTB通信传输的是曼彻斯特信号,曼彻斯特编码解码模块107编码的目的是实现NRZ信号与曼彻斯特码的转换。 [0070] The communication transmission IEC61375 WTB predetermined signal is Manchester, Manchester coding module 107 decoding the encoded NRZ signal conversion object is achieved with the Manchester code. 具体地,将链路层HDLC帧的NRZ信号与IM时钟信号做异或逻辑后,用D触发器锁存输出曼彻斯特码,完成曼彻斯特编码的过程; 采用16M时钟采样WTB传输线上的曼彻斯特码,同时做同步校正,判断跳沿类型译出'1'还是'0',作为NRZ信号传输给链路层。 Specifically, after the NRZ signal and the IM clock signal link layer of the HDLC frame XOR logic, the D flip-flop latches the output of the Manchester code, through the process of Manchester encoding; using 16M clock sampling Manchester code WTB transmission line, while make the synchronization correction, determines the type of the jump along unscrambled '1' or '0', as the NRZ signal is transmitted to the link layer.

[0071] 曼彻斯特编码解码模块107对所述HDLC帧发送器单元103生成的HDLC帧进行曼彻斯特编码,并将编码后的WTB帧头和WTB帧尾与编码后的HDLC帧组成WTB帧,通过外部接口(在实际中可以是控制装置对外的WTB物理接口)发送至传输通道中,还用于对通过外部接口接收到的WTB帧中的HDLC帧进行曼彻斯特解码。 [0071] Manchester encoding and decoding module 107 Manchester encoded HDLC frame to the HDLC frame generated by the transmitting unit 103, the header of the encoded WTB WTB frames and tail frames encoding the HDLC frame WTB, via the external interface (in practice it may be a physical interface WTB external control means) to the transmission channel, also for WTB frame received through the external interface to the HDLC frame Manchester decoding.

[0072] WTB定时器是在WTB总线控制装置中设置的多个参数寄存器,根据用户的需求,可以对寄存器参数进行相应设置实现相应的功能。 [0072] WTB timer is provided in a plurality of parameter registers WTB bus control apparatus in accordance with the user's needs, it can be set to achieve the appropriate function corresponding to the parameter register. WTB定时器包括在WTB总线控制装置中设置的多个延时定时器和线路监测定时器,用于监测网络运行。 WTB timer comprising a delay timer and a plurality of line monitoring bus WTB timer provided in the control apparatus, for monitoring the network operation. 信号接收完成、信号发送完成、定时器和MAU报告等通过WTB中断及中断状态寄存器反馈给用户。 Reception completion signal, completion signal is transmitted, and the timer interrupt WTB MAU reports by the interrupt status register and the feedback to the user.

[0073] WTB物理层控制模块105是HDLC链路层与物理层之间的接口,用来协调物理层各模块配合工作,传递上层的指示信号和反映物理层状态。 [0073] WTB physical layer control module 105 is the interface between the HDLC link layer and the physical layer, the physical layer of each module to coordinate with the work, passing the upper layer indication signal and reflect the physical state. 表1示出了WTB物理层控制模块105提供的一种WTB物理接口的具体实现,表2示出了WTB物理层控制模块105提供的一种链路层接口的具体实现。 Table 1 shows a specific realization of a physical interface WTB WTB physical layer control module 105, and Table 2 shows a specific link-layer interface to implement a physical layer control module 105 WTB provided.

[0074] 表1 [0074] TABLE 1

[0075] [0075]

信号 功能描述 方向WTBJNIA 方向IA通道输入 输入WTB_IN2A 方向M通道输入 输入WTB—INlB 方向IB通道输入 输入WTB—IN2B 方向2B通道输入 输入WTB—OUTIA 方向IA通道正向输出 输出WTB—OUT1A—L 方向IA通道反向输出 输出WTB—0UT1B 方向IB通道正向输出 输出WTB—0UT1B—L 方向IB通道反向输出 输出WTB—0UT2A 方向2k通道正向输出 输出WTB—0UT2A—L 方向2k通道反向输出 输出WTB—0UT2B 方向2B通道正向输出 输出WTB—0UT2B—L 方向2B通道反向输出 输出WTB—C0NTR0LA—L A通道终端设定控制 输出WTB—C0NTR0LB—L B通道终端设定控制 输出 Function Signal Description direction WTBJNIA direction IA channel input WTB_IN2A direction M input channels WTB-INlB direction IB input channel WTB-IN2B direction input channel 2B WTB-OUTIA forward direction IA channel output WTB-OUT1A-L channel direction IA reverse direction output WTB-0UT1B IB forward channel output WTB-0UT1B-L IB direction reverse channel output WTB-0UT2A forward direction of the output channel 2k WTB-0UT2A-L 2k direction reverse channel output WTB- 2B 0UT2B direction forward channel output WTB-0UT2B-L direction reverse output channel 2B WTB-C0NTR0LA-LA terminal setting control channel WTB-C0NTR0LB-LB output channel setting control output terminal

[0076]表 2 [0076] TABLE 2

[0077] [0077]

Figure CN101860467BD00101

[0078] 另外,本发明实施例优选地,在物理层中还包括:存储转发模块111。 [0078] Further, preferred embodiments of the present invention embodiment, the physical layer further comprising: a storage module 111 forward. 随着列车总线长度的增加,列车通信必须面对信号衰减引起的问题。 With the increase of the length of the train bus, train traffic must face the problem of signal attenuation caused. 增加了存储转发模块111,可以实现信号的再生和放大,延长信号的传输距离,起到一个中继器的作用。 Forwarding increases the storage module 111, reproduced and amplified signal can be realized, and extend the transmission distance of the signal, acts as a repeater. 该存储转发模块111 根据上层控制信号和输入信号质量对信号采样存储转发。 The forwarding module 111 forwards the stored signal samples are stored according to an upper layer control signal and the input signal quality. 在实际中,即便提供了存储转发模块111,也可以根据用户需要设置该功能是否有效。 In practice, even if the forwarding is provided a storage module 111, the function may be set according to whether a valid user.

[0079] 综上可知,本发明实施例提供的控制装置考虑到了WTB总线控制器的全局,在满足物理层各项功能的基础上实现链路层的帧转发功能,通用性好,不受专用的HDLC收发芯片的限制。 [0079] To sum up, the frame control device provided in the embodiment of the present invention takes into account the global bus controller WTB, based on the link layer to realize various functions of the physical layer satisfies the forwarding function, general good, not specific restriction transceiver chip HDLC.

[0080] 以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。 [0080] The above are only preferred embodiments of the present invention, it should be noted that those of ordinary skill in the art, in the present invention without departing from the principles of the premise, can make various improvements and modifications, such modifications and modifications should also be regarded as the protection scope of the present invention.

Claims (6)

  1. 1. 一种专用绞线式列车总线WTB控制装置,其特征在于,包括链路层模块接口、链路层模块和物理层模块,其中所述链路层接口模块包括:发送缓存模块和接收缓存模块,所述链路层模块包括HDLC帧发送器单元和HDLC帧接收器单元,所述物理层模块包括物理层控制模块、通道管理模块、曼彻斯特编码解码模块、定时器、中断器和寄存器;其中,所述发送缓存模块用于为待发送数据提供缓存;所述HDLC帧发送器单元用于从发送缓存中读取待发送数据,并利用该取出的数据生成循环冗余校验码及形成HDLC帧; 所述物理层控制模块用于为所述链路层和物理层之间提供接口,所述通道管理模块用于对WTB帧头和帧尾进行编码和解码,信号监测和线路选择;所述曼彻斯特编码解码模块用于对所述HDLC帧发送器单元生成的HDLC帧进行曼彻斯特编码,并将编码后的WTB帧头和WTB A special wire train bus WTB control apparatus, wherein the interface module comprises a link layer, a link layer module and the physical layer module, wherein said link-layer interface module comprising: a transmission buffer and a receive buffer module module, the link layer module comprises a HDLC frame transmitter unit and a receiver unit of the HDLC frame, the physical layer control module includes a physical layer module, the channel management module, Manchester encoding and decoding module, a timer, and an interrupt register; wherein the transmission buffer cache module for providing data to be transmitted; the HDLC frame transmitting unit for transmitting data to be read from the transmission buffer, data generated using a cyclic redundancy check code is formed and taken out of the HDLC a frame; the physical layer control module for providing an interface between the link layer and the physical layer, the channel management module for WTB header and trailer encoding and decoding, signal monitoring, and line selection; the said means for decoding Manchester encoded HDLC frames to said HDLC frame generated by the transmitter unit Manchester encoding, the WTB WTB header and the encoded 尾与编码后的HDLC帧组成WTB帧,通过外部接口发送至传输通道中,还用于对通过外部接口接收到的WTB帧中的HDLC帧进行曼彻斯特解码;所述HDLC帧接收器单元用于接收曼彻斯特编码解码模块解码后的HDLC帧,进行解帧得到HDLC帧中的数据,发送至接收缓存模块中。 Tail with encoded frames WTB HDLC frame to the transmission channel through an external interface, also for WTB frame received through the external interface HDLC frame Manchester decoding; the HDLC frame receiving unit for receiving Manchester encoded HDLC frame decoded block decoding, de-frame data obtained in the HDLC frame, the reception buffer to the transmission module.
  2. 2.根据权利要求1所述的专用绞线式列车总线WTB控制装置,其特征在于,所述HDLC 帧发送器单元包括:读取单元,用于从发送缓存中读取待发送数据;校验码生成单元,用于利用读取单元取出的待发送数据生成循环冗余校验码;标志位插入单元,用于构建HDLC帧的帧头和帧尾,所述HDLC帧头和帧尾为'01111110,;零比特插入单元,用于对待发送数据进行扫描,在5个'1'后插入一个'0' ;组帧单元,用于将构建的HDLC帧的帧头、经过零比特插入单元插零后的待发送数据、 构建的HDLC帧的帧尾组成HDLC帧,将构建的HDLC帧和所述生成的循环冗余校验码发送至物理层控制模块中。 The dedicated wire train bus WTB control apparatus according to claim 1, wherein said HDLC frame transmission unit comprising: a reading unit configured to read from the transmission buffer data to be transmitted; check code generating means for utilizing the transmission data reading unit to be taken out cyclic redundancy check code; flag bit inserting unit, for constructing the HDLC frame header and the trailer, the header and trailer to HDLC ' 01111110 ,; zero bit insertion unit configured to scan data to be sent, after inserting a '0' in the 5 '1'; framing unit for constructing the header of the HDLC frame, through zero bit insertion unit inserted zero data to be sent after the frame of the HDLC frame constructed tail composition HDLC frame, and transmitting HDLC frames constructed the generated cyclic redundancy check code to the physical layer control module.
  3. 3.根据权利要求2所述的专用绞线式列车总线WTB控制装置,其特征在于,所述HDLC 帧接收器单元包括:帧同步单元,用于检测HDLC帧的帧头;剔零单元,用于扫描HDLC帧中HDLC帧头后的数据,剔除5个'1'后面的'0' ;校验单元,用于根据剔零单元剔除后的HDLC帧数据生成循环冗余校验码,并与包括该HDLC帧的WTB帧中的循环冗余校验码进行比较,完成循环冗余校验;所述接收缓存模块用于接收从HDLC帧接收器单元中经剔零单元剔零后的HDLC帧中的数据。 The dedicated wire train bus WTB control apparatus according to claim 2, wherein the HDLC frame receiving unit comprises: frame synchronization means for detecting the header of the HDLC frame; zero tick unit, with after the scan data to the header of the HDLC frame in HDLC, excluding '0' 5 '1' behind; checking unit, for generating a cyclic redundancy check code data in accordance with the HDLC frame tick zero unit removed, and with WTB including cyclic redundancy check code of the frame of the HDLC frame are compared, to complete a cyclic redundancy check; the receive buffer means for receiving HDLC frames from the receiver unit via the unit tick tick zero zero HDLC frame the data.
  4. 4.根据权利要求1所述的专用绞线式列车总线WTB控制装置,其特征在于,所述通道管理模块包括:帧头帧尾编码解码单元,用于实现WTB帧的帧头和帧尾的编码和识别;线路选择与冗余控制单元,用于实现依据线路上的有效帧和无效帧对线路进行选择;载波与信号品质监测单元,用于对载波和信号品质进行监测。 The dedicated wire train bus WTB control apparatus according to claim 1, wherein the channel management module comprises: a header frame end codec unit for implementing WTB frame header and the frame tail coding and recognition; redundant line selection control means, for realizing the basis of valid and invalid frames on the frame line of the selected line; carrier and signal quality monitoring means for monitoring signal quality and a carrier.
  5. 5.根据权利要求2或3所述的专用绞线式列车总线WTB控制装置,其特征在于,所述校验码生成单元为采用并行循环校验生成算法生成循环校验码的校验码生成单元。 The dedicated strand WTB train bus control apparatus of claim 2 or claim 3, wherein the check code generating unit using a parallel loop check code generation algorithm to generate parity check code generated cyclic unit.
  6. 6.根据权利要求1至4中任意一项所述的专用绞线式列车总线WTB控制装置,其特征在于,所述物理层模块还包括存储转发模块,用于对传输线路上的信号采样并进行存储转发。 The dedicated wire train bus WTB 1 to 4, the control device according to any one of the preceding claims, wherein the physical layer module further comprises a store and forward means for sampling the signal on the transmission line and to store and forward.
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