CN101859726B - Method for improving MOSFET STI dislocation - Google Patents

Method for improving MOSFET STI dislocation Download PDF

Info

Publication number
CN101859726B
CN101859726B CN200910133938XA CN200910133938A CN101859726B CN 101859726 B CN101859726 B CN 101859726B CN 200910133938X A CN200910133938X A CN 200910133938XA CN 200910133938 A CN200910133938 A CN 200910133938A CN 101859726 B CN101859726 B CN 101859726B
Authority
CN
China
Prior art keywords
sti
dislocation
substrate
degree
qualification rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200910133938XA
Other languages
Chinese (zh)
Other versions
CN101859726A (en
Inventor
初曦
刘光
高永亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Warship chip manufacturing (Suzhou) Limited by Share Ltd
Original Assignee
Hejian Technology Suzhou Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hejian Technology Suzhou Co Ltd filed Critical Hejian Technology Suzhou Co Ltd
Priority to CN200910133938XA priority Critical patent/CN101859726B/en
Publication of CN101859726A publication Critical patent/CN101859726A/en
Application granted granted Critical
Publication of CN101859726B publication Critical patent/CN101859726B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The invention relates to a method for improving MOSFET STI dislocation, which provides a substrate with the insulation structure of a shallow groove, wherein the upper surface of the substrate is coated with an SiN layer; and a sacrificial oxide layer grows on the SiN layer, and nitrogen gas with a preset temperature is introduced within a section of preset time during growth to carry out tempering treatment. By adopting the method, the phenomenon of dislocation can be obviously lowered, the qualification rate is enhanced, the cost is lowered, and the technological period is shortened.

Description

A kind of method of improving MOSFET STI difference row
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of method of improving shallow trench isolation (STI) the difference row (Dislocation) of mos field effect transistor (MOSFET).
Background technology
In the production process of chip, in the processing procedure of leading portion (FEOL) shallow trench isolation, regular meeting is because the effect of stress produces difference row phenomenon, and shown in Fig. 1 centre circle, this difference row's phenomenon can cause and connect the rapid rising of face leakage current, causes chip failure.And the reason that produces difference row phenomenon mainly contains following two:
(1) when heating and cooling, because the coefficient of expansion missionary society between oxide and the substrate produces stress;
(2) profile/degree of depth of STI can be to the generation stress intensity and the influence to some extent that distributes.
Semiconductor chip develops to more exquisite direction always at present, and the experiment surface, the trend of assembly district downsizing is unfavorable for the mitigation of stress, perplexs greatly so difference row phenomenon becomes industry one.
Summary of the invention
The objective of the invention is to overcome the problems referred to above, a kind of MOSFET of improvement STI difference row's method is provided.
The invention provides a kind of MOSFET of improvement STI difference row's method, this method is:
Provide one have an insulation structure of shallow groove substrate, this upper surface of substrate is coated with the SiN layer;
The sacrificial oxide layer of on the SiN layer, growing, the nitrogen that in one period scheduled time, feeds predetermined temperature in the time of growth carries out temper.
Above-mentioned predetermined high temperature is 900~1200 degree.
Above-mentioned predetermined high temperature is preferably 1100 degree.
The above-mentioned scheduled time is 10~120 minutes.
The above-mentioned scheduled time is preferably 30 minutes.
Adopt the inventive method can significantly reduce difference row phenomenon, improve qualification rate, and reduce cost and shorten process cycle.
Description of drawings
Fig. 1 representes lattice difference row's of the prior art sketch map;
Fig. 2 representes the stress envelope of the present invention when sacrificial oxide layer heats up;
Fig. 3 representes to adopt the effect contrast figure of the inventive method and prior art;
Fig. 4 representes to adopt and the curve comparison diagram that does not adopt the qualification rate of tempering method for treating of the present invention.
Embodiment
Below in conjunction with specific embodiment, a kind of method of improving MOSFET STI difference row of the present invention is done further to specify.
In the methods of the invention, at first provide one have an insulation structure of shallow groove substrate, this upper surface of substrate is coated with the SiN layer; The sacrificial oxide layer of on the SiN layer, growing; In the process of growth sacrificial oxide layer; At certain hour, for example be feed uniform temperature in 10~120 minutes, for example be that the nitrogen (N2) of 900~1200 degree carries out temper, reduce and eliminate difference and arrange phenomenon through this method.In a preferred embodiment, the time that feeds N2 is 30 minutes, and temperature is 1100 degree.
So-called sacrificial oxide layer is meant, when silicon places under the oxygenous environment, oxygen molecule will reach the surface of silicon through one deck boundary layer (boundary layer), then with the SiO2 layer of silicon atom reaction generation.The effect of sacrificial oxide layer is: eliminate the damage of SIN displacement to wafer surface 1.; 2. prevent to produce when N/P trap ion from implanting channeling effect.
Tempering is a kind of process technique very common in the metallurgical material processing procedure, its objective is will eliminate in the material (especially metal material) internal stress of accumulating because of defective.The method that is adopted is with being placed following a period of time of suitable high temperature by the tempering material, utilizing heat energy to make the atom of material have the ability to carry out the rearrangement of lattice position, to reduce defect concentration in the material.
After sacrificial oxide layer heated up, the STI stress distribution was as shown in Figure 2, and the part that is positioned at the channel bottom place at substrate is born tension stress, and compression is born at other positions of substrate, and wherein the stress that bears of the highest point of substrate and lowest part reaches maximum.
With reference to Fig. 3, wherein Fig. 3 (a) is the situation of not passing through N2 temper of the present invention, and Fig. 3 (b) is the situation of having passed through temper of the present invention.It is thus clear that when not passing through N2 temper of the present invention, difference row's phenomenon clearly and will obviously be improved difference row phenomenon carry out 1100 degree tempering through N2 after.
Fig. 4 representes to adopt temper of the present invention and the curve comparison diagram that does not adopt the qualification rate of temper of the present invention; The content that each curve referred to is shown in Fig. 4 right side; Wherein circular lines is illustrated in without the qualification rate under the 1100 degree temper conditions, and the square frame line is represented through the qualification rate under the 1100 degree temper conditions; Triangle line representes not adopt the percentage that in the qualification rate test, causes qualification rate to lose efficacy because of the excessive reason of quiescent current under the 1100 degree temper conditions, and little cross wires is represented through the percentage that in the qualification rate test, causes qualification rate to lose efficacy because of the excessive reason of quiescent current under the 1100 degree temper conditions; Lineae trapezoidea is represented the degree of depth of shallow trench isolation.Visible by figure, obviously increase through qualification rate under the 1100 degree temper conditions.
1100 degree tempering through N2 can significantly reduce difference row's phenomenon, improve qualification rate, and reduce cost and shorten process cycle.
The above is merely preferred embodiment of the present invention, is not to be used for limiting practical range of the present invention; If do not break away from the spirit and scope of the present invention, the present invention is made amendment or is equal to replacement, all should be encompassed in the middle of the protection range of claim of the present invention.

Claims (3)

1. a method of improving MOSFET STI difference row is characterized in that
Provide one have an insulation structure of shallow groove substrate, this upper surface of substrate is coated with the SiN layer;
The sacrificial oxide layer of on the SiN layer, growing, the nitrogen that feeds 900~1200 degree in the time of growth carries out 10~120 minutes temper of duration.
2. method according to claim 1, the temperature that it is characterized in that the nitrogen of said feeding are 1100 degree.
3. method according to claim 2 is characterized in that said duration is 30 minutes.
CN200910133938XA 2009-04-10 2009-04-10 Method for improving MOSFET STI dislocation Active CN101859726B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200910133938XA CN101859726B (en) 2009-04-10 2009-04-10 Method for improving MOSFET STI dislocation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN200910133938XA CN101859726B (en) 2009-04-10 2009-04-10 Method for improving MOSFET STI dislocation

Publications (2)

Publication Number Publication Date
CN101859726A CN101859726A (en) 2010-10-13
CN101859726B true CN101859726B (en) 2012-07-18

Family

ID=42945524

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200910133938XA Active CN101859726B (en) 2009-04-10 2009-04-10 Method for improving MOSFET STI dislocation

Country Status (1)

Country Link
CN (1) CN101859726B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6548366B2 (en) * 2001-06-20 2003-04-15 Texas Instruments Incorporated Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
CN101246837A (en) * 2007-02-13 2008-08-20 中芯国际集成电路制造(上海)有限公司 Semiconductor isolation structure and forming method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6548366B2 (en) * 2001-06-20 2003-04-15 Texas Instruments Incorporated Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
CN101246837A (en) * 2007-02-13 2008-08-20 中芯国际集成电路制造(上海)有限公司 Semiconductor isolation structure and forming method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP平5-299344A 1993.11.12

Also Published As

Publication number Publication date
CN101859726A (en) 2010-10-13

Similar Documents

Publication Publication Date Title
CN107710417B (en) Method for manufacturing semiconductor device
WO2003096426A1 (en) Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods
JP2006351612A (en) Semiconductor device and manufacturing method thereof
US9123671B2 (en) Silicon wafer strength enhancement
JP4876442B2 (en) SIMOX wafer manufacturing method and SIMOX wafer
US7723195B2 (en) Method of forming a field effect transistor
CN101859726B (en) Method for improving MOSFET STI dislocation
KR101219358B1 (en) Method for separating substrate and production method for bonding substrate using the same
US20100213554A1 (en) Gate structure and method for trimming spacers
CN109904058A (en) A method of reducing silicon polished front edge damage
CN103262222B (en) The heat oxide film formation method of silicon single crystal wafer
US8759198B2 (en) Accelerated furnace ramp rates for reduced slip
WO2008023701A1 (en) Method for heat-treating silicon wafer
CN101989574B (en) Method for manufacturing semiconductor device with strain memory action
CN111430234B (en) Rapid heat treatment method for wafer control wafer
CN104992966B (en) A kind of preparation method of the low bipolar high frequency power transistor chip of heat budget
CN102210011A (en) Semiconductor device and method of producing the same
CN110364436B (en) Semiconductor device and method of forming the same
CN101567329B (en) Method for producing STI lining oxide layer
CN105140180A (en) Manufacturing method of thin-film transistor array substrate and preparation method of polycrystalline silicon material
CN102427043B (en) Method for improving carrier mobility of PMOS (P-channel Metal Oxide Semiconductor) device
CN106856165B (en) Low-temperature silicon germanium epitaxy method
KR100772021B1 (en) Method for producing virtual gallium nitride epitaxial wafer and vertical conduction device
JP2022064306A (en) Nitride semiconductor device and manufacturing method of nitride semiconductor device
CN101211786A (en) Annealing method for enhancing transverse diffusion metal oxide semiconductor sparking resistance

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP03 Change of name, title or address
CP03 Change of name, title or address

Address after: 215123 333 Xinghua street, Suzhou Industrial Park, Jiangsu

Patentee after: Warship chip manufacturing (Suzhou) Limited by Share Ltd

Address before: 215025 Xinghua street, Suzhou Industrial Park, Suzhou, Jiangsu 333

Patentee before: Hejian Technology (Suzhou) Co., Ltd.