CN101840972B - Semiconductor photoelectric element structure of inverted chip type and making method thereof - Google Patents

Semiconductor photoelectric element structure of inverted chip type and making method thereof Download PDF

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CN101840972B
CN101840972B CN 200910119833 CN200910119833A CN101840972B CN 101840972 B CN101840972 B CN 101840972B CN 200910119833 CN200910119833 CN 200910119833 CN 200910119833 A CN200910119833 A CN 200910119833A CN 101840972 B CN101840972 B CN 101840972B
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light emitting
forming
semiconductor
substrate
layer
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CN 200910119833
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CN101840972A (en )
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叶颖超
吴芃逸
曾文良
林文禹
涂博闵
詹世雄
郭子毅
陈隆欣
黄世晟
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展晶科技(深圳)有限公司
荣创能源科技股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

The invention relates to a semiconductor photoelectric element structure of an inverted chip type and a making method thereof. The making method comprises the following steps of: firstly, forming a sacrifice layer on an extensive substrate; forming a semiconductor luminous structure on the sacrifice layer; etching the semiconductor luminous structure; fixing a semiconductor photoelectric bare chip on the encapsulated substrate in the inverted chip mode, and then separating the extensive substrate by using a lift-off technology. The making method of the semiconductor photoelectric element structure of the inverted chip type has simple process, and the semiconductor photoelectric element made by using the making method has high luminous efficiency and good heat dispersion.

Description

倒装芯片式半导体光电元件的结构及其制造方法 Structure and manufacturing method of the semiconductor flip chip type photovoltaic element

技术领域 FIELD

[0001] 本发明关于ー种倒装芯片式半导体光电元件的结构及其制造方法,特别是有关于以倒装芯片方式将裸片固定于封装基板后,再以剥离技术(Lift Off)将暂时外延分离的半导体光电元件的结构及其制造方法。 [0001] The present invention relates to structure and method of flip-chip semiconductor ー species photovoltaic element, particularly, the flip-chip die is fixed to the package substrate, and then to lift-off technique (Lift Off) temporarily structure and method of separating an epitaxial semiconductor photovoltaic element.

背景技术 Background technique

[0002] 发光二极管(Light Emitting Diode ;简称LED),为ー种可将电能转化为光能的电子元件,并同时具备ニ极管的特性。 [0002] The light-emitting diode (Light Emitting Diode; referred to as the LED), is a species ー electrical energy into light may be an electronic component, and also includes Ni diode characteristics. 发光二极管最特别之处在于只有从正极通电才会发光,一般给予直流电时,发光二极管会稳定地发光。 Most notably light emitting diodes from the positive power will only emit light when a direct current is generally given, the light emitting diode can stably emit light. 但如果接上交流电,发光二极管会呈现闪烁的型态。 But if connected to an alternating current, the LED will blink patterns. 闪烁的频率依据输入交流电的频率而定。 Flashing frequency based on the frequency of AC input may be. 发光二极管的发光原理是外加电压,使得电子与空穴在半导体内结合后,将能量以光的形式释放。 LED light-emitting principle is the applied voltage, so that the electrons and holes in the semiconductor After binding, the energy released in the form of light.

[0003] 对于发光二极管而言,寿命长、低发热量及低耗电量、节约能源及減少污染是其最大的优点。 [0003] For a light emitting diode, long life, low power consumption and low heat, saving energy and reduce pollution is its greatest advantage. 发光二极管的应用面很广,但发光效率为其中ー个有待提高的问题,也始終困扰着发光二极管照明技术的推广普及。 Application of surface-emitting diode is very broad, but in which the luminous efficiency needs to be improved ー a problem, always plagued popularizing LED lighting technology. 发光效率要提高,就要有效增加光输出效率。 To improve light emission efficiency, it is necessary to effectively increase the light output efficiency.

[0004] 发光二极管的封装元件可分为水平元件及垂直元件两种。 [0004] The light emitting diode package component can be divided into two kinds of the horizontal member and the vertical member. 请參考图Ia及图lb,其为传统打线接合技术与倒装芯片技术的封装结构比较图。 Referring to FIG Ia and FIG. Lb, compare the package structure of FIG flip chip technology and conventional technology which engage wire. 所谓水平元件为外延所使用的基板为不导电的蓝宝石基板,且其n型电极105及p型电极107位于元件的同一面向。 The so-called horizontal elements epitaxial substrate used is a non-conductive sapphire substrate, and the n-type electrode 105 and the p-type electrode 107 positioned facing the same element. 元件封装主要以打线接合技术(Wire Bonding)及倒装芯片技术(Flip Chip)两种方式。 The main element package to the wire bonding technique (Wire Bonding) and flip-chip technology (Flip Chip) in two ways. 以图Ia所示,图Ia中向上的箭头为主要发光方向,向下的箭头为主要散热方向,打线接合技术是将发光二极管裸片123直接粘贴于封装基板115上,再利用金属线311电性连接发光ニ极管裸片123与封装基板115。 In Figure Ia the upward arrows in FIG. Ia is a main light emitting direction of the main cooling down arrow direction, the wire bonding technique to the LED die 123 is directly attached to the package substrate 115, and then by metal lines 311 ni electrically connecting the light emitting diode die 123 and the package substrate 115. 如图Ib所示,图Ib中向上的箭头为主要发光方向,向下的箭头为主要散热方向,倒装芯片技术是将发光二极管裸片123反置于凸块113上,再由凸块113与封装基板115固定以及电性连接。 As shown in FIG. Ib, Ib upward arrow in FIG main emission direction, as the main cooling down arrow direction, flip chip technology LED die 123 is placed on the bumps 113 trans, and then the bumps 113 connected to the package substrate 115 is fixed and electrically. 打线接合技术为目前应用最广的技术,其可迅速获得大量的量产。 Wire bonding technology is currently the most widely used technique that can quickly get a lot of production. 但是,倒装芯片技术因无电极及金属线在发光表面上干扰,所以倒装芯片技术相対的可以比打线接合技术的亮度高。 However, flip-chip technology, and because there is no electrode on the light emitting surface of the metal wire interference, so that high brightness can be wire bonding technique than Dui phase of flip chip technology. 另外,倒装芯片技术是以凸块垫高裸片,其散热性相対的也比直接粘合于封装基板上的打线接合技术好。 Additionally, flip-chip technology is boosted die bumps, the cooling phase Dui also better than directly bonded wire bonded to the package substrate technology.

[0005] 请參考图2,其为现有技术的垂直元件结构图,该图中向上的箭头为主要发光方向,向下的箭头为主要散热方向。 [0005] Please refer to FIG 2, which is a block diagram of a vertical element of the prior art, the drawing up of the main emission direction of the arrow, down arrow the main cooling direction. 所谓垂直元件为近年来发展出的发光二极管结构,其特色为改用导电性较佳的基板如碳化硅(SiC)取代蓝宝石基板,或是以剥离技术(Lift off)将蓝宝石基板与发光结构分离。 The so-called vertical structure light emitting diode element in recent years developed, which use characteristics of a conductive substrate is preferred such as silicon carbide (SiC) substituted sapphire substrate, or to lift-off technique (Lift off) The sapphire substrate is separated from the light emitting structure . 另外,垂直元件的第一电极215可以为n型电极或是p型电极及第ニ电极217位于元件的相对面向,其中第一电极215为n型电极则第二电极217为P型电极,第一电极215为p型电极则第二电极217为n型电极。 The first electrode 215 may be perpendicular to the element Ni electrode 217 is located opposite faces of an n-type element or a p-type electrode and the second electrode, wherein the first electrode is an n-type electrode 215 of the second electrode 217 is a P-type electrode, the first electrode 215 is a p-type electrode of the second electrode 217 is an n-type electrode. 封装时,一端的第一电极215可直接与封装基板115黏合,另ー端的第二电极217则需以金属线311打线接合方式才能达到电性连接。 When the package, one end of the first electrode 215 may be directly bonding the package substrate 115, the other end of the second electrode 217 ー need a metal wire 311 wire bonding in order to achieve electrical connection. 垂直元件比水平元件的散热性及发光率佳,尤其是以剥离技术去除基板,更使得元件的导电性増加。 Better than the vertical component of the radiation and the level of the light emitting element, in particular in removing the substrate lift-off technique, so that the conductive zo more elements added. 由于垂直元件的一端第二电极217形成于发光区域上,在元件发光时,第二电极217会因遮蔽发光面积而影响元件的发光强度。 Since the second electrode end of the vertical member 217 is formed on the light emitting region, when the light emitting element, the second electrode 217 will affect the intensity of the light emitting element of the light emitting area due to shadowing. 尤其是在元件发光面积越小时,其电极的相对遮蔽面积越大,发光強度越受影响。 Especially in the area of ​​the light emitting element is smaller, the greater the area of ​​the electrode opposite the shield, the light emission intensity affected. 理论上为避开电极的遮蔽,改以倒装芯片技术加以封装可以达到散热性佳及亮度高等优点,但是エ艺上有其困难度。 Theoretically avoid the shielding electrode, to be changed to a flip-chip packaging technology can achieve high brightness and good heat dissipation advantages, but there are difficulties on Ester arts. 请參考图3a、图3b及图3c,其为蚀刻、剥离外延基板及倒装芯片封装的简单示意图。 Please refer to FIG. 3a, 3b and to Figure 3c, which is etched, a simple schematic of an epitaxial substrate and the flip chip package peeling. 由图3a所不,当外延基板101形成ー发光结构309后,于所述发光结构309上再形成一第一电极215。 FIG 3a is not, when the substrate 101 is formed ー epitaxial light emitting structure 309, 309 on the light emitting structure and then a first electrode 215 is formed. 接着蚀刻至发光结构309并暴露出n型导电层。 Then etched to expose the light emitting structure 309 and the n-type conductive layer. 再由图3b所示,以溅镀的方式形成第二电极217于n型导电层上方,再个别将凸块113置于第二电极217与第一电极215上方以达到电性连接。 FIG. 3b again, is formed by sputtering of the second electrode layer 217 over the n-type conductivity, then the individual bumps 113 disposed over the second electrode 217,215 in order to achieve electrically connected to the first electrode. 接下来移除所述外延基板101。 Next, the epitaxial substrate 101 is removed. 图3c则为裸片切割,形成为个别的裸片,该图中虚线箭头为切割方向。 Figure 3c was die cut, formed into individual die, the broken line arrows in FIG cutting direction. 实际上,所述エ艺中有几个部分是需要克服的。 In fact, the Ester Arts has several parts that need to be overcome. 第一部分为蚀刻过程。 The first part of the etching process. 由于发光结构309与第一电极215之间的实际厚度比例可以达到I : 20以上的差距,在蚀刻的过程中要先将第一电极215完全去除后才能到达发光结构309。 Since the ratio between the actual thickness of the light emitting structure 309 and the first electrode 215 can reach I: 20 or more gaps in the process of etching the first to reach the first electrode 309 after the light emitting structure 215 is completely removed. 所以,蚀刻必须要考量第一电极的厚度,但往往难以拿捏发光结构蚀刻的深度。 Therefore, the etching must consider the thickness of the first electrode, it is often difficult to draw the depth of etching the light emitting structure. 第二部分为形成第二电极的过程。 The second part of the second electrode forming process. 一般以溅镀的方式形成电极。 Generally is formed by sputtering of an electrode. 由图3a可见,形成第二电极217的位置为ー深U型空间313。 Be seen from Figure 3a, the position of the second electrode 217 is formed as a U-shaped space 313 ー deep. 对于溅镀技术而言已经增加其形成第二电极217的困难度。 For purposes of sputtering technology has increased the difficulty of forming a second electrode 217. 当形成第二电极217的要求还包含电极的高度与第一电极215需同高、第二电极217必须保留与第一电极215及发光结构309的距离才不会造成电性短路以及保留后段裸片切割的空间等,要在深U型空间313中形成电极就更难了。 When required to form the second electrode 217 further comprises a first electrode and a height of 215 with high demand, we must keep the second electrode 217 from the first electrode 215 and the light emitting structure 309 will not cause an electrical short circuit and a rear section reserved die cutting space, an electrode is to be formed deep in the U-shaped space 313 even harder. 第三部分为第一电极215与发光结构309之间的热应力。 The third part is a thermal stress between the first electrode 215 and the light emitting structure 309. 电极的材料主要为金属材料,而发光结构则为III-V族化合物。 The main material of the electrode material is a metal, the light emitting structure compared with Group III-V compound. 一般金属材料的热膨胀系数(Thermal expansion coefficient ;TEC)比GaN的热膨胀系数高。 Usually the thermal expansion coefficient of the metal material (Thermal expansion coefficient; TEC) higher than the thermal expansion coefficient of GaN. 请參考图3b,当进行雷射剥离技术(Laser Lift Off ;LL0)移除外延基板101时,其温度将到达400度左右,容易使得第一电极215与发光结构309之间产生热应カ,因而造成第一电极215的变形及发光结构309的碎裂。 Please refer to Figure 3b, when performing the laser lift-off technique (Laser Lift Off; LL0) epitaxial substrate 101 is removed, it will reach a temperature of about 400 degrees, it is easy to generate heat between the first electrode 215 and the light emitting structure 309 should ka, resulting in deformation and cracking of the light emitting structure 309 of the first electrode 215.

[0006] 因此,本发明提供一种倒装芯片式半导体光电元件的封装结构,用以改善上述不足。 [0006] Accordingly, the present invention provides a flip-chip package structure of the semiconductor of the photovoltaic element, to improve the above deficiencies.

发明内容 SUMMARY

[0007] 鉴于所述的背景技术中的不足,为了符合市场的需求,本发明要解决的技术问题是提供一种倒装芯片式半导体光电元件的封装结构及其制造方法,其エ艺简单、发光率高、散热性好。 [0007] In view of the deficiencies of the background art, in order to meet the market demand, the present invention is to solve the technical problem package structure and method of manufacturing to provide a flip chip type semiconductor optoelectronic device is simple Ester arts, high light, good heat dissipation.

[0008] 为解决上述技术问题,本发明提供一种倒装芯片式半导体光电元件结构,包含:一封装基板,具有一第一表面以及相对于第一表面的第二表面,其中该第一表面具有一第一焊垫及一第二焊垫,一第一凸块位于该第一焊垫上,一第二凸块位于该第二焊垫上;ー半导体发光结构,具有一第一表面以及相对于第一表面的第二表面,其中该第一表面包含一n型电极与一P型电极,该n型电极与该第一凸块电性连接,该p型电极与该第二凸块电性连接;一绝缘层,位于该n型电极与该p型电极之间,电性隔离该n型电极与该p型电极;以及一透明胶材,位于该封装基板的第一表面与该半导体发光结构的第一表面之间,包覆该第ー焊垫、该第二焊垫、该第一凸块以及该第二凸块。 [0008] To solve the above problems, the present invention provides a flip chip type semiconductor optoelectronic device structure, comprising: a package substrate having a first surface and a second surface opposite the first surface, wherein the first surface having a first pad and a second pad, a first protrusion located at the first bonding pad, a second protrusion located at the second bonding pad; ー semiconductor light emitting structure having a first surface and a relative the second surface of the first surface, wherein the surface comprises a first n-type electrode and a P-type electrode, the n-type first electrode and the bump is electrically connected to the p-type electrode and the second bump is electrically connection; an insulating layer between the n-type electrode and the p-type electrode, electrically isolated from the n-type electrode and the p-type electrode; and a transparent adhesive, the first surface of the package substrate and the semiconductor light emitting between the first surface of the structure, the second cladding ー pad, the second pad, the first bump and the second bump.

[0009] 为解决上述另ー技术问题,本发明提供一种倒装芯片式半导体光电元件的制造方法,该方法为:提供一外延基板;形成ー牺牲层于ー外延基板上;形成一半导体发光结构于所述牺牲层上,该半导体发光结构具有一第一表面以及相对于第一表面的第二表面,该牺牲层位于该半导体发光结构的第二表面;形成一n型电极与一p型电极于该半导体发光结构的第一表面上;反置该半导体发光结构于一封装基板上,该封装基板具有一第一表面以及相对于第一表面的第二表面,其中该第一表面具有一第一焊垫及一第二焊垫,该封装基板上还包含一第一凸块与一第二凸块,该第一凸块位于该第一焊垫上,该第二凸块位于该第二焊垫上,该n型电极与该第一凸块电性连接,该p型电极与该第二凸块电性连接;填充ー透明胶材于该封装基板的第一表面与半导体发光结 [0009] In order to solve another technical problem ー, the present invention provides the a flip-chip semiconductor manufacturing photovoltaic element, the method of: providing an epitaxial substrate; forming a sacrificial layer ー ー epitaxial substrate; forming a semiconductor light emitting structure on the sacrificial layer, the semiconductor light emitting structure having a first surface and a second surface opposite the first surface, the second surface of the sacrificial layer located on the light emitting semiconductor structure; forming a n-type electrode and a p-type a first electrode on the light emitting surface of the semiconductor structure; inverted the semiconductor light emitting structure on a package substrate, the package substrate having a first surface and a second surface opposite the first surface, wherein the first surface having a a first pad and second pad, the package substrate further comprising a first bump and a second bump, the first protrusion located at the first bonding pad, the second protrusion located at the second bonding pad, the n-type electrode connected electrically to the first bump, the p-type electrode connected electrically to the second bump; ー transparent filling adhesive on the first surface of the package substrate and the semiconductor light emitting junction 的第一表面之间,包覆该第一焊垫、该第二焊垫、该第一凸块以及该第二凸块;蚀刻所述牺牲层以剥离所述外延基板。 Between the first surface, covering the first pad, the second pad, the first bump and the second bump; etching the sacrificial layer to release the epitaxial substrate.

[0010] 本发明的有益技术效果在于:比较一般传统半导体光电水平兀件的发光率,本发明的半导体光电元件以倒装芯片技术封装后再剥离外延基板,其元件射出的光线受到基板及电极干扰少,因此其发光率高于一般传统半导体光电水平元件的发光率。 [0010] Advantageous effects of the present invention is characterized in: emission of more general level Wu conventional semiconductor optoelectronic device, a semiconductor optoelectronic device according to the present invention, the flip-chip packaging technology after peeling epitaxial substrate for light emitted by the element substrate and the electrode little interference, so it is generally higher than that of the conventional light-emitting semiconductor light emitting level of the photovoltaic element. 另外,半导体光电元件在散热性方面也比一般半导体光电元件的散热性佳。 Further, the optoelectronic device in the heat than the average in terms of good heat dissipation of the semiconductor of the photovoltaic element. 另外,本发明的半导体光电元件的エ艺方法较简単。 Further, a semiconductor arts Ester photovoltaic element according to the present invention is relatively simple radiolabeling. 附图说明 BRIEF DESCRIPTION

[0011] 图Ia及图lb,为传统打线接合技术与倒装芯片技术的封装结构比较图; [0011] FIG Ia and FIG lb, for the conventional wire bonding technology package comparing FIG flip chip technology;

[0012] 图2为现有技术的垂直元件结构图; [0012] FIG. 2 is a block diagram of a vertical element of the prior art;

[0013] 图3a至图3c为蚀刻、剥离外延基板及倒装芯片封装的简单示意图; [0013] Figures 3a to 3c is etched, and a simple diagram peeling epitaxial substrate of the flip chip package;

[0014] 图4为本发明的主要方法流程图; The main method of [0014] FIG. 4 is a flow chart of the invention;

[0015] 图5a至图5q为本发明的倒装芯片式半导体光电元件的各步骤形成示意图(图5a至图5e为本发明的第一种形成牺牲层方法的各步骤形成示意图); [0015] Figures 5a to step 5q respective flip-chip semiconductor optoelectronic device of the present invention for forming a schematic diagram (FIG. 5a to 5e of the present invention, the steps of a first method for forming the sacrificial layer is a schematic view);

[0016] 图6a至图6e为本发明的第二种形成牺牲层方法的各步骤形成示意图;以及 The steps of [0016] Figures 6a-6e second invention of the present method of forming a sacrificial layer for forming a schematic view; and

[0017] 图7a至图7e为本发明的第三种形成牺牲层方法的各步骤形成示意图。 [0017] Figures 7a-7e third step of the present invention, each of the sacrificial layer forming method of forming a schematic view.

[0018] 其中,附图标记说明如下: [0018] wherein reference numerals as follows:

[0019] 101外延基板 121柱体 [0019] The cartridge 101 of the epitaxial substrate 121

[0020] 103遮罩 123裸片 [0020] 103 123 die mask

[0021] 105n型电极 125半导体光电元件 [0021] 105n-type semiconductor electrode 125 of the photovoltaic element

[0022] 107p型电极 127凹槽 [0022] 107p-type electrode 127 recess

[0023] 109发光区域 201第一III族氮化物 [0023] 109 light-emitting region 201 of the first group III nitride

[0024] 111切割平台 203第III族氮化物 [0024] Cutting platform 111 203 Group III nitride

[0025] 113凸块 205第三III族氮化物 [0025] 113 third bumps 205 III nitride

[0026] 115封装基板 207欧姆接触层 [0026] The package substrate 115 in ohmic contact layer 207

[0027] 117焊垫 209绝缘层 [0027] The insulating layer 117 pad 209

[0028] 119孔洞 305电子阻挡层 [0028] 119 electron hole blocking layer 305

[0029] 211透明胶材 307p型导电层 [0029] 211 transparent adhesive type conductive layer 307p

[0030] 213保护层 309发光结构 [0030] The light emitting structure 213 protective layer 309

[0031] 215第一电极 311金属线 [0031] The metal wire 215 of the first electrode 311

[0032] 217第二电极 313U型空间 [0032] The second electrode 217 313U type space

[0033] 301n型导电层 303发光层具体实施方式 [0033] 301n-type conductive layer 303 light-emitting layer DETAILED DESCRIPTION

[0034] 本发明在此所探讨的方向为ー种倒装芯片式半导体光电元件的封装结构及其制造方法。 [0034] The present invention is discussed herein in the direction of the package structure and a manufacturing method for the flip-chip semiconductor photovoltaic element ー species. 为了能彻底地了解本发明,将在下列的描述中提出详尽的步骤及其组成。 In order to thoroughly understand the present invention, the step will be set forth in the following detailed description and its composition. 显然地,本发明的实施并未限定于半导体光电エ艺的技术人员所熟知的特殊细节。 Obviously, the embodiment of the present invention is not limited to the specific details of semiconductor optoelectronic Ester arts skill in the art. 另ー方面,众所周知的组成或步骤并未描述于细节中,以避免造成本发明不必要的限制。 Another aspect ー known composition or are not described in detail, to avoid unnecessarily limiting the present invention. 本发明的较佳实施例会详细描述如下,然而除了这些详细描述之外,本发明还可以广泛地被实施在其他的实施例中,且本发明的范围不受限定,其以权利要求书界定的范围为准。 Regular preferred embodiment of the present invention are described in detail below, however, in addition to the detailed description, the present invention can be widely implemented in other embodiments, and the scope of the present invention is not limited to the book which is defined in the claims range prevail.

[0035] 本发明提供一种倒装芯片式半导体光电元件的封装结构,包含一封装基板,具有一第一表面以及相对于第一表面的第二表面。 [0035] The present invention provides a flip chip type semiconductor package photovoltaic element, comprising a packaging substrate having a first surface and a second surface with respect to the first surface. 其中所述第一表面具有一第一焊垫及一第二焊垫。 Wherein said first surface having a first pad and a second pad. 一第一凸块位于所述第一焊垫上,一第二凸块位于所述第二焊垫上。 A first bump in the first bonding pad, a second protrusion located at the second bonding pad. 一半导体发光结构,具有一第一表面以及相对于第一表面的第二表面。 A light emitting structure having a first surface and a second surface with respect to the first surface. 其中所述第一表面包含一n型电极与ーP型电极。 Wherein said first surface comprises an n-type electrode and the P-type electrode ー. 所述n型电极与所述第一凸块电性连接。 The n-type electrode and the first bump is electrically connected. 所述p型电极与所述第二凸块电性连接。 The p-type electrode and the second bump is electrically connected. 一绝缘层,位于所述n型电极与所述p型电极之间,电性隔离所述n型电极与所述P型电极。 An insulating layer positioned between the n-type electrode and the p-type electrode, electrically isolated from the n-type electrode and the P-type electrode. 以及,一透明胶材,位于所述封装基板的第一表面与所述半导体发光结构的第一表面之间。 And, a transparent plastic material in the first surface of the package substrate and the first surface of the semiconductor between the light emitting structure. 所述透明胶材同时包覆所述第一焊垫、所述第二焊垫、所述第一凸块以及所述第二凸块。 The transparent adhesive simultaneously covers the first pad, the second pad, the first bump and the second bump.

[0036] 上述封装基板可为印刷电路板(Printed Circuit Board ;PCB)、BT树脂印刷电路板(Bismaleimide Triazine resin Printed Circuit Board ;BT PCB)、高热系数招基板(Metal Core Printed Circuit Board ;MCPCB)、软性印刷电路板(Flexible PrintedCircuit Board ;Flexible PCB)、陶瓷基板(Ceramic)、娃基板。 [0036] The package substrate may be a printed circuit board (Printed Circuit Board; PCB), BT resin, a printed circuit board (Bismaleimide Triazine resin Printed Circuit Board; BT PCB), high thermal coefficient move the substrate (Metal Core Printed Circuit Board; MCPCB), The flexible printed circuit board (Flexible PrintedCircuit board; Flexible PCB), a ceramic substrate (ceramic), baby substrate.

[0037] 上述的凸块可为钯锡合金(Pd/Tin)。 [0037] The bump may be a tin alloy, a palladium (Pd / Tin).

[0038] 上述的n型电极可为钛/铝/钛/金合金(Ti/Al/Ti/Au)、铬金合金(Cr/Au)或是铅金合金(Pd/Au)。 [0038] The n-type electrode may be titanium / aluminum / titanium / gold alloy (Ti / Al / Ti / Au), chromium gold alloy (Cr / Au) or lead alloy, gold (Pd / Au).

[0039] 上述的p型电极可为镍金合金(Ni/Au)、钼金合金(Pt/Au)、铬金合金(Cr/Au)、鹤(W)或钯(Pd)。 [0039] The p-type electrode may be a nickel alloy, gold (Ni / Au), molybdenum alloy, gold (Pt / Au), chromium gold alloy (Cr / Au), Hok (W) or palladium (Pd).

[0040] 上述的绝缘层可为ニ氧化硅(SiO2)、环氧树脂(Epoxy)、氮化硅(Si3N4)、ニ氧化钛(Ti02)或是氮化铝(AlN)。 [0040] The insulating layer may be a Ni silicon oxide (SiO2), epoxy resin (Epoxy), silicon nitride (Si3N4), titanium oxide Ni (Titania and) or aluminum nitride (AlN).

[0041] 上述的透明胶材可为ニ氧化硅(SiO2)、环氧树脂(Epoxy)、或是氮化硅(Si3N4)。 [0041] The adhesive material may be a transparent Ni silicon oxide (SiO2), epoxy resin (Epoxy), or silicon nitride (Si3N4).

[0042] 上述的保护层可为ニ氧化硅(SiO2)。 [0042] The protective layer may be silicon oxide (SiO2) is Ni.

[0043]另外,本发明也提供一种倒装芯片式半导体光电元件结构的制造方法,包含提供一外延基板。 [0043] Further, the present invention also provides a method of manufacturing a flip chip type semiconductor optoelectronic device structure, comprising providing an epitaxial substrate. 形成一牺牲层于所述外延基板上。 Forming a sacrificial layer on said epitaxial substrate. 形成一半导体发光结构于所述牺牲层上。 Forming a semiconductor light emitting structure on the sacrificial layer. 所述半导体发光结构具有一第一表面以及相对于第一表面的第二表面。 The semiconductor light emitting structure having a first surface and a second surface with respect to the first surface. 所述牺牲层位于所述半导体发光结构的第二表面。 The sacrificial layer located on the second surface of the semiconductor light emitting structure. 形成一n型电极与一p型电极于所述半导体发光结构的第一表面上。 Formed on the light emitting surface of the semiconductor structure of a first n-type electrode and a p-type electrode. 倒装所述半导体发光结构于一封装基板上。 The flip-chip semiconductor light emitting structure on a package substrate. 所述封装基板具有一第一表面以及相对于第一表面的第二表面。 The package substrate having a first surface and a second surface with respect to the first surface. 其中所述第一表面具有一第一焊垫及一第二焊垫。 Wherein said first surface having a first pad and a second pad. 一第一凸块位于所述第一焊垫上,一第二凸块位于所述第二焊垫上。 A first bump in the first bonding pad, a second protrusion located at the second bonding pad. 所述基板上包含一第一凸块与一第二凸块。 The protrusion comprises a first and a second bump on a substrate. 所述n型电极与所述第一凸块电性连接,所述p型电极与所述第二凸块电性连接。 The n-type electrode and the first bump is electrically connected to the p-type electrode and the second bump is electrically connected. 填充一透明胶材于所述封装基板的第一表面与半导体发光结构的第一表面之间。 Between the first surface of the first surface of the semiconductor light emitting structure is filled with a transparent adhesive to the package substrate. 所述透明胶材同时包覆所述第一焊垫、所述第二焊垫、所述第一凸块以及所述第二凸块。 The transparent adhesive simultaneously covers the first pad, the second pad, the first bump and the second bump. 蚀刻所述牺牲层以剥离所述外延基板。 Etching the sacrificial layer to release the epitaxial substrate.

[0044] 上述形成所述牺牲层于所述外延基板上的步骤,包含形成一第一III族氮化物于所述外延基板上。 [0044] The step of forming said epitaxial layer on the sacrificial substrate, comprising a first group III nitride formed on the epitaxial substrate. 接下来形成一图案化的遮罩于所述第一III族氮化物上。 Next, a patterned mask is formed on the first group III nitride. 再蚀刻所述第一III族氮化物,以及移除所述图案化的遮罩。 Then etching the first group III nitride, and removing the patterned mask.

[0045] 另外,形成所述牺牲层于所述外延基板上的步骤,包含形成一第一III族氮化物于所述外延基板上。 [0045] Further, the step of forming an epitaxial layer on the sacrificial substrate, comprising a first group III nitride formed on the epitaxial substrate. 形成一图案化的遮罩于所述第一III族氮化物。 Forming a patterned mask on the first group III nitride. 形成一第二III族氮化物于所述图案化的遮罩上,以及移除所述图案化的遮罩形成多个孔洞。 Forming a second group III nitride plurality of holes formed on the patterned mask, and removing the patterned mask.

[0046] 另外,形成所述牺牲层于该外延基板上的步骤,包含形成ー遮罩于所述外延基板上。 [0046] Further, the step of forming the epitaxial layer on the sacrificial substrate, comprising ー mask is formed on said epitaxial substrate. 退火形成一图案化的遮罩。 Annealed to form a patterned mask. 蚀刻所述外延基板,以及移除所述图案化的遮罩。 Epitaxial substrate, and removing said mask of said patterned etch.

[0047] 上述的蚀刻可为湿蚀刻、干蚀刻或是电感式等离子体蚀刻系统(Inductivelycoupled plasma etcher ;ICP)。 [0047] The etching may be wet etching, dry etching or inductive plasma etch system (Inductivelycoupled plasma etcher; ICP).

[0048] 上述的方法还包含形成一绝缘层位于所述n型电极与所述P型电极之间,可増加半导体发光结构的结构硬度以及电性隔离所述n型电极与所述p型电极。 [0048] The method further comprises forming an insulating layer between the n-type electrode and the P-type electrode is located, to increase in structural rigidity and may be electrically isolated from the n-type semiconductor electrode and the light emitting structure of the p-type electrode .

[0049] 上述的方法还包含先形成一保护层于所述半导体发光结构外围,再蚀刻所述牺牲层以剥离所述外延基板。 [0049] The method further comprises forming a protective layer to the release layer to the semiconductor epitaxial substrate of the light emitting structure to a peripheral, and then etching the sacrifice.

[0050] 上述的外延基板可为蓝宝石(Al2O3)基板、碳化硅(SiC)基板、铝酸锂基板(AlLiO2)、镓酸锂基板(LiGaO2)、硅(Si)基板、氮化镓(GaN)基板,氧化锌(ZnO)基板、氧化铝锌基板(AlZnO)、神化镓(GaAs)基板、磷化镓(GaP)基板、锑化镓基板(GaSb)、磷化铟(InP)基板、神化铟(InAs)基板或硒化锌(ZnSe)基板。 [0050] The epitaxial substrate may be a sapphire (Al2O3) substrate, a silicon carbide (SiC) substrate, a lithium aluminum substrate (AlLiO2), lithium gallate substrate (LiGaO2), silicon (Si) substrate, a gallium nitride (GaN) a substrate, a zinc oxide (ZnO) substrate, a zinc-aluminum substrate (AlZnO), deification gallium (GaAs) substrate, a gallium phosphide (GaP) substrate, the substrate gallium antimonide (GaSb), indium phosphide (InP) substrate, indium deification (InAs) substrate or a zinc selenide (ZnSe) substrate.

[0051] 请參考图4,其为主要形成本发明的方法流程图。 [0051] Please refer to FIG 4, a flowchart of the main process of the present invention is formed. 第一步骤,本发明先形成ー牺牲层,且所述牺牲层可利用三种方法形成。 A first step of the present invention is first formed ー sacrificial layer and the sacrificial layer may be formed using the three methods. 第一种方法包含形成一第一III族氮化物于所述外延基板上。 The first method comprises forming a first group III nitride on said epitaxial substrate. 接下来形成一图案化的遮罩于所述第一III族氮化物上。 Next, a patterned mask is formed on the first group III nitride. 再蚀刻所述第一III族氮化物,以及移除所述图案化的遮罩。 Then etching the first group III nitride, and removing the patterned mask. 第二种方法包含先形成一第一III族氮化物于所述外延基板上。 The second method comprises first forming a first group III nitride on said epitaxial substrate. 接下来形成一图案化的遮罩于所述第一III族氮化物。 Next, a patterned mask is formed on the first group III nitride. 再形成一第二III族氮化物于所述图案化的遮罩上,以及移除所述图案化的遮罩形成多个孔洞。 Then forming a second group III nitride plurality of holes formed on the patterned mask, and removing the patterned mask. 第三种方法包含先形成ー遮罩于所述外延基板上。 A third method comprises first forming a mask on the epitaxial ー substrate. 再以退火方式形成一图案化的遮罩。 Then annealing is formed a patterned mask. 接下来蚀刻所述外延基板,以及最后移除所述图案化的遮罩。 Next, etching the epitaxial substrate, and finally removing the patterned mask. 形成牺牲层是ー种较简易的方式在的后的エ艺以去除所述外延基板,而不需要利用雷射。 Forming a sacrificial layer is ー species in a relatively simple manner after Ester arts to remove the epitaxial substrate, without using a laser.

[0052] 第二步骤,形成一半导体发光结构于上述牺牲层上。 [0052] The second step of forming a semiconductor light emitting structure on the sacrificial layer. 可利用有机金属气相沉积法(Metal Organic Chemical Vapor Deposition ;MOCVD)或是分子束外延(Molecular BeamEpitaxy ;MBE)等技木,将半导体发光结构沉积于所述牺牲层上。 Can be used metal organic chemical vapor deposition method (Metal Organic Chemical Vapor Deposition; MOCVD) or molecular beam epitaxy (Molecular BeamEpitaxy; MBE) technique and the like of wood, a semiconductor light emitting structure deposited on the sacrificial layer. 所述半导体发光结构可包含n型导电层、发光层、电子阻挡层以及p型导电层。 The semiconductor light emitting structure may include n-type conductive layer, a light emitting layer, an electron blocking layer and a p-type conductive layer. 另外,可在所述p型导电层上再形成一层欧姆接触层,使得电流-电压特性曲线呈现线性,増加元件的稳定性。 Further, the ohmic contact layer may be further formed on the layer of p-type conductive layer, so that the current - voltage characteristic curve exhibits linearity, to increase in stability of the device.

[0053] 第三步骤,蚀刻上述半导体发光结构,形成ー发光区域、切割平台及暴露出n型导电层。 [0053] The third step of etching the semiconductor light emitting structure, the light emitting region is formed ー, cutting platform and exposes the n-type conductive layer. 个别形成n型电极于n型导电层上,p型电极于欧姆接触层上,以达到电性连接。 Individual n-type electrode is formed on the n-type conductive layer, P-type electrode on the ohmic contact layer, in order to achieve electrical connection. 此夕卜,提供一绝缘层形成于n型电极与p型电极之间,不但可支撑半导体发光结构以及增加结构的硬度,也可以让n型电极与p型电极减少互相的干扰。 Bu this evening, there is provided an insulating layer is formed between the n-type electrode and the p-type electrode structure not only supports the semiconductor light emitting structure and the increase in hardness, but also allows the n-type electrode and the p-type electrode to reduce mutual interference.

[0054] 第四步骤,反置上述半导体发光结构于一封装基板上。 [0054] a fourth step, the semiconductor light emitting inverted structure on a package substrate. 先于上述半导体发光结构的n型电极与p型电极上各形成一凸块。 Prior to the n-type electrode and the p-type electrode of each of the semiconductor light emitting structure is formed of a bump. 利用倒装芯片技木,将所述凸块与一封装基板的焊垫电性连接,可避免电极遮蔽发光区域而影响发光率。 Using flip-chip technology of wood, the bump pads connected to a package substrate electrically, the shield electrode can be avoided and the light emitting region of Luminescence.

[0055] 第五步骤,蚀刻上述牺牲层以剥离上述外延基板。 [0055] a fifth step of etching the sacrificial layer to peeling the epitaxial substrate. 在进行蚀刻之前,需保护元件不受蚀刻液的伤害而导致受损。 Before etching, for an etching solution of the protective element from damage caused by injury. 故,提供一透明胶材填充于所述半导体发光结构与所述封装基板之间,包覆所述凸块与焊垫以保持电性连接。 Therefore, there is provided a transparent adhesive is filled between the semiconductor light emitting structure and the encapsulation substrate, covering the bump and the pad to maintain the electrical connection. 此外,用一保护层包覆于半导体发光结构及封装基板不受蚀刻液影响。 Further, with a protective layer to the etching solution is not coated on the light emitting semiconductor structure and the package substrate. 然后将适当选择比的蚀刻液经由牺牲层的孔洞破坏牺牲层,达到剥离所述外延基板。 Then suitably selected etchant than the destruction of the sacrificial layer through the holes of the sacrificial layer, the epitaxial substrate reaches the release. 最后,去除所述的保护层。 Finally, the removal of the protective layer.

[0056] 上述的本发明方法流程图其实施内容,将搭配图示与各步骤的结构示意图,详细介绍本发明的结构与各步骤的形成方式。 [0056] The present invention is a method flow chart showing the contents of embodiment, with a schematic structural diagram illustrating the respective steps in detail and the steps of forming structure embodiment of the present invention.

[0057] 首先形成ー牺牲层于ー外延基板上。 [0057] First sacrificial layer ー ー formed on an epitaxial substrate. 本发明提出三种形成所述牺牲层的方法。 The present invention proposes a method of forming three kinds of the sacrificial layer. 第ー种形成牺牲层的方法,请參考图5a至图5e。 The first sacrificial layer ー seed forming method, refer to Figures 5a to 5e. 依图5a所示,形成一第一III族氮化物201于所述外延基板101上。 According to FIG. 5a, forming a first group III nitride on the epitaxial substrate 201 to 101. 如图5b所示,再形成一图案化的遮罩103于所述第一III族氮化物201上。 5b, then forming a patterned mask 103 in the first group III nitride on the object 201. 如图5c所示,接下来蚀刻所述第一III族氮化物201。 As shown in FIG 5c, the next etching the first group III nitride 201. 如图5d所示,从所述第一III族氮化物201上移除所述图案化的遮罩103形成一牺牲层,所述牺牲层包含多个凹槽127及多个柱体121。 As shown in FIG 5D, the patterned mask is removed from said first group III nitride 201,103 form a sacrificial layer, the sacrificial layer 127 and the plurality of pillars comprises a plurality of recesses 121. 最后,由图5e所示,形成一第二III族氮化物203当作缓冲层,位于所述牺牲层上。 Finally, a shown in FIG. 5E, forming a second group III nitride as the buffer layer 203, located on the sacrificial layer. 关于本第一种形成牺牲层的步骤其详细的内容与形成方式,可以參阅先进开发光电股份有限公司的专利申请提案,中国台湾专利申请号097107609,专利名称为三族氮化合物半导体光电元件的制造方法及其结构。 About this first step of forming a sacrificial layer formed detailed contents manner, see Advanced Optoelectronic Co. Patent Application proposal, China Taiwan Patent Application No. 097107609, entitled Pat group III nitrogen compound semiconductor photovoltaic element manufacturing method and structure.

[0058] 另外,另ー种形成牺牲层的方法,请參考图6a至图6e。 [0058] Further, another ー method for forming the sacrificial layer, refer to Figures 6a to 6e. 如图6a所示,首先形成一第一III族氮化物201于所述外延基板101上。 As shown in Figure 6a, the first formed a first group III nitride on the epitaxial substrate 201 to 101. 如图6b所示,接下来形成一图案化的遮罩103于所述第一III族氮化物201上。 6b, next forming a patterned mask 103 in the first group III nitride on the object 201. 如图6c所示,再形成一第二III族氮化物203于所述图案化的遮罩103上。 As shown in FIG 6c, 203 is formed on the mask 103 and then a second group III nitride on said patterned. 如图6d所示,移除所述图案化的遮罩103形成多个孔洞119,使得所述第二III族氮化物203变成ー牺牲层。 Removing the patterned mask shown in FIG. 6d 103 are formed a plurality of holes 119, such that the second group III nitride layer 203 into the sacrificial ー. 最后,由图6e所示,形成一第三III族氮化物205当作缓冲层,位于所述牺牲层上。 Finally, a shown in FIG. 6E, forming a third group III nitride as the buffer layer 205, located on the sacrificial layer. 关于本第二种形成牺牲层的步骤其详细的内容与形成方式,可以參阅先进开发光电股份有限公司的专利申请提案,中国台湾专利申请号097115512,专利名称为三族氮化合物半导体光电元件的制造方法及其结构。 This step is formed on the second sacrificial layer is formed and the detailed contents of the way, can be found in Patent Application Advanced Optoelectronic Corp. proposal, China Taiwan Patent Application No. 097115512, entitled Pat group III nitrogen compound semiconductor photovoltaic element manufacturing method and structure.

[0059] 另外,又ー种形成牺牲层的方法,请參考图7a至图7e。 [0059] Further, the sacrificial layer and ー forming method, please refer to FIGS. 7a to 7e. 如图7a所示,最先形成一第一电极215于所述外延基板101上。 As shown in FIG 7a, the first electrode 215 is formed on a first substrate 101 of the upper epitaxial. 如图7b所不,将所述第一电极215退火形成ー图案化的遮罩103。 Figure 7b is not, the first electrode 215 is formed ー annealing the patterned mask 103. 如图7c所示,再蚀刻所述外延基板101,形成ー牺牲层。 As shown in FIG 7C, and then etching the epitaxial substrate 101, the sacrificial layer is formed ー. 所述牺牲层包含多个凹槽127及多个柱体121。 The sacrificial layer 127 comprises a plurality of grooves 121 and a plurality of pillars. 如图7d所示,移除所述图案化的遮罩103。 Shown in Figure 7d, removing the mask 103 is patterned. 最后,由图7e所示,形成一III族氮化物201当作缓冲层,位于所述牺牲层上。 Finally, a shown in FIG. 7E, forming a group III nitride as the buffer layer 201, located on the sacrificial layer. 关于本第三种形成牺牲层的步骤其详细的内容与形成方式,可以參阅先进开发光电股份有限公司的专利申请提案,中国台湾专利申请号097117099,专利名称为分离半导体及其基板的方法。 This third step of forming a sacrificial layer on the detailed contents of the way formed, can be found in Patent Application Advanced Optoelectronic Corp. proposal, No. 097117099, and entitled Method of separating the semiconductor substrate and China Taiwan patent application.

[0060] 后续的步骤说明,将以第一种形成牺牲层的方法为例进行详细叙述。 [0060] The subsequent steps are described, it will be the first method for forming the sacrificial layer is described in detail as an example.

[0061] 接下来,如图5f所示,掺杂四族的原子以形成n型导电层301在第二III族氮化物203上。 [0061] Next, as shown in FIG 5f, group IV dopant atoms to form an n-type conductive layer 301 on the second group III nitride 203. 在本实施例中的掺杂子为硅原子(Si),而硅的先驱物在有机金属化学气相沉积机台中可以使用硅甲烷(SiH4)或是硅こ烷(Si2H6)。 Doped sub-embodiment in the present embodiment is a silicon atom (Si), and silicon precursor may be used monosilane (SiH4) in a metal organic chemical vapor deposition machine frame or silicone ko alkoxy (Si2H6). n型导电层301的形成方式依序由高浓度參杂硅原子(Si)的氮化镓层(GaN)或是氮化铝镓层(AlGaN)至低浓度參杂硅原子(Si)的氮化镓层或是氮化铝镓层(AlGaN)。 Embodiment is formed of n-type conductive layer 301 sequentially from the high concentration of nitrogen doped silicon atoms (Si), gallium nitride layer (GaN) or aluminum gallium nitride layer (AlGaN) doped to a low concentration of silicon atoms (Si), gallium layer or an aluminum gallium nitride layer (AlGaN). 高浓度參杂硅原子(Si)的氮化镓层(GaN)或是氮化铝镓层(AlGaN)可以提供n型电极之间较佳的导电效果。 High concentration of doped silicon atoms (Si), gallium nitride layer (GaN) or aluminum gallium nitride layer (AlGaN) may be provided between the effect of the preferred electrically conductive n-type electrode. 、[0062] 接着是形成一发光层303在n型导电层301上。 , [0062] Next is formed on a n-type conductive layer 301 in the light emitting layer 303. 其中发光层303可以是单异质结构、双异质结构、单量子阱层或是多重量子阱层结构。 Wherein the light emitting layer 303 may be a single heterostructure, double heterostructure, single quantum well layer or a multi-quantum well layer structure. 目前多采用多重量子阱层结构,也就是多重量子阱层/阻障层的结构。 The current use of multi-quantum well layer structure, the structure is a multiple quantum well layer / barrier layer. 量子阱层可以使用氮化铟镓(InGaN),而阻障层可以使用氮化铝镓(AlGaN)等的三元结构。 The quantum well layer may be indium gallium nitride (InGaN), and the barrier layer may be aluminum gallium nitride (AlGaN) ternary like structure. 另外,也可以采用四元结构,也就是使用氮化铝镓铟(AlxInyGa1^yN)同时作为量子阱层以及阻障层。 It is also possible quaternion structure, i.e. the use of aluminum gallium indium nitride (AlxInyGa1 ^ yN) at the same time as the quantum well layer and a barrier layer. 其中调整铝与铟的比例使得氮化铝镓铟晶格的能阶可以分别成为高能阶的阻障层与低能阶的量子阱层。 Wherein adjusting the ratio of aluminum to indium aluminum gallium indium nitride such lattice energy level may be high energy-order low energy barrier order quantum well layer, respectively. 发光层303可以掺杂n型或是P型的掺杂子(dopant),可以是同时掺杂n型与p型的掺杂子,也可以完全不掺杂。 The light emitting layer 303 may be doped n-type or P-type doped sub (Dopant), may be simultaneously doped n-type dopant and the p-type promoter, may be completely undoped. 并且,可以是量子阱层掺杂而阻障层不掺杂、量子阱层不掺杂而阻障层掺杂、量子阱层与阻障层都掺杂或是量子阱层与阻障层都不掺杂。 Further, the quantum well layer may be doped and undoped barrier layer, an undoped quantum well layer and the barrier layer is doped quantum well layers and barrier layers are doped quantum well layer or layers and the barrier not doping. 此外,也可以在量子阱层的部份区域进行高浓度的掺杂(delta doping)。 Further, a high concentration may be doped (delta doping) in the region of the quantum well layer of the part.

[0063] 之后,在发光层303上形成一p型导电的电子阻挡层305。 After the electronic [0063], a p-type conductivity is formed on the light emitting layer 303 barrier layer 305. p型导电的电子阻挡层305包括第一种III-V族半导体层以及第ニ种III-V族半导体层。 Layer 305 comprises a first group III-V semiconductor layer and the second Group III-V Ni species semiconductor layer of p-type conduction electron-blocking. 这两种III-V族半导体层的能隙不同,且具有周期性地重复沉积在上述发光层303上,前周期性地重复沉积动作可形成能障较高的电子阻挡层(能障高于主动发光层的能障),用以阻挡过多电子(e_)溢流发光层303。 These two different band gap III-V semiconductor layer, and having a periodically repeated deposited on the light emitting layer 303, the deposition is periodically repeated energy barrier may be formed prior to operation of the high electron blocking layer (energy barrier is higher than emitting active layer energy barrier), to block excess electrons (E_) light emitting layer 303 overflows. 所述第一种III-V族半导体层可为氮化铝铟镓(AlxInyGa1IyN)层,所述第ニ种III-V族半导体层可为氮化铝铟镓(AluInvGa1IvN)层。 The first Group III-V semiconductor layer may be an aluminum indium gallium nitride (AlxInyGa1IyN) layer, the second kind of Group III-V ni semiconductor layer may be an aluminum indium gallium nitride (AluInvGa1IvN) layer. 其中,0<x彡1,0彡y<l,x+y < 1,0 < u < 1,0 < V < I 以及u+v < I。 Where, 0 <x 1,0 San San y <l, x + y <1,0 <u <1,0 <V <I, and u + v <I. 当X = u 时,y デV。 When X = u when, y by Du V. 另外,所述III-V 族半导体层也可为氮化镓(GaN)、氮化铝(AlN)、氮化铟(InN)、氮化铝镓(AlGaN)、氮化铟镓(InGaN)或氮化铝铟(AlInN)。 Further, the group III-V semiconductor layer may be gallium nitride (GaN), aluminum nitride (AlN), indium nitride (of InN), aluminum gallium nitride (the AlGaN), indium gallium nitride (InGaN) or aluminum indium nitride (AlInN).

[0064] 最后,掺杂ニ族的原子以形成p型导电层307于电子阻挡层305上。 [0064] Finally, dopant atoms to form the group Ni conductive layer 307 on the p-type electron blocking layer 305. 在本实施例中是镁原子。 In the present embodiment, it is a magnesium atom. 而镁的先驱物在有机金属化学气相沉积机台中可以使用CP2Mg。 And magnesium precursor may be used CP2Mg metalorganic chemical vapor deposition in a machine frame. p型导电层307的形成方式依序由低浓度參杂镁原子(Mg)的氮化镓层(GaN)或是氮化铝镓层(AlGaN)至高浓度參杂镁原子(Mg)的氮化镓层或是氮化铝镓层(AlGaN)。 Forming a nitride layer 307 p-type conductive manner sequentially from the low-concentration doped magnesium atoms (Mg) layer of gallium nitride (GaN) or aluminum gallium nitride layer (AlGaN) doped to a high concentration of magnesium atoms (Mg) of gallium layer or an aluminum gallium nitride layer (AlGaN). 高浓度參杂镁原子(Mg)的氮化镓层(GaN)或是氮化铝镓层可以提供p型电极之间较佳的导电效果。 Doped high concentration of magnesium atoms (Mg) layer of gallium nitride (GaN) or aluminum gallium nitride layer may provide better conductivity between the p-type electrode effect.

[0065] 如图5g所不,接着形成ー欧姆接触层207位于发光结构309上方。 [0065] FIG 5g are not, then the light emitting structure 309 formed above the ohmic contact layer 207 ー. 一般以蒸镀,溅镀等物理气相沉积法形成欧姆接触层207于发光结构309上。 In general vapor deposition, sputtering, physical vapor deposition is formed on the ohmic contact layer 207 on the light emitting structure 309. 其材料可为镍/金(Ni/Au)、氧化铟锡(Indium Tin Oxide ;IT0)、氧化铟锋(Indium Zinc Oxide ;IZ0)、氧化铟鹤(Indium Tungsten Oxide ;IW0)、氧化铟嫁(Indium Gallium Oxide ;IG0)、钼/金(Pt/Au)、铬/ 金(Cr/Au)、镍/ 铬(Ni/Cr)或是镍/ 镁/ 镍/ 铬(Ni/Mg/Ni/Cr)。 The material may be nickel / gold (Ni / Au), indium tin oxide (Indium Tin Oxide; IT0), indium oxide Feng (Indium Zinc Oxide; IZ0), indium oxide crane (Indium Tungsten Oxide; IW0), indium oxide marry ( Indium Gallium Oxide; IG0), a molybdenum / gold (Pt / Au), chromium / gold (Cr / Au), nickel / chromium (Ni / Cr) or nickel / magnesium / nickel / chromium (Ni / Mg / Ni / Cr ).

[0066] 如图5h所示,在覆盖欧姆接触层207后,通过光致抗蚀剂自旋涂布机以离心カ将光致抗蚀剂全面涂布于欧姆接触层207的表面上方以形成光致抗蚀剂膜。 [0066] As shown, after covering the ohmic contact layer 207, the upper photoresist by a spin coater centrifuged ka the photoresist is applied to the overall surface of the ohmic contact layer 207 to form 5h The photoresist film. 再以光微影法(Photolithography)将光致抗蚀剂膜图案化而形成遮罩,使得预计蚀刻部份显露。 Then photolithographic method (Photolithography) The photoresist film is patterned to form a mask, etching is expected that the exposed portion. 再以湿式蚀刻、干式蚀刻或是电感式等离子体蚀刻系统(Inductively coupled plasma etcher ;I CP)进行mesa(台式)エ艺。 And then wet etching, dry etching or inductive plasma etch system (Inductively coupled plasma etcher; I CP) for Mesa (desktop) Ester arts. 所述mesaエ艺为蚀刻发光结构309,以形成ー发光区域109及切割平台111,同时暴露出n型导电层301。 Ester The mesa etching the light emitting structure 309 arts, to form a light-emitting region 109 and ー cutting platform 111 and the n-type conductive layer 301 is exposed. 最后再以雷射切割将圆片切割成裸片123,该图中的虚线箭头方向为切割方向。 Finally, the wafer is cut to a laser cutting die 123, the direction of a dotted arrow in the figure is the cutting direction.

[0067] 如图5i所示,形成一n型电极105于n型导电层301上,一p型电极107于欧姆接触层207上。 [0067] As shown in FIG. 5i, 105 formed on the n-type conductive layer 301, a p-type electrode 107 on the ohmic contact layer 207 on an n-type electrode. 上述n型电极105及p型电极107可利用溅镀、蒸镀等物理气相沉积的方法将金属沉积于上述n型导电层301以及欧姆接触层207上。 The n-type electrode 105 and the p-type electrode 107 may be by sputtering, vapor deposition, physical vapor deposition method of depositing metal on said n-type conductive layer 301 and the ohmic contact layer 207. 上述n型电极105可为钛/铝/钛/金(Ti/Al/Ti/Au)、铬金合金(Cr/Au)或是铅金合金(Pd/Au)。 The n-type electrode 105 may be a titanium / aluminum / titanium / gold (Ti / Al / Ti / Au), chromium gold alloy (Cr / Au) or lead alloy, gold (Pd / Au). p型电极107可为镍金合金(Ni/Au)、钼金合金(Pt/Au)、鹤(W)、铬金合金(Cr/Au)或钮(Pd)。 p-type electrode 107 may be a nickel-gold alloy (Ni / Au), molybdenum alloy, gold (Pt / Au), Hok (W), chromium gold alloy (Cr / Au) or button (Pd).

[0068] 如图5j所示,形成一绝缘层209位于n型电极105与p型电极107之间。 [0068] As shown in FIG. 5j, 107,209,105 is formed between p-type electrode and the n-type electrode an insulating layer. 所述绝缘层209可減少所述n型电极105与p型电极107之间的互相干扰,也可強化所述发光结构309,使之不易破碎。 The insulating layer 209 can reduce the mutual interference between the n-type electrode 107, 105 and the p-type electrode, the light emitting structure may be reinforced 309, so easily broken. 所述绝缘层可为ニ氧化娃(SiO2)、环氧树脂(Epoxy)、氮化娃(Si3N4)、ニ氧化钛(TiO2)或是氮化铝(AlN)。 The oxide insulating layer may be a Ni Wa (SiO2), epoxy resin (Epoxy), baby nitride (Si3N4), Ni oxide (TiO2) or aluminum nitride (AlN).

[0069] 如图5k及图51所示,以倒装芯片接合技术将ー个或多个裸片123电性连接于ー封装基板上115上。 [0069] As shown in FIG. 51 and FIG. 5k, flip-chip bonding technique ー one or more dies 123 are electrically connected to the package substrate 115 on ー. 先个别形成凸块113于n型电极105与p型电极107上,再将凸块113分别对应于封装基板上的焊垫117,以达到电性连接。 Individual first bumps 113 are formed on the n-type electrode 105 and the p-type electrode 107, then the bump pads 113 respectively correspond to the pads 117 on the package substrate, in order to achieve electrical connection. 倒装芯片接合的凸块113成分一般使用铅锡合金,其比例的选择取决于基板的种类及组装程序。 113 bump flip chip bonding component of pewter generally used in a proportion selected depends on the type of substrate and the assembly procedure. 最常被使用的比例为95%铅-5%锡。 Most commonly used ratio of 95% lead and 5% tin. 所述封装基板115可为印刷电路板(Printed Circuit Board ;PCB)、BT树脂印刷电路板(Bismaleimide Triazine resin Printed Circuit Board ;BT PCB)、高热系数招基板(Metal Core Printed Circuit Board ;MCPCB)、软性印刷电路板(Flexible PrintedCircuit Board !Flexible PCB)、陶瓷基板(Ceramic)、或娃基板。 The package substrate 115 may be a printed circuit board (Printed Circuit Board; PCB), BT resin, a printed circuit board (Bismaleimide Triazine resin Printed Circuit Board; BT PCB), high thermal coefficient move the substrate (Metal Core Printed Circuit Board; MCPCB), soft printed circuit board (Flexible PrintedCircuit board! Flexible PCB), a ceramic substrate (ceramic), baby, or the substrate. 关于所述娃基板封装的详细的内容及步骤,可參阅先进开发光电股份有限公司的专利申请提案,中国台湾专利号码1292962,专利名称为固态发光元件的封装结构及其制造方法。 And the step of detailed contents on the package substrate baby, see Advanced Optoelectronic Patent Application proposal Co., China Taiwan patent number 1,292,962, and entitled package structure and a method of manufacturing a solid-state light-emitting element.

[0070] 如图5m及图5n所示,在进行剥离外延基板101之前,必须先保护凸块113与封装基板115的电性连接以及整个发光元件不受化学溶液侵蚀导致损害。 Before [0070] As shown in FIG. 5N and 5m shown, the substrate 101 during the peeling epitaxial must protect the bumps 113 and the package substrate 115 is electrically connected to the light emitting element and the entire solution against chemical attack causing damage. 先以一透明材料覆盖凸块113与封装基板115,再以一保护层包覆整个发光元件,但不包含外延基板101以及第一III族氮化物层201。 A first transparent material to cover the bumps 113 and the package substrate 115, and then a protective layer to cover the entire light emitting element, but does not include an epitaxial substrate 101, and a first group III nitride layer 201. 所述的透明胶材可为ニ氧化硅(SiO2)、环氧树脂(Epoxy)、或是氮化硅(Si3N4)。 The transparent adhesive may be a Ni silicon oxide (SiO2), epoxy resin (Epoxy), or silicon nitride (Si3N4). 所述保护层213可为ニ氧化硅(SiO2)。 The protective layer 213 may be a Ni silicon oxide (SiO2).

[0071] 如图5o所示,元件保护完成后,将以湿式蚀刻剥离所述外延基板101。 [0071] As shown in FIG 5o, the protection element is completed, it will be peeled off by wet etching the epitaxial substrate 101. 通过化学溶液的选取与调配,将所述化学溶液注入第一III族氮化物层201。 By selecting the formulation of a chemical solution, the chemical solution is injected into a first group III nitride layer 201. 所述将使得第一III族氮化物层201与化学溶液产生化学反应,而导致第一III族氮化物层201的结构瓦解。 It will cause the first group III nitride layer 201 generates a chemical reaction with a chemical solution, resulting in the structure of a first group III nitride layer 201 collapse. 因此,在第一III族氮化物层201上的外延基板101立即被剥离。 Thus, the epitaxial substrate 101 on the first group III nitride layer 201 is peeled off immediately.

[0072] 最后,由图5p及图5q所不,除去兀件上的保护层213后,切割封装基板115 (图5p中的虚线箭头方向为切割方向),即形成多个半导体光电元件125。 [0072] Finally, FIG. 5p and 5q FIG do not, on the protective layer 213 is removed Wu, cut package substrate 115 (broken line arrow direction of FIG. 5p in a cutting direction), i.e., a plurality of semiconductor photovoltaic elements 125 are formed. 可利用湿式及干式两种方法去除所述的保护层213。 It can be used wet and dry two methods of removing the protective layer 213. 湿式法是利用有机溶液将保护材料溶解而达到去保护层的目的,所使用的有机溶剂如丙酮(Acetone)、甲基卩比咯烧酮(N-Methyl-Pyrolidinone ;NMP)、ニ甲基亚楓(Dimethyl Sulfoxide ;DMS0)、2_ (2_ 氨こ氧基)こ醇2_ (2_Aminoethoxyethanol)、こ醇胺(MonoEthanolAmine ;MEA)、以及こニ醇单丁醚(ButoxyDiGlycol ;BDG)等。 The wet method using an organic protective material solution to achieve dissolution of the protective layer, the organic solvent used such as acetone (Acetone-), Jie methyl pyrrole burning -one (N-Methyl-Pyrolidinone; NMP), ni methylsulfinyl Feng (Dimethyl Sulfoxide; DMS0), 2_ (2_ ammonia ko yloxy) ko alcohol 2_ (2_Aminoethoxyethanol), ko alkanolamine (MonoEthanolAmine; MEA), and ko ni glycol monobutyl ether (ButoxyDiGlycol; BDG) and the like. 另ー湿式方法则可以使用无机溶液如硫酸和双氧水的混和溶液(SPM),此方法エ艺成本较低。 Another ー wet method may be used mixed solution of an inorganic solution such as sulfuric acid and hydrogen peroxide (SPM), the method arts Ester lower cost. 干式去遮罩法则是使用氧气或其等离子体将光致抗蚀剂加以去除。 Dry rule is to mask using oxygen plasma or the photoresist to be removed. 去除保护层213后,以一般刀工切割封装基板115,形成多个半导体光电兀件125。 After removing the protective layer 213, a general knife cut package substrate 115, a plurality of semiconductor photoelectric Wu member 125.

[0073] 上述的方法步骤可依在不同条件下更换顺序,使得エ艺更能达到实际需求。 [0073] The above-described method steps to follow in order to replace under different conditions, so that the actual needs can be better achieved Ester arts.

[0074] 综合上述的说明,比较一般传统半导体光电水平元件的发光率,本发明的半导体光电元件以倒装芯片技术封装后再剥离外延基板,其元件射出的光线减少受到基板及电极干扰,因此其发光率高于一般传统半导体光电水平元件的发光率。 [0074] The above description is generally conventional semiconductor light-emitting rate comparing levels photovoltaic element, the photovoltaic element of the present invention, a semiconductor flip-chip technology package after peeling epitaxial substrate element emits light by the substrate and the electrode to reduce interference, so luminous emission higher than the general rate of a conventional semiconductor photoelectric element level. 另外,半导体光电元件在散热性方面也比一般半导体光电元件的散热性佳。 Further, the optoelectronic device in the heat than the average in terms of good heat dissipation of the semiconductor of the photovoltaic element. 另外,本发明的半导体光电元件的エ艺方法较简単。 Further, a semiconductor arts Ester photovoltaic element according to the present invention is relatively simple radiolabeling.

[0075] 显然地,依照上面实施例中的描述,本发明可能有许多的修正与差异。 [0075] Clearly, in the embodiment in accordance with the embodiment described above, the present invention may have many differences and correction. 因此需要在权利要求书的范围内加以理解,除了上述详细的描述外,本发明还可以广泛地在其他的实施例中施行。 Therefore it needs to be understood that within the scope of the appended claims, in addition to the foregoing detailed description, the present invention can be widely implemented in other embodiments. 上述仅为本发明的较佳实施例而已,并非用以限定本发明的申请专利范围;凡其它未脱离本发明所掲示的精神下所完成的等效改变或修饰,均应包含在本发明的权利要求书界定的范围内。 While the invention has the above-described preferred embodiments only, not intended to limit the scope of the present patent disclosure; where other alterations or modifications without departing from the equivalent of the present invention shown kei spirit completed, should be included in the present invention within the scope defined by the appended claims.

Claims (8)

  1. 1. 一种倒装芯片式半导体光电元件结构的制造方法,包含: 提供一外延基板; 形成ー牺牲层于该外延基板上,所述牺牲层包含多个凹槽及多个柱体; 形成一半导体发光结构于该牺牲层上,该半导体发光结构具有一第一表面以及相对于第一表面的第二表面,该牺牲层位于该半导体发光结构的第二表面,所述半导体发光结构没有填充所述多个凹槽; 形成一n型电极与一p型电极于该半导体发光结构的第一表面上; 反置该半导体发光结构于一封装基板上,该封装基板具有一第一表面以及相对于第一表面的第二表面,其中该第一表面具有一第一焊垫及一第二焊垫,该封装基板上还包含一第一凸块与一第二凸块,该第一凸块位于该第一焊垫上,该第二凸块位于该第二焊垫上,该n型电极与该第一凸块电性连接,该p型电极与该第二凸块电性连接; 填充一透明胶 CLAIMS 1. A method of manufacturing a flip chip type semiconductor optoelectronic device structure, comprising: providing an epitaxial substrate; forming a; ー sacrificial epitaxial layer on the substrate, the sacrificial layer comprises forming a plurality of grooves and a plurality of posts the semiconductor light emitting structure on the sacrificial layer, the semiconductor light emitting structure having a first surface and a second surface opposite the first surface, the second surface of the sacrificial layer located on the light emitting semiconductor structure, the semiconductor light emitting structure is not filled said plurality of grooves; forming an n-type electrode and a p-type electrode on the first surface of the semiconductor light emitting structure; inverted the semiconductor light emitting structure on a package substrate, the package substrate having a first surface and a relative the second surface of the first surface, wherein the first surface having a first pad and a second pad, the package substrate further comprising a first bump and a second bump, the first bump located the first bonding pad, the second protrusion located at the second bonding pad, the first n-type electrode and the bump is electrically connected to the p-type electrode and the second bump is electrically connected; filled a transparent glue 材于该封装基板的第一表面与半导体发光结构的第一表面之间,包覆该第一焊垫、该第二焊垫、该第一凸块以及该第二凸块; 蚀刻该牺牲层以剥离该外延基板。 Material between the first surface and the first surface of the semiconductor light emitting structure of the package substrate, covering the first pad, the second pad, the first bump and the second bump; etching the sacrificial layer, to release the epitaxial substrate.
  2. 2.如权利要求I所述的倒装芯片式半导体光电元件结构的制造方法,其中所述形成该牺牲层于该外延基板上的步骤,包含: 形成一第一三族氮化物于该外延基板上; 形成一图案化的遮罩于该第一三族氮化物上; 蚀刻该第一三族氮化物;以及移除该图案化的遮罩。 I 2. A method for producing the photovoltaic element flip-chip semiconductor structure as claimed in claim, wherein said step of forming the sacrificial layer on the epitaxial substrate, comprising: forming a first group III nitride on the epitaxial substrate on; forming a patterned mask on the first group III nitride; etching the first group III nitride; and removing the patterned mask.
  3. 3.如权利要求I所述的倒装芯片式半导体光电元件结构的制造方法,其中所述形成该牺牲层于该外延基板上的步骤,包含: 形成一第一三族氮化物于该外延基板上; 形成一图案化的遮罩于该第一三族氮化物; 形成一第二三族氮化物于该图案化的遮罩上;以及移除所述图案化的遮罩形成多个孔洞。 The manufacturing method of the I flip-chip semiconductor optoelectronic device structure as claimed in claim, wherein said step of forming the sacrificial layer on the epitaxial substrate, comprising: forming a first group III nitride on the epitaxial substrate on; forming a patterned mask on the first group-III nitride; a second group III nitride is formed on the patterned mask; and removing the patterned mask to form a plurality of holes.
  4. 4.如权利要求I所述的倒装芯片式半导体光电元件结构的制造方法,其中所述形成该牺牲层于该外延基板上的步骤,包含: 形成一遮罩于该外延基板上; 退火形成一图案化的遮罩; 蚀刻该外延基板;以及移除该图案化的遮罩。 The manufacturing method of the I flip-chip semiconductor structure according to claim photovoltaic element, wherein said step of the sacrificial layer is formed on the epitaxial substrate, comprising: forming a mask on the epitaxial substrate; forming annealing a patterned mask; etching the epitaxial substrate; and removing the patterned mask.
  5. 5.如权利要求I所述的倒装芯片式半导体光电元件结构的制造方法,其中所述的蚀刻为湿蚀刻、干蚀刻或是电感式等离子体蚀刻系统。 The manufacturing method of the I flip-chip semiconductor optoelectronic device structure as claimed in claim, wherein said etching is a wet etching, dry etching or plasma etching inductive system.
  6. 6.如权利要求I所述的倒装芯片式半导体光电元件结构的制造方法,其中所述的方法还包含形成一绝缘层位于该n型电极及该p型电极之间以增加半导体发光结构的结构硬度以及电性隔离该n型电极及该p型电极。 The production method I of the flip chip type semiconductor structure according to claim photovoltaic element, wherein said method further comprises forming an insulating layer on the n-type electrode and the p-type electrode between the semiconductor light emitting structure to increase the structural rigidity and electrically isolates the n-type electrode and the p-type electrode.
  7. 7.如权利要求I所述的倒装芯片式半导体光电元件结构的制造方法,其中所述的方法还包含先形成一保护层于该半导体发光结构外围,再蚀刻该牺牲层以剥离该外延基板。 The manufacturing method of the I flip-chip semiconductor structure according to claim photovoltaic element, wherein said method further comprises a protective layer is first formed in the periphery of the semiconductor light emitting structure, and then etching the sacrificial layer to release the epitaxial substrate .
  8. 8.如权利要求I所述的倒装芯片式半导体光电元件结构的制造方法,其中所述的蚀刻牺牲层剥离该外延基板为湿式蚀刻法。 I as claimed in claim 8. A method for manufacturing the flip-chip semiconductor optoelectronic device structure, wherein the etching sacrificial layer of the epitaxial substrate is peeled wet etching method.
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