CN101819996B - Semiconductor structure - Google Patents

Semiconductor structure Download PDF

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Publication number
CN101819996B
CN101819996B CN 201010151192 CN201010151192A CN101819996B CN 101819996 B CN101819996 B CN 101819996B CN 201010151192 CN201010151192 CN 201010151192 CN 201010151192 A CN201010151192 A CN 201010151192A CN 101819996 B CN101819996 B CN 101819996B
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layer
semiconductor
strain
bandgap
wide
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CN 201010151192
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Chinese (zh)
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CN101819996A (en )
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王敬
许军
郭磊
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清华大学
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391Gated diode structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides a semiconductor structure which comprises a substrate, a transition layer or an insulating layer formed on the substrate, a first strain wide bandgap semiconductor layer, a strain narrow bandgap semiconductor layer, a second strain wide bandgap semiconductor layer, a grid stacking layer formed on the second strain wide bandgap semiconductor layer, a source electrode and a drain electrode, wherein the first strain wide bandgap semiconductor layer, the strain narrow bandgap semiconductor layer and the second strain wide bandgap semiconductor layer are sequentially formed on the transition layer or the insulating layer; and the source electrode and the drain electrode are formed in the first strain wide bandgap semiconductor layer, the strain narrow bandgap semiconductor layer and the second strain wide bandgap semiconductor layer. The semiconductor structure not only can suppress the generation of two kinds of BTBT (Band-to-Band Tunneling) electric leakages, but also can generate a cavity potential well in the middle strain narrow bandgap semiconductor layer (such as a strain GE layer or a strain SiGe layer) so as to improve the mobility of carriers and the property of devices.

Description

半导体结构 The semiconductor structure

技术领域 FIELD

[0001] 本发明涉及半导体制造及设计领域,特别涉及一种半导体结构,更特别地涉及一种能够抑制MOS器件BTBT(BancKr0-Band Tunneling,带带隧穿)漏电的半导体结构。 [0001] The present invention relates to semiconductor design and manufacturing, and more particularly relates to a semiconductor structure, and more particularly to a MOS device capable of suppressing BTBT (BancKr0-Band Tunneling, band tunneling) of the semiconductor structure leakage.

背景技术 Background technique

[0002] 随着半导体制造工艺的不断进步,漏电流已经成为了非常关键而且不可忽视的问题。 [0002] With the progress of semiconductor manufacturing process, leakage current has become very critical and can not be ignored. 由于高迁移率的窄禁带半导体材料的禁带宽度比较小,例如Ge的禁带宽度约为0. 67ev, InSb的禁带宽度约为0. 18eV,其禁带宽度比Si材料的禁带宽度小的多。 Since the band gap of narrow bandgap semiconductor materials with high mobility is relatively small, such as Ge band gap of about 0. 67ev, InSb band gap of about 0. 18eV, band gap than the forbidden band of Si material much smaller width. 因此,随着Ge等高迁移率窄禁带半导体材料的使用,BTBT漏电的问题也变得越来越严重。 Thus, with the high mobility Ge narrow bandgap semiconductor material is used, BTBT leakage problem has become increasingly serious.

[0003] 现有技术存在的缺点是,随着半导体尺寸的不断减小,以及窄禁带半导体材料的使用,使得BTBT漏电变得越来越严重。 [0003] disadvantages of the prior art is that with the decreasing size of semiconductor, and a narrow bandgap semiconductor material is used, so that the drain BTBT getting worse.

发明内容 SUMMARY

[0004] 本发明的目的旨在至少解决上述技术缺陷之一,特别是解决BTBT漏电的问题。 [0004] The object of the present invention to solve at least one of the above technical defects, in particular the problem of leakage BTBT.

[0005] 为达到上述目的,本发明一方面提出了一种半导体结构,包括衬底,形成在所述衬底之上的过渡层或绝缘层,形成在所述过渡层或绝缘层之上的第一应变宽禁带半导体层, 形成在所述第一应变宽禁带半导体层之上的应变窄禁带半导体层,形成在所述应变窄禁带半导体层之上的第二应变宽禁带半导体层,形成在所述第二应变宽禁带半导体层之上的栅堆叠,和形成在所述第一应变宽禁带半导体层、应变窄禁带半导体层和第二应变宽禁带半导体层之中的源极和漏极。 [0005] To achieve the above object, an aspect of the present invention provides a semiconductor structure comprising a substrate, a buffer layer or an insulating layer over the substrate, the buffer layer formed over the insulating layer, or strain should first wide bandgap semiconductor layer formed on said first strained wide bandgap semiconductor layer of narrow bandgap semiconductor layer, is formed to be narrowed in the second strained over the wide-gap semiconductor layer with a bandgap a semiconductor layer formed over the strained second wide bandgap semiconductor layer, a gate stack formed on the first strained wide bandgap semiconductor layer, narrow bandgap semiconductor layer and the second wide bandgap semiconductor layer is strained among the source and drain. 该类半导体结构不仅能抑制两种BTBT漏电的产生,另外还能在中间的应变窄禁带半导体层,例如应变Ge层中产生空穴势阱,提高载流子的迁移率,改善器件性能。 Such a semiconductor structure can be suppressed not only produce two BTBT leakage, but also additionally in the middle of the narrow bandgap semiconductor layer, for example, holes are generated in the strained Ge layer a potential well, to improve the mobility of carriers and improve device performance.

[0006] 本发明另一方面还提出了一种半导体结构,包括衬底,形成在所述衬底之上的过渡层或绝缘层,形成在所述过渡层或绝缘层之上的第一应变宽禁带半导体层,形成在所述第一应变宽禁带半导体层之上的应变窄禁带半导体层,形成在所述应变窄禁带半导体层之上的栅堆叠,和形成在所述第一应变宽禁带半导体层和应变窄禁带半导体层之中的源极和漏极。 [0006] In another aspect of the present invention further provides a semiconductor structure comprising a substrate, a buffer layer or an insulating layer over the substrate, forming a first strain buffer layer on the insulating layer, or wide bandgap semiconductor layer formed over the first strained wide bandgap semiconductor layer of narrow bandgap semiconductor layer, forming the gate stack to be narrowed on the bandgap semiconductor layer and the second a strained wide bandgap semiconductor layer and the source and drain electrodes should be narrowed within the bandgap of the semiconductor layer. 该类半导体结构通过增加的第一应变宽禁带半导体层,例如应变Si层,能够有效抑制在漏端高偏压时源漏结处产生的BTBT漏电,从而减轻BTBT漏电的影响。 Such semiconductor structures by adding a first strained wide bandgap semiconductor layer, e.g. strained Si layer can be effectively suppressed BTBT source-drain junction leakage generated when a high bias drain terminal, thereby reducing influence of the leakage BTBT. 另外,通过在第一应变宽禁带半导体层之下的绝缘层能够更好的抑制该类BTBT漏电。 Further, it is possible to suppress such BTBT better leakage through the insulating layer under the first strained wide bandgap semiconductor layer.

[0007] 本发明附加的方面和优点将在下面的描述中部分给出,部分将从下面的描述中变得明显,或通过本发明的实践了解到。 [0007] The present additional aspects and advantages of the invention will be set forth in part in the description which follows, from the following description in part be apparent from, or learned by practice of the present invention.

附图说明 BRIEF DESCRIPTION

[0008] 本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解,需要说明的是,本发明的附图仅是示意性的,因此没有必要按比例绘制,其中:[0009] 图1为本发明实施例一的半导体结构示意图; [0008] The present invention described above and / or additional aspects and advantages of the drawings will be described embodiments become apparent and more readily appreciated embodiments, it is noted that the drawings of the present invention is illustrative only from the following, thus not necessarily drawn to scale, wherein: [0009] Figure 1 is a schematic structural diagram of the semiconductor of the embodiment of the invention;

[0010] 图2为本发明实施例二的半导体结构示意图; [0010] FIG semiconductor structure according to a second embodiment of a schematic diagram of the present invention;

[0011] 图3为本发明实施例三的半导体结构示意图; [0011] FIG. 3 of the semiconductor structure according to a third embodiment of a schematic diagram of the present invention;

[0012] 图4为本发明实施例的FinFET结构示意图。 [0012] FIG. 4 is a schematic structural embodiment of the FinFET embodiment of the present invention.

具体实施方式 detailed description

[0013] 下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。 [0013] Example embodiments of the present invention is described in detail below, exemplary embodiments of the embodiment shown in the accompanying drawings, wherein same or similar reference numerals designate the same or similar elements or elements having the same or similar functions. 下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。 By following with reference to the embodiments described are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0014] 下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。 [0014] The following disclosure provides many different embodiments or examples to achieve different structures of the present invention. 为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。 To simplify the disclosure of the present invention, be described hereinafter and the members of the specific examples provided. 当然,它们仅仅为示例,并且目的不在于限制本发明。 Of course, they are only illustrative, and are not intended to limit the present invention. 此外,本发明可以在不同例子中重复参考数字和/或字母。 Further, the present disclosure may repeat reference numerals and / or letters in the various examples. 这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。 This repetition is for the purpose of simplicity and clarity, and does not indicate a relationship between the embodiments and / or arrangements being discussed. 此外,本发明提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。 Further, the present invention provides various specific examples of materials and processes, but one of ordinary skill in the art that other processes can be applied to use and / or other materials. 另外,以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例,也可以包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征可能不是直接接触。 Further, the first characteristic configuration described below in the "on" a second feature may comprise first and second features are formed in direct contact embodiment may also include additional features may be formed between the first and second feature embodiments, so that the first and second features may not be in direct contact.

[0015] 在本发明中,对BTBT漏电进行了分析,目前BTBT漏电主要包括漏端高偏压时在源漏结处产生的BTBT漏电,和GIDL (栅极感应漏极漏电)漏电两类,其中,GIDL漏电是指在栅漏交叠处,当漏端处于高电位,栅极处于低电位时,产生的BTBT漏电。 [0015] In the present invention, the leakage BTBT analyzed, including leakage current BTBT BTBT leakage generated when the source and drain junction of the high drain bias, and the GIDL (gate induced drain leakage) leakage categories, wherein, the GIDL leakage refers to leakage BTBT overlapping the drain when the gate, when the drain terminal at a high potential, the gate is at a low potential, generated. 以下就以具体实施例的方式进行描述,以下实施例可至少抑制上述两类BTBT漏电中的一种,但需要说明的是以下实施例仅是实现本发明的优选方式,并不是说本发明仅能够通过以下实施例实现,本领域技术人员可对以下实施例中的部分特征做出等同的修改或替换,在不脱离本发明思想的范围内,这些等同的修改或替换均应包含在本发明的保护范围之内。 The following specific embodiments in the manner described embodiment, the following embodiment can suppress the leakage of at least one of these two categories BTBT, but should be noted that the following embodiments are merely preferred embodiment of the present invention is implemented, the present invention is not to say that only can be achieved by the following examples, some of the features of the embodiment make modifications or equivalent replacement skilled in the art may implement the following, without departing from the scope of the idea of ​​the present invention, such equivalent modifications or substitutions shall be included in the present invention, within the scope of protection.

[0016] 实施例一, [0016] Example I.

[0017] 该实施例通过在Ge、InSb等窄禁带半导体材料的下方增加一层宽禁带半导体层, 从而可抑制漏端高偏压时在源漏结处产生的BTBT漏电。 [0017] This embodiment by adding a layer of wide bandgap semiconductor layer under Ge, InSb and other narrow bandgap semiconductor materials, thereby suppressed leakage BTBT generated when the source and drain junction of the high drain bias. 需要说明的是,在本发明的本实施例及以下实施例中,所谓宽禁带半导体材料仅是相对于Ge、InSb等窄禁带半导体材料来说,例如Si,其自身的禁带宽度并不大,但相对于Ge来说,在本发明的各个实施例中Si可被称为宽禁带半导体材料。 Incidentally, in the following Examples and Examples in the present invention, a so-called wide bandgap semiconductor material with respect to only narrow bandgap semiconductor materials Ge, InSb, etc., for example Si, the band gap of its own and small, but with respect to Ge is, in various embodiments of the present invention, Si may be referred to as wide bandgap semiconductor material.

[0018] 如图1所示,为本发明实施例一的半导体结构示意图。 [0018] FIG. 1, a schematic structural diagram of a semiconductor of the present embodiment of the invention. 该半导体结构1000可包括衬底100,该衬底可为任何半导体衬底材料,包括但不限于硅、锗、锗化硅、SOI (绝缘体上硅)、碳化硅、砷化镓或者任何III/V族化合物半导体等衬底。 The semiconductor structure 1000 may include a substrate 100, the substrate can be any semiconductor substrate material, including but not limited to, silicon, germanium, silicon germanium, the SOI (silicon on insulator), silicon carbide, gallium arsenide, or any III / V group compound semiconductor substrate.

[0019] 该半导体结构1000还可包括形成在衬底100之上的过渡层或绝缘层200。 [0019] The semiconductor structure 1000 may also include a buffer layer 100 over the substrate or the insulating layer 200 is formed. 在本发明的一个实施例中,过渡层200可为驰豫SiGe虚拟衬底层,当然也可采用其他材料作为过渡层。 In one embodiment of the present invention, the transition layer 200 may be relaxed SiGe virtual substrate layer, of course, other materials may also be used as a buffer layer. 在本发明的另一个实施例中,绝缘层200可包括S^2等绝缘材料,从而能够更好地抑制源漏结处产生的BTBT漏电。 In another embodiment of the present invention, the insulating layer 200 may include an insulating material such as S ^ 2, and thus better able to suppress the source-drain junction leakage BTBT generated.

[0020] 该半导体结构1000还可包括形成在过渡层或绝缘层200之上的第一应变宽禁带半导体层400,和形成在该第一应变宽禁带半导体层400之上的应变窄禁带半导体层500。 First strained wide bandgap semiconductor layer [0020] 1000 may also include the semiconductor structure is formed on the buffer layer 400 or the insulating layer 200, formed on the first strained wide bandgap semiconductor layer 400 should be narrower forbidden band of the semiconductor layer 500. 其中,在本发明实施例中,宽禁带半导体材料可包括但不限于Si、SiC, GaN, InAlAs、InP或其组合等,窄禁带半导体材料可包括但不限于Ge、InSb,GaAs, InGaAs或其组合等。 Wherein, in the embodiment of the present invention, a wide bandgap semiconductor materials may include, but are not limited to, Si, SiC, GaN, InAlAs, InP or combinations thereof, narrow bandgap semiconductor materials may include, but are not limited to Ge, InSb, GaAs, InGaAs or combinations thereof. 当然本领域技术人员还可选择其他材料实现本发明,但是在不脱离本发明思想的范围内,任何对上述材料的等同替换也均应包含在本发明的保护范围之内。 Of course, the skilled artisan can also select other materials to achieve the present invention, without departing from the scope of the idea of ​​the present invention, any equivalents of the above materials may also be included within the scope of the present invention.

[0021 ] 其中,优选地,在本发明的一个实施例中,第一应变宽禁带半导体层400可包括应变Si层,应变窄禁带半导体层500可包括应变Ge或应变SiGe层。 [0021] wherein, preferably, in one embodiment of the present invention, the first strained wide bandgap semiconductor layer 400 may include a strained Si layer, should be narrower bandgap semiconductor layer 500 may include a strained Ge or SiGe layer strained embodiment.

[0022] 其中,在本发明的另一个优选实施例中,第一应变宽禁带半导体层400和应变窄禁带半导体层500可均包括应变SiGe层,但是应变窄禁带半导体层500中Ge的浓度远大于第一应变宽禁带半导体层400中Ge的浓度。 [0022] wherein, in another preferred embodiment of the present invention, the first strained wide bandgap semiconductor layer 400 and the narrow bandgap semiconductor layer 500 may each comprise a strained SiGe layer, but the narrow bandgap semiconductor layer 500 of Ge much larger than the concentration of Ge in a concentration of 400 wide bandgap semiconductor layer of the first strain. 在此需要说明的是,本领域技术人员应当可以意识到,在该实施例中第一应变宽禁带半导体层400和应变窄禁带半导体层500也可作为一层应变SiGe层,通过控制掺杂条件使得该应变SiGe层中上部分的Ge浓度大于下部的Ge浓度,从而达到与本发明相同的技术效果。 To be noted that those skilled in the art should be appreciated that, in this embodiment, the first strained wide bandgap semiconductor layer 400 and the narrower bandgap semiconductor layer 500 may also be strained SiGe layer as a layer, by controlling the doping heteroaryl conditions such that the strained SiGe layer, Ge concentration in the upper portion of the lower portion is greater than the Ge concentration to achieve the same technical effect of the present invention. 另外,本领域技术人员还可意识到,上述第一应变宽禁带半导体层400和应变窄禁带半导体层500也可包括多层的应变SiGe层,或者第一应变宽禁带半导体层400包括由多层应变Si层和应变SiGe层组成的多层结构,再或者应变窄禁带半导体层500可包括由多层应变Ge层和应变SiGe层组成的多层结构等等,因此这些均可认为是对本发明上述实施例的等同替换,均应包含在本发明的保护范围之内。 Additionally, one skilled in the art may be appreciated, the above-described first strained wide bandgap semiconductor layer 400 and the narrow bandgap semiconductor layer 500 may also include multiple layers of strained SiGe layer, or the first strained wide bandgap semiconductor layer 400 comprising a plurality of layers and strained Si layer strained SiGe layer composed of a multilayer structure, or a further strained narrow bandgap semiconductor layer 500 may comprise a multilayer strained Ge SiGe layer and a strained multilayer structure consisting of layers, etc., so that these can be is equivalents of the above embodiments of the present invention should be included within the scope of the present invention.

[0023] 该半导体结构1000还可包括形成在应变窄禁带半导体层500之上的栅堆叠300, 和形成在第一应变宽禁带半导体层400和应变窄禁带半导体层500之中的源极和漏极600。 [0023] The semiconductor structure 1000 may further include a gate formed over the strained narrow bandgap semiconductor material layer 500 stack 300, and a source formed in a first strained wide bandgap semiconductor layer 400 and the narrow bandgap semiconductor layer 500 and a drain electrode 600. 在本发明的一个实施例中,栅堆叠300可包括栅介质层和栅极,优选地,可包括高k栅介质层和金属栅极,当然其他氮化物或氧化物介质层或多晶硅栅极也可应用在本发明中,因此也应包含在本发明的保护范围之内。 In one embodiment of the present invention, the gate stack 300 may include a gate dielectric layer and gate electrode, preferably, can include a high-k gate dielectric and a metal gate layer, although other dielectric oxide or nitride layer or a polysilicon gate also It can be used in the present invention, and therefore should also be included within the scope of the present invention. 在其他实施例中,栅堆叠300还可包含其他材料层以改善栅极的某些其他特性,可以看出本发明对栅堆叠的结构并没有限制,可采用任何类型的栅结构。 In other embodiments, gate stack 300 may also include layers of other materials to improve certain other properties of the gate, the gate can be seen that the present invention does not limit the stacked structure, any type of gate structure. 在另一个实施例中,在栅堆叠300的两侧还可包括一层或多层侧墙。 In another embodiment, both sides of the gate stack 300 may also include one or more spacers.

[0024] 该半导体结构通过增加的第一应变宽禁带半导体层400,例如应变Si层,从而能够有效抑制在漏端高偏压时源漏结处产生的BTBT漏电,减轻BTBT漏电的影响。 [0024] By increasing the semiconductor structure with a first strained wide bandgap semiconductor layer 400, for example, the strained Si layer, thereby effectively suppressing drain source drain junction BTBT occurs when a high drain bias terminal, BTBT mitigate the effects of leakage. 另外,通过在第一应变宽禁带半导体层400之下的绝缘层200也能够更好的抑制该类BTBT漏电。 Further, an insulating layer beneath the first strained wide bandgap semiconductor layer 200, 400 can be better suppressed BTBT such leakage.

[0025] 实施例二, [0025] Example II.

[0026] 与实施例一不同的是,在该实施例中,是在Ge、^iSb等窄禁带半导体材料的上方增加一层宽禁带半导体层,从而可抑制GIDL漏电,同样在该实施例中,所谓宽禁带半导体材料仅是相对于Ge、InSb等窄禁带半导体材料而言的。 [0026] Example a except that, in this embodiment, an additional layer of a wide bandgap semiconductor layer over the narrow bandgap semiconductor materials Ge, ^ iSb, so as GIDL leakage can be suppressed, similarly to the embodiment in embodiment, a so-called wide bandgap semiconductor materials are only relative to Ge, InSb and other narrow bandgap semiconductor materials concerned.

[0027] 如图2所示,为本发明实施例二的半导体结构示意图。 [0027] As shown in FIG 2, a schematic view of a semiconductor structure according to a second embodiment of the present invention. 该半导体结构2000与实施例一的半导体结构1000类似,也包括衬底100和衬底100之上的过渡层或绝缘层200以及栅堆叠300等,不同的是该半导体结构2000包括在过渡层或绝缘层200之上的应变窄禁带半导体层500,和形成在应变窄禁带半导体层500之上的第二应变宽禁带半导体层700。 The semiconductor structure 2000 similar to the embodiment of a semiconductor structure 1000, and the gate stack 200 also includes a buffer layer or other insulating layer 300 over the substrate 100 and the substrate 100, except that the semiconductor structure includes a buffer layer 2000 or the insulating layer 200 over the narrow bandgap semiconductor layer 500, and formed in the narrow bandgap semiconductor layer 500 on the second strained wide bandgap semiconductor layer 700. 其中源极和漏极600形成在应变窄禁带半导体层500和第二应变宽禁带半导体层700之中。 Wherein the source and drain electrodes 600 are formed among the 700 narrow bandgap semiconductor layer 500 and the second wide bandgap semiconductor layer is strained. 其中,在本发明的其他实施例中,在过渡层或绝缘层200与应变窄禁带半导体层500之间还可以包括其他的层,以改善两者之间的应力条件或接触条件,或者为了其他目的。 Wherein, in other embodiments of the present invention, the buffer layer 200 or the insulating layer 500 and the other should be narrowed between the forbidden band of the semiconductor layer may further include a layer to improve the stress conditions or contact condition therebetween, or to other purposes. 在本发明的一个实施例中,宽禁带半导体材料可包括但不限于Si、SiC、GaN, InAlAs, InP或其组合等,窄禁带半导体材料可包括但不限于Ge、InSb、GaAsUnGaAs或其组合等。 In one embodiment of the present invention, the wide bandgap semiconductor materials may include, but are not limited to, Si, SiC, GaN, InAlAs, InP or combinations thereof, narrow bandgap semiconductor materials may include, but are not limited to Ge, InSb, GaAsUnGaAs or combination. 优选地,在本发明的一个实施例中,变窄禁带半导体层500可包括应变Ge或应变SiGe层,第二应变宽禁带半导体层700可包括应变Si层。 Preferably, in one embodiment of the present invention, the narrow bandgap semiconductor layer 500 may include a strained Ge layer or a strained SiGe, strained second wide bandgap semiconductor layer 700 may include a strained Si layer. 在另一个优选实施例中,变窄禁带半导体层500和第二应变宽禁带半导体层700可均包括应变SiGe层,但是应变窄禁带半导体层500中Ge的浓度远大于第二应变宽禁带半导体层700中Ge的浓度。 In another preferred embodiment, the narrow bandgap semiconductor layer 500 and the second strained wide bandgap semiconductor layer 700 may each comprise a strained SiGe layer, but the concentration should be narrower bandgap semiconductor layer 500 is much greater than in the second strained Ge width bandgap semiconductor material layer 700 of Ge concentration. 该半导体结构2000能够有效抑制GIDL 漏电的产生,从而减轻BTBT漏电的影响。 The semiconductor structure 2000 GIDL leakage can be effectively suppressed, thereby reducing influence of the leakage BTBT.

[0028] 实施例三, [0028] Example III.

[0029] 在该实施例中综合了上述两个实施例的优点,从而可以同时抑制两种BTBT漏电的产生。 [0029] The above embodiment combines the advantages of two embodiments of this embodiment, it can be suppressed simultaneously generate two BTBT leakage. 另外,该实施例还有一个附加的优点,即可形成空穴势阱,从而提高载流子的迁移率,改善器件性能。 Further, there is an additional advantage of this embodiment, the hole potential well can be formed, thereby improving the mobility of carriers and improve device performance.

[0030] 如图3所示,为本发明实施例三的半导体结构示意图。 [0030] FIG. 3, a schematic view of the present semiconductor structure according to a third embodiment of the invention. 该半导体结构3000与上述半导体结构1000和2000类似,不同的是在该实施例中,采用宽禁带半导体层包围窄禁带半导体层的方式来抑制上述两种BTBT漏电。 The semiconductor structure of the semiconductor structure 1000 and 3000 and 2000 are similar except that in this embodiment, by way of wide bandgap semiconductor layer surrounding the narrow bandgap semiconductor layer to suppress the leakage of the two BTBT. 如图3所示,不同于上述实施例的是,该半导体结构3000还包括形成在过渡层或绝缘层200之上的第一应变宽禁带半导体层400、形成在该第一应变宽禁带半导体层400之上的应变窄禁带半导体层500、和形成在应变窄禁带半导体层500之上的第二应变宽禁带半导体层700。 3, different from the above embodiment that the semiconductor structure 3000 further includes a buffer layer formed on the insulating layer 200 or the first strained wide bandgap semiconductor layer 400 formed on the first strained wide bandgap the semiconductor layer 400 over the narrow bandgap semiconductor layer 500, and formed in the narrow bandgap semiconductor layer 500 on the second strained wide bandgap semiconductor layer 700. 在本发明的一个实施例中,宽禁带半导体材料可包括但不限于Si、SiC、GaN、InAlAs、InP或其组合等,窄禁带半导体材料可包括但不限于Ge、InSb, GaAs, InGaAs或其组合等。 In one embodiment of the present invention, a wide bandgap semiconductor materials may include, but are not limited to, Si, SiC, GaN, InAlAs, InP or combinations thereof, narrow bandgap semiconductor materials may include, but are not limited to Ge, InSb, GaAs, InGaAs or combinations thereof. 在本发明实施例中,上述宽禁带半导体材料和窄禁带半导体材料可任意组合,也就是说第一应变宽禁带半导体层400和第二应变宽禁带半导体层700可采用相同的宽禁带半导体材料,如都采用应变Si,也可以采用不同的宽禁带半导体材料,例如第一应变宽禁带半导体层400采用应变Si,而第二应变宽禁带半导体层700采用应变SiGe,等等。 In an embodiment of the present invention, the wide bandgap semiconductor material and narrow bandgap semiconductor material can be any combination, i.e. the same width of the first strained wide bandgap semiconductor layer 400 and the second strained wide bandgap semiconductor layer 700 may be employed bandgap semiconductor material, are used as strained Si, various wide bandgap semiconductor materials may also be employed, for example, the first strained wide bandgap semiconductor layer 400 using strained Si, strained and a second wide bandgap semiconductor layer 700 using strained SiGe, and many more.

[0031] 优选地,在本发明的一个实施例中,第一应变宽禁带半导体层400和第二应变宽禁带半导体层700包括应变Si层,应变窄禁带半导体层500包括应变Ge层或应变SiGe层。 [0031] Preferably, in one embodiment of the present invention, the first strained wide bandgap semiconductor layer 400 and the second strained wide bandgap semiconductor layer 700 comprising a layer of strained Si, strained narrow bandgap semiconductor layer comprises a strained Ge layer 500 or strained SiGe layer. 在其他优选实施例中,第一应变宽禁带半导体层400、第二应变宽禁带半导体层700和应变窄禁带半导体层500均包括应变SiGe层,其中,应变窄禁带半导体层500中Ge的浓度远大于第一应变宽禁带半导体层400和第二应变宽禁带半导体层700中Ge的浓度。 In other preferred embodiments, the first strained wide bandgap semiconductor layer 400, a second strained wide bandgap semiconductor layer 700 and the narrow bandgap semiconductor layer 500 includes a strained SiGe layer, wherein the strained narrow bandgap semiconductor material layer 500 concentrations of Ge were much greater than the concentration of the wide bandgap semiconductor layer 400 and the second strained wide bandgap semiconductor layer 700 of Ge in the first strain. 在该实施例中,采用了应变窄禁带半导体层500作为沟道层,例如应变Ge层或应变SiGe层,因此由于异质能带结构,大部分的空穴载流子都聚集在高迁移率的应变窄禁带半导体层500中,因此可以有效提高饱和电流,改善器件性能。 In this embodiment, using a narrower bandgap semiconductor layer to be the channel layer 500, for example, strained Ge layer or a strained SiGe layer, the energy band structure due to the heterogeneity, most of hole carriers are gathered in the high mobility rate of narrow bandgap semiconductor layer 500, it is possible to improve the saturation current, improving device performance. 在本发明中上述第一应变宽禁带半导体层400、 应变窄禁带半导体层500和第二应变宽禁带半导体层700的厚度和掺杂根据需要而定,本发明对上述层的厚度做了一个简单的介绍,例如根据驰豫SiGe虚拟衬底层中Ge的含量,上述各层的厚度不能超过临界厚度,以免发生驰豫从而在材料层中引入新的缺陷,例如第一应变宽禁带半导体层400的厚度约为3-5nm,不超过临界厚度情况下越厚越好;应变窄禁带半导体层500的厚度约为3-lOnm,不超过临界厚度,但又必须保证满足载流子运输的要求, 且低掺杂或者不掺杂以得到更高的载流子迁移率;第二应变宽禁带半导体层700的厚度约为2-5nm,优选为3nm,重掺杂以提供合适的载流子密度。 In the present invention, the first strained wide bandgap semiconductor layer 400, the narrow bandgap semiconductor layer 500 and the second strained wide bandgap semiconductor layer 700 thickness and doping may be required, the present invention is to make the thickness of the layer a simple presentation, for example in accordance relaxed SiGe virtual substrate layer of Ge content, thickness of each layer can not exceed the critical thickness, in order to avoid introducing new relaxation defects in the material layer, the first strained wide bandgap e.g. the thickness of the semiconductor layer 400 is about 3-5nm, does not exceed the critical thickness where the thicker the better; thickness bandgap semiconductor material layer 500 should be narrowed about 3-lOnm, without exceeding the critical thickness, but must be guaranteed carrier transport requirement, and a low doped or doped to a carrier mobility is higher; thickness 700 of second strained wide bandgap semiconductor layer is about 2-5 nm, preferably 3nm, heavily doped to provide a suitable carrier density. 本发明所提出的上述半导体结构不仅可适用于垂直栅结构,还可适用于FinFET结构,当然其他结构或者今后发展的新的半导体结构也可采用本发明的各个实施例来抑制BTBT漏电。 The semiconductor structure proposed by the present invention is applicable not only to a vertical gate structure, may also be applied to a FinFET structure, although other structures or future development of a new semiconductor structure may also be employed in various embodiments of the present invention to suppress leakage BTBT. 如图4所示,为本发明实施例的FinFET结构示意图。 4, a schematic diagram of the FinFET structure of the embodiment of the present invention. 如图4,FinFET结构包括栅极4100和栅介质层4300,以及源极/漏极4200,源极/漏极4200包括位于衬底(未示出)之上的第一应变宽禁带半导体层4400,位于第一应变宽禁带半导体层4400之上的应变窄禁带半导体层4500,以及包围应变窄禁带半导体层4500的第二应变宽禁带半导体层4600。 4, FinFET structure is shown comprising a gate dielectric layer 4100 and gate electrode 4300, and source / drain electrode 4200, the source / drain electrode 4200 includes a substrate (not shown) on a first wide bandgap semiconductor layer is strained 4400, located in the first strained wide bandgap semiconductor layer 4400 above the narrow bandgap semiconductor layer 4500, and surrounds the narrow bandgap semiconductor layer a second strained wide forbidden band of the semiconductor layer 4500 of 4600. 其中,在本发明的一个实施例中,第一应变宽禁带半导体层4400和第二应变宽禁带半导体层4600可为应变Si层,应变窄禁带半导体层4500可为应变Ge层或应变SiGe层。 Wherein, in one embodiment of the present invention, the first strained wide bandgap semiconductor layer 4400 and the second strained wide bandgap semiconductor layer 4600 may be a layer of strained Si, strained narrow bandgap semiconductor layer 4500 may be a strained layer or a strained Ge SiGe layer. 在本发明的另一个实施例中,第一应变宽禁带半导体层4400、应变窄禁带半导体层4500和第二应变宽禁带半导体层4600均可为应变SiGe 层,但应变窄禁带半导体层4500中Ge浓度远高于第一应变宽禁带半导体层4400和第二应变宽禁带半导体层4600。 In another embodiment of the present invention, the first strained wide bandgap semiconductor layer 4400, should be narrower bandgap semiconductor layer 4500 and the second strained wide bandgap semiconductor layer 4600 can be a strained SiGe layer, it will be narrow bandgap semiconductor material the Ge concentration in layer 4500 is much higher than a first strained wide bandgap semiconductor layer 4400 and the second strained wide bandgap semiconductor layer 4600. 尽管已经示出和描述了本发明的实施例,但是对于本领域的普通技术人员而言,可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型,本发明的范围由所附权利要求及其等同限定。 While there have been illustrated and described embodiments of the present invention, but those of ordinary skill in the art, to be understood that various changes may be made to these embodiments without departing from the principles and spirit of the invention, modifications, substitutions and modifications, the scope of the invention being indicated by the appended claims and their equivalents.

Claims (15)

  1. 1. 一种半导体结构,其特征在于,包括: 衬底;形成在所述衬底之上的过渡层或绝缘层; 形成在所述过渡层或绝缘层之上的第一应变宽禁带半导体层; 形成在所述第一应变宽禁带半导体层之上的应变窄禁带半导体层; 形成在所述应变窄禁带半导体层之上的第二应变宽禁带半导体层; 形成在所述第二应变宽禁带半导体层之上的栅堆叠;和形成在所述第一应变宽禁带半导体层、应变窄禁带半导体层和第二应变宽禁带半导体层之中的源极和漏极。 1. A semiconductor structure comprising: a substrate; forming a buffer layer or an insulating layer over the substrate; forming a first strained semiconductor forbidden band width over the insulating layer or buffer layer layer; formed over the first strained wide bandgap semiconductor layer of narrow bandgap semiconductor layer; forming a second strained wide bandgap semiconductor layer over the forbidden band of the semiconductor layer should be narrowed; formed in the a second gate over the strain wide bandgap semiconductor layer stack; and a strain formed in the first wide bandgap semiconductor layer, narrow bandgap semiconductor layer and the second source and drain strained among wide bandgap semiconductor layer, pole.
  2. 2.如权利要求1所述的半导体结构,其特征在于,所述栅堆叠包括高k栅介质层和金属栅极。 2. The semiconductor structure according to claim 1, wherein said gate stack comprises a high-k gate dielectric layer and a metal gate.
  3. 3.如权利要求1所述的半导体结构,其特征在于,所述过渡层包括驰豫SiGe虚拟衬底层。 The semiconductor structure according to claim 1, wherein the transition layer comprises a relaxed SiGe virtual substrate layer.
  4. 4.如权利要求1-3任一项所述的半导体结构,其特征在于,所述第一应变宽禁带半导体层和第二应变宽禁带半导体层包括应变Si层,所述应变窄禁带半导体层包括应变Ge或应变SiGe层。 4. The semiconductor structure of any one of claims 1-3, wherein the first strained wide bandgap semiconductor layer and the second strained wide bandgap semiconductor layer comprises a strained Si layer, the cut-off should be narrowed band of the semiconductor layer comprises a strained Ge or SiGe layer strained.
  5. 5.如权利要求1-3任一项所述的半导体结构,其特征在于,所述第一应变宽禁带半导体层、第二应变宽禁带半导体层和所述应变窄禁带半导体层均包括应变SiGe层,其中,所述应变窄禁带半导体层中Ge的浓度大于所述第一应变宽禁带半导体层和第二应变宽禁带半导体层中Ge的浓度。 5. The semiconductor structure of any one of claims 1-3, wherein the first strained wide bandgap semiconductor layer, a second wide bandgap semiconductor layer and the strained semiconductor layer, the bandgap narrowing should have It comprises a strained SiGe layer, wherein said narrow bandgap semiconductor layer is greater than the first concentration of Ge strained wide bandgap semiconductor layer and the second strained wide bandgap semiconductor layer of Ge concentration.
  6. 6.如权利要求1所述的半导体结构,其特征在于,宽禁带半导体材料包括Si、SiC、GaN、 InAIAs、InP或其组合。 6. The semiconductor structure according to claim 1, wherein the wide bandgap semiconductor material comprises Si, SiC, GaN, InAIAs, InP, or combinations thereof.
  7. 7.如权利要求1所述的半导体结构,其特征在于,窄禁带半导体材料包括Ge、InSb, GaAs、InGaAs或其组合。 7. The semiconductor structure according to claim 1, characterized in that the narrow bandgap semiconductor material comprises Ge, InSb, GaAs, InGaAs, or combinations thereof.
  8. 8. 一种半导体结构,其特征在于,包括: 衬底;形成在所述衬底之上的过渡层或绝缘层; 形成在所述过渡层或绝缘层之上的第一应变宽禁带半导体层; 形成在所述第一应变宽禁带半导体层之上的应变窄禁带半导体层; 形成在所述应变窄禁带半导体层之上的栅堆叠;和形成在所述第一应变宽禁带半导体层和应变窄禁带半导体层之中的源极和漏极。 A semiconductor structure comprising: a substrate; forming a buffer layer or an insulating layer over the substrate; forming a first strained semiconductor forbidden band width over the insulating layer or buffer layer layer; formed over the first strained wide bandgap semiconductor layer of narrow bandgap semiconductor layer; forming a gate over the strained narrow bandgap semiconductor layer stack; and a strain formed in the first wide bandgap semiconductor narrow bandgap layer and the source and drain in the semiconductor layer.
  9. 9.如权利要求8所述的半导体结构,其特征在于,所述栅堆叠包括高k栅介质层和金属栅极。 The semiconductor structure as claimed in claim 8, wherein said gate stack comprises a high-k gate dielectric layer and a metal gate.
  10. 10.如权利要求8所述的半导体结构,其特征在于,所述过渡层包括驰豫SiGe虚拟衬底层。 10. The semiconductor structure according to claim 8, wherein the transition layer comprises a relaxed SiGe virtual substrate layer.
  11. 11.如权利要求8-10任一项所述的半导体结构,其特征在于,所述第一应变宽禁带半导体层包括应变Si层,所述应变窄禁带半导体层包括应变Ge层或应变SiGe层。 11. The semiconductor structure of any one of claims 8-10, wherein the first strained wide bandgap semiconductor layer comprises a strained Si layer, the bandgap semiconductor layer comprises a strained Ge layer should narrowing or strain SiGe layer.
  12. 12.如权利要求11所述的半导体结构,其特征在于,所述第二应变宽禁带半导体层包括应变Si层或应变SiGe层。 12. The semiconductor structure according to claim 11, wherein the second strained wide bandgap semiconductor layer comprises a strained Si layer or a strained SiGe layer.
  13. 13.如权利要求8-10任一项所述的半导体结构,其特征在于,所述第一应变宽禁带半导体层和所述应变窄禁带半导体层均包括应变SiGe层,其中,所述应变窄禁带半导体层中Ge的浓度大于所述第一应变宽禁带半导体层中Ge的浓度。 13. The semiconductor structure of any one of claims 8-10, wherein the first strained wide bandgap semiconductor layer and the bandgap of the semiconductor layer comprises a strained SiGe strained narrow layer, wherein said narrow bandgap semiconductor layer is greater than the first concentration of Ge strained wide bandgap semiconductor layer of Ge concentration.
  14. 14.如权利要求8所述的半导体结构,其特征在于,宽禁带半导体材料包括Si、SiC、 GaN、InAlAs、InP 或其组合。 14. The semiconductor structure according to claim 8, wherein the wide bandgap semiconductor material comprises Si, SiC, GaN, InAlAs, InP or a combination thereof.
  15. 15.如权利要求8所述的半导体结构,其特征在于,窄禁带半导体材料包括Ge、InSb, GaAs、InGaAs或其组合。 15. The semiconductor structure according to claim 8, characterized in that the narrow bandgap semiconductor material comprises Ge, InSb, GaAs, InGaAs, or combinations thereof.
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