CN101819815B - Static random-access memory for eliminating reading interference - Google Patents

Static random-access memory for eliminating reading interference Download PDF

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Publication number
CN101819815B
CN101819815B CN201010164945.9A CN201010164945A CN101819815B CN 101819815 B CN101819815 B CN 101819815B CN 201010164945 A CN201010164945 A CN 201010164945A CN 101819815 B CN101819815 B CN 101819815B
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nmos tube
pmos
tube
nmos
access memory
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CN101819815A (en
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胡剑
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

The invention provides a static random-access memory for eliminating reading interference, which comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube and a fifth NMOS tube. The first PMOS tube, the first NMOS tube, the second PMOS tube and the second NMOS tube forms two COMS phase reversers and form a flip and flop generator through cross-coupling; the third NMOS tube is connected with the second PMOS tube; the fourth NMOS tube is connected with the PMOS tube; and the fifth NMOS tube is respectively connected with the first PMOS tube and the second PMOS tube. The fifth NMOS tube is added in the static random-access memory, and the fifth NMOS tube is shut off when reading tasks are executed, so that the reading interference phenomenon is avoided, and the stability of the reading state of the static random-access memory is improved.

Description

A kind of static RAM eliminating reading interference
Technical field
The present invention relates to a kind of semiconductor devices, particularly relate to a kind of static RAM eliminating reading interference.
Background technology
Component density within integrated circuit can utilize integrated circuit (IC) design (the reducedgeometry integrated circuit designs) principle in reduction space, increases the performance of integrated circuit and reduces its real cost.Comprise Flash, SRAM (static RAM), obvious example that the modern integrated circuits memory device of OUM, EEPROM, FRAM, MRAM etc. is all the principle utilizing this poke unit (memory cell).Density in integrated circuit memory devices increases just constantly, and adjoint be with it the corresponding reduction of the unit carrying cost of this kind of device.The increase of density utilizes in device, make less structure, and utilize the compartment between reduction element or between the structure of composed component to complete.Usually, the design criteria (design rules) of this kind of reduced size can be attended by layout, the correction of design and structure, when using the design criteria of this kind of reduced size, these are revised and change and could will be realized by the size of reduction element, but also will maintain device performance.As a kind of example, the reduction of its operating voltage among multiple existing integrated circuit is owing to such as reducing gate oxide thicknesses, and the error of promoting in micro-shadow programmed control just may complete.On the other hand, the design criteria of size reduction also makes to reduce operating voltage and becomes necessary, if when small-sized component is with existing higher operation voltage operation, to be limited the hot carrier (hot carriers) that can produce.First generation SRAM module adopts large scale DIP encapsulation, and this encapsulation has certain height, because battery and RAM chip are stacked among DIP encapsulation.The advantage of DIP encapsulation is that device can insert DIP socket, convenient replacement and storage, or transfers to another from a printed board.Although these advantages are still very useful so far, by contrast, be more necessary to develop surface mounting technology, and operating voltage is become 3.3V from 5V.Second generation SRAM module adopts two-piece type scheme---and PowerCap module (PCM), is namely made up of the pedestal (comprising SRAM) and PowerCap (namely lithium battery) two parts that are welded direct to printed panel.Compared with DIP module, this kind of device has two major advantages: they adopt surface mount, and has standard pin configuration.In other words, no matter how jumbo SRAM, its encapsulation and number of pins are identical.Therefore, designer can strengthen system memory size, and need not worry to need to change PCB layout.Battery altering gets up and is also easy to.The third generation i.e. up-to-date SRAM module, it not only solves the problem existing for previous product, adds greater functionality simultaneously.This kind of novel sram is monolithic BGA module, built-in chargeable lithium cell.The same with PCM, adopt all SRAM no matter its amount of capacity of this packing forms, package dimension and pin configuration are all identical.This generic module adopts surface mount, and is monolithic device.Therefore design more reliably firm, stronger mechanical shock can be born compared with previous generation device.Because battery is chargeable, therefore the concept of data retention over time has had other one deck implication.Describe more appropriate with equivalence word in serviceable life one, this kind of device equivalence serviceable life can up to 200 years.In addition, this module can bear the Reflow Soldering temperature of+230 DEG C, and the Lead-free in Electronic Packaging device provided can bear the temperature of+260 DEG C.
Cellar area and cell stability are two importances of SRAM design.Cellar area determines the size of memory chip to a great extent; Cell stability determines the data reliability of storer, and stability described here comprises read stability and write stability.The main flow cellular construction of SRAM comprises 6 MOS transistor, and its formation can be whole CMOS planar structure, also can be laminated type three-dimensional structure.Please refer to Fig. 1, Fig. 1 is the structural representation of the SRAM of six transistors in prior art, in figure, described SRAM is made up of six transistors, in described six transistors, comprise four NMOS tube (N1, N2, N3, N4) and two PMOS (P1, P2), wherein the first PMOS P1, the first NMOS tube N1 and the second PMOS P2, the second NMOS tube N2 form two COMS phase inverters, and cross-couplings forms trigger flip-flop; Gate tube the 3rd NMOS tube N3, the 4th NMOS tube N4 provide approach and the control of data input and output; BL in figure, for bitline control signals, WL is the wordline of this unit, in read operation, when V1 voltage increases, just may cause the change of Current lock state.And after CMOS technology enters sub-micro; the bad stability of D S RAM; especially the bad stability of reading state; its main cause is 2 PMOS load pipes is manufactured by non-aligned backgate technology; when repeatedly reading the data stored by the same block in storer; reading times such as between 10 ten thousand to hundred ten thousand times; it is wrong that read data probably can occur, even this repeatedly to be read in block the data that stores can occur abnormal or lose.And this type of phenomenon has with field of the present invention and usually knows used be called " reading interference " (read-disturb) of the knowledgeable, also because there being such phenomenon to also exist, invariably ordering about Ge Jia manufacturer and must develop the technology preventing from reading interference, reading interference odds so as to effectively suppressing.Please refer to Fig. 2, Fig. 2 is the structural representation of the static RAM improved in prior art, SRAM in Fig. 2 adds two NMOS tube (N6 than SRAM in Fig. 1, N7), when the data that will store the block in storage period reads, extra two NMOS tube increased will be used, thus avoid producing in the process read reading interference, ensure the accuracy read, but, originally the shortcoming of SRAM is that integrated level is low, power consumption is larger, identical content volume is larger, add two NMOS tube, the volume of SRAM will certainly be increased to a great extent, be unfavorable for the service efficiency improving SRAM.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of static RAM, solves the problem that interference easily occurs when reading to read static RAM.
To achieve these goals, the present invention proposes a kind of static RAM eliminating reading interference, comprise: the first NMOS tube, second NMOS tube, 3rd NMOS tube, 4th NMOS tube, first PMOS and the second PMOS, wherein said first PMOS, described first NMOS tube and described second PMOS, described second NMOS tube forms two COMS phase inverters, cross-couplings forms trigger flip-flop, described 3rd NMOS tube is connected with described second PMOS, described 4th NMOS tube is connected with described first PMOS, described static RAM also comprises the 5th NMOS tube, described 5th NMOS tube and described first PMOS, described second PMOS is connected respectively.
Optionally, the source electrode of described 5th NMOS tube is connected with the source electrode of described first PMOS or drain electrode, and the drain electrode of described 5th NMOS tube is connected with the grid of described second PMOS.
Optionally, the drain electrode of described 5th NMOS tube is connected with the source electrode of described first PMOS or drain electrode, and the source electrode of described 5th NMOS tube is connected with the grid of described second PMOS.
A kind of Advantageous Effects eliminating the static RAM reading interference of the present invention is: the present invention adds the 5th NMOS tube in static RAM, when performing reading task, the 5th NMOS tube is closed, thus avoid the generation of reading interference phenomenon, improve the stability of static RAM reading state.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art static RAM.
Fig. 2 is the structural representation of the static RAM improved in prior art.
Fig. 3 is a kind of structural representation eliminating the static RAM reading interference of the present invention.
Fig. 4 is a kind of operation form eliminating the static RAM reading interference of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Please refer to Fig. 3, Fig. 3 is a kind of static RAM eliminating reading interference of the present invention, this static RAM is on the basis of the static RAM of existing six transistors, add a NMOS tube, existing SRAM is made up of six transistors, in described six transistors, comprise four NMOS tube (N1, N2, N3, N4) and two PMOS (P1, P2), wherein the first PMOS P1, the first NMOS tube N1 and the second PMOS P2, the second NMOS tube N2 form two COMS phase inverters, and cross-couplings forms trigger flip-flop; Gate tube the 3rd NMOS tube N3, the 4th NMOS tube N4 provide approach and the control of data input and output; BL in figure, for bitline control signals, WL is the wordline of this unit, and described static RAM also comprises the 5th NMOS tube, and described 5th NMOS tube is connected respectively with described first PMOS, described second PMOS.
The principle of work of SRAM memory cell of the present invention is: when word line control signal WL is high level, gate tube the 3rd NMOS tube M n3, the 4th NMOS tube M n4conducting, by the first PMOS M p1, the first NMOS tube M n1with the second PMOS M p2, the second NMOS tube M n2composition cross coupled flip-flop can from bit line BL, export or input signal, when use second NMOS tube and the 4th NMOS tube carry out read operation, close the 5th NMOS tube, block the electric current of this circuit, thus avoid the generation of reading interference, improve the stability of static RAM reading state.The source electrode of described 5th NMOS tube is connected with the source electrode of described first PMOS or drain electrode, and the drain electrode of described 5th NMOS tube is connected with the grid of described second PMOS.The drain electrode of described 5th NMOS tube is connected with the source electrode of described first PMOS or drain electrode, and the source electrode of described 5th NMOS tube is connected with the grid of described second PMOS.About the connection of source electrode and drain electrode, actual when using, also can exchange use.
The signal read exports after sense amplifier, and the amplifier that transistor is formed will be accomplished to be amplified by signal voltage without distortion, just must ensure that the emitter junction positively biased of transistor, collector junction are reverse-biased, namely should arrange its working point.So-called working point be exactly make the base stage of transistor by the setting of external circuit, emitter and collector is in required current potential (can obtain according to calculating).These external circuits are just called biasing circuit (can be regarded as, arrange the positive and negative inclined circuit of PN junction), and the electric current that biasing circuit provides to transistor is just called bias current.Go ahead with conventional total radio amplifier, main flow is the IC from emitter to collector, and bias current is exactly the IB from emitter to base stage, and relative and main circuit, for base stage provides the circuit of electric current to be exactly so-called biasing circuit.
Finally, please refer to Fig. 4, Fig. 4 is a kind of operation form eliminating the static RAM reading interference of the present invention, when carrying out read operation, the signal in Fig. 3 on RWL is " 1 ", continues precharge to RBL, signal on WL is " 0 ", and BL is upper without operation, and the signal on WLx is " 0 "; When carrying out write operation, the signal in Fig. 3 on RWL is " 1 ", and the signal on RBL is " 0 " or " 1 ", and the signal on WL is " 1 ", and the signal on BL is " 0 " or " 1 ", and the signal on WLx is " 1 "; When storer carries out state maintenance, the signal in Fig. 3 on RWL is " 0 ", and the signal on RBL is " 1 ", and the signal on WL is " 0 ", and the signal on BL is " 1 ", and the signal on WLx is " 1 ".
Although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Have in technical field of the present invention and usually know the knowledgeable, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on those as defined in claim.

Claims (1)

1. eliminate the static RAM reading interference for one kind, comprise: the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the first PMOS and the second PMOS, wherein said first PMOS, described first NMOS tube and described second PMOS, described second NMOS tube form two COMS phase inverters, cross-couplings forms trigger flip-flop, described 3rd NMOS tube is connected with described second PMOS, described 4th NMOS tube is connected with described first PMOS
It is characterized in that: described static RAM also comprises the 5th NMOS tube, described 5th NMOS tube is connected respectively with described first PMOS, described second PMOS;
Wherein, the source electrode of described 5th NMOS tube is connected with the source electrode of described first PMOS or drain electrode, and the drain electrode of described 5th NMOS tube is connected with the grid of described second PMOS; Or
The drain electrode of described 5th NMOS tube is connected with the source electrode of described first PMOS or drain electrode, and the source electrode of described 5th NMOS tube is connected with the grid of described second PMOS.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998040973A1 (en) * 1997-02-28 1998-09-17 Rambus, Inc. Low-latency small-swing clocked receiver
CN1408118A (en) * 2000-03-03 2003-04-02 睦塞德技术公司 Improved high density memory cell
CN1875428A (en) * 2003-10-27 2006-12-06 日本电气株式会社 Semiconductor storage device
CN101165806A (en) * 2006-10-19 2008-04-23 松下电器产业株式会社 Semiconductor memory device
CN101529521A (en) * 2006-11-17 2009-09-09 飞思卡尔半导体公司 Two-port SRAM having improved write operation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998040973A1 (en) * 1997-02-28 1998-09-17 Rambus, Inc. Low-latency small-swing clocked receiver
CN1408118A (en) * 2000-03-03 2003-04-02 睦塞德技术公司 Improved high density memory cell
CN1875428A (en) * 2003-10-27 2006-12-06 日本电气株式会社 Semiconductor storage device
CN101165806A (en) * 2006-10-19 2008-04-23 松下电器产业株式会社 Semiconductor memory device
CN101529521A (en) * 2006-11-17 2009-09-09 飞思卡尔半导体公司 Two-port SRAM having improved write operation

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