CN101789845B - Method and circuit applying SFEC to realize bit width transformation of bus in OTN (optical transport network) - Google Patents

Method and circuit applying SFEC to realize bit width transformation of bus in OTN (optical transport network) Download PDF

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CN101789845B
CN101789845B CN 201010111571 CN201010111571A CN101789845B CN 101789845 B CN101789845 B CN 101789845B CN 201010111571 CN201010111571 CN 201010111571 CN 201010111571 A CN201010111571 A CN 201010111571A CN 101789845 B CN101789845 B CN 101789845B
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朱齐雄
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烽火通信科技股份有限公司
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本发明公开了一种应用SFEC的光传送网中总线位宽变换实现方法及电路,该方法包括以下步骤:S10、将从64位系统总线输入的OTN帧的数据按外码RS(1023,1007)编码规则编码后存入缓存M,缓存M由8块RAM构成,每块RAM的大小分别为1530×10;S20、每次分别从缓存M的8块RAM中读取10个RS(1023,1007)编码数据并按内码BCH(2040,1952)编码规则编码后存入缓存N,缓存N由8块RAM构成,每块RAM的大小分别为244×64;S30、依次从缓存N的8块RAM中输出64个BCH(2040,1952)编码数据至64位系统总线。 The present invention discloses an application of the bus width converting SFEC optical transport network and a circuit-implemented method, the method comprising the steps of: S10, from the 64-bit data bus input of the OTN frame system according to an outer code RS (1023,1007 ) encoding rules coded into the cache M, M is composed of a cache RAM 8, the size of each block of RAM are 1530 × 10; S20, respectively, each read 10 RS (1023 from 8 M of RAM cache, 1007) and press the inner code coded data BCH (2040,1952) the encoded coding rule cached N, N consists of eight cache RAM, the size of each block of RAM are 244 × 64; S30, sequentially from the cache 8 N RAM block output 64 BCH (2040,1952) the encoded data to a 64-bit system bus. 本发明通过对缓存的读写操作的控制,完成了输入64位宽到外码所要求的80位宽的总线变换以及从80位宽的总线再到64位宽总线的变换,实现方法简便有效、操作性强。 The present invention, by controlling the read and write operations to the cache, the complete 64-bit wide input to the outer code of the desired 80-bit wide bus conversion from 80 bit wide bus, and then converting the 64-bit wide bus, simple and effective implementation method , workable.

Description

应用SFEC的光传送网中总线位宽变换实现方法及电路 Application of the bus width converting SFEC OTN implementation method and circuit

技术领域 FIELD

[0001] 本发明涉及OTN光传送网的编解码技术,具体涉及应用SFEC的光传送网中总线位宽变换实现方法及电路。 [0001] The present invention relates to encoding and decoding technology OTN optical transport network, particularly relates to the use of SFEC optical transport network and the bus width converting circuit implementation.

背景技术 Background technique

[0002] 随着网络化时代的到来,人们对信息的需求与日俱增。 [0002] With the advent of the Internet era, people's growing demand for information. 由于光通信技术具有巨大的带宽资源和相对低廉的制造成本,因此,目前OTN作为下一代宽带通信网的基础,并作为信息传输技术的重要支撑平台,在未来信息社会中将会起着十分重要的作用。 As the optical communication technology has huge bandwidth and relatively low manufacturing costs, therefore, the current OTN as the basis for the next generation of broadband communications network, and as an important support platform for information transmission technology in the future information society will play a very important role. [0003] 随着人们对信息需求的日趋增长,极大地拓展了电信网对光通信系统的需求空间并刺激了光通信系统自身技术的飞速发展。 [0003] With the growing information needs of people, and greatly expand the telecommunications network of the demand for space optical communication system and stimulate the rapid development of its own technology, optical communication systems. 进一步增加传输系统的容量与降低每比特传输成本的较好的办法就是光波分复用(WDM)技术的使用。 Further increase in capacity and better ways to reduce the cost per bit of the transmission system is the optical wavelength division multiplexing (WDM) technique is used. 近年来,随着波分复用技术的大量应用与发展,使一对光纤上的信息传输总速率已在向太比特每秒的数量级进军。 In recent years, with the large number of applications and the development of wavelength division multiplexing technology, the total information transfer rate over one pair of optical fiber has to enter in the order of terabits per second.

[0004] 由于通信技术的发展和新业务的不断涌现,特别是IP业务的迅猛崛起,导致全球信息量呈数量级增长,通信业务由传统单一的电话业务向高速IP数据和多媒体为代表的宽带业务,对通信网络的带宽和容量提出了越来越高的要求。 [0004] Since the development of communication technology and new businesses are emerging, especially the rapid rise of IP services, leading to global information orders of magnitude growth in traffic from the traditional single telephone service as the representative of the high-speed IP data and multimedia broadband services , the bandwidth capacity of communication networks and increasingly high demands. 然而,光纤通信网络的许多不利因素影响了其传输性能。 However, many unfavorable factors of optical fiber communication network affected its transmission performance. 随着光通信系统向超高速、超大容量与超长距离方向的发展以及同步数字系列(SDH)体系结构、掺铒光纤放大器(EDFA)的应用、密集波分复用(DWDM)系统、全光网及光交叉连接(OXC)等技术在光纤通信系统中不断应用,加之器件性能不断改善,系统速率得到了跳跃式地提升,系统容量得到了成倍的扩大。 With the application of ultra-high speed optical communication systems, the development of very large capacity and long distance and direction of the Synchronous Digital Hierarchy (SDH) architecture, erbium-doped fiber amplifier (EDFA), the dense wavelength division multiplexing (DWDM) system, the total light networks and optical cross-connect (OXC) technology has applications in other optical communication system, together with device performance continues to improve, the system rate was abruptly increase, the system capacity has been expanded exponentially. 但传输的有效性和可靠性是一对矛盾体,更高的单信道速率、更小的信道间隔和更远的无电中继传输距离的同时,色散、色散斜率、偏振模色散、非线性效应(四波混频、交叉相位调制等)、放大自发辐射噪声积累、接收机性能等也成为限制系统性能的主要因素。 However, the effectiveness and reliability of the transmission of the contradiction is, the higher the rate of one pair of single channel, while the smaller channel and the radio relay transmission interval longer distances, dispersion, dispersion slope, polarization mode dispersion, nonlinear effects (four-wave mixing, cross-phase modulation, etc.), the accumulation of amplified spontaneous emission noise, the performance of the receiver, also a major factor limiting system performance. 光通信容量的扩大也会引起一系列诸如各路光信号之间的串扰,信号的同步、定时、恢复的问题。 Expanding the capacity of the optical communication such as will cause a series of synchronization between the brightest light signal crosstalk, signal, timing recovery problems. 这些问题会引起光通信系统中误码的产生,降低通信的可靠性。 These problems lead to error in the generation of optical communication system, reducing the reliability of communication. 通信可靠性的降低最终又制约了通信质量的提高、多路复用的大规模应用以及通信设备成本的降低等等,因而会阻碍光通信系统的发展。 Reduce the reliability of communication eventually restricted the improvement of communication quality, large-scale multiplexing applications and communications equipment cost reduction, etc., thus hampering the development of optical communication systems.

[0005] 而前向纠错(FEC)编码技术是力求用最少的冗余来纠正尽可能多的错误,在速率和可靠性之间找到一个最佳的平衡点。 [0005] The forward error correction (FEC) coding techniques are sought with a minimum of redundancy to correct errors as much as possible, to find an optimal balance between speed and reliability. 所以采用FEC技术来降低光通信系统中的误码率,则不会过多地加大系统成本,但却可明显地改善光通信系统的误码率性能,从而提高系统通信的可靠性。 So the use of FEC techniques to reduce the error rate of an optical communication system, the system will not increase too much cost, but can significantly improve the bit error rate performance of an optical communication system, thereby improving the reliability of the communication system.

[0006] FEC技术在高速光通信系统中应用,具有能够延长光信号传输距离,降低光发射机发射功率等优点。 [0006] FEC technology used in high-speed optical communication system having an optical signal transmission distance can be extended, reducing the transmission power of the advantages of the optical transmitter. FEC技术最早在超长距离的海底光缆系统中得到应用,随着陆地光通信系统的发展,单信道速率的提高,FEC技术的应用将成为降低设备要求容限和系统组网成本的优选方案之一。 FEC technology was first used in ultra-long distance submarine cable system, with the development of terrestrial optical communication system, improve the single channel rate channel, will be the application of FEC techniques preferred embodiment to reduce equipment requirements and tolerances of the system networking costs one. 理论和实践均已经证明FEC技术是改善长途大容量光通信系统性能的一种有效方法。 Have proven both theory and practice FEC technique is an effective method for improving the long-haul large-capacity optical communication system performance. 在光通信系统中利用FEC技术可以使系统能够容许光通信线路中FEC译码前有比较大的线路比特误码率(BER)(大于10_12),FEC的应用容许放宽对系统的光参数的要求和以较低的成本构建长途大容量光通信系统。 In the optical communication system using FEC techniques may allow the system to allow the optical communication line in a relatively large line bit error rate (the BER) (greater than 10_12) before FEC decoding, the FEC system applications allow relaxation of optical parameters Construction of a low cost and a large-capacity long-distance optical communication system. [0007] 但随着光通信系统向更长距离、更大容量和更高速度的日益发展,光纤中的传输效应(如色散、PMD和非线性效应等)会严重影响传输速率和传输距离的进一步提高。 [0007] However, with the optical communication system will seriously affect the transmission rate and transmission distance to a longer distance, larger capacity and higher speed of growing, the transmission effects in optical fibers (e.g., chromatic dispersion, nonlinear effects, etc., and the PMD) Further improve. 因而有必要研究性能更好的SFEC码型,使其获得更高的净编码增益和更好的纠错性能。 Hence the need to study better performance SFEC pattern, so that a higher net coding gain and better error correction performance.

[0008] 近来,ITU-T针对光通信系统开展了FEC码的研究,相继提出了若干与此相关的建议(如G. 975、G. 709和G. 975. I等),其中ITU_T G. 975. I (高速DWDM海底系统中的前向纠错)中定义了8种SFEC的码型和编码规则,其中的I. 4种SFEC码型为:外码RS (1023,1007)+内码BCH(2040,1952)的级联码,其中外码的伽逻华域为GF (21°),这意味着每一个外码RS (1023,1007)的码元符号为lObit,因此在进行外码编码时需要将入口的总线位宽变换成10的倍数,而内码BCH(2040,1952)码是一个定义在伽逻华域GF(211)上的二进制码,每一OTN帧中有64个BCH(2040,1952)码字,由此需要将外码编码后的以10为倍数的总线位宽变换成以64为倍数的总线位宽。 [0008] Recently, ITU-T for the optical communication system FEC code studies conducted, have made a number of recommendations associated with this (such as G. 975, G. 709 and G. 975. I and the like), wherein ITU_T G. 975. I (forward error correction in high-speed DWDM submarine systems) defines eight SFEC in the pattern and encoding rules, I. 4 wherein the code pattern is SFEC Species: outer code RS (1023,1007) + inner code BCH (2040,1952) concatenated codes, wherein the outer code logic gamma Chinese domain GF (21 °), which means that each outer code RS (1023,1007) symbols symbol lObit, thus making the outer the inlet bus width required when the transform coded code is a multiple of 10, and the inner code BCH (2040,1952) code is a binary logic code on gamma Chinese domain GF (211) is defined, each OTN frame 64 a BCH (2040,1952) code word, whereby the need for the outer code encoding multiple of 10 bit wide bus 64 into a multiple of the bus width.

[0009] 但ITU_T G. 975. I建议中对I. 4超强FEC码型的这种总线变换具体实现并未提及,这些都会给硬件设计人员带来设计上的困难。 [0009] However, ITU_T G. 975. I recommend no mention of I. 4 super FEC code type transformation realization of this bus, which will bring difficulties to the design of the hardware designers.

[0010] 综上所述,现有I. 4超强FEC技术在硬件电路实现方面具有如下不足: [0010] In summary, the prior I. 4 of super FEC has insufficient hardware circuit in terms of:

[0011] 1、ITU_T G. 975. I建议中只是简单的描述了I. 4SFEC码型和编码规则并未提及具体编译码的硬件实现方法; [0011] 1, the proposed simply described I. 4SFEC pattern and encoding rules ITU_T G. 975. I did not mention the specific hardware implementation of the encoding and decoding;

[0012] 2、ITU_T G. 975. I建议中对I. 4SFEC中需要的不同的伽逻华域上的总线变换未曾提及。 [0012] 2, ITU_T G. 975. I never mentioned recommendation I. 4SFEC different pairs on the bus conversion gamma logic required field Hua.

发明内容 SUMMARY

[0013] 本发明所要解决的技术问题是解决应用SFEC编码规则的OTN系统存在总线位宽不匹配的问题。 [0013] The present invention solves the technical problem is a problem to solve mismatch bit wide bus application SFEC OTN system encoding rules.

[0014] 为了解决上述技术问题,本发明所采用的技术方案是提供一种应用SFEC的光传送网中总线位宽变换实现方法,包括以下步骤: [0014] To solve the above technical problem, the technical solution adopted in the present invention to provide a bus width conversion SFEC OTN applications implemented method, comprising the steps of:

[0015] S10、将从64位系统总线输入的OTN帧的数据按外码RS (1023,1007)编码规则编码后存入缓存M,缓存M由8块RAM构成,每块RAM的大小分别为1530 X 10,缓存M的读写时钟与系统总线时钟频率相同; [0015] S10, from the 64-bit data bus input of the OTN frame by the system after the outer code RS (1023,1007) coding rule cached M, M is eight RAM cache configuration, the size of each block of RAM, respectively 1530 X 10, the same as the write clock frequency of the system bus clock buffer of M;

[0016] S20、每次分别从缓存M的8块RAM中读取10个RS(1023,1007)编码数据并按内码BCH (2040,1952)编码规则编码后存入缓存N,缓存N由8块RAM构成,每块RAM的大小分别为244X64,缓存N的读写时钟与系统总线时钟频率相同; [0016] S20, respectively, each read from the RS 10 8 M in buffer RAM (1023,1007) the encoded data into the press code BCH (2040,1952) coding rule cache N, N from the buffer a RAM 8, the size of each block of RAM are 244X64, N cache read and write the same system clock and the bus clock frequency;

[0017] S30、依次从缓存N的8块RAM中输出64个BCH(2040,1952)编码数据至64位系统总线。 [0017] S30, sequentially output from the BCH 64 N 8 in the RAM buffer (2040,1952) the encoded data to a 64-bit system bus.

[0018] 上述方法中,缓存M中的RAM均为双口RAM,并以地址765为界划分为Al和BI两个区,读Al区时,写BI区,读BI区时,写Al区。 [0018] In the above method, the RAM cache M are dual-port RAM, the address and the boundary 765 is divided into two regions Al and BI, Al zone reading, writing area BI, BI zone reading, writing area Al .

[0019] 步骤SlO包括以下步骤: [0019] Step SlO comprises the steps of:

[0020] SlOl、根据SFEC外码RS (1023,1007)编码规则将缓存M的每一个RAM地址划分为RS (O)-RS (15) 16 组地址,其中RS (O)- RS (14)以RS (1023,1007)的缩短码RS (781,765)为编码规则,RS(15)以RS(778,762)为编码规则; [0020] SlOl, SFEC according to the outer code RS (1023,1007) each coding rule cache RAM address is divided into M RS (O) -RS (15) 16 group address, wherein the RS (O) - RS (14) to RS (1023,1007) codes shortened RS (781,765) coding rule, RS (15) to RS (778,762) coding rule;

[0021] S102、将从64位系统总线输入的一帧OTN数据依次写进缓存M的每块RAM中,写入的规则是,OTN帧中的FEC开销字节不写入缓存M,一帧OTN数据按照bit传送顺序以10X765为单位分别对应写入每块RAM中RS(0)-RS(15)对应的地址单元中,其中RS (O) -RS (7)分别对应Al区,RS⑶-RS (15)分别对应BI区,当开始写RAM的0#地址时,送出一个缓存M的BI区编码指示信号,当开始写765#地址时,送出一个缓存M的Al区编码指示信号。 [0021] S102, sequentially written from a 64-bit data bus input OTN system each M in the RAM cache, the rule is written, the FEC overhead bytes in the OTN frame is not written into the cache M, a OTN data transmission order in accordance with bit 10X765 units respectively corresponding to each block is written in the RAM RS (0) -RS (15) corresponding to an address unit, wherein the RS (O) -RS (7) area corresponding Al, RS⑶- RS (15) zone respectively BI, when starting writing the RAM address # 0, sending a signal indicative of a region encoding BI M cache when a write start address # 765, sends a signal indicating a coding region Al buffer of M.

[0022] 缓存N由8块相同的RAM构成,该RAM为双口RAM,并以地址122为界划分为A2区和B2区,读A2区时,写B2区,读B2区时,写A2区。 [0022] buffer N by like a RAM 8, the RAM is a dual port RAM, and the address 122 as the boundary is divided into A2 region and the B2 region, reading A2 region, the write region B2, reading region B2, write A2 Area.

[0023] 所述的步骤S20包括以下步骤: [0023] Step S20 comprises the steps of:

[0024] S201、当检测到缓存M的Al区编码指示信号时,缓存N—次读取缓存M中Al区RAM中的80bit数据,当检测到缓存M的BI区编码指示信号时,缓存N —次读取缓存M中BI区中的80bit数据; [0024] S201, when detecting the Al region encoding instruction signal M buffer, the buffer read times N- 80bit data buffer area of ​​the RAM in the Al M when detected BI region encoding instruction signal M buffer, the buffer N - M times the read data in the cache 80bit BI region;

[0025] S202、将缓存M输出的80bit数据依次分配到缓存N中的RAM中,其中RS (O) -RS (7)分别对应A2区,RS (8) -RS (15)分别对应B2区,当开始写RAM的0#地址时,送出一个缓存N的A2区编码指示信号,当开始写122#地址时,送出一个缓存N的B2区编码指示信号; [0025] S202, the 80bit data buffer are sequentially allocated to the M output of the RAM buffer N, where RS (O) -RS (7) respectively corresponding to areas A2, RS (8) -RS (15) respectively corresponding to region B2 when starting writing the RAM address # 0, sending a signal indicative of a coding region A2 N cache when a write start address # 122, sends a buffer zone B2 of the N coding instruction signal;

[0026] S203、缓存N中的每块RAM缓存两个外码编码后不同RS地址的数据;具体为1#RAM 缓存外码RS (O)和RS⑶中的编码数据,2#RAM缓存外码RS码字的1#和9#RS码编码数据,3#RAM缓存外码RS码字的2#和10#RS码编码数据,4#RAM缓存外码RS码字的3#和11#RS码编码数据,5#RAM缓存外码RS码字的4#和12#RS码编码数据,6#RAM缓存外码RS码字的5#和13#RS码编码数据,7#RAM缓存外码RS码字的6#和14#RS码编码数据,8#RAM缓存外码RS码字的7#和15#RS码编码数据; [0026] S203, each cache RAM cache data in N different addresses after two RS outer code encoding; 1 # RAM cache is specifically an outer code RS (O) and the coded data in RS⑶, 2 # RAM cache outer code 1 # and. 9 # RS code encoded data of the RS codeword, 3 # RAM cache outer code RS code word # 2 and 10 # RS code encoded data, 4 # RAM cache outer code RS code words 3 # and. 11 # RS code encoded data, # 4, and 12 is # RS codes the coded data # 5 the RAM cache outer code of the RS codeword, 6 # RAM cache outer code RS code words 5 # and 13 is # RS code encoded data, 7 # RAM cache outer code RS codeword # 6 and # 14 RS code encoded data, 8 # RAM cache outer code RS code words # 7 and # 15 RS code encoded data;

[0027] S204、当检测到缓存N中A2区编码指示信号时,从缓存N的B2区的第1#RAM的122#地址开始读操作,依次读完1#RAM的B2区后,接着读2#RAM的B2区,直到1_8#RAM的B2区数据都读完为止;当检测到缓存N的B2区编码指示信号时,从缓存N的A2区的第WRAM的0#地址开始读操作,依次读完1#RAM的A2区后,接着读2#RAM的A2区,直到1_8#RAM的A2区数据都读完为止。 After the [0027] S204, when detecting region A2 coding instruction signal N in the buffer, the first # 122 # 1 RAM address buffer zone B2 of the N read operation begins sequentially reading area B2 of 1 # RAM, then read 2 # RAM area of ​​B2, B2 until the 1_8 # RAM area until the read data; when the detected coding indication signal buffer zone B2 is N, from the first address # 0 WRAM region A2 of the N cache read operation begins, sequentially reading after the 1 # RAM region A2, then A2 is read 2 # RAM area, data area A2 until 1_8 # RAM are read so far.

[0028] 本发明还提供了一种应用SFEC的光传送网中总线位宽变换电路,包括缓存M和缓存N,缓存M由8块RAM构成,每块RAM的大小分别为1530 X 10 ;缓存N由8块RAM构成,每块RAM的大小分别为244X64。 [0028] The present invention also provides an application SFEC bus width conversion circuit in an optical transport network includes a buffer cache M and N, M consists buffer RAM 8, the size of each block of RAM are 1530 X 10; Cache N consists of eight RAM, the size of each block of RAM, respectively 244X64.

[0029] 上述电路中,缓存M中的RAM均为双口RAM,该RAM以地址765为界划分为Al和BI两个区,读Al区时,写BI区,读BI区时,写Al区。 When [0029] the above-described circuit, the RAM cache M are dual-port RAM, the address of the RAM 765 as the boundary is divided into two regions Al and BI, Al zone reading, writing area BI, BI read area, write Al Area.

[0030] 缓存N中的RAM均为双口RAM,并以地址122为界划分为A2区和B2区,读A2区时,写B2区,读B2区时,写A2区。 [0030] N in the cache RAM are dual-port RAM, and the address 122 is divided into boundary region A2 and region B2, A2 zone reading, writing region B2, B2 zone reading, writing area A2.

[0031] 本发明,通过对缓存的读写操作的控制,完成了输入64位宽到外码所要求的80位宽的总线变换以及从80位宽的总线再到64位宽总线的变换,实现方法简便有效、操作性强。 [0031] The present invention, by controlling the read and write operations to the cache, the complete 64-bit wide input bit wide bus 80 to the outer code conversion desired and then converted from 80 bit wide bus 64 bit wide bus, implementation simple and effective, easy to operate.

附图说明 BRIEF DESCRIPTION

[0032] 图I为OTN帧结构示意图; [0032] Figure I is a schematic view of the OTN frame;

[0033] 图2为SFEC结构示意图;[0034] 图3为SFEC外码RS (1023,1007)编码示意图; [0033] FIG. 2 is a schematic structural SFEC; [0034] FIG. 3 is a SFEC outer code RS (1023,1007) encoding a schematic view;

[0035] 图4为SFEC内码BCH (2040,1952)编码示意图; [0035] FIG. 4 is a (2040,1952) encoding the BCH schematic SFEC inner code;

[0036] 图5为本发明的流程示意图; [0036] FIG. 5 is a schematic flow invention;

[0037] 图6为本发明缓存M结构示意图; [0037] Fig 6 a schematic structural diagram of the present invention, the cache M;

[0038] 图7为本发明缓存N结构示意图。 [0038] Figure 7 a schematic structure of the present invention is N cache.

具体实施方式 detailed description

[0039] 本发明提供了一种应用SFEC的光传送网中总线位宽变换的实现方法及电路,用于实现OTN帧的64位输入总线位宽到SFEC外码RS(1023,1007)编码处理所需的80位总线位宽的变换处理以及经SFEC外码RS(1023,1007)编码处理后80位总线位宽到内码BCH(2040,1952)编码所需的64位总线位宽的变换处理,以适应SFEC外码RS (1023,1007)编码处理以及SFEC内码BCH (2040,1952)编码处理。 [0039] The present invention provides a (1023,1007) coding SFEC implemented method of treating one and the bus width converting circuit OTN applications, the input 64-bit bus width for the realization of the OTN frame to the outer code RS SFEC conversion process required 80 bit wide bus and 64-bit wide bus 80 to the bus width required BCH code (2040,1952) the encoded (1023,1007) coding process by the outer code RS transform SFEC process to accommodate SFEC outer code RS (1023,1007) coding and the code SFEC BCH (2040,1952) coding process.

[0040] 为更好地理解本发明,下面首先介绍SFEC外码RS(1023,1007)和内码BCH(2040,1952)的编码原理。 [0040] For a better understanding of the present invention, the following first describes SFEC outer code RS (1023,1007) and an inner code BCH (2040,1952) coding principle.

[0041] ITU_T G. 709建议中规定的OTN帧结构如图I所示,该帧结构为4行、4080列的块状字节结构,其中前面16列为OTN的开销区域、17〜3824列之间为净荷区域、3825〜4080列之间为前向纠错FEC开销区域,因此,一个完整的OTN帧比特数为:4X4080X8 =130560bits,ITU_T G. 975. I中规定一个完整OTN帧中将最先传送的比特编号为otu [O],紧接着otu [I],一直编号到最后传送的比特otu [130559],至此一个完整的OTN帧编号完毕。 [0041] predetermined ITU_T G. 709 Recommendation OTN frame structure shown in Figure I, the structure is a frame structure byte block 4 rows, 4080, wherein as the overhead area 16 in front of the OTN, the column 17~3824 between between payload area, 3825~4080 column to a forward error correction FEC overhead area, and therefore, the number of bits of a complete OTN frame: 4X4080X8 = 130560bits, a predetermined full OTN frame in ITU_T G. 975. I the number of bits transmitted as the first otu [O], followed otu [I], up to the last transmitted number of bits otu [130559], so far a complete number of the OTN frame is completed.

[0042] ITU_T G. 795. I中I. 4超强前向纠错SFEC的结构见图2所示,该超强FEC由外码和内码级联而成,外码为伽逻华域GF(21°)上的RS(1023,1007),内码为伽逻华域GF(2n)上的BCH(2040,1952),其中RS (1023,1007)为多进制BCH 码,BCH(2040,1952)为二进制BCH码。 [0042] In the front ITU_T G. 795. I I. 4 SFEC error correction super Figure 2 shows the structure of the super FEC by the inner code and the outer code concatenation, an outer code is gamma logic HUAYU RS (1023,1007) on the (21 °) GF, the code BCH (2040,1952) on gamma logic Chinese domain GF (2n), where RS (1023,1007) is ary BCH code, BCH ( 2040,1952) is a binary BCH code.

[0043] 图3为外码RS (1023,1007)的编码规则,根据OTN帧结构,OTN帧中除去FEC开销字节后的总bit数为:4X3824X8 = 122368bits,这些比特被分成16组,前15组用RS(1023,1007)码的缩短码RS (781,765)进行编码,这15个RS (1023,1007)码的缩短码RS (781,765)依次编号为RS (O)-RS (14),最后一组第16组用RS (1023,1007)码的缩短码RS (778,762)进行编码并编号为RS(15);将OTN帧中最先传送的bit编号为odu[0],紧接着传送的编号为odu[l],依次类推,直到编号到odu[122367]为止,此时一个完整OTN帧编号结束,编号中不包括OTN中的FEC开销字节。 [0043] FIG. 3 is an outer code RS (1023,1007) coding rule, the total number of bit byte FEC overhead is removed after the OTN frame, the OTN frame according to: 4X3824X8 = 122368bits, the bits are divided into 16 groups, the former 15 shortened RS code with group RS (1023,1007) code (781,765) for encoding, to shorten the 15 RS code RS (1023,1007) code (781,765) are numbered RS (O) -RS (14) reduced code RS last group of 16 with a group RS (1023,1007) code (778,762) RS encoded and numbered (15); the bit number of the OTN frame is transmitted first ODU [ 0], followed by transfer of the number of odu [l], and so on, until the number odu [122367], at which point a complete end OTN frame number, number does not include the FEC overhead bytes in the OTN. 由此,整个外码编码流程如下:odu[0]-odu[9]这10比特构成第一个RS(781,765)码RS(O)的第一个码元符号,odu[10]-odu[19]构成RS(O)的第二个码元符号,依次类推,odu[7640]-odu[76499]构成RS(O)的第765个码元符号,至此RS(O)码的信息部分编码完毕,紧接着产生160比特的RS(O)码的效验比特,整个一个完整的RS(O)码编码完毕,ITU_T G. 975. I中规定将odu [O]-odu [7649]这7650比特对应的依次编号为OTN帧的otu[0]-otu[7649],RS(O)码的160比特效验位顺次的编号为otu [7650]-otu [7809],这样就将第一个完整的RS(O)码的所有码元对应地映射到了OTN帧的相应位置。 Thus, the entire outer code encoding process is as follows: odu [0] -odu [9] which defines a first 10-bit RS (781,765) code RS (O) symbol in the first symbol, odu [10] - odu [19] the second symbol symbols RS (O), and so on, [7640] [76499] 765 symbols constituting the symbol RS (O), the information odu -odu point RS (O) code portion of the coding is completed, followed by generating a 160-bit RS (O) efficacy bit code, a whole full RS (O) of coded symbols, ITU_T G. 975. I specified in the odu [O] -odu [7649] this 7650 corresponding to the bit sequence number of the OTN frame otu [0] -otu [7649], 160 successive RS (O) than the effects of parity bit code numbered otu [7650] -otu [7809], this will be the first complete all the symbols RS (O) mapped to the code corresponding to the respective position of the OTN frame.

[0044] 按照这种规律,依次对RS(1)_RS(15)进行编码,在编码RS(15)也就是RS(778,762)的最后一个信息码兀符号也就是第762个码兀符号时,由于此时OTN巾贞只剩下odu[122360]-odu[122367]这8个比特未进行编码,故在编码RS(15)的第762个码元符号时,将odu[122360]-odu[122367]这8个比特置于第762个码元符号的低位,高位加2bit的0,这样凑成10比特的码元符号参与RS (15)码的后面的160比特效验位计算,但在传送时,该2bit是不传送的,仅仅用于效验位的计算,也不会对应的映射到OTN巾贞的区域中,这样处理完成后,即可接着进行RS (15)最后160比特效验位的产生,由此可以完成SFEC外码RS (1023,1007)对一个完整OTN帧的编码。 [0044] According to this law, sequentially RS (1) _RS (15) encoding (15) is RS (778,762) code Wu last information symbol which is the first 762 yards Wu encoded symbols RS when, at this time since the OTN towel Zhen only odu [122360] -odu [122367] the eight bits are not encoded, so in the 762 symbol encoding symbol RS (15) will odu [122360] - odu [122367] the eight lower bits to symbol 762 symbols, plus high 2bit 0, such symbols make up a 10-bit symbol participation RS (15) 160 calculated specific effects behind the parity bit code, but when transmitting, the transmission 2bit is not only used to calculate efficacy bits, not mapped to a region corresponding to the OTN towel Zhen, after this process is completed, can be followed by RS (15) effects posterior than the last 160 bit generation, thereby to complete the outer code SFEC RS (1023,1007) encoding a complete OTN frame.

[0045] 在SFEC外码RS (1023,1007)编码的基础上还需要进行内码BCH(2040,1952)的编码,OTN帧外码编码完成后,产生的总的比特数为:不包括FEC开销字节的OTN帧的总比特数122368+所有的效验比特数2560 = 124928,对应的编号为otu [O]-otu [124927]; [0045] The need for the inner code BCH (2040,1952) code SFEC outer code based on RS (1023,1007) on the encoding, the total number of bits after outer code encoding the OTN frame is completed, it is generated: FEC not included total number of bits of the overhead byte of the OTN frame 122368+ efficacy all numbers 124928 bits = 2560, corresponding numbered otu [O] -otu [124927];

[0046] 内码BCH(2040,1952)编码规则见图4所示,ITU_T G. 975. I建议中规定外码编码后的124928bit分成64组,每组1952bit,由此构成64个内码BCH(2040,1952)的信息码元部分,64个内码BCH(2040,1952)依次编号为BCH[O]、BCH[1]直到BCH[63],BCH码信息码元分配规则如下:otu[0]为BCH(O)码的第一个码元,otu [I]为BCH(I)码的第一个码元,依次类推,otu[63]为BOK63)码的第一个码元,otu[64]为BCH(O)码的第二个码元,循环重复,这样124928bit刚好映射到64个BCH(2040,1952)码的信息码元位置,每个BCH(2040,1952)码根据各自信息码元会产生88bit的效验码元,这64组88bit的效验码元映射分配规则如下:BCH[0]的第一个效验码元分配为otu[124928],BCH[1]的第一个效验码元分配为otu [124929],依次类推,BCH[63]的第一个效验码元分配为otu [124991],BCH[0]的第二个效验码元分配为otu [124992],循环重复直到所有的效验码元分配完 [0046] The inner code BCH (2040,1952) coding rule shown in Figure 4, the proposed predetermined outer code encoding 124928bit divided into 64 groups ITU_T G. 975. I, each 1952bit, thereby constituting the inner code BCH 64 (2040,1952) of the information symbol section, within 64 yards BCH (2040,1952) are numbered BCH [O], BCH [1] until the BCH [63], BCH code information symbol allocation rules are as follows: otu [ 0] as the first symbol of BCH (O) codes, otu [I] as the first symbol of BCH (I) codes, and so on, otu [63] is the first symbol BOK63) code, otu [64] the second symbol of BCH (O) code, the cycle is repeated, so that just 124928bit 64 BCH is mapped to the location information symbols (2040,1952) code, each BCH (2040,1952) code according to the each information symbol will produce efficacy symbols 88bit, the efficacy symbol mapping allocation rule of the 64 group 88bit follows: BCH [0] of the first-tested symbols allocated otu [124928], BCH [1] of the first an efficacy symbols allocated otu [124929], and so on, BCH [63] of the first-tested symbols allocated otu [124991], BCH [0] posteriori symbol allocation second effect is otu [124992], the cycle is repeated until all symbols have been distributed efficacy ,这样经过SFEC的外码和内码编码以后产生了一个完整OTN帧的所有比特,124928+64X88 = 130560bit,图4中的bit传送顺序为从左至右,从上至下。 , So that after SFEC through outer code and an inner code encoding to generate a complete all the bits of the OTN frame, 124928 + 64X88 = 130560bit, bit transmission order is from left to right in FIG. 4, from top to bottom.

[0047] 本发明提供的方法是使用一定数量的RAM来实现ITU_T G. 975. I中SFEC编码输入总线64位宽到SFEC外码RS (1023,1007)所要求的以10为倍数的80位总线位宽,再用一定数量的RAM来实现外码编码后的以10为倍数的80位总线位宽到总线位宽为64的转换,以满足内码BCH(2040,1952)的编码要求,如图5所示,具体包括以下步骤: [0047] The method of the present invention provides the use of a certain amount of RAM that ITU_T G. 975. I SFEC the coded input bit wide bus 64 to the SFEC outer code RS (1023,1007) required multiple of 10 to 80 bus width, and then a certain amount of RAM that the outer code encoding multiple of 10-bit wide bus 80 to the bus width for the conversion of 64 to meet the code BCH (2040,1952) coding requirements, 5, includes the following steps:

[0048] S10、将从64位系统总线输入的OTN帧的数据按外码RS (1023,1007)编码规则编码后存入缓存M,缓存M由8块RAM构成,每块RAM的大小分别为1530 X 10,缓存M的读写时钟与系统总线时钟频率相同; [0048] S10, from the 64-bit data bus input of the OTN frame by the system after the outer code RS (1023,1007) coding rule cached M, M is eight RAM cache configuration, the size of each block of RAM, respectively 1530 X 10, the same as the write clock frequency of the system bus clock buffer of M;

[0049] S20、每次分别从缓存M的8块RAM中读取10个RS(1023,1007)编码数据并按内码BCH (2040,1952)编码规则编码后存入缓存N,缓存N由8块RAM构成,每块RAM的大小分别为244X64,缓存N的读写时钟与系统总线时钟频率相同; [0049] S20, respectively, each read from the RS 10 8 M in buffer RAM (1023,1007) the encoded data into the press code BCH (2040,1952) coding rule cache N, N from the buffer a RAM 8, the size of each block of RAM are 244X64, N cache read and write the same system clock and the bus clock frequency;

[0050] S30、依次从缓存N的8块RAM中输出64个BCH(2040,1952)编码数据至64位系统总线。 [0050] S30, sequentially output from the BCH 64 N 8 in the RAM buffer (2040,1952) the encoded data to a 64-bit system bus.

[0051] 步骤SlO的具体实施如图6所示,缓存M由8块RAM构成,每块RAM(双口RAM,A 口写,B 口读)的深度和宽度分别为1530X10,刚好可以将一个完整的OTN帧中除去FEC开销字节后的所有数据写进8块RAM中,每块RAM以地址765为界,分成Al区(地址空间0-764)和BI区(地址空间765-1529),当写Al区,就读BI区,当写BI区时,就读Al区,输入的64bit 数据中MSB (MostSignificant Bit,最高有效位)为bit O, LSB (Lest SignificantBit,最低有效位)为bit 63。 [0051] Step SlO particular embodiment shown in Figure 6, consists of 8 M cache RAM, each RAM (dual port RAM, a write port A, B port read) depth and width are 1530X10, may be just a remove all the FEC overhead bytes of data written to complete the OTN frame in the RAM 8, each address in RAM 765 as a boundary, into a region Al (0-764 address spaces) and BI area (address space 765-1529) when writing Al areas, enrolled BI area, when writing BI area, attending Al district, 64bit data input MSB (MostSignificant bit, the most significant bit) is bit O, LSB (Lest SignificantBit, the least significant bit) is bit 63 . [0052] 缓存M的写方法为:在OTN帧起始时刻的第一个时钟周期之内,将输入的64位宽数据中的60bit写进1#-6#RAM中的0#地址,并寄存4bit数据,其中1#RAM的0#地址写输入的64bit数据的9:0,2#RAM的0#地址写输入的64bit数据的19:10,3#RAM的0#地址写输入的64bit数据的29:20,4#RAM的0#地址写输入的64bit数据的39:30,5#RAM的0#地址写输入的64bit数据的49:40,6#RAM的0#地址写输入的64bit数据的59:50,1#_6#RAM中的0#地址的数据是在一个时钟周期之内同时写进去的,下一个时钟周期,同时写7#、8#RAM的0#地址,同时写1#-4#RAM的1#地址,其中7#RAM的写数据为:本时钟周期的5:Obit数据对应放进IObit中的[9:4],上一时钟周期寄存的4bit数据[63:60]放进IObit中的[3:0],8#RAM的0#地址写本时钟周期输入的64bit数据的15:6,1#RAM的1#地址写本时钟周期输入的64bit数据的25:16,2#RAM的1#地址写本时钟周期输入的64bit数据的35:26 Writing method [0052] M is the buffer: in the first clock cycle starting time of the OTN frame, 64-bit wide data inputted 60bit 1 # -6 # RAM written in addresses # 0, and 4bit data register, wherein the address # 0. 1 9 # write input of the RAM data 64bit: 0 # 0,2 # 64bit address of the RAM write data input of 19: 10,3 # RAM # 0 of the write address input of 64bit 39 # 0 # 20,4 RAM write address input of the 64bit data:: 49 # 0 # 30,5 write address of the RAM data input 64bit: 0 # 40,6 # RAM address 29 to write the input data 59 64bit data: 50,1 # _6 # RAM # 0 is the address of the data within one clock cycle of the same time written into the next clock cycle, while writing 7 #, 8 # RAM addresses 0 #, while write 1 # -4 # RAM addresses 1 #, 7 # RAM where data is written: the clock cycle 5: Obit into data corresponding to the IObit [9: 4], 4bit data of a clock period register [ 63:60] [3 placed in IObit: 0], 8 # RAM write address # 0 64bit data of the present period of the input clock 15: 1 to # 6,1 # RAM write address period of the input clock of the present 64bit data 25 : 1 # 16,2 # RAM write address according to a clock period of the input data 64bit 35:26 ,3#RAM的1#地址写本时钟周期输入的64bit数据的45:36,4#RAM的1#地址写本时钟周期输入的64bit数据的55:46,同时寄存本时钟周期的[63:56]bit的数据,依照这种写规律,完成整个OTN帧数据的写入。 1 # 3 # RAM write address 64bit data of the present period of the input clock of 45: 1 55:46 # 36,4 # RAM write address present clock cycle 64bit input data, while the present clock cycle register [63:56] bit data, in accordance with the laws of this writing, writes the entire OTN frame data is completed. 按照外码RS(1023,1007)编码的RS(15)中的第762 个码元符号的填充2bit “O”的规则,在第5#RAM的第1529#地址写数据时,数据位的[9:8]bit填充2个bit “O”。 In accordance with the outer code RS 2bit "O" fill rule (1023,1007) RS (15) in the encoded symbol 762 symbols, to write data in the first 5 # RAM address # 1529, the data bits [ 9: 8] bit filling two bit "O".

[0053] 每当写方向开始写RAM的0#地址时,送出一个时钟宽度的高电平BI区RS编码指示信号,以指示RS编码器可以从缓存的BI区中读取数据开始RS编码,当写方向开始写765#地址时,送出另一个时钟宽度的高电平Al区RS编码指示信号,以指示RS编码器可以从缓存的Al区中读取数据开始RS编码,经过这样的写方法后,RS (O)-RS (7)的第一个起始码元符号分别落在了缓存M的Al区中的不同的8块RAM上,具体为:RS(0)的第一个码元符号落在了1#RAM,RS(I)的第一个码元符号落在了6#RAM,RS (2)的第一个码元符号落在了3#RAM,RS (3)的第一个码元符号落在了8#RAM,RS (4)的第一个码元符号落在了5#RAM,RS(5)的第一个码元符号落在了2#RAM,RS(6)的第一个码元符号落在了7#RAM,RS(7)的第一个码元符号落在了4#RAM,这样就为一个时钟周期内同时读出8块RAM中Al区的RS(O)-RS(7)的码元符号创造了条件。 When the [0053] direction whenever a write start address # 0 of the write RAM, sends a high level clock width BI on RS coding instruction signal to instruct the RS encoder RS-encoded data can be read from the beginning of the buffer area BI, when writing direction write start address # 765, sends another clock width high Al on RS coding instruction signal to instruct the RS encoder RS-encoded data can be read from the start in the area of ​​the buffer Al, after such writing method after, RS (O) -RS (7) of the first start symbol symbols are landed on the area of ​​the buffer M Al in eight different RAM, specifically: RS (0) of a first code metasymbol fell 1 # RAM, RS (I) in the first symbol of the symbol falls 6 # RAM, RS (2) in the first symbol of the symbol falls 3 # RAM, RS (3) of the the first symbol of the symbol falls 8 # RAM, RS (4) in the first symbol of the symbol falls 5 # RAM, RS (5) in the first symbol of the symbol falls 2 # RAM, RS (6) in the first symbol of the symbol falls 7 # RAM, RS (7) in the first symbol of the symbol falls 4 # RAM, so that a clock cycle the RAM 8 is read out Al region RS (O) -RS (7) symbols symbols to create the conditions. 同理RS(8)-RS(15)的第一个起始码元符号分别落在了缓存M的BI区中不同的8块RAM上。 Similarly RS (8) -RS (15) in a first start symbol symbols are landed on a different area of ​​the buffer RAM BI 8 M's. 这样也为一个时钟周期内同时读出8块RAM中BI区的RS(8)-RS(15)的码元符号创造了条件。 This also is one clock cycle the read block RS 8 BI area RAM (8) -RS (15) symbols to create the conditions symbols.

[0054] 缓存M读方法为:当检查到一个时钟宽度的高电平Al区RS编码指示信号时,开始读缓存M中的8块RAM的Al区,每个时钟周期读取8块RAM中的不同的地址获得RS(O)-RS(7)中相同序号的码元符号,这样每个时钟周期都能获得RS(0)-RS(7)中的每个RS码IObit总共80bit数据,例如,当Al区RS编码指示信号为高时: [0054] M read caching method: When a clock to check the width of the high level instruction signal RS encoding region Al, Al starts reading area of ​​the buffer RAM 8 M in each clock cycle, reads the RAM 8 different address obtained RS (O) -RS (7) in the same symbol number of symbols so that each clock cycle can get RS (0) -RS IObit each RS code (7) total 80bit data, For example, when the RS region coding indication signal is high Al:

[0055] 第一个时钟周期读取方法如下: [0055] The first clock cycle, reads as follows:

[0056] 1#RAM的0#地址,得到RS (O)第I号码元IObit数据; # 0 Address [0056] 1 # RAM to give RS (O) number of I element IObit transactions;

[0057] 2#RAM的478#地址;得到RS (5)第I号码元IObit数据; Address # 478 [0057] 2 # RAM; and give RS (5) number of I element IObit transactions;

[0058] 3#RAM的191#地址;得到RS⑵第I号码元IObit数据; Address # 191 [0058] 3 # RAM; a number I of metadata obtained RS⑵ IObit transactions;

[0059] 4#RAM的669#地址;得到RS (7)第I号码元IObit数据; Address # 669 [0059] 4 # RAM; and give RS (7) number of I element IObit transactions;

[0060] 5#RAM的382#地址;得到RS⑷第I号码元IObit数据; Address # 382 [0060] 5 # RAM; a number I of metadata obtained RS⑷ IObit transactions;

[0061] 6#RAM的95#地址;得到RS (I)第I号码元IObi t数据; Address # 95 [0061] 6 # RAM; and obtain the RS (I) of I element number IObi t transactions;

[0062] 7#RAM的573#地址;得到RS (6)第I号码元IObit数据;[0063] 8#RAM的286#地址;得到RS (3)第I号码元IObit数据; Address # 573 [0062] 7 # RAM; and give RS (6) number of I element IObit transactions; Address # 286 [0063] 8 # RAM; and give RS (3) number of I element IObit transactions;

[0064] 第二个时钟周期读取方法如下: [0064] The second clock cycle to read as follows:

[0065] 2#RAM的0#地址,得到RS (O)第2号码元IObit数据; # 0 Address [0065] 2 # RAM to give RS (O) 2 IObit data element number;

[0066] 3#RAM的478#地址;得到RS (5)第2号码元IObit数据; Address # 478 [0066] 3 # RAM; and give RS (5) the second number IObit meta data;

[0067] 4#RAM的191#地址;得到RS⑵第2号码元IObit数据; Address # 191 [0067] 4 # RAM; a number to obtain a second element RS⑵ IObit transactions;

[0068] 5#RAM的669#地址;得到RS (7)第2号码元IObit数据; Address # 669 [0068] 5 # RAM; and give RS (7) the second element IObit number data;

[0069] 6#RAM的382#地址;得到RS⑷第2号码元IObit数据; Address # 382 [0069] 6 # RAM; a number to obtain a second element RS⑷ IObit transactions;

[0070] 7#RAM的95#地址;得到RS (I)第2号码元IObit数据; Address # 95 [0070] 7 # RAM; and give RS (I) the second number IObit data element;

[0071] 8#RAM的573#地址;得到RS (6)第2号码元IObit数据; Address # 573 [0071] 8 # RAM; and give RS (6) the second number IObit data element;

[0072] 1#RAM的287#地址;得到RS⑶第2号码元IObit数据; Address # 287 [0072] 1 # RAM; a number to obtain a second element RS⑶ IObit transactions;

[0073] 按照这种规律读下去可以每个时钟周期获得8个不同RS码的数据,从而可以进行8个不同RS码的并行编码处理,虽然每个RS码编码产生效验bit时,会停止从缓存M中读取数据,但由于80 > 64,不会造成数据在缓存M中的堆积现象。 [0073] Data can be obtained for each clock cycle 8 different RS codes in accordance with this law read on, so that the encoding process can be performed in parallel eight different RS code, although the code generator of each RS code efficacy 'bit, from the stops M cache read data, but because 80> 64, will not cause the phenomenon of accumulation of data in the cache M.

[0074] 当检查到一个时钟宽度的高电平BI区RS编码指示信号时,开始读缓存M中的8块RAM的BI区,每个时钟周期读取8块RAM中的不同的地址获得RS(8)-RS(15)中相同序号的码元符号,这样每个时钟周期都能获得RS (8) -RS (15)中的每个RS码IObit总共SObit数据,例如,当BI区RS编码指示信号为高时: [0074] When a clock to check the width of the region of high BI RS coding indication signal to start reading the RAM 8 BI area of ​​the buffer is M, each clock cycle the RAM 8 to read a different address obtained RS (8) -RS symbols symbol (15) in the same number, so that each clock cycle can get RS (8) -RS IObit in each RS code (15) in total SObit data, for example, when BI on RS coding instruction signal is high:

[0075] 第一个时钟周期读取方法如下: [0075] The first clock cycle, reads as follows:

[0076] 1#RAM的765#地址,得到RS⑶第I号码元IObit数据; Address # 765 [0076] 1 # RAM, the number I of metadata obtained RS⑶ IObit transactions;

[0077] 2#RAM的1243#地址;得到RS (13)第I号码元IObit数据; Address # 1243 [0077] 2 # RAM; and obtain (13) of the RS data I IObit element number;

[0078] 3#RAM的956#地址;得到RS (10)第I号码元IObit数据; Address # 956 [0078] 3 # RAM; and obtain (10) of the RS data I IObit element number;

[0079] 4#RAM的1434#地址;得到RS (15)第I号码元IObit数据; Address # 1434 [0079] 4 # RAM; and give RS (15) number of I element IObit transactions;

[0080] 5#RAM的1147#地址;得到RS (12)第I号码元IObit数据; Address # 1147 [0080] 5 # RAM; and give RS (12) number of I element IObit transactions;

[0081] 6#RAM的860#地址;得到RS (9)第I号码元IObit数据; Address # 860 [0081] 6 # RAM; and give RS (9) number of I element IObit transactions;

[0082] 7#RAM的1338#地址;得到RS (14)第I号码元IObit数据; Address # 1338 [0082] 7 # RAM; and give RS (14) number of I element IObit transactions;

[0083] 8#RAM的1051#地址;得到RS(Il)第I号码元IObit数据; Address # 1051 [0083] 8 # RAM; and give RS (Il) number of I element IObit transactions;

[0084] 第二个时钟周期读取方法如下: [0084] The second clock cycle to read as follows:

[0085] 2#RAM的765#地址,得到RS⑶第2号码元IObit数据; Address # 765 [0085] 2 # RAM to obtain the second number RS⑶ metadata IObit transactions;

[0086] 3#RAM的1243#地址;得到RS (13)第2号码元IObit数据; Address # 1243 [0086] 3 # RAM; and obtain (13) a second number of data element IObit the RS;

[0087] 4#RAM的956#地址;得到RS (10)第2号码元IObit数据; Address # 956 [0087] 4 # RAM; and give RS (10) a second number IObit data element;

[0088] 5#RAM的1434#地址;得到RS (15)第2号码元IObit数据; Address # 1434 [0088] 5 # RAM; and give RS (15) a second number IObit data element;

[0089] 6#RAM的1147#地址;得到RS (12)第2号码元IObit数据; Address # 1147 [0089] 6 # RAM; and give RS (12) a second number IObit data element;

[0090] 7#RAM的860#地址;得到RS (9)第2号码元IObit数据; Address # 860 [0090] 7 # RAM; and give RS (9) of the second element IObit number data;

[0091] 8#RAM的1338#地址;得到RS (14)第2号码元IObit数据; Address # 1338 [0091] 8 # RAM; and give RS (14) a second number IObit data element;

[0092] 1#RAM的1052#地址;得到RS(Il)第2号码元IObit数据; Address # 1052 [0092] 1 # RAM; and give RS (Il) IObit second data element number;

[0093] 依此规律依次读取数据,由此即可以完成输入数据总线64位宽到输出总线80位宽的转换处理。 [0093] so the law of reading data sequentially, i.e. whereby complete 64-bit wide input data bus to the output bus 80 bits wide conversion process.

[0094] 步骤S20具体实施见图7所示,缓存N由8 ±夹RAM构成,每块RAM (双口RAM,A 口写,B 口读)的深度和宽度分别为244X64,刚好可以将OTN帧经外码RS (1023,1007)处理后的数据写进8块RAM中,每块RAM以地址122为界,分成A2区(地址空间0-121)和B2区(地址空间122-243),当写A2区,就读B2区,当写B2区时,就读A2区,1-8#RAM的A2区对应分别装载RS (O) -RS (7)的数据,而1-8#RAM的B2区对应分别装载RS (8) -RS (15)数据。 [0094] Step S20 in Figure 7. In particular embodiments, the buffer consists of N RAM 8 ± folder, each RAM (dual port RAM, A write port, B port read) depth and width were 244X64, it may be just OTN frame is an outer code RS (1023,1007) the processed data written into the RAM 8, each address in RAM 122 as a boundary, into a region A2 (address space 0-121) and B2 region (address spaces 122-243) , when the write region A2, B2 school district, when a write zone B2, A2 region studied, 1-8 # RAM and A2 respectively correspond to the loading region RS (O) (7) -RS data, while the 1-8 # RAM B2, respectively corresponding to the loading region RS (8) -RS (15) data.

[0095] 缓存N写方法为:当检查到一个时钟宽度的高电平A2区RS编码指示信号时,可以同时收到RS(0)、RS (I)、RS (2)、RS (3)、RS (4)、RS (5)、RS (6)和RS (7)编码后的第1# 码元共计8X10 = 80bit,分配RS(O)的IObit数据给1#RAM的A2区,分配RS(I)的IObit数据给2#RAM的A2区,分配R S⑵的IObit数据给3#RAM的A2区,分配RS (3)的IObit数据给4#RAM的A2区,分配RS⑷的IObit数据给5#RAM的A2区,分配RS(5)的IObit数据给6#RAM的A2区,分配RS (6)的IObit数据给7#RAM的A2区,分配RS (7)的IObit数据给8#RAM的A2区,这样总线位宽虽然是80bit的数据,但经过分配以后,每块RAM每个时钟周期只有IObit数据,由于每块RAM的宽度为64bit,因此必须等到各个RAM的A2 口数据凑齐64bit数据后才执行1_8#RAM的写动作。 [0095] N write cache method: When a clock is to check the width of the high level A2 on RS coding indication signal may be received RS (0), RS (I), RS (2) simultaneously, RS (. 3) , RS (4), RS (5), RS (6) and RS (7) encoded # first symbol total 8X10 = 80bit, IObit data distribution RS (O) to 1 # RAM A2 of the area allocated IObit data RS (I) of IObit data to 2 # RAM of the area A2, assigned R S⑵ of IObit data to the 3 # RAM of the area A2, assigned RS (3) to 4 # RAM of the area A2, assigned IObit data RS⑷ of IObit data IObit data IObit data to 5 # RAM of the area A2, assigned RS (5) to the 6 # RAM of the area A2, assigned RS (6) to 7 # RAM of the area A2, assigned RS (7) to 8 #RAM the region A2, so that although the data bus width of 80bit, but after dispensing, each RAM only IObit data every clock cycle, since the width of each RAM for 64bit, it is necessary to wait until each of the RAM data port A2 1_8 # RAM write operation to cobble together a 64bit data after the execution. 其中2#RAM的0#地址64bit数据必须等到RS(O)在1#RAM的A2区中写完之后才能进行写该地址的操作,由于2#RAM的0#地址的写口数据的低2位来自于RS(O)码数据写完1#RAM的A2区间后剩下的。 Wherein the address # 0 # 2 64bit data must wait until the RAM is RS (O) to be written after the address is finished in 1 # RAM area A2, due to the low data write port address 0 # 2 # 2 of the RAM after bit from RS (O) A2 code data written section 1 # RAM remaining. 其他1#,3#_8#RAM中也存在这种写处理的方法。 Other 1 #, 3 # _8 # RAM write process in this method are also present.

[0096] 每块RAM凑齐64bit数据方法如下,以1#和2#RAM为例(3#_8#RAM操作方法一样),输入的8个IObitRS码数据中MSB为bit 0,LSB为bit 9 : [0096] Each RAM 64bit data put together as follows to # 1 and # 2 as an example RAM (3 # _8 # RAM the same method of operation), the input code data 8 IObitRS MSB is bit 0, LSB for the bit 9 :

[0097] 在收到RS (O)-RS (7)的第l#10bit码元的第I个时钟周期里,首先拼凑RAM的写 [0097] In received RS (O) -RS (7) of l # 10bit I-th symbol clock cycle, the first RAM write patchwork

口数据: Port Data:

[0098] 1#RAM 的A2 口写数据[9:0] = RS(O)的l#10bit 码元; [0098] 1 # RAM port A2 of the write data [9: 0] = RS (O) of l # 10bit symbols;

[0099] 2#RAM 的A2 口写数据[11:2] =RS(I)的l#10bit 码元; [0099] 2 # RAM port A2 of the write data [11: 2] = RS (I) is l # 10bit symbols;

[0100] 在收到RS(O)-RS(7)的第2#10bit码元的第2个时钟周期里,寄存RAM的写口数据如下: [0100] In received RS (O) -RS (7) 2 # 10bit of the second symbol clock cycle, the write port RAM data register as follows:

[0101] 1#RAM 的A2 口写数据[19:10] =RS(O)的2#10bit 码元; [0101] 1 # RAM port A2 of the write data [19:10] = RS (O) 2 # 10bit of symbols;

[0102] 2#RAM 的A2 口写数据[21:12] =RS(I)的2#10bit 码元; [0102] 2 # RAM port A2 of the write data [21:12] = RS (I) is 2 # 10bit symbols;

[0103] 在收到RS(O)-RS(7)的第3#10bit码元的第3个时钟周期里,寄存RAM的写口数据如下: [0103] In received RS (O) -RS (7) of 3 # 10bit third symbol clock cycle, the write port RAM data register as follows:

[0104] 1#RAM 的A2 口写数据[29:20] =RS(O)的3#10bit 码元; [0104] 1 # RAM port A2 of the write data [29:20] = RS (O) 3 # 10bit of symbols;

[0105] 2#RAM 的A2 口写数据[31:22] =RS(I)的3#10bit 码元; [0105] 2 # RAM port A2 of the write data [31:22] = RS (I) is 3 # 10bit symbols;

[0106] 在收到RS(O)-RS(7)的第4#10bit码元的第4个时钟周期里,寄存RAM的写口数据如下: [0106] In received RS (O) (7) the fourth clock cycle 4 # 10bit -RS of symbols, the write port RAM data register as follows:

[0107] 1#RAM 的A2 口写数据[39:30] =RS(O)的4#10bit 码元; [0107] 1 # RAM port A2 of the write data [39:30] = RS (O) of 4 # 10bit symbols;

[0108] 2#RAM 的A2 口写数据[41:32] =RS(I)的4#10bit 码元; [0108] 2 # RAM port A2 of the write data [41:32] = RS (I) is 4 # 10bit symbols;

[0109] 在收到RS(O)-RS(7)的第5#10bit码元的第5个时钟周期里,寄存RAM的写口数据如下: [0109] In received RS (O) -RS fifth clock cycle (7) of 5 # 10bit symbols, the write port RAM data register as follows:

[0110] 1#RAM 的A2 口写数据[49:40] =RS(O)的5#10bi t 码元; [0110] 1 # RAM port A2 of the write data [49:40] = RS (O) 5 # 10bi t of symbols;

[0111] 2#RAM 的A2 口写数据[51:42] =RS(I)的5#10bit 码元; [0111] 2 # RAM port A2 of the write data [51:42] = RS (I) is 5 # 10bit symbols;

[0112] 在收到RS(O)-RS(7)的第6#10bit码元的第6个时钟周期里,寄存RAM的写口数据如下:[0113] 1#RAM 的A2 口写数据[59:50] =RS(O)的6#10bit 码元; [0112] In received RS (O) -RS (7) of symbol 6 # 10bit 6th clock cycle, the write port RAM data register as follows: [0113] 1 # RAM write data port A2 of [ 59:50] = RS (O) of 6 # 10bit symbols;

[0114] 2#RAM 的A2 口写数据[61:52] =RS(I)的6#10bit 码元; [0114] 2 # RAM port A2 of the write data [61:52] = RS (I) is 6 # 10bit symbols;

[0115] 在收到RS(O)-RS(7)的第7#10bit码元的第7个时钟周期里,寄存RAM的写口数据如下: [0115] In received RS (O) -RS (7) of the first seven clock cycles 7 # 10bit symbols, the write port RAM data register as follows:

[0116] 1#RAM 的A2 口写数据[63:60] =RS(O)的7#10bit 码元中的[3:0],此时1#RAM完成了A2 口写64bit数据的拼凑,可以进行一次1#RAM的0#地址的写操作,同时用寄存器寄存7#10bit码元中的[9:4]位的6bit数据,在下一个时钟周期里将该6bit数据拼凑进下一个64bit数据的[5:0]中; [0116] 1 # RAM port A2 of the write data [63:60] = RS (O) of symbol 7 # 10bit [3: 0], then completed the 1 # RAM port A2 patchwork 64bit data write, 1 may be a RAM address # 0 # write operation, while the register 7 # 10bit symbol [9: 4] 6bit data register bits, the next clock cycle, the data is put together into a next 6bit data 64bit [5: 0];

[0117] 2#RAM 的A2 口写数据[63:62] =RS(I)的7#10bit 码元中的[I: O],此时2#RAM还未完成A2 口64bit数据的拼凑,还必须等到RS(O)码字都写进1#RAM的A2区之后,也就是写完1#RAM的第121#地址之后,才可以得到该RS(O)写完1#RAM的A2区之后剩下的2bit数据,此时将该2bit数据再拼凑进2#RAM的0#地址所对应的64bit数据的[1:0],才可以进行2#RAM的0#地址的写操作,在未进行2#RAM的0#地址的写操作以前,该地址已经拼凑完的比特数据暂时放入寄存器中寄存。 [0117] 2 # RAM port A2 of the write data [63:62] = RS (I) in the # 7 10bit symbol [I: O], has not been completed at this time 2 # RAM port A2 patchwork 64bit data, after must wait until after the RS (O) codeword is written into the 1 # RAM region A2, which is the finished 1 # RAM address # 121, can obtain the RS (O) finished 1 # RAM area A2 of after 2bit remaining data, this time data and then put together into the 2bit # 2 # 0 64bit data RAM address corresponding to the [1: 0], can be # 2 # 0 RAM write address in # 2 # 0 RAM write address is not performed before the address has finished piece together bits of data is temporarily registered in a register.

[0118] 接下来进行1#RAM和2#RAM的1#地址写口数据的拼凑,当拼凑到64bit时,即可以进行一次RAM的写操作,之后的写操作按照这种方法进行,直到所有的RS (O) -RS (7)都写进了缓存N的A2区中为止,当检查到一个时钟宽度的高电平B2区RS编码指示信号时,采用同样的方法进行缓存N的B2区的写操作,直到所有的RS (O)-RS (15)都写进了整个缓存N的B2区中,当下一帧OTN经过外码RS编码后的数据到来时,又开始了新一轮的写缓存N的操作。 [0118] Next, the address for 1 # 1 # 2 # and a RAM write port data RAM patchwork, when piecing 64bit, i.e., a write operation may be performed once the RAM, after the write operation according to this method until all the RS (O) -RS (7) N are written into the cache area A2 so far, when a clock to check the width of the high level instruction signal RS encoding region B2, the same method employed in the N buffer region B2 write operation, until all the RS (O) -RS (15) are written into the N region B2 of the entire cache, the next frame after outer code RS OTN encoded data arrival, began a new round of N write caching operations.

[0119] 缓存N读方法为:当缓存N写A2区的0#地址时,从缓存N的B2区中读数据,先读1#RAM的122#地址,下一个时钟周期读1#RAM的123#地址,这样一直读到1#RAM的243#地址,再下一个时钟周期读2#RAM的122#地址,再下一个时钟周期读2#RAM的123#地址,这样依次进行直到缓存B2区中的所有数据都被读出。 [0119] Cache N Read method: When the cache N write Zone A2 0 # address, read data from the B2 region of the cache N, the first read 1 # RAM 122 # address, the next clock cycle the read 1 # RAM of address # 123, and thus has been read 243 # 1 # RAM address, and then reading the next clock cycle # 2 # RAM 122 address, then reading the next clock cycle # 2 # RAM 123 address, so successively until the buffer B2 All the data area are read out. 当缓存N写B2区的0#地址时,从缓存N的A2区中读数据,先读1#RAM的0#地址,下一个时钟周期读1#RAM的1#地址,这样一直读到1#RAM的121#地址,再下一个时钟周期读2#RAM的0#地址,再下一个时钟周期读2#RAM的1#地址,这样依次进行直到缓存A2区中的所有数据都被读出。 When the cache address # 0 B2 N write area, N is read from the cache data area A2, # 1 to the RAM read address # 0, the next clock cycle # 1 is read to the RAM address # 1, and continuing until 1 #RAM address # 121, and then reads the next clock cycle # 2 # RAM address 0, and then reads the next clock cycle # 2 # RAM 1 address, so that all the data sequentially until the cache area A2 are read out .

[0120] 经过缓存N的处理后,即完成了总线位宽从80到总线位宽64的输出。 [0120] N buffer after treatment, i.e. complete bit wide output bus from 80 to 64 bit wide bus.

[0121 ] 基于上述方法的电路包括缓存M和缓存N,缓存M由8块RAM构成,每块RAM的大小分别为1530X10 ;缓存N由8块RAM构成,每块RAM的大小分别为244X64。 [0121] Based on the above method includes a buffer circuit and a cache M N, M is composed of eight cache RAM, the size of each block of RAM, respectively 1530X10; N consists of eight cache RAM, the size of each block of RAM, respectively 244X64. 缓存M中的RAM均为双口RAM,该RAM以地址765为界划分为Al和BI两个区,读Al区时,写BI区,读BI区时,写Al区。 M in the cache RAM are dual-port RAM, the address of the RAM 765 as the boundary is divided into two regions Al and BI, Al zone reading, writing area BI, BI zone reading, writing area Al. 缓存N中的RAM均为双口RAM,并以地址122为界划分为A2区和B2区,读A2区时,写B2区,读B2区时,写A2区。 N is the cache RAM are dual-port RAM, and the address 122 is divided into boundary region A2 and region B2, A2 zone reading, writing region B2, B2 zone reading, writing area A2.

[0122] 本发明不局限于上述最佳实施方式,任何人应该得知在本发明的启示下作出的结构变化,凡是与本发明具有相同或相近的技术方案,均落入本发明的保护范围之内。 [0122] The present invention is not limited to the preferred embodiments, and any structural changes that should be made in light of the present invention, the present invention all have the same or similar technical solutions, all fall within the scope of the present invention within.

Claims (8)

  1. 1.应用SFEC的光传送网中总线位宽变换实现方法,其特征在于包括以下步骤: S10、将从64位系统总线输入的OTN帧的数据按外码RS (1023,1007)编码规则编码后存入缓存M,缓存M由8块RAM构成,每块RAM的大小分别为1530X 10,缓存M的读写时钟与系统总线时钟频率相同; S20、每次分别从缓存M的8块RAM中读取10个RS (1023,1007)编码数据并按内码BCH (2040,1952)编码规则编码后存入缓存N,缓存N由8块RAM构成,每块RAM的大小分别为244X64,缓存N的读写时钟与系统总线时钟频率相同; S30、依次从缓存N的8块RAM中输出64个BCH(2040,1952)编码数据至64位系统总线。 After SlO, will press the outer code RS (1023,1007) coding rule 64-bit data bus input of the OTN frame of the system: 1. The application of the bus width converting SFEC OTN implemented method, comprising the steps of cached M, M is composed of eight cache RAM, the size of each block of RAM are 1530X 10, the same read and write clocks M cache system bus clock frequency; S20, respectively, each read from the cache RAM 8 in M take 10 RS (1023,1007) the encoded data and press the inner code BCH (2040,1952) coding rule cached N, N consists of eight cache RAM, the size of each block of RAM are 244X64, the cache N the same as the system read clock to the bus clock frequency; S30, sequentially outputs 64 BCH (2040,1952) the encoded data to the system bus 64 from the cache RAM 8 in N.
  2. 2.如权利要求I所述的应用SFEC的光传送网中总线位宽变换实现方法,其特征在于缓存M中的RAM均为双口RAM,并以地址765为界划分为Al和BI两个区,读Al区时,写BI区,读BI区时,写Al区。 2. The use of optical transport network I SFEC according to the bus width conversion method of claim 1., wherein M is a RAM cache are dual-port RAM, the address and the boundary 765 is divided into two Al and BI area, reading area Al, write BI area, reading area BI, write Al district.
  3. 3.如权利要求2所述的应用SFEC的光传送网中总线位宽变换实现方法,其特征在于所述的步骤SlO包括以下步骤: 5101、根据SFEC外码RS (1023,1007)编码规则将缓存M的每一个RAM地址划分为RS (O)-RS (15) 16 组地址,其中RS (O)-RS (14)以RS (1023,1007)的缩短码RS (781,765)为编码规则,RS (15)以RS (778,762)为编码规则; 5102、将从64位系统总线输入的一帧OTN数据依次写进缓存M的每块RAM中,写入的规则是,OTN帧中的FEC开销字节不写入缓存M,一帧OTN数据按照bit传送顺序以10 X 765为单位分别对应写入每块RAM中RS (O)-RS (15)对应的地址单元中,其中RS (O)-RS (7)分别对应Al区,RS (8)-RS (15)分别对应BI区,当开始写RAM的0#地址时,送出一个缓存M的BI区编码指示信号,当开始写765#地址时,送出一个缓存M的Al区编码指示信号。 3. The use of claim 2 SFEC optical transport network bus width conversion implemented method of claim, wherein said step comprises the step SlO: 5101, SFEC according to the outer code RS (1023,1007) coding rule each address buffer RAM is divided into M RS (O) -RS (15) 16 group address, wherein the RS (O) -RS (14) to RS (1023,1007) codes shortened RS (781,765) coding rule, RS (15) to RS (778,762) coding rule; 5102, are sequentially written into each block from the cache RAM 64 M in a data bus input of the OTN system, the rule is written, OTN frame FEC overhead bytes are not the M write caching, data in an OTN bit transmission order of 10 X 765 units respectively corresponding to the RAM write each RS (O) -RS (15) corresponding to an address unit, wherein RS (O) -RS (7) area corresponding Al, RS (8) -RS (15) zone respectively BI, when starting writing the RAM address # 0, sending a buffer area BI encoding instruction signal M, when # writing start address 765, a cache sends an Al M region coding instruction signal.
  4. 4.如权利要求3所述的应用SFEC的光传送网中总线位宽变换实现方法,其特征在于缓存N由8块相同的RAM构成,该RAM为双口RAM,并以地址122为界划分为A2区和B2区,读A2区时,写B2区,读B2区时,写A2区。 SFEC bus width of transform application as claimed in claim 3 optical transport network, characterized in that the N cache RAM. 8 is composed of the same block of the dual port RAM is a RAM, and the address 122 as the demarcation A2 and B2 for the district area, reading area A2, B2 write zone, reading zone B2, A2 writing area.
  5. 5.如权利要求4所述的应用SFEC的光传送网中总线位宽变换实现方法,其特征在于所述的步骤S20包括以下步骤: S201、当检测到缓存M的Al区编码指示信号时,缓存N —次读取缓存M中Al区RAM中的80bit数据,当检测到缓存M的BI区编码指示信号时,缓存N —次读取缓存M中BI区中的80bit数据; S202、将缓存M输出的80bit数据依次分配到缓存N中的RAM中,其中RS (O) -RS (7)分别对应A2区,RS⑶-RS (15)分别对应B2区,当开始写RAM的0#地址时,送出一个缓存N的A2区编码指示信号,当开始写122#地址时,送出一个缓存N的B2区编码指示信号; S203、缓存N中的每块RAM缓存两个外码编码后不同RS地址的数据;具体为WRAM缓存外码RS(O)和RS (8)中的编码数据,2#RAM缓存外码RS码字的1#和9#RS码编码数据,3#RAM缓存外码RS码字的2#和10#RS码编码数据,4#RAM缓存外码RS码字的3#和11#RS码编码数据,5#RAM缓存外码RS 5. The use of optical transport network SFEC 4 in the bus width conversion implemented method as claimed in claim, wherein said step comprises the steps of S20: S201, when the Al region encoding instruction signal M is detected in the cache, cache N - 80bit data read buffer area of ​​the RAM in the Al M times, and when detecting BI region encoding instruction signal M buffer, the buffer N - M read 80bit data buffer area in the sub-BI; S202, cached 80bit data outputted sequentially allocated to the M N of the RAM cache, wherein the RS (O) -RS (7) corresponding area A2, RS⑶-RS (15) respectively corresponding to region B2, to start writing when the RAM address 0 # , sends a cache region A2 of the N coding instruction signal, when the write start address # 122, sends a buffer zone B2 of the N coding instruction signal; S203, each of the N buffer RAM cache after the outer code encoding two different addresses RS data; specifically, the encoded data WRAM cache outer code RS (O) and RS (8), 1 # and 9 # RS code encoded data 2 # RAM cache outer code RS code words, 3 # RAM cache outer code RS codeword # 10 and # 2 RS code encoded data, # 3 and # RS code. 11 4 # RAM buffer encoded data of the outer code of RS code words, 5 # RAM cache outer code RS 字的4#和12#RS码编码数据,6#RAM缓存外码RS码字的5#和13#RS码编码数据,7#RAM缓存外码RS码字的6#和14#RS码编码数据,8#RAM缓存外码RS码字的7#和15#RS码编码数据;S204、当检测到缓存N中A2区编码指示信号时,从缓存N的B2区的第1#RAM的122#地址开始读操作,依次读完1#RAM的B2区后,接着读2#RAM的B2区,直到1_8#RAM的B2区数据都读完为止;当检测到缓存N的B2区编码指示信号时,从缓存N的A2区的第WRAM的0#地址开始读操作,依次读完1#RAM的A2区后,接着读2#RAM的A2区,直到1_8#RAM的A2区数据都读完为止。 4 # and 12 is # RS code encoded data word, 6 # RAM cache outer code RS code words 5 # and 13 is # RS code encoded data, 7 # RAM cache outer code RS code words 6 # and 14 # RS code encoding data, 8 # RAM cache outer code RS code words 7 # and 15 # RS code encoded data; S204, upon detection of the A2 region coding indication signal buffer N, from # first 1 RAM B2 region cache N of 122 after the read start address #, 1 # RAM sequentially reading the regions B2, then B2 is read 2 # RAM region until the region B2 1_8 # RAM data read so far; the buffer when the detected N signals indicative of the coding region B2 after the time, from the first address # 0 WRAM region A2 of the N cache read operation begins sequentially reading area A2 of 1 # RAM, then read the 2 # RAM area A2, and A2 until 1_8 # RAM region read data until.
  6. 6.应用SFEC的光传送网中总线位宽变换电路,其特征在于包括: 缓存M,由8块RAM构成,每块RAM的大小分别为1530 X 10 ; 缓存N,由8块RAM构成,每块RAM的大小分别为244X64 ; 缓存M用于存入将从64位系统总线输入的OTN帧的数据按外码RS (1023,1007)编码规则编码后的数据; 缓存N用于存入每次分别从缓存M的8块RAM中读取10个RS (1023,1007)编码数据并按内码BCH(2040,1952)编码规则编码后的数据,并依次从缓存N的8块RAM中输出64个BCH (2040,1952)编码数据至64位系统总线; 缓存M和缓存N的读写时钟与系统总线时钟频率相同。 6. Application of OTN SFEC the bus width conversion circuit, comprising: a buffer M, composed of RAM 8, the size of each block of RAM are 1530 X 10; cache N, constituted by the RAM 8, each the size of the RAM block were 244X64; M for the deposit from the buffer by an outer code of RS data (1023,1007) coding rule 64-bit data bus input of the OTN frame system; N cache for each deposit RS 10 respectively read from the cache RAM 8 M in the data (1023,1007) the encoded data and press the inner code BCH (2040,1952) coding rule, and 64 are sequentially output from the buffer RAM 8 in N a BCH (2040,1952) the encoded data to the system bus 64; the same cache buffer N and M read and write clock frequency of the system bus clock.
  7. 7.如权利要求6所述的应用SFEC的光传送网中总线位宽变换电路,其特征在于缓存M中的RAM均为双口RAM,该RAM以地址765为界划分为Al和BI两个区,读Al区时,写BI区,读BI区时,写Al区。 7. The use of claim 6 SFEC optical transport network bus width conversion circuit as claimed in claim, wherein M is a RAM cache are dual-port RAM, the address of the RAM 765 as the boundary is divided into two Al and BI area, reading area Al, write BI area, reading area BI, write Al district.
  8. 8.如权利要求6所述的应用SFEC的光传送网中总线位宽变换电路,其特征在于缓存N中的RAM均为双口RAM,并以地址122为界划分为A2区和B2区,读A2区时,写B2区,读B2区时,写A2区。 8. The use of claim 6 SFEC optical transport network bus width conversion circuit as claimed in claim, wherein N is a RAM cache are dual-port RAM, and the address 122 is divided into boundary region A2 and region B2, reading zone A2, B2 write zone, reading zone B2, A2 writing area.
CN 201010111571 2010-02-22 2010-02-22 Method and circuit applying SFEC to realize bit width transformation of bus in OTN (optical transport network) CN101789845B (en)

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