CN101763780A - Pixel structure and driving method thereof - Google Patents

Pixel structure and driving method thereof Download PDF

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CN101763780A
CN101763780A CN201010118833A CN201010118833A CN101763780A CN 101763780 A CN101763780 A CN 101763780A CN 201010118833 A CN201010118833 A CN 201010118833A CN 201010118833 A CN201010118833 A CN 201010118833A CN 101763780 A CN101763780 A CN 101763780A
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transistor
terminal
switching transistor
data
driving
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CN201010118833A
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CN101763780B (en
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陈屏先
陈弼先
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华映光电股份有限公司
中华映管股份有限公司
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Abstract

The invention relates to a pixel structure and a driving method thereof. The pixel structure comprises a storage capacitor, a data switch transistor, a disturbance switch transistor, a driving transistor, a display switch transistor and an organic light emitting diode, wherein the data switch transistor can supply data signals to the first end of the storage capacitor according to scanning signals; when the data switch transistor is switched off, the disturbance switch transistor can supply disturbance signals to the first end of the storage capacitor; the first end and the gate electrode of the driving transistor are respectively coupled with constant voltage and the second end of the storage capacitor; and the first end and the second end of the display switch transistor are respectively coupled with the second end of the driving transistor and the positive electrode of the organic light emitting diode. Thus, the service life of the pixel structure can be prolonged.

Description

画素结构及其驱动方法 Pixel structure and a driving method

[0001] 技术领域 [0001] Technical Field

[0002] 本发明是有关于一种画素结构,且特别是有关于一种有机发光显示器的画素结构及其驱动方法。 [0002] The present invention relates to a pixel structure, and more particularly to a pixel structure and a driving method relates to an organic light emitting display.

[0003] 背景技术 [0003] BACKGROUND OF THE INVENTION

[0004] 使用有机发光二极管(organiclightemittingdiode,OLED)的有机发光显示器(organiclightemittingdisplay)由于具有自发光、高亮度、高对比、广视角以及反应速度快等优点,目前有关的研究单位无不致力于其特性与驱动电路的研究。 [0004] The organic light emitting diode (organiclightemittingdiode, OLED) of an organic light emitting display (organiclightemittingdisplay) because of self-emission, high brightness, high contrast, wide viewing angle, and fast response speed, etc., all current relevant research units committed to its characteristics Study driving circuit. 虽然有机发光显示器具有上述的优点,但仍然有些问题亟待解决。 Although the above-described organic light emitting display has advantages, but there are still some problems to be solved.

[0005] 图1是习知的一种画素结构的示意图。 [0005] FIG. 1 is a schematic view of a conventional pixel structure. 请参照图1,此画素结构使用两个晶体管(TFT_S、TFT_D),以及一个储存电容Cs,此画素结构被称为2T1C的画素电路。 Referring to FIG. 1, this pixel structure using two transistors (TFT_S, TFT_D), and a storage capacitor Cs, the pixel structure of this pixel circuit is called the 2T1C. 晶体管TFT_S的闸极耦接扫描线GL,可依据扫描线GL提供的扫描讯号而导通。 TFT_S transistor is coupled to the gate scan line GL, the scan signal may be based on the scan line GL is turned on provided. 当晶体管TFT_S导通时,数据线DL的数据讯号可传递至储存电容Cs的第一端与晶体管TFT_D的闸极端,对此画素结构进行数据写入。 TFT_S When the transistor is turned on, the data line DL data signals can be transferred to the storage capacitor Cs and a first end of the gate terminal of the transistor TFT_D, this pixel data writing structure.

[0006] 晶体管TFT_D可用以控制流经OLEDD1的电流Io,藉由控制闸极(Gate)电压,即可控制TFT_D源极/汲极(Source/Drain)两端的电压和电流。 [0006] TFT_D transistor may be used to control the current Io flowing through the OLEDD1, by the control gate (Gate) voltage, to control TFT_D source / drain (Source / Drain), and the voltage across the current. 因晶体管TFT_D与OLEDD1为串联组合,当施加一个固定的电压Vdd于TFT_D汲极时,即可透过TFT_D的源极/汲极的改变,来控制通过OLEDD1的电流Io,而达成控制灰阶的目的。 Since the transistor in series combination OLEDD1 TFT_D and when a fixed voltage Vdd is applied to drain TFT_D, the electrode can be changed through TFT_D source / drain, is controlled by the current Io OLEDD1, and control to achieve grayscale purpose.

[0007] 值得一提的是,晶体管TFT_D会因为制程上的误差、长时间操作或环境温度等因素,造成临界电压(ThresholdVoltage)产生变异,进而使通过OLEDD1的电流Io产生改变,而影响画素亮度上的表现。 [0007] It is worth mentioning that the transistors TFT_D because of errors in the manufacturing process, a long time operation or the environmental temperature and other factors, resulting in the threshold voltage (ThresholdVoltage) mutate, thereby enabling to produce altered by the current Io OLEDD1, and the impact pixel luminance on the performance.

[0008] 另外,若画面长时间处于白画面时,晶体管TFT_D必须持续提供大电流给OLEDD1,晶体管TFT_D会长时间处于高电流应力(highcurrentstress),易造成劣化问题,降低使用寿命。 [0008] Further, if the picture is a long white picture, the transistor TFT_D must continue to supply a large current OLEDD1, the transistor will be a long time in a high current TFT_D stress (highcurrentstress), easily causes degradation problems, reduce the service life.

[0009] 发明内容 [0009] SUMMARY OF THE INVENTION

[0010] 本发明提供一种画素结构,可延长画素结构的寿命。 [0010] The present invention provides a pixel structure, extend the life of the pixel structure.

[0011] 本发明提供一种画素结构的驱动方法,可改善高电流应力造成劣化的问题。 [0011] The present invention provides a driving method of a pixel structure, can improve the high current stress caused by deterioration problems.

[0012] 本发明提出一种画素结构,包括储存电容、数据开关晶体管、扰动开关晶体管、驱动晶体管、显示开关晶体管与有机发光二极管。 [0012] The present invention provides a pixel structure, comprising a storage capacitor, a data switching transistor, a switching transistor, a driving transistor disturbance, the switching transistor and the organic light emitting display diodes. 储存电容具有第一端与第二端。 A storage capacitor having a first end and a second end. 数据开关晶体管可依据扫描讯号提供数据讯号至储存电容的第一端。 The data switching transistor may be provided based on the scan data signal to store a first signal terminal of the capacitor. 当数据开关晶体管截止时,扰动开关晶体管可提供扰动讯号至储存电容的第一端。 When the data switching transistor is turned off, the switching transistor may be provided perturbation perturbation signal to a first terminal of the storage capacitor. 驱动晶体管具有第一端、第二端与闸极。 A driving transistor having a first end, a second end of the gate. 驱动晶体管的第一端耦接定电压。 The first terminal of the driving transistor is connected to a constant voltage. 驱动晶体管的闸极耦接储存电容的第二端。 A gate of the driving transistor coupled to the second terminal of the storage capacitor. 显示开关晶体管具有第一端、第二端与闸极。 Display switching transistor has a first terminal, a second terminal and a gate. 显示开关晶体管的第一端耦接驱动晶体管的第二端。 Display switching transistor is coupled to a first terminal of a second terminal of the driving transistor. 显示开关晶体管的闸极接收显示控制讯号。 Shutter display switching transistor receives the display control signal. 有机发光二极管的阳极耦接显示开关晶体管的第二端。 The anode of the organic light emitting diode display coupled to a second terminal of the switch transistor. 有机发光二极管的阴极耦接接地端。 OLED cathode coupled to the ground terminal.

[0013] 在本发明的一实施例中,数据开关晶体管具有第一端、第二端与闸极。 [0013] In an embodiment of the invention, the data switching transistor having a first end, a second end of the gate. 数据开关晶体管的第一端耦接数据线并接收数据讯号。 A first terminal coupled to the data line and the switching transistor receiving a data signal data. 数据开关晶体管的闸极耦接扫描线并接收扫描讯号。 The data switching transistor gate is coupled to the scan lines and receive scan signal. 数据开关晶体管的第二端耦接储存电容的第一端。 The data switching transistor is coupled to a second terminal of the first terminal of the storage capacitor.

[0014] 承上述,在另一实施例中,扰动开关晶体管具有第一端、第二端与闸极。 [0014] Bearing the above, in another embodiment, the disturbance of the switching transistor having a first terminal and a second end of the gate. 扰动开关晶体管的第一端接收扰动讯号。 Disturbance of the switching transistor receives a first disturbance signal. 扰动开关晶体管的闸极耦接扫描线并接收扫描讯号。 Disturbance of the switching transistor gate is coupled to the scan lines and receive scan signal. 扰动开关晶体管的第二端耦接储存电容的第一端。 Disturbance of the switching transistor second terminal coupled to a first terminal of the storage capacitor. 扰动开关晶体管与数据开关晶体管由P信道晶体管与N信道晶体管所组成。 Disturbance data switching transistor and the switching transistor by a P-channel transistor and N-channel transistors formed.

[0015] 在本发明的一实施例中,画素结构更包括临界电压电容。 [0015] In an embodiment of the present invention, the pixel structure further comprises a threshold voltage of the capacitor. 临界电压电容耦接于显示开关晶体管的第一端与闸极之间。 The threshold voltage of the first capacitor is coupled between the gate terminal of the switching transistor in the display.

[0016] 在本发明的一实施例中,画素结构更包括分流驱动晶体管与分流开关晶体管。 [0016] In an embodiment of the present invention, the pixel structure further comprising a shunt shunt switching transistor and a driving transistor. 分流驱动晶体管具有第一端、第二端与闸极。 A first driving transistor having a split end, a second end of the gate. 分流驱动晶体管的第一端耦接定电压。 Shunt driving transistor is coupled to a first terminal of a constant voltage. 分流驱动晶体管的第二端耦接驱动晶体管的第二端。 Shunt drive transistor coupled to a second terminal of the second terminal of the driving transistor. 分流开关晶体管具有第一端、第二端与闸极。 Shunt switching transistor having a first end, a second end of the gate. 分流开关晶体管的第一端耦接分流驱动晶体管的闸极。 Shunt switching transistor is coupled to a first terminal of the driving transistor gate shunt. 分流开关晶体管的第二端耦接驱动晶体管的闸极。 Shunt switching transistor is coupled to a second terminal of the drive transistor gate. 分流开关晶体管的闸极接收显示控制讯号。 Shunt switching transistor has a gate receiving the display control signal.

[0017] 在本发明的一实施例中,驱动晶体管与显示开关晶体管配置于画素数组之内。 [0017] In an embodiment of the present invention, the driving transistor and the switching transistor is disposed in the display pixel of the array. 分流驱动晶体管与分流开关晶体管配置于画素数组之外。 A shunt shunt switching transistor and the driving transistor arranged outside the pixel array.

[0018] 在本发明的一实施例中,扰动讯号为周期讯号。 [0018] In an embodiment of the present invention, the disturbance signal is a periodic signal. 扰动讯号以零电压位准在正周期与负周期分别进行振幅大小相同的反相扰动。 Perturbation signal to a zero voltage level for the same amplitude of the inverted perturbation positive and the negative cycle period respectively.

[0019] 从另一角度来看,本发明提出一种画素结构的驱动方法。 [0019] From another perspective, the present invention provides a driving method of a pixel structure. 画素结构包括数据开关晶体管、储存电容、驱动晶体管与有机发光二极管。 The pixel data structure comprises a switching transistor, a storage capacitor, the driving transistor and the organic light emitting diode. 数据开关晶体管具有第一端、第二端与闸极。 The data switching transistor having a first end, a second end of the gate. 储存电容具有第一端与第二端。 A storage capacitor having a first end and a second end. 驱动晶体管具有第一端、第二端与闸极。 A driving transistor having a first end, a second end of the gate. 数据晶体管的第二端耦接储存电容的第一端。 Data transistor second terminal coupled a first terminal of the storage capacitor. 储存电容的第二端耦接驱动晶体管的闸极。 The second terminal of the storage capacitor is connected to the drive transistor gate. 驱动晶体管的第一端与第二端分别耦接定电压与有机发光二极管。 A first driving transistor and second ends are coupled with the organic light emitting diode constant voltage. 驱动方法包括依据扫描讯号导通数据开关晶体管。 The driving method according to a scanning signal comprising data switching transistor is turned on. 当数据开关晶体管导通时,可提供数据讯号至储存电容的第一端,藉以透过驱动晶体管驱动有机发光二极管。 When the data switching transistor is turned on, the data signal may be provided to the first end of the storage capacitor, so as to drive the organic light emitting diode through the driving transistor. 当数据开关晶体管截止时,透过扰动开关晶体管,提供扰动讯号至储存电容的第一端。 When the data switching transistor is turned off, the switching transistor through the disturbance, the disturbance signal to provide a first terminal of the storage capacitor.

[0020] 基于上述,本发明停止提供数据讯号至画素结构时,可提供扰动讯号至画素结构。 [0020] Based on the above signals to provide data, the present invention is to stop the pixel structure, the disturbance signal may be provided to the pixel structure. 如此一来,可提升画素结构的寿命。 Thus, the pixel structure can be improved lifetime.

[0021] 为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附图式作详细说明如下。 [0021] In order to make the above features and advantages of the present invention can be more fully understood, the following non-limiting embodiment, and the accompanying figures are described in detail below.

[0022] 附图说明 [0022] BRIEF DESCRIPTION OF DRAWINGS

[0023] 图1是习知的一种画素结构的示意图。 [0023] FIG. 1 is a schematic view of a conventional pixel structure.

[0024] 图2是依照本发明的第一实施例的一种画素结构的示意图。 [0024] FIG. 2 is a schematic diagram of a pixel structure according to a first embodiment of the present invention.

[0025] 图3是依照本发明的第一实施例的一种扰动讯号的示意图。 [0025] FIG. 3 is a schematic view of a first embodiment according to one embodiment of the disturbance signal of the present invention.

[0026] 图4是图2的一种操作状态的示意图。 [0026] FIG. 4 is a schematic view of an operating state 2.

[0027] 图5是图2的另一种操作状态的示意图。 [0027] FIG. 5 is a schematic diagram of another operating state of FIG.

[0028] 图6是依照本发明的第一实施例的一种驱动波形的示意图。 [0028] FIG. 6 is a schematic view of driving waveforms according to one embodiment of the first embodiment of the present invention.

[0029] 图7是依照本发明的第一实施例的一种画素结构的驱动方法的流程图。 [0029] FIG. 7 is a flowchart of a method of driving the pixel configuration of a first embodiment of the present invention.

[0030] 图8是依照本发明的第一实施例的一种画素结构的示意图。 [0030] FIG. 8 is a schematic diagram of a pixel structure according to a first embodiment of the present invention.

[0031] 图9是图8的一种操作状态的示意图。 [0031] FIG. 9 is a schematic view of an operation state 8.

[0032] 图10是图8的另一种操作状态的示意图。 [0032] FIG. 10 is a schematic diagram of another operating state of FIG. 8.

[0033] 图11是依照本发明的第一实施例的一种扰动讯号的示意图。 [0033] FIG. 11 is a schematic view of a first embodiment according to one embodiment of the disturbance signal of the present invention.

[0034] 【主要组件符号说明】 [0034] The main component symbol DESCRIPTION

[0035] 10、11:画素结构 [0035] 10, 11: pixel structure

[0036] Ccs、Cs:储存电容 [0036] Ccs, Cs: storage capacitor

[0037] Cth:临界电压电容 [0037] Cth: the threshold voltage of the capacitor

[0038] P1:资料开关晶体管 [0038] P1: Data switching transistor

[0039] P2:扰动开关晶体管 [0039] P2: Disturbance of the switching transistor

[0040] P3:显示开关晶体管 [0040] P3: Display switching transistor

[0041] P4:驱动晶体管 [0041] P4: of the driving transistor

[0042] P5:分流开关晶体管 [0042] P5: shunt switching transistor

[0043] P6:分流驱动晶体管 [0043] P6: shunting of the driving transistor

[0044] D1:OLED [0044] D1: OLED

[0045] DL:资料线 [0045] DL: Data line

[0046] GL:扫描线 [0046] GL: scan line

[0047] CSL:扰动讯号 [0047] CSL: perturbation signal

[0048] DCL:显示控制讯号 [0048] DCL: display control signal

[0049] C、S、G、D:端点 [0049] C, S, G, D: endpoint

[0050] Vdd:定电压 [0050] Vdd: constant voltage

[0051] TFT_S、TFT_D:晶体管 [0051] TFT_S, TFT_D: Transistor

[0052] Io、ISD:电流 [0052] Io, ISD: Current

[0053] S701~S703:驱动方法的各步骤。 [0053] S701 ~ S703: the steps of the method of driving.

[0054] [0054]

[0055] 具体实施方式 [0055] DETAILED DESCRIPTION

[0056] 习知的画素结构具有高电流应力的问题,容易缩短画素结构的寿命。 [0056] Problems of conventional pixel structure having a high current stress easily shorten the life of the pixel structure.

[0057] 反观,本发明的实施例提供了多种画素结构,可改善习知的问题。 [0057] In contrast, embodiments of the present invention provides a variety of pixel structures, the conventional problems can be improved.

[0058] 第一种画素结构: [0058] The first pixel structure:

[0059] 1.将临界电压电容于驱动晶体管的第一端与闸极之间,可加强驱动晶体管的临界电压。 [0059] 1. The threshold voltage of the driving transistor capacitance between the gate and the first terminal, the threshold voltage can enhance the driving transistor. 可解决驱动晶体管因为制程上的差异、长时间操作或环境温度等因素,而使其工作特性有所差异,进而造成其临界电压(ThresholdVoltage)变异。 Solve because of the difference of the driving transistor manufacturing process, a long time operation or environmental factors such as temperature, and so the operating characteristics vary, thus causing its threshold voltage (ThresholdVoltage) variation. 如此一来,驱动晶体管输出的电流则不易受临界电压所影响。 Thus, the current output from the drive transistor threshold voltage is not affected by the vulnerability.

[0060] 2.从此画素结构的外部输入一上下振幅相等的扰动讯号,藉此扰动讯号可使通过OLED的电流(电压)于一固定值作扰动。 [0060] 2. From the external input amplitude equal to the perturbation signal is a vertical pixel structure, whereby the disturbance signal can OLED current (voltage) by a fixed value as a disturbance acting. 因此,若长时间使用于白画面显示时,可改善因驱动晶体管必须持续提供大电流给OLED,而处于高电流应力(highcurrentstress)所造成劣化问题,可延长晶体管的使用寿命。 Therefore, if a long time to the white screen display can improve the problem of deterioration due to continuous driving transistor must supply a large current to the OLED, and in a high current stress (highcurrentstress) caused extend the life of the transistor. 另外,由于人眼有视觉暂留现象,因此只要扰动讯号的频率高于人眼所能辨识的频率,画素的显示亮度几乎会呈现一固定值。 In addition, because the human eye phenomenon of persistence of vision, so long as the frequency perturbation signal frequency is higher than the human eye can identify, the display will show the brightness of pixels is almost a fixed value.

[0061] 第二种画素结构: [0061] The second pixel structure:

[0062] 1.使用分流(SharingCurrent)的方法,可改善当长时间显示白画面时,驱动晶体管必须持续提供大电流给OLED,而处于高电流应力(highcurrentstress)所造成劣化问题,可延长TFT的使用寿命。 [0062] 1. shunt (SharingCurrent) method can be improved when displaying a white screen, the driving transistor to supply a large current must continue to the OLED, and the problem of deterioration in a high current stress (highcurrentstress) caused, the TFT extended life.

[0063] 2.利用此画素结构,可使驱动晶体管的操作电压降低。 [0063] 2. With this pixel structure, the operating voltage of the driving transistor is reduced. 因此可选用耐压较低的驱动晶体管,降低成本。 Therefore the use of lower voltage driving transistor, to reduce costs. 同时也可减少功率消耗。 It can also reduce power consumption.

[0064] (a)提供至驱动晶体管的数据讯号,其电压可降低至原 [0064] (a) providing a data signal to the driving transistor, the voltage may be reduced to the original

.

[0065] (b)同理,利用扰动讯号对此画素结构进行扰动时,扰动讯号的电压也可降低至原 When [0065] (b) Similarly, the pixel structure by the disturbance signal for this disturbance, the disturbance voltage signals may also be reduced to the original

. 下面将参考附图详细阐述本发明的实施例,附图举例说明了本发明的示范实施例,其中相同标号指示同样或相似的步骤。 The embodiments set forth in detail below with reference to the accompanying drawings of embodiments of the present invention, the drawings illustrate exemplary embodiments of the present invention, wherein like numerals indicate the same or similar steps.

[0066] 第一实施例 [0066] First embodiment

[0067] (一)画素结构说明 [0067] (a) described pixel structure

[0068] 图2是依照本发明的第一实施例的一种画素结构的示意图。 [0068] FIG. 2 is a schematic diagram of a pixel structure according to a first embodiment of the present invention. 请参照图2,在本实施例中,画素结构使用了4T2C的架构。 Referring to FIG 2, in the embodiment, the pixel structure used in a 4T2C architecture of the present embodiment. 画素结构10包括储存电容Ccs、临界电压电容Cth、数据开关晶体管P1、扰动开关晶体管P2、显示开关晶体管P3、驱动晶体管P4与OLEDD1。 The pixel structure 10 comprises a storage capacitor Ccs, the threshold voltage capacitor Cth, the data switching transistor P1, a switching transistor disturbance P2, the display switching transistors P3, P4 and the driving transistor OLEDD1. 在本实施例中,数据开关晶体管P1以N通道晶体管为例进行说明,扰动开关晶体管P2、显示开关晶体管P3与驱动晶体管P4以P通道晶体管为例进行说明,但本发明并不限于此。 In the present embodiment, the data switching transistor P1 is an N-channel transistor as an example, perturbation of the switching transistor P2, P3 display switching transistor and the driving transistor in a P-channel transistor P4 will be described as an example, but the present invention is not limited thereto.

[0069] 数据开关晶体管P1的闸极耦接扫描线GL,可接收扫描讯号。 [0069] The data switching transistor P1 is coupled to the gate scan line GL, the scan signal may be received. 数据开关晶体管P1的第一端耦接数据线DL,可接收数据讯号。 The data switching transistor P1 is coupled to a first end of the data line DL, the data signal may be received. 数据开关晶体管P1的第二端耦接储存电容Ccs的第一端与扰动开关晶体管P2的第二端。 The first end of the switching transistor P2 and the disturbance data switching transistor P1 is coupled to a second terminal of the storage capacitance Ccs. 扰动开关晶体管P2的第一端可接收扰动讯号CSL。 Disturbance of the switching transistor P2 may receive a first end of the disturbance signal CSL. 扰动开关晶体管P2的闸极耦接扫描线GL。 Disturbance switching transistor P2 is coupled to the gate scanning line GL.

[0070] 储存电容Ccs的第二端耦接临界电压电容Cth的第一端与驱动晶体管P4的闸极。 [0070] The storage capacitance Ccs is coupled to a second terminal of the capacitor Cth the threshold voltage of the driving end of the first gate electrode of the transistor P4. 驱动晶体管P4的第一端耦接定电压Vdd、临界电压电容Cth的第二端。 The driving transistor P4 is coupled to a first terminal of a constant voltage Vdd, a second terminal of the threshold voltage of the capacitor Cth. 驱动晶体管P4的第二端耦接显示开关晶体管P3的第一端。 A second terminal of the driving transistor P4 is coupled to a first terminal of the display switching transistor P3. 显示开关晶体管P3的闸极接收显示控制讯号DCL。 Display switching transistor P3 has a gate receiving the display control signal DCL. 显示开关晶体管P3的第二端耦接OLEDD1的阳极。 Displaying a second terminal coupled to an anode of the switching transistor P3 in OLEDD1. OLEDD1的阴极耦接接地端。 A cathode coupled to the ground terminal of OLEDD1.

[0071] 在本实施例中,数据开关晶体管P1、扰动开关晶体管P2与显示开关晶体管P3可作为开关使用。 [0071] In the present embodiment, the data switching transistors P1, P2 and display disturbance switching transistor the switching transistor P3 may be used as a switch. 驱动晶体管P4则用来驱动OLEDD1。 It is used to drive the drive transistor P4 OLEDD1.

[0072] 更详细地说,资料开关晶体管P1可依据扫描线GL提供的扫描讯号而导通,藉以将数据线DL的数据讯号传递至储存电容Ccs的第一端。 [0072] In more detail, the switching transistor P1 may be based on information on the scanning signal line GL provided in the scanning turned on, thereby transferring the data lines DL data signal to the first end of the storage capacitance Ccs. 扰动开关晶体管P2可配合数据开关晶体管P1的操作,将外部输入的扰动讯号CSL传递至储存电容Ccs的第一端。 The switching transistor P2 disturbance data can be used with the switching operation of the transistor P1, to transmit an externally input perturbation signal CSL to the first end of the storage capacitance Ccs. 当资料开关晶体管P1截止时,扰动开关晶体管P2则导通;反之,当资料开关晶体管P1导通时,扰动开关晶体管P2则截止。 When the switching transistor P1 is turned off data, the disturbance switching transistor P2 is turned on; the other hand, when the data switching transistor P1 is turned on, the switching transistor P2 is turned off disturbances.

[0073] 请注意,在本实施例中,由于数据开关晶体管P1与扰动开关晶体管P2分别为N信道晶体管与P信道晶体管,因此扰动开关晶体管P2的闸极可耦接扫描讯GL,与数据开关晶体管P1共享同一扫描讯号。 [0073] Note that in the present embodiment, since the data switching transistor P1 and the disturbance switching transistor P2 are N-channel transistors and P-channel transistors, thus disturbing the switching transistor P2 gate may be coupled to scan information GL, and the data switch transistor P1 share the same scan signal. 如此一来,则无须额外提供控制讯号来控制扰动开关晶体管P2的操作,但本发明并不限于此。 Thus, there is no need to provide an additional control signal for controlling the switching operation of transistor P2 disturbance, but the present invention is not limited thereto. 在其它实施例中,也可另外提供控制讯号来控制扰动开关晶体管P2的操作。 In other embodiments, the control signal may be additionally provided to control the operation of the switching transistor P2 disturbance.

[0074] 驱动晶体管P4可依据G端点的电压而驱动OLEDD1。 [0074] The driving transistor P4 may be driven according to the voltage G OLEDD1 endpoint. 显示开关晶体管P3可依据显示控制讯号DCL而决定是否导通。 Display switching transistor P3 may be turned on according to decide whether the display control signal DCL. 显示控制讯号DCL输入至显示开关晶体管P3的闸极,可作为控制OLEDD1是否可通过电流的开关。 Display control signal DCL input to the display switching transistor P3 gate, as a control OLEDD1 whether the current through the switch. 当显示开关晶体管P3截止时,OLEDD1不会发亮;当显示开关晶体管P3导通时,OLEDD1会受控于驱动晶体管P4而发出对应灰阶的亮度。 When the display switching transistor P3 is turned off, OLEDD1 not light; when the display switching transistor P3 is turned on, OLEDD1 be controlled corresponding to the driving transistor P4 issued grayscale brightness.

[0075] 另一方面,临界电压电容Cth主要可储存驱动晶体管P4的临界电压。 [0075] On the other hand, the threshold voltage of the main capacitor Cth may store the threshold voltage of the driving transistor P4. 储存电容Ccs主要可储存数据线DL所提供数据讯号。 The main storage capacitor Ccs store data provided by the data signal line DL. 另外,需注意的是,储存电容的第一端(C端点)更与扰动开关晶体管P2的第二端相连接,扰动开关晶体管P2的第一端外接扰动讯号CSL,主要是为了将数据讯号于一个画框期间,变成带有扰动讯号CSL的数据讯号。 Further, it is noted that a first end of the storage capacitor (C terminal) and a second end connected to more disturbance switching transistor P2, a first transistor P2 switching the disturbance of an external disturbance signal CSL, mainly in order to transfer data signals during a frame, into the data signal with the perturbation signal CSL. 扰动讯号CSL藉由储存电容Ccs耦合到驱动晶体管P4的闸极,以调整驱动晶体管P4的输出电流,使OLEDD1发出要显示的亮度。 CSL disturbance signal by the storage capacitance Ccs is coupled to the gate of the driving transistor P4 to adjust the output current of the driving transistor P4, so that luminance of emitted OLEDD1 be displayed.

[0076] (二)、画素驱动方法 [0076] (b), the driving method of pixel

[0077] (1)、通过OLEDD1的电流 [0077] (1), the current through OLEDD1

:

[0078] [0078]

(1-1) (1-1)

[0079] 上述公式(1-1)中, [0079] the above formula (1-1),

为氧化层电容(OxideCapacitance)。 It is oxide capacitance (OxideCapacitance).

为电子漂移率(ElectronMobility)。 Electronic drift rate (ElectronMobility). W为通道宽度(ChannelWidth)。 W is a channel width (ChannelWidth). L为通道长度(ChannelLength)。 L is a channel length (ChannelLength).

为流经驱动晶体管P4的电流。 For the current flowing through the driving transistor P4. 其中 among them

为端点S与端点G的压差。 Differential pressure endpoint with the endpoint G, S.

为驱动晶体管P4的临界电压。 The threshold voltage of the driving transistor P4. 本实施例假设 Embodiment of the present embodiment is assumed

,

、W及L为固定值。 , W, and L is a fixed value. 因此可得下列公式(1-2),其中K为常数。 Thus it can be obtained the following equation (1-2), where K is a constant.

[0080] [0080]

(1-2) (1-2)

[0081] 接着,由公式(1-1)可获得下列公式(1-3)。 [0081] Next, the (1-1) equation is obtained by the following equation (1-3).

[0082] [0082]

(1-3) (1-3)

[0083] 另外,端点S连接到定电压Vdd,端点S的电压与定电压Vdd相同,因此可得下列公式(1-4),其中 [0083] Further, S is connected to a constant voltage terminal Vdd, the same voltage and fixed voltage Vdd terminal S, and thus can be obtained the following equation (1-4), wherein

为端点S的电压。 Is the voltage at terminal S.

[0084] [0084]

(1-4) (1-4)

[0085] 将公式(1-4)代入公式(1-3),可得下列公式(1-5),其中 [0085] Equation (1-4) is substituted into equation (1-3), can be obtained the following equation (1-5), wherein

为端点G的电压。 Is the voltage at terminal G.

[0086] [0086]

(1-5) (1-5)

[0087] (2)、临界电压储存: [0087] (2), the threshold voltage of storage:

[0088] 图3是依照本发明的第一实施例的一种扰动讯号的示意图。 [0088] FIG. 3 is a schematic view of a first embodiment according to one embodiment of the disturbance signal of the present invention. 图4是图2的一种操作状态的示意图。 4 is a schematic view of an operating state 2. 请合并参照图3与图4,在本实施例中,扰动讯号CSL以接地电压为准位,作上下振幅相同的扰动(±Δ)。 Please refer to FIG. 3 and FIG. 4, in the present embodiment, the disturbance signal CSL to the ground voltage taken as the level for the same vertical amplitude perturbation (± Δ). 在正周期,扰动讯号CSL的电压 In the positive voltage cycle, the perturbation signals CSL

以Vcsh表示之;在负周期,扰动讯号CSL的电压以Vcsl表示之,如下列公式(1-6)。 To represent the Vcsh; negative cycle, the voltage of the disturbance signal CSL to Vcsl of a representation, such as the following equation (1-6).

[0089] [0089]

or

(1-6) (1-6)

[0090] 图4中虚线代表开关为截止状态,亦即此时扰动开关晶体管P2与显示开关晶体管P3为截止状态,资料开关晶体管P1为导通状态。 [0090] FIG 4 is a broken line denotes a switch OFF state, i.e. this time disturbance of the switching transistor the switching transistor P2 and P3 to the display OFF state, the data switching transistor P1 is turned state. when

被充电到 It is charged to

时,驱动晶体管P4会截止(因为 When the drive transistor P4 will be turned off (because

)。 ). 此时端点C的电压与数据线DL所提供的数据讯号的电压 At this time, the data signal terminal C of the voltage of the data lines DL supplied voltage

相同,如下列公式(1-7)。 The same as the following equation (1-7).

[0091] C端点的电压: [0091] C endpoint voltage:

(1-7) (1-7)

[0092] 承上述,端点G的电压如下列公式(1-8)所示。 [0092] Bearing the above, the voltage at terminal G, as in the following equation (1-8) shown in FIG. 储存电容Ccs的跨压 The voltage across the storage capacitor Ccs

如下列公式(1-9)所示。 As shown in the following equation (1-9).

[0093] [0093]

(1-8) (1-8)

[0094] [0094]

(1-9) (1-9)

[0095] (3)、扰动讯号: [0095] (3), the disturbance signal:

[0096] 图5是图2的另一种操作状态的示意图。 [0096] FIG. 5 is a schematic diagram of another operating state of FIG. 图5中,虚线代表开关为截止状态,亦即此时数据开关晶体管P1为截止状态,扰动开关晶体管P2与显示开关晶体管P3为导通状态。 5, the dotted line represents a state switch is turned off, i.e., the data at this time the switching transistor P1 is turned off, the switching transistor P2 disturbance transistor P3 switching the display ON state.

[0097] 当扰动讯号CSL在负周期时,可获得下列公式(1-10),此时端点C的电压Vc如下列公式(1-11)。 [0097] When the disturbance signal CSL in a negative cycle, the following equation is obtained (1-10), when the voltage Vc of the terminal C as in the following equation (1-11).

[0098] [0098]

(1-10) (1-10)

[0099] [0099]

(1-11) (1-11)

[0100] 端点C的电位变化量 A potential variation of [0100] the terminal C

如下列公式(1-12)。 The following equation (1-12). 端点G的电位变化量 G is the amount of potential change in the endpoint

如下列公式(1-13)。 The following equation (1-13).

[0101] [0101]

(1-12) (1-12)

[0102] [0102]

(1-13) (1-13)

[0103] 接着可由下列公式(1-14)推得端点G的电压,并由下列公式(1-15)推得流经OLEDD1的电流。 [0103] followed by the following formula (1-14) is deduced terminal voltage G, and the following equation (1-15) is deduced OLEDD1 current flows.

[0104] [0104]

(1-14) (1-14)

[0105] [0105]

(1-15) (1-15)

[0106] 同理可类推,当扰动讯号CSL在正周期时,公式(1-15)中的 [0106] Similarly by analogy, when the disturbance signal CSL during a positive cycle, equation (1-15) in

会由 It will be made

所取代,如下列公式(1-15')。 Substituted, as in the following formula (1-15 ').

[0107] [0107]

(1-15') (1-15 ')

[0108] 若定义 [0108] When the defined

. 假设 Hypothesis

经过扰动而变为 After the disturbance becomes

的情况下,流经OLEDD1的电流则为下列公式(1-16)。 In the case where the current flowing through OLEDD1 compared with the following equation (1-16).

[0109] [0109]

(1-16) (1-16)

[0110] 假设 [0110] Suppose

经过扰动而变为 After the disturbance becomes

的情况下,公式(1-16)中的 In the case where, in equation (1-16) in

会由 It will be made

所取代,如下列公式(1-16')。 Substituted, as in the following formula (1-16 ').

[0111] [0111]

(1-16') (1-16 ')

[0112] (三)、画素波型设计 [0112] (c), pixel design wave

[0113] 图6是依照本发明的第一实施例的一种驱动波形的示意图。 [0113] FIG. 6 is a schematic view of driving waveforms according to one embodiment of the first embodiment of the present invention. 图7是依照本发明的第一实施例的一种画素结构的驱动方法的流程图。 FIG 7 is a flowchart of a method of driving the pixel configuration of a first embodiment of the present invention. 请合并参照图6与图7。 Please refer to FIG. 6 and FIG. 7.

[0114] 图6中,扫描线GL的扫描讯号可控制是否将数据线DL的数据讯号写入储存电容Ccs。 In [0114] FIG. 6, the scanning of the scanning signal line GL can control whether the data signal is written to the data line DL storage capacitor Ccs. 显示控制讯号DCL可控制驱动晶体管P4的输出电流是否流入OLEDD1。 DCL display control signal may control whether the driving current of the output transistor P4 flows OLEDD1. 扰动讯号CSL为画素外部输入的扰动讯号,此讯号以零电压位准,作±Δ的周期扰动。 Disturbance signal CSL external disturbance inputted pixel signal, this signal to a zero voltage level, for the periodic perturbations ± Δ.

可使驱动晶体管P4产生电流输出的电压讯号。 P4 driving transistor can generate a voltage signal current output. 期间T1为临界电压储存与数据写入。 T1 is the threshold voltage during storage and data writing. 期间T2为资料扰动。 During T2 to data disturbance.

[0115] 在图7中,资料开关晶体管P1可依据扫描讯号而决定导通与否(步骤S701)。 [0115] In FIG. 7, the data switching transistor P1 may be turned on or not is determined (step S701) based on a scanning signal. 当数据开关晶体管P1导通时,数据线DL的数据讯号可传递至储存电容Ccs的第一端,藉以透过驱动晶体管P4来驱动OLEDD1(步骤S702),如期间T1。 When the data switching transistor P1 is turned on, the data signal line DL data may be transmitted to the first end of the storage capacitance Ccs, so as to drive through the drive transistor P4 OLEDD1 (step S702), such as the period T1. 当数据开关晶体管P1截止时,透过扰动开关晶体管P2,扰动讯号CSL可传递至储存电容Ccs的第一端(步骤S703),如期间T2。 When the data switching transistor P1 is turned off, the switching transistor P2 through the disturbance, the disturbance signal CSL may be transmitted to the first end of the storage capacitance Ccs (step S703), as during T2.

[0116] 请注意,扰动讯号CSL进行周期性的扰动时,流经驱动晶体管P4的电流以及流经OLEDD1的电流也会随之周期性的扰动。 [0116] Note that the disturbance signal CSL periodic disturbance, the current flowing through the driving transistor and the current flowing through P4 OLEDD1 will follow a periodic disturbance. 此作法可有效改善习知高电流应力的情形,改善组件劣化的情况,并能延长画素结构的寿命。 This approach can improve the situation of the conventional high current stress, improvement of component deterioration, and can extend the life of the pixel structure. 不仅如此,扰动讯号CSL的频率高于人眼所能辨识的频率时,人眼仍会将OLEDD1发出的亮度是为一固定值,而不会有闪烁的情况发生。 Not only that, a frequency higher than the frequency disturbance signal CSL can identify the human eye, the human eye will still OLEDD1 luminance is emitted to a fixed value, the situation will not flicker.

[0117] 值得一提的是,虽然上述实施例中已经对画素结构及其驱动方法描绘出了一个可能的型态,但所属技术领域中具有通常知识者应当知道,各厂商对于画素结构及其驱动方法的设计都不一样,因此本发明的应用当不限制于此种可能的型态。 [0117] It is worth mentioning that, although the above embodiment has the pixel structure and a driving method for depicts one possible patterns, but those skilled in the art having ordinary knowledge should be appreciated that, for the pixel structure and the manufacturers design driving method is different, and therefore the present invention when applied is not limited to such patterns possible. 换言之,只要是停止提供数据讯号至画素结构时,提供扰动讯号至画素结构,就已经是符合了本发明的精神所在。 In other words, as long as the data signal when to stop providing pixel structure, providing perturbation signals to the pixel structure, it is already in line with the spirit of the invention. 以下再举几个实施例以便本领域具有通常知识者能够更进一步的了解本发明的精神,并实施本发明。 The following examples are provided to further few ordinary skills in the art can be better understanding of the spirit of the present invention, and the embodiment of the present invention.

[0118] 第二实施例 [0118] Second Embodiment

[0119] (一)画素结构说明 [0119] (a) described pixel structure

[0120] 图8是依照本发明的第一实施例的一种画素结构的示意图。 [0120] FIG. 8 is a schematic diagram of a pixel structure according to a first embodiment of the present invention. 图9是图8的一种操作状态的示意图。 9 is a schematic view of an operation state 8. 图10是图8的另一种操作状态的示意图。 FIG 10 is a schematic diagram of another operating state of FIG. 8. 图11是依照本发明的第一实施例的一种扰动讯号的示意图。 FIG 11 is a schematic view of a first embodiment according to one embodiment of the disturbance signal of the present invention. 请合并参照图8~图11。 Please refer to FIGS. 8 to 11. 图8的画素结构11与图2的画素结构相类似。 Pixel structure 11 of FIG. 8 is similar to the pixel structure of FIG. 不同之处在于,画素结构11更包括分流驱动晶体管P6与分流开关晶体管P5。 Except that, the pixel structure further includes a bypass drive transistor 11 and shunt switching transistor P6 P5. 画素结构11使用了分流技术,为6T2C的画素结构。 11 pixel structure using streaming technology, to the pixel structure of 6T2C.

[0121] 分流驱动晶体管P6的第一端耦接定电压Vdd。 [0121] driving the shunt transistor P6 is coupled to a first terminal of constant voltage Vdd. 分流驱动晶体管P6的第二端耦接驱动晶体管P4的第二端。 Driving a second shunt transistor P6 terminal is coupled to drive the second terminal of the transistor P4. 分流开关晶体管P5具有第一端、第二端与闸极。 Shunt switching transistor P5 having a first end, a second end of the gate. 分流开关晶体管P5的第一端耦接分流驱动晶体管P6的闸极。 Shunt switching transistor P5 is coupled to a first end of the shunt gate of the driving transistor P6. 分流开关晶体管P5的第二端耦接驱动晶体管P4的闸极。 A second terminal of the shunt switching transistor P5 is coupled to the driving gate electrode of the transistor P4. 分流开关晶体管P5的闸极可接收显示控制讯号DCL。 Shunt switch gate of transistor P5 may receive a display control signal DCL. 在本实施例中,分流驱动晶体管P6与驱动晶体管P4同为P通道晶体管,分流开关晶体管P5与显示开关晶体管P3同为P通道晶体管。 In the present embodiment, the shunt transistor P6 driving of the driving transistor is a P-channel transistor with P4, P5 and the shunt switching transistor the switching transistor display the same P-channel transistor P3.

[0122] 分流开关晶体管P5的功能与显示开关晶体管P3的功能相类似,可作为开关使用。 [0122] The shunt switching transistor P5 transistor P3 switching functions and display similar functions, can be used as a switch. 分流驱动晶体管P6的功能与驱动晶体管P4的功能相类似,可用来驱动OLEDD1。 Shunt transistor P6 driving function of the drive transistor P4 functions similarly, be used to drive OLEDD1. 当显示开关晶体管P3导通时,分流开关晶体管P5也会随之导通;反之,当显示开关晶体管P3截止时,分流开关晶体管P5也会随之截止。 When the display switching transistor P3 is turned on, the shunt switch will also transistor P5 is turned on; the other hand, when the display switching transistor P3 is turned off, transistor P5 will follow the shunt switch is turned off. 值得注意的是,当显示开关晶体管P3与分流开关晶体管P5导通时,分流驱动晶体管P6的闸极与驱动晶体管P4的闸极能获得大致上相同的电压,使分流驱动晶体管P6与驱动晶体管P4具有相同的工作模式。 Notably, when the display switching transistor P3 and the shunt switching transistor P5 is turned on, the driving transistor P6 shunt gate of the driving transistor P4 and a gate voltage is substantially the same can be obtained, so that the shunt transistor driving the drive transistor P4 P6 It has the same operating mode. 定电压Vdd所提供的电流可分别透过分流驱动晶体管P6与驱动晶体管P4而流至OLEDD1。 Current constant voltage Vdd is provided to drive the transistor P6 may be the drive transistor P4 flows through the shunt to OLEDD1. 换言之,分流驱动晶体管P6具有分流功能,可分摊流经驱动晶体管P4的电流。 In other words, the driving transistor P6 having a shunt shunt function, the current flowing through the driving transistor P4 can be shared.

[0123] 画素结构11不但具有与图2中画素结构10相类似的功能,而且可使驱动晶体管P4、分流驱动晶体管P6的操作电压降低。 [0123] The pixel structure 11 only has functions similar to those in the pixel structure of FIG. 210, and can drive transistor P4, P6 shunt operation voltage of the driving transistor is reduced. 驱动晶体管P4与分流驱动晶体管P6可选用耐压较低晶体管来实施,同时也可减少功率消耗。 Driving the drive transistor P4 of the shunt transistor P6 optional low voltage transistors embodiment, it can also reduce power consumption. 以下提供公式说明供熟习本领域技术者参详。 The following formulas provide instructions for those skilled in the present art reference details.

[0124] (二)、画素驱动方法 [0124] (b), the driving method of pixel

[0125] 驱动晶体管P4的输出电流如公式(2-1),其中 [0125] the output current of the driving transistor P4 as shown in Equation (2-1), wherein

为氧化层电容。 An oxide layer capacitance. W为通道宽度。 W is the channel width. L为通道长度。 L is the channel length.

[0126] [0126]

(2-1) (2-1)

[0127] 这里假设 [0127] It is assumed here

,

、W及L为固定值。 , W, and L is a fixed value. 因此令 So make

[0128] [0128]

(2-2) (2-2)

[0129] 上述K为常数。 [0129] The K is a constant.

[0130] 所以(2-1)可写成下列公式(2-3): [0130] Therefore (2-1) can be written as the following equation (2-3):

[0131] [0131]

(2-3) (2-3)

[0132] [0132]

(2-4) (2-4)

[0133] 将公式(2-4)代入公式(2-3),可得公式(2-5)。 [0133] Equation (2-4) is substituted into equation (2-3), the formula can be obtained (2-5).

[0134] [0134]

(2-5) (2-5)

[0135] 临界电压储存:当扰动开关晶体管P2、显示开关晶体管P3、分流开关晶体管P5与分流驱动晶体管P6为截止状态,数据开关晶体管P1为导通状态(如图9所示)。 [0135] the threshold voltage of storage: When the disturbance switching transistors P2, P3 display switching transistor, the shunt transistor P5 shunt switch drive transistor P6 is turned off, the data switching transistor P1 is turned on state (FIG. 9).

[0136] 当 [0136] When

被充到电到 To be charged to electricity

时,驱动晶体管P4为截止状态(因为 When the driving transistor P4 is OFF state (since

)。 ).

[0137] 当 [0137] When

时或当 Or when

时 (2-6) When (2-6)

[0138] 端点C的电压 Voltage [0138] of the terminal C

(2-7) (2-7)

[0139] 上述公式(2-7)中,m为实数,且 [0139] the above formula (2-7), m is a real number, and

. 即假设本实施例的 I.e., the present embodiment is assumed

为第一实施例 A first embodiment

的m倍。 M times.

[0140] 端点G的电压为 [0140] G is the voltage at terminal

(2-8) (2-8)

[0141] 则 [0141] the

上跨压 The voltage across the

(2-9) (2-9)

[0142] 扰动讯号:当资料开关晶体管P1为截止状态,扰动开关晶体管P2、显示开关晶体管P3、分流开关晶体管P5为导通状态(如图10所示)。 [0142] Disturbance Signal: data when the switching transistor P1 is turned off, the switching transistor P2 disturbance, display switch transistor P3, P5 shunt switching transistor to a conducting state (see Figure 10).

[0143] 当扰动讯号CSL在负周期时。 [0143] When the disturbance signal CSL negative cycle.

[0144] [0144]

(2-10) (2-10)

[0145] [0145]

(2-11) (2-11)

[0146] 端点C的电位变化量如下列公式(2-12)。 A potential variation of [0146] terminal C as the following equation (2-12). 端点G的电位变化量如下列公式(2-13)。 G endpoint amount of potential change as the following equation (2-13).

[0147] [0147]

(2-12) (2-12)

[0148] [0148]

(2-13) (2-13)

[0149] [0149]

(2-14) (2-14)

[0150] 接着可推得流经驱动晶体管P4的电流 [0150] may then push the driving current flowing through the transistor P4

,如下列公式(2-15)。 As the following equation (2-15). 流经分流驱动晶体管P6的电流 Through the shunt current drive transistor P6

,如下列公式(2-16)。 As the following equation (2-16).

[0151] [0151]

(2-15) (2-15)

(2-16) (2-16)

[0152] 同理可类推,当扰动讯号CSL在正周期时,公式(2-15)与公式(2-16)中的 [0152] Similarly by analogy, when the disturbance signal CSL during a positive cycle, equation (2-15) and equation (2-16) in

会由 It will be made

所取代,如下列公式(2-15')与公式(2-16')。 Substituted, as in the following formula (2-15 ') and the formula (2-16').

[0153] [0153]

(2-15') (2-15 ')

[0154] [0154]

(2-16') (2-16 ')

[0155] 若定义 [0155] When the defined

.

. 假设 Hypothesis

经过扰动而变为 After the disturbance becomes

的情况下,公式(2-15)可改写为下列公式(2-17),公式(2-16)可改写为下列公式(2-18)。 In the case of formula (2-15) can be rewritten as the following equation (2-17), the formula (2-16) can be rewritten as the following equation (2-18).

[0156] [0156]

(2-17) (2-17)

[0157] [0157]

(2-18) (2-18)

[0158] 假设 [0158] Suppose

经过扰动而变为 After the disturbance becomes

的情况下,公式(2-17)、公式(2-18)中的 In the case of formula (2-17), the formula (2-18) in

会由 It will be made

所取代,如下列公式(2-17')、公式(2-18')。 Substituted, as in the following formula (2-17 '), the formula (2-18').

[0159] [0159]

(2-17') (2-17 ')

[0160] [0160]

(2-18') (2-18 ')

[0161] 结论:临界电压的影响抵消,可使分流驱动晶体管P6与驱动晶体管P4的输出电流不受临界电压变异影响。 [0161] Conclusion: Effect of the threshold voltage canceling, can affect driving shunt transistor P6 and P4 output the driving current from the transistor threshold voltage variations.

[0162] 接着,分析通过驱动晶体管P4、分流驱动晶体管P6与OLEDD1的电流。 [0162] Next, by analyzing the driving transistor P4, and the current driving transistor P6 OLEDD1 shunt. 在此假设本实施例流经OLEDD1的电流量与第一实施例相同,如公式(2-19)。 In the present embodiment is assumed here that the amount of current flowing through the same OLEDD1 embodiment of the first embodiment, as shown in equation (2-19). 另外,假设驱动晶体管P4与分流驱动晶体管P6的K值相同或相近,如公式(2-20)。 It is assumed that the same or similar drive transistor P4 and P6 of the drive transistor shunt K value, equation (2-20).

[0163] [0163]

(2-19) (2-19)

[0164] [0164]

(2-20) (2-20)

[0165] 由公式(17)与公式(18),且令 [0165] by equation (17) with equation (18), and let

[0166] [0166]

or

(2-21) (2-21)

[0167] [0167]

(2-22) (2-22)

[0168] 上述公式(2-22)中, [0168] the above formula (2-22), and

,

,

为常数。 It is a constant. 接着,可获得下列公式(2-23)。 Subsequently, obtained the following equation (2-23).

[0169] [0169]

(2-23) (2-23)

[0170] 在本实施例中,驱动画素晶体管P4与分流驱动画素晶体管P6的总输出电流为( [0170] In the present embodiment, the pixel driving transistors P4 and P6 of the shunt transistor driven pixel total output current (

),可得下列公式(2-24),其中 ), Can be obtained the following equation (2-24), wherein

为第一实施例驱动画素晶体管P4的输出电流。 Example pixel output current driving transistor P4 first embodiment. 另一方面, on the other hand,

可由下列公式(2-25)所获得,且 By the following formula (2-25) is obtained, and

可由下列公式(2-26)所获得。 By the following formula (2-26) is obtained.

[0171] [0171]

(2-24) (2-24)

[0172] [0172]

(2-25) (2-25)

[0173] [0173]

(2-26) (2-26)

[0174] 将公式(2-25)与公式(2-26)代入公式(2-24),可获得下列公式(2-27)。 [0174] The equation (2-25) and equation (2-26) are substituted into equation (2-24), obtained the following equation (2-27).

[0175] [0175]

[0176] [0176]

[0177] [0177]

(2-27) (2-27)

[0178] 所得的 [0178] The resulting

有两个值 There are two values

versus

.

[0179] [0179]

(2-28) (2-28)

[0180] 因为 [0180] because

And

[0181] 当 [0181] When

时: Time:

(合), (Co),

(不合) (Sub)

[0182] 当 [0182] When

时: Time:

(合), (Co),

(合) (Co)

[0183] 因此,同时满足 [0183] Accordingly, while meeting

时, Time,

[0184] [0184]

(2-29) (2-29)

[0185] 公式(2-29)代入公式(2-23)式,可得到本实施例的一个驱动晶体管的输出电流,如下列公式(2-30) [0185] Formula (2-29) are substituted into equation (2-23), we obtain the output current of a driving transistor of the present embodiment, as in the following equation (2-30)

[0186] [0186]

(2-30) (2-30)

[0187] 接着,令 [0187] Next, to make

[0188] [0188]

;

(2-31) (2-31)

[0189] [0189]

(2-32) (2-32)

[0190] 结论: [0190] Conclusion:

[0191] 1.本实施例中,驱动晶体管P4与分流驱动晶体管的闸极所需的操作电压为第一实施例驱动晶体管P4的 [0191] 1. In the present embodiment, the driving transistor P4 and the gate of the driving transistor shunt required operating voltage of a first embodiment of the driving transistor P4

.

[0192] 2.本实施例中,扰动讯号CSL的电压为第一实施例的 [0192] 2. In this embodiment, the disturbance voltage signal CSL is a first embodiment

.

[0193] 分流电流分析: [0193] Shunt Current Analysis:

[0194] 由公式(2-21)与公式(2-32)式,验证公式(2-19) [0194] by the equation (2-21) and equation (2-32), we verify equation (2-19)

[0195] [0195]

[0196] 结论:本实施例的画素结构11使用两个相近的驱动晶体管(P4、P6),可获得与第一实施例通过OLEDD1相同的电流大小。 [0196] Conclusion: the pixel structure 11 of the present embodiment is similar to the use of two drive transistors (P4, P6), obtained in the first embodiment by the same magnitude current OLEDD1.

[0197] 晶体管的功率消耗分析: [0197] Analysis of the power consumption of the transistor:

[0198] [0198]

(3-33) (3-33)

[0199] 公式(3-33)可简化如下公式(3-33')。 [0199] Formula (3-33) can be simplified to the following formula (3-33 ').

[0200] [0200]

(3-33') (3-33 ')

[0201] 所以驱动晶体管的功率消耗如下列公式(3-34): [0201] the power consumption of the driving transistor such as the following equation (3-34):

[0202] [0202]

(3-34) (3-34)

[0203] 再由公式(3-34)可知: [0203] and then clear from equation (3-34):

[0204] [0204]

(3-35) (3-35)

[0205] 结论:本实施例分流驱动晶体管P6与驱动晶体管P4总消耗功率小于第一实施例驱动晶体管P4的消耗功率。 [0205] Conclusion: Example shunt driving transistor P6 and the total power consumption of the driving transistor P4 is smaller than the first embodiment, the power consumption of the driving transistor P4 to the present embodiment.

[0206] (三)、画素波型设计 [0206] (c), pixel design wave

[0207] 请参照图11,扫描线GL的扫描讯号可控制是否将数据线DL的数据讯号写入储存电容Ccs。 [0207] Referring to FIG 11, the scanning of the scanning signal line GL can control whether the data signal is written to the data line DL storage capacitor Ccs. DL表示一条dataline的讯号。 DL represents a dataline signal. 显示控制讯号DCL可控制驱动晶体管P4与分流驱动晶体管P4的输出电流是否流入OLEDD1。 DCL display control signal may control the driving of the driving transistor P4 whether the output current of the shunt transistor P4 flows OLEDD1. 扰动讯号CSL为画素外部输入的扰动讯号,此讯号以零电压位准,作±Δnew的周期扰动。 Disturbance signal CSL external disturbance inputted pixel signal, this signal to a zero voltage level, for the periodic perturbations ± Δnew.

可使驱动晶体管P4与分流驱动晶体管P4产生电流输出的电压讯号。 The driving transistor can shunt the driving transistor P4 and P4 to generate current output voltage signal. 期间T1为临界电压储存与数据写入。 T1 is the threshold voltage during storage and data writing. 期间T2为资料扰动。 During T2 to data disturbance.

[0208] 综合上述,第二实施例不但可达成与第一实施例相类似的功效,还可降低驱动晶体管与分流驱动晶体管的闸极操作电压以及扰动讯号的电压。 [0208] In summary, the second embodiment can be achieved only with the first embodiment, a similar effect, can reduce gate of the shunt transistor driving the driving transistor and the operating voltage of the signal disturbance. 此作法不但可有效降低画素结构11的总功率消耗。 This approach is not only effective in reducing the pixel structure 11 of the total power consumption. 驱动晶体管与分流驱动晶体管的规格限制也较为宽松,有利于实施时晶体管的选用。 Specification limits of the driving transistor and the driving transistor of the shunt is relatively relaxed, facilitate selection transistor implementation.

[0209] 另外,熟习本领域技术者也可依其需求改变上述实施例的画素结构。 [0209] Further, those skilled in the present art also according to their needs change pixel structure of the above embodiment. 举例来说,在第二实施例中,可将分流驱动晶体管P6与分流开关晶体管P5配置在画素数组之外,例如可配置于显示器的边框中。 For example, in the second embodiment, the drive transistor can shunt and the shunt switching transistor P5 P6 arranged outside the pixel array, for example arranged on the bezel of the display. 如此可有效改善画素结构11的开口率(aperturerate)。 So can effectively improve the pixel aperture ratio (aperturerate) structure 11.

[0210] 又例如,第一实施例中,储存电容Ccs并非必要构件。 [0210] As another example, in the first embodiment, the storage capacitance Ccs is not essential components. 熟习本领域技术者可依其需求省略储存电容Ccs。 Those skilled in this art will be omitted according to their needs storage capacitor Ccs.

[0211] 综上所述,本发明停止提供数据讯号至画素结构时,可提供扰动讯号至画素结构。 [0211] In summary, the present invention provides a data signal is stopped to when pixel structure, the disturbance signal may be provided to the pixel structure. 如此一来,可提升画素结构的寿命。 Thus, the pixel structure can be improved lifetime. 另外,本发明的实施例还具有下列功效: Further, embodiments of the present invention has the following effects:

[0212] 1.在驱动晶体管的第一端与闸极端之间配置一个临界电压电容,可降低临界电压的变异,使画素的亮度表现更加稳定。 [0212] 1 disposed between the first end and the gate terminal of the drive transistor threshold voltage of a capacitor, it can reduce the threshold voltage variation of the pixel brightness performance more stable.

[0213] 2.在画素结构中可配置分流驱动晶体管与分流开关晶体管,藉以分摊驱动晶体管的电流量。 [0213] 2. In the pixel structure can be configured in shunt shunt switching transistor and the driving transistor, thereby sharing the current amount of the driving transistor. 如此不但可降低画素结构的总耗电量。 So not only can reduce the total power consumption of the pixel structure. 驱动晶体管与分流晶体管的闸极操作电压也能被降低,亦及其晶体管的规格限制也能够降低,以利实施时晶体管的选用。 The gate of the driving transistor and a shunt transistor operating voltage can also be reduced, and also limit the size of the transistor can be reduced to facilitate the selection transistor implementation. 另外,扰动讯号的电压也能够被降低。 Further, the voltage perturbation signal can also be reduced.

[0214] 3.分流驱动晶体管与分流开关晶体管可配置于画素数组之外,藉以改善画素结构的开口率。 [0214] 3. The shunt shunt switching transistor and the driving transistor may be disposed outside the pixel array, so as to improve the aperture ratio of the pixel structure.

[0215] 虽然本发明已以实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作些许更动与润饰,故本发明的保护范围当视后附的申请专利范围所界定者为准。 [0215] Although the present invention has been disclosed in the above embodiments, they are not intended to limit the present invention, any skilled in the art having ordinary knowledge, without departing from the spirit and scope of the present disclosure, may make various modifications and retouch, so the scope of the invention as defined by the appended scope of the following claims and their equivalents.

Claims (8)

1.一种画素结构,其特征是包括:一储存电容,具有一第一端与一第二端;一数据开关晶体管,依据一扫描讯号提供一数据讯号至该储存电容的第一端;一扰动开关晶体管,当该资料开关晶体管截止时,该扰动开关晶体管提供一扰动讯号至该储存电容的第一端;一驱动晶体管,具有一第一端、一第二端与一闸极,该驱动晶体管的第一端耦接一定电压,该驱动晶体管的闸极耦接该储存电容的第二端;一显示开关晶体管,具有一第一端、一第二端与一闸极,该显示开关晶体管的第一端耦接该驱动晶体管的第二端,该显示开关晶体管的闸极接收一显示控制讯号;以及一有机发光二极管,其阳极耦接该显示开关晶体管的第二端,其阴极耦接一接地端。 A pixel structure, which is characterized in comprising: a storage capacitor having a first end and a second end; a data switching transistor, providing a data signal to a first terminal of the storage capacitor according to a scan signal; a disturbance switching transistor when the switching transistor is turned off material, the disturbance of the switching transistor provides a perturbation signal to a first terminal of the storage capacitor; a driving transistor having a first terminal, a second terminal and a gate, the driving a second end coupled to a first terminal of the constant voltage of the transistor, a gate electrode of the driving transistor coupled to the storage capacitor; a display switching transistor having a first terminal, a second terminal and a gate, the display switching transistor a first terminal coupled to the second terminal of the drive transistor, the display switching transistor gate receives a display control signal; and an organic light emitting diode display having an anode coupled to the second terminal of the switch transistor and a cathode coupled a ground terminal.
2.根据权利要求1所述的画素结构,其特征是:其中该数据开关晶体管具有一第一端、一第二端与一闸极,该资料开关晶体管的第一端耦接一数据线并接收该数据讯号,该数据开关晶体管的闸极耦接一扫描线并接收该扫描讯号,该数据开关晶体管的第二端耦接该储存电容的第一端。 2. The pixel structure according to claim 1, characterized in that: wherein the data switching transistor having a first terminal, a second terminal and a gate, the switching transistor of the first data terminal coupled to a data line and receiving the data signal, the data switching transistor gate electrode coupled to a scan line receiving the scan signal and the data terminal of a second switching transistor coupled to a first terminal of the storage capacitor.
3.根据权利要求2所述的画素结构,其特征是:其中该扰动开关晶体管具有一第一端、一第二端与一闸极,该扰动开关晶体管的第一端接收该扰动讯号,该扰动开关晶体管的闸极耦接该扫描线并接收该扫描讯号,该扰动开关晶体管的第二端耦接该储存电容的第一端,该扰动开关晶体管与该资料开关晶体管由一P信道晶体管与一N信道晶体管所组成。 3. The pixel structure according to claim 2, characterized in that: wherein the disturbance switching transistor having a first terminal, a second terminal and a gate, a first terminal for receiving the disturbance of the disturbance signal of the switching transistor, the gate disturbance switching transistor is coupled to the scan lines and receiving the scan signals, the disturbance of the switching transistor second terminal coupled to a first terminal of the storage capacitor, the switching transistor and the disturbance data switching transistor is a P-channel transistor an N-channel transistor is formed.
4.根据权利要求1所述的画素结构,其特征是更包括:一临界电压电容,耦接于该显示开关晶体管的第一端与闸极之间。 4. The pixel structure according to claim 1, characterized in further comprising: a threshold voltage capacitor coupled between the first terminal and the gate of the switching transistor of the display.
5.根据权利要求1所述的画素结构,其特征是更包括:一分流驱动晶体管,具有一第一端、一第二端与一闸极,该分流驱动晶体管的第一端耦接该定电压,该分流驱动晶体管的第二端耦接该驱动晶体管的第二端;以及一分流开关晶体管,具有一第一端、一第二端与一闸极,该分流开关晶体管的第一端耦接该分流驱动晶体管的闸极,该分流开关晶体管的第二端耦接该驱动晶体管的闸极,该分流开关晶体管的闸极接收该显示控制讯号。 The pixel structure according to claim 1, characterized in further comprising: driving a shunt transistor having a first terminal, a second terminal and a gate, the shunt drive transistor coupled to the first end of a given voltage, a second terminal of the second terminal of the shunt transistor is coupled to the driving of the driving transistor; and a shunt switching transistor having a first terminal, a second terminal and a gate, a first terminal of the shunt switching transistor the shunt is connected to a gate of the driving transistor, the shunt switching transistor is coupled to the second terminal of the driving transistor, a gate of the shunt switching transistor has a gate receiving the display control signal.
6.根据权利要求5所述的画素结构,其特征是:其中该驱动晶体管与该显示开关晶体管配置于一画素数组之内,该分流驱动晶体管与该分流开关晶体管配置于该画素数组之外。 6. The pixel structure as claimed in claim 5, characterized in that: wherein the drive transistor and the display switching transistors in a pixel array of the drive transistor shunt disposed outside the pixel array and the shunt switching transistor.
7.根据权利要求5所述的画素结构,其特征是:其中该扰动讯号为周期讯号,该扰动讯号以零电压位准在正周期与负周期分别进行振幅大小相同的反相扰动。 7. The pixel structure as claimed in claim 5, characterized in that: wherein the signal is a periodic disturbance signal, the disturbance signal to a zero voltage level for the same amplitude of the inverted perturbation positive and the negative cycle period respectively.
8.一种画素结构的驱动方法,其特征是:该画素结构包括一数据开关晶体管、一储存电容、一驱动晶体管与一有机发光二极管,该数据开关晶体管具有一第一端、一第二端与一闸极,该储存电容具有一第一端与一第二端,该驱动晶体管具有一第一端、一第二端与一闸极,该数据晶体管的第二端耦接该储存电容的第一端,该储存电容的第二端耦接该驱动晶体管的闸极,该驱动晶体管的第一端与第二端分别耦接一定电压与该有机发光二极管,该驱动方法,包括:依据一扫描讯号导通一数据开关晶体管;当该数据开关晶体管导通时,提供一数据讯号至该储存电容的第一端,藉以透过该驱动晶体管驱动该有机发光二极管;以及当该数据开关晶体管截止时,透过一扰动开关晶体管,提供一扰动讯号至该储存电容的第一端。 8. A driving method of a pixel structure, wherein: the data structure includes a pixel switching transistor, a storage capacitor, a driving transistor and an organic light emitting diode, the data switching transistor having a first end, a second end and a gate, the storage capacitor having a first end and a second end, the driving transistor having a first terminal, a second terminal and a gate, the transistor of the second data terminal coupled to the storage capacitor a first terminal, a second terminal of the storage capacitor is coupled to the gate of the driving transistor, the first and second ends of the driving transistor are coupled to a constant voltage to the organic light emitting diode, the driving method comprising: based on a a scan signal data switching transistor is turned on; when the data switching transistor is turned on, providing a data signal to the first terminal of the storage capacitor, so as to pass through the driving transistor drives the organic light emitting diode; and a switching transistor is turned off when the data when the switching transistor through a disturbance, a disturbance signal is provided to a first terminal of the storage capacitor.
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US6229506B1 (en) * 1997-04-23 2001-05-08 Sarnoff Corporation Active matrix light emitting diode pixel structure and concomitant method
US20050068271A1 (en) * 2003-09-29 2005-03-31 Shin-Tai Lo Active matrix organic electroluminescence display driving circuit
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WO2015149399A1 (en) * 2014-04-01 2015-10-08 深圳市华星光电技术有限公司 Pixel drive circuit and drive method of oled display

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