CN101715113B - Two-way radio embedded gateway based on ground digital television channels - Google Patents
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Abstract
The invention designs a two-way radio embedded gateway based on ground digital television channels, which is used for transmitting Ethernet data based on digital television radio channels. A system of the radio embedded gateway is used for converting the Ethernet data into TS flow data suitable for radio transmission, simultaneously receiving the TS flow data and converting the TS flow data into IP data. Different kinds of equipment of two network segments are distributed according to different IP addresses by users; IP packets transmitted by equipment which corresponds to all IPs are all packed into uniform TS flow data packets; the TS flow data packets are collected to a TS modulator interface for radio transmission; a receiving end executes opposite work; finally, the received TS packets are restored into IP packets; and an embedded processor is used for carrying out address analysis work for realizing the corresponding transmission of a transmitting end and a terminal. According to different application needs, the gateway can be used for building different network frames, such as one-way and two-way transmission in the same network segment, and one-way and two-way transmissionacross network segments. All kinds of flexible configurations can be realized by modifying power scripts and the support of all kinds of configurations is only used on the difference of software processing protocols practically.
Description
Technical field
Nowadays the technology of DTV through wireless transmission comparative maturity; Mainly be to realize through TDS-OFDM (Time DivisionSynchronic Orthogonal Frequency Division Multiplexing, time-division synchronous OFDM) technology.The wireless modulation-demodulation apparatus that now widespread has standard TS (Transport Stream, MPTS) stream on the market carries out the transmission of digital television signal.The present invention is exactly the gateway of these equipment interfaces of coupling, is used for remote, high-speed wireless Internet down and transmits, and has expanded the range of application of DTV wireless channel.
Background technology
The maturation of Along with computer technology and Internet technology, more and more equipments provide network interconnection function.The main purpose of these functions is to satisfy the demand of real-time Data Transmission.But current internet transmission technology only limits to wire transmission and short distance, hangs down the wireless transmission under the translational speed.The TS interface is mated in the present invention, can realize remote, high data rate transfers through the TS modulator-demodulator.The present invention can do various configurations flexibly according to the various network structure, as: single, double between two IP (InternetProtocol, the agreement that interconnects between the network) address field to wireless telecommunications; An address field single, double to wireless telecommunications.
Summary of the invention
Major function of the present invention utilizes digital-TV channel to transmit Ethernet data exactly.Native system is caught the IP packet of Ethernet, and whether the decision data bag needs to transmit.Transmit if desired and then the IP packet is packaged as the TS packet, otherwise, this packet abandoned.Simultaneously, when receiving the TS packet, need filter to the flag of frame position it, if transmitted be the IP data, then the TS data that receive are repacked the data into IP, and then send through Ethernet.
The user can distribute the distinct device of two network segments through different IP addresses; And the IP that all IP corresponding equipment are sent bag all is packaged into unified TS stream packets; Be aggregated into TS modulator interface and carry out wireless transmit, receiving terminal is done opposite work, at last the TS bag that receives is reduced into the IP bag; And carry out address resolution work by flush bonding processor, corresponding transmission with the terminal has realized making a start.
This gateway can be made various configurations flexibly according to the various network framework, as: unidirectional in the network segment, two-way, inter-network section unidirectional, transmitted in both directions.In fact support to various configurations only occurs in the difference of software processes agreement.The difference of casting aside software layer is come simple from hardware view whole system, and the connecting frame of summarizing hardware is as shown in Figure 1.
System's annexation and function are following among the present invention:
1, a kind of two-way radio embedded gateway based on ground digital television channels as shown in Figure 2 contains flush bonding processor (1), flash memory (2), series arrangement mouth (3), data storage (4), ethernet control chip (5), netting twine socket (6), output dual port buffer (7), input dual port buffer (8), programmable logic device (9), TS delivery outlet (10), TS input port (11).Wherein:
1.1. flush bonding processor (1) is through ethernet control chip (5) and network linking; Receive or send the IP bag; And process the work of data, i.e. the mutual conversion of IP bag and standard TS stream format claims that this process is that the IP bag is encapsulated as the TS stream packets and TS stream packets deblocking is the IP bag.
1.2. flash memory (2), series arrangement mouth (3), data storage (4) and flush bonding processor (1) are formed embedded minimum system, flash memory (2) is used for loading operation system kernel, driver and upper level applications; Data storage (4) is used as the cache exchanging space in the data handling procedure; Series arrangement mouth (3) is used for programming program, configuration script file, configuration-system attribute and transmission means.
1.3. output dual port buffer (7), input dual port buffer (8) are respectively as the data buffering that sends, receives two data path directions.Realize the data communication of flush bonding processor and programmable logic device according to concluding an agreement certainly.
1.4. programmable logic device (9) is responsible for the coupling of TS stream interface sequential, connects TS delivery outlet (10) and TS input port (11) simultaneously, carries out full duplex work, and can be according to different TS modulator-demodulator flexible configuration interface sequence parameters.The TS interface comprises 11 holding wires altogether, 8 parallel-by-bit data wires wherein, and 1 bit clock signal line, 1 bit synchronization signal line, 1 bit data useful signal line, the interface sketch map is shown in Fig. 3 (a), Fig. 3 (b).
2, be the 10MHz/100MHz adaptive chip at the ethernet control chip described in 1.1 (5).Flush bonding processor (1) drives this chip through driver, is connected to Ethernet and carries out full duplex transmitting-receiving IP bag.
3, transplanting be can realize through series arrangement mouth (3), and driver and upper level applications integrated operating system.All drivers and upper level applications all are stored in the flash memory (2), comprise unidirectional drive program, bi-directional drive program, inter-network section analysis program, same network segment analysis program.Revise the start configurable gateway address of script and configuration-system framework, the i.e. unidirectional or bilateral system of the unidirectional or bilateral system of same network segment, inter-network section.
4, two dual port buffers are separate, respectively receive, sending direction is as the data buffer zone between flush bonding processor (1) and the programmable logic device (9).
The job step of TS outbound course is following after the system power-up:
4.1. programmable logic device (9) reads the highest address bit of output dual port buffer, affirmation will be exported the load marking signal line level of dual port buffer (7) and drawn high.After this, the load marking signal line of programmable logic device (9) cycle detection output buffer.When treating that load marking signal line level is dragged down, programmable logic device (9) begins to get into operating state.
After 4.2. flush bonding processor (1) powers up; The load operation system; The load driver program; After driver load to be accomplished, write output dual port buffer (7) highest address bit arbitrary data the load marking signal line level of output dual port buffer (7) is dragged down, inform that programmable logic device (9) starts working.
4.3. sending output to flush bonding processor (1), programmable logic device (9) interrupts.Flush bonding processor (1) response output is interrupted, and writes frame TS data to exporting dual port buffer (7), and simultaneously, highest address bit arbitrary data notice programmable logic device (9) data of writing output dual port buffer (7) are successfully write.
4.4. programmable logic device (9) sends in the output and has no progeny, the load marking signal line of cycle detection output dual port buffer (7).When detecting its level and being dragged down, programmable logic device (9) reading of data and cooperate transmission timing that data are sent to TS delivery outlet (10) from output buffer, standard TS stream frame format is as shown in Figure 4, and TS MPTS sketch map is as shown in Figure 5.After frame data sent completion, programmable logic device (9) sent output once more and interrupts, and got into load marking signal detected state.So back and forth.
5, the job step of TS input direction is following after the system power-up:
5.1. programmable logic device (9) is caught the data that the TS demodulator is sent here through TS input port (11).At first detect frame head data and whether be hexadecimal 47, detect whether the characteristic flag bit is hexadecimal 177.If above-mentioned two conditions are all set up, programmable logic device (9) writes input dual port buffer (8) with the TS frame that receives, and sends the input interruption and give flush bonding processor (1).
5.2. flush bonding processor (1) responds in the input and has no progeny, and from the input block, reads frame data, gives the inner upper level applications of embedded system and handles, input is interrupted to wait for next time then.
6, programmable logic device (9) is responsible for the coupling of TS stream interface sequential.Though TS data packet frame form is fixed, because the data flow sequential that various TS modulator-demodulators receive and send there are differences, so through revising time sequence parameter in the programmable logic device to adapt to various TS modulator-demodulators.
The invention has the advantages that for different radio modems,, only need to change the parameter of control TS stream sequential in the programmable logic device if on TS stream interface sequential, change.If change at the IP end, for example be improved to IPv6 (Internet ProtocolVersion 6th, interconnection agreement sixth version between the network) agreement from IPv4 (InternetProtocol Version 4th, interconnection agreement is the 4th edition between the network) agreement.Program only need be made improvement at the flush bonding processor end and get final product.And all drivers and upper level applications all can be stored in the flash memory, only need to adjust the start script according to the network architecture of user's needs and get final product.
Description of drawings
Fig. 1 is a kind of typical application sketch map of the present invention.
Fig. 2 is a hardware configuration frame diagram of the present invention.
Fig. 3 is user interface diagram and signal definition.
Fig. 4 is a standard TS frame format.
Fig. 5 is the sequential sketch map of system transmissions TS stream of the present invention.
Fig. 6 is two network segment networking sketch mapes.
Embodiment
1, system works method and host-host protocol
For transmit direction, data are to become the TS bag by the IP data transaction, are deposited in the dual port buffer 7 by 1 TS flow data, notify programmable logic device to read then.The work of programmable logic device is that data are read and to meet the specific time sequence of TS stream modulator, sent data from 10 interfaces from buffering area, gives modulator and carries out wireless transmit, and the transfer of data sequential is as shown in Figure 5.Because programmable logic device control flexibly, so TS stream interface of the present invention can adapt to most of TS modulator.
For receive direction, programmable logic device 9 is caught valid data from TS demodulator interface, and accomplishes the rejecting work of empty frame.Useful signal is deposited in the twoport buffering area 8, and notice flush bonding processor 1 reads the data in the buffer memory.Flush bonding processor 1 is reduced into the IP bag with it after taking data, resists distribution according to the home address mechanism for resolving, sends in the network.
In the present invention, it is essential communication protocol between flush bonding processor 1 and the programmable logic device 9, this directly has influence on the transmittability of system.Dual port buffer provides the processing method of two port synchronization of access of a kind of control, i.e. load marking signal (Mail signal).When the left end device of dual port buffer writes any data of highest address bit.The Mail holding wire of right-hand member is dragged down; When right-hand member read one time to highest address bit, the Mail signal of right-hand member was drawn high; When the right-hand member device write one time to highest address bit, the Mail signal of left end was dragged down; When the left end device read highest address bit one time, left end Mail holding wire was drawn high.Following mask body is set forth agreement manner of execution.
The workflow of output is following after the system power-up:
Programmable logic device 9 reads output buffer 7 highest address bits rapidly, confirms the Mail line of output buffer 7 is drawn high.After this, the Mail holding wire of programmable logic device 9 cycle detection output buffers 7.When treating that the Mail holding wire is dragged down, programmable logic device 9 begins to get into operating state.
After flush bonding processor 1 powered up, at first load operation system and driver write data " 0 " to output buffer 7 highest address bits then to drag down the Mail line of output buffer, informed that programmable logic device starts working.
When programmable logic device 9 reads the Mail holding wire of output buffer 7, then send output and interrupt to flush bonding processor 1.Flush bonding processor 1 response output is interrupted, and writes frame TS data to output buffer 7, and simultaneously, highest address bit arbitrary data notice programmable logic device 9 data of writing output buffer 7 are successfully write.
Programmable logic device 9 sends in the output has no progeny the Mail holding wire of cycle detection output buffer 7.When detecting Mail output buffer 7 holding wires and being dragged down, programmable logic device 9 reading of data and cooperate transmission timing to send from output buffer 7.After frame data sent completion, programmable logic device 9 sent output once more and interrupts, and got into output buffer Mail detected state.So back and forth.
The workflow of input is following after the system power-up:
The Mail signal that programmable logic device 9 detects output buffer gets into normal operating conditions when being dragged down for the first time.This moment, programmable logic device 9 inputs began to receive data from the TS demodulator.Whether receiving after the data programmable logic device 9, at first to detect frame head be 0x47, detects whether the characteristic flag bit is 0x177.If above-mentioned two conditions are all set up, programmable logic device 9 writes input block 8 with the TS frame that receives, and sends the input interruption and give flush bonding processor 1.Flush bonding processor 1 responds in the input and has no progeny, and from input block 8, reads frame data, and any signal of not redispatching is given programmable logic device 9.
The basis of formulating the above agreement is to be less than time that flush bonding processor write or read a TS frame programmable logic device to send a TS frame to the TS modulator time with from time of a TS frame of wireless demodulation device reception.In test macro, the wireless data bandwidth is under the situation of 2Mbps.The time that programmable logic device receives a TS frame is 864us, and the flush bonding processor response is interrupted, and the time of complete operation is 47us.
2, network architecture
Two IP address fields (inter-network section) system configuration is the most frequently used in the gateway application, simple configuration mode.Through this configuration with two each other the network segment of wired isolation realize connecting and visit through Radio Link.
In the configuration of inter-network section, the access role of the present invention at wireless two ends is the system default gateway.Support through to Ethernet bottom link realizes the support to upper-layer protocol.In the layoutprocedure of reality, only need the gateway that native system is configured to height place subnet be got final product.All configurations and management all can be connected on the PC through 3 interfaces among Fig. 2 to be accomplished through hyper terminal.Simultaneously, this network architecture is supported unidirectional, bidirectional data transfers.When carrying out the one-way data transmission, only support the transport layer udp protocol, support TCP, udp protocol when carrying out bidirectional data transfers.
The system architecture signal of carrying out wireless transmission at the different IP network segment is as shown in Figure 6, and the interconnected ability of two sub-net is provided through this gateway.Subnet 192.168.8.xx and 192.169.0.xx two sub-net have been connected through Radio Link.The inner data of each subnet exchange directly to be handled through switch, and packet can not be passed to gateway.When data needed the transmission of inter-network section, according to the IPv4 protocol, data were at first handed to this network segment default gateway and are carried out the data forwarding first time.Therefore data are forwarded to gateway.IP over TS gateway is dressed up the TS packet then through the wireless another one subnet that is transmitted to the IP data envelope.The gateway of another subnet forwards the data to destination address through switch after receiving data.Exchanges data is so far accomplished.
Claims (6)
1. two-way radio embedded gateway based on ground digital television channels; It is characterized in that: contain flush bonding processor (1), flash memory (2), series arrangement mouth (3), data storage (4), ethernet control chip (5), netting twine socket (6), output dual port buffer (7), input dual port buffer (8), programmable logic device (9), TS delivery outlet (10), TS input port (11), wherein:
1.1. flush bonding processor (1) is through ethernet control chip (5) and network linking; Receive or send the IP bag; And process the work of data, the process that IP bag and standard TS stream format are changed each other is called the IP bag, and to be encapsulated as the TS stream packets be that IP wraps with TS stream packets deblocking;
1.2. flash memory (2), series arrangement mouth (3), data storage (4) and flush bonding processor (1) are formed embedded minimum system, flash memory (2) is used for loading operation system kernel, driver and upper level applications; Data storage (4) is used as the cache exchanging space in the data handling procedure; Series arrangement mouth (3) is used for programming program, configuration script file, configuration-system attribute and transmission means;
1.3. output dual port buffer (7), input dual port buffer (8) are realized the data communication of flush bonding processor and programmable logic device respectively as the data buffering that sends, receives two data path directions according to concluding an agreement certainly;
1.4. programmable logic device (9) is responsible for the coupling of TS stream interface sequential, connects TS delivery outlet (10) and TS input port (11) simultaneously, carries out full duplex work; And can be according to different TS modulator-demodulator flexible configuration interface sequence parameters; The TS interface comprises 11 holding wires altogether, 8 parallel-by-bit data wires wherein, 1 bit clock signal line; 1 bit synchronization signal line, 1 bit data useful signal line.
2. according to a kind of two-way radio embedded gateway described in the claim 1 based on ground digital television channels; It is characterized in that: the ethernet control chip in described 1.1 (5) is the 10MHz/100MHz adaptive chip; Flush bonding processor (1) drives this chip through driver, is connected to Ethernet and carries out full duplex transmitting-receiving IP bag.
3. according to a kind of two-way radio embedded gateway described in the claim 1 based on ground digital television channels; It is characterized in that: in described 1.2; Transplanting be can realize through series arrangement mouth (3), and driver and upper level applications integrated operating system; All drivers and upper level applications all are stored in the flash memory (2), comprise unidirectional drive program, bi-directional drive program, inter-network section analysis program, same network segment analysis program; Revise the start configurable gateway address of script and configuration-system framework, the i.e. unidirectional or bilateral system of the unidirectional or bilateral system of same network segment, inter-network section.
4. according to a kind of two-way radio embedded gateway described in the claim 1 based on ground digital television channels; It is characterized in that: in described 1.3; Two dual port buffers are separate; Respectively receive, sending direction is as the data buffer zone between flush bonding processor (1) and the programmable logic device (9), the job step of TS outbound course is following after the system power-up:
4.1. programmable logic device (9) reads the highest address bit of output dual port buffer, affirmation will be exported the load marking signal line level of dual port buffer (7) and drawn high; After this, the load marking signal line of programmable logic device (9) cycle detection output buffer, when treating that load marking signal line level is dragged down, programmable logic device (9) begins to get into operating state;
After 4.2. flush bonding processor (1) powers up; The load operation system; The load driver program; After driver load to be accomplished, write output dual port buffer (7) highest address bit arbitrary data the load marking signal line level of output dual port buffer (7) is dragged down, inform that programmable logic device (9) starts working;
Interrupt 4.3. programmable logic device (9) sends output to flush bonding processor (1): flush bonding processor (1) response output is interrupted; And write frame TS data to exporting dual port buffer (7); Simultaneously, the highest address bit arbitrary data of writing output dual port buffer (7) promptly notifies programmable logic device (9) data successfully to be write;
4.4. programmable logic device (9) sends in the output and has no progeny; The load marking signal line of cycle detection output dual port buffer (7); When detecting its level and dragged down, programmable logic device (9) reading of data and cooperate transmission timing that data are sent to TS delivery outlet (10) from output buffer; After frame data sent completion, programmable logic device (9) sent output once more and interrupts, and got into load marking signal detected state, and is so reciprocal.
5. according to a kind of two-way radio embedded gateway described in the claim 1, it is characterized in that the job step of TS input direction is following after the system power-up based on ground digital television channels:
5.1. whether programmable logic device (9) is caught the data that the TS demodulator is sent here through TS input port (11), at first detect frame head data and be hexadecimal 47, detects whether the characteristic flag bit is hexadecimal 177; If above-mentioned two conditions are all set up, programmable logic device (9) writes input dual port buffer (8) with the TS frame that receives, and sends the input interruption and give flush bonding processor (1);
5.2. flush bonding processor (1) responds in the input and has no progeny, and from the input block, reads frame data, gives the inner upper level applications of embedded system and handles, input is interrupted to wait for next time then.
6. according to a kind of two-way radio embedded gateway described in the claim 1 based on ground digital television channels; It is characterized in that: the coupling of being responsible for TS stream interface sequential at the programmable logic device described in 1.4 (9); Though TS data packet frame form is fixed; But because the data flow sequential that various TS modulator-demodulators receive and send there are differences, so through revising time sequence parameter in the programmable logic device to adapt to various TS modulator-demodulators.
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| CN103458483B (en) * | 2012-05-31 | 2017-05-31 | 安凯(广州)微电子技术有限公司 | Link control method and device between a kind of Bluetooth audio data transmission |
| CN103763749A (en) * | 2013-12-06 | 2014-04-30 | 中国人民解放军理工大学 | TS-IP routing module and broadcast routing system |
| CN104618059A (en) * | 2015-01-14 | 2015-05-13 | 华为技术有限公司 | Method, device and system for transmitting transport stream data |
| CN106254018B (en) * | 2016-08-12 | 2018-07-03 | 深圳欧奇科技有限公司 | High speed signal receives the integrated system and data processing method with demultiplexing |
| CN108989896B (en) * | 2017-06-12 | 2020-02-21 | 视联动力信息技术股份有限公司 | Video-on-demand request processing method and device |
| CN109617965A (en) * | 2018-12-13 | 2019-04-12 | 视联动力信息技术股份有限公司 | A kind of communication connection method for building up and view networked system |
| CN111800488B (en) * | 2020-06-23 | 2023-01-24 | 翱捷科技股份有限公司 | Data transmission method and system based on UDP (user Datagram protocol) and IPV6 (Internet protocol video protocol) |
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| CN2563852Y (en) * | 2002-08-29 | 2003-07-30 | 上海信业计算机网络工程有限公司 | Digital video frequency gate way |
| EP1463328A1 (en) * | 2003-03-28 | 2004-09-29 | Norsat International Inc. | Highly integrated, compact and portable baseband apparatus for newsgathering |
| CN1602074A (en) * | 2004-09-21 | 2005-03-30 | 深圳国微技术有限公司 | Special equipment for realizing DVB return channel based on PCMCIA interface and realizing method thereof |
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