CN101702400A - Circuit substrate and technology thereof - Google Patents

Circuit substrate and technology thereof Download PDF

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Publication number
CN101702400A
CN101702400A CN 200910221778 CN200910221778A CN101702400A CN 101702400 A CN101702400 A CN 101702400A CN 200910221778 CN200910221778 CN 200910221778 CN 200910221778 A CN200910221778 A CN 200910221778A CN 101702400 A CN101702400 A CN 101702400A
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CN
China
Prior art keywords
layer
connection pad
connecting pads
conducting block
external connecting
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Granted
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CN 200910221778
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Chinese (zh)
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CN101702400B (en
Inventor
宫振越
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Via Technologies Inc
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Via Technologies Inc
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Priority to CN 200910221778 priority Critical patent/CN101702400B/en
Publication of CN101702400A publication Critical patent/CN101702400A/en
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Publication of CN101702400B publication Critical patent/CN101702400B/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention is a circuit substrate, comprising a base layer, a patterning conductive layer, a dielectric layer, an outer pad and a conductive block. The patterning conductive layer is arranged above the base layer and is provided with an inner pad; the dielectric layer is arranged above the base layer and covers the patterning conductive layer; the outer pad is arranged above the dielectric layer; the conductive block penetrates the dielectric layer and is connected between the outer pad and the inner pad; and the outer pad and the conductive block is integrated, and the outer diameter of the outer pad is equal to that of the conductive block substantially. In addition, the invention also provides a circuit substrate technology.

Description

Circuit base plate and technology thereof
Technical field
The present invention relates to a kind of circuit base plate and technology thereof, and be particularly related to a kind of connection pad and integrally formed circuit base plate and the technology thereof of conducting block.
Background technology
In semiconductor packaging, circuit base plate (circuit substrate) is one of packaging element that often uses at present.Mainly be superimposed forms circuit base plate by multi-layered patterned line layer (patterned conductivelayer) and multilayer dielectric layer (dielectric layer), and can see through conductive hole (conductive via) between two line layers and be electrically connected to each other.How raising along with the line density of circuit base plate effectively utilizes limited space to carry out the day by day important problem that is configured as of circuit.
Summary of the invention
The present invention proposes a kind of circuit substrate process.At first, provide a basal layer, a patterned conductive layer and a dielectric layer, wherein patterned conductive layer is configured on the basal layer and has an inner connection pad, and dielectric layer is configured on the basal layer and the overlay pattern conductive layer.Then, form a pattern metal and be masked on the dielectric layer, wherein the pattern metal mask has one first opening, and first opening exposes the part dielectric layer.Remove the part dielectric layer that first opening is exposed, to form a dielectric opening, wherein the dielectric opening exposes inner connection pad.Form one first pattern mask on the pattern metal mask, wherein first pattern mask has one second opening, and second opening exposes inner connection pad.Form a conductive structure and cover inner connection pad, wherein conductive structure comprises a conducting block, an external connecting pads and a first metal layer, and conducting block is filled the dielectric opening, and external connecting pads is filled first opening, and the first metal layer is filled second opening.Remove first pattern mask, the first metal layer and pattern metal mask.
The present invention proposes a kind of circuit base plate, comprises a basal layer, a patterned conductive layer, a dielectric layer, an external connecting pads and a conducting block.Patterned conductive layer is disposed on the basal layer and has an inner connection pad.Dielectric layer is configured on the basal layer and the overlay pattern conductive layer.External connecting pads is disposed on the dielectric layer.Conducting block run through dielectric layer and be connected in external connecting pads and inner connection pad between, wherein external connecting pads and conducting block are integrally formed.
The present invention proposes a kind of circuit substrate process.At first, provide a basal layer, a conductive layer and one first pattern mask, wherein conductive layer is configured on the basal layer, and first pattern mask is disposed on the conductive layer and has a plurality of openings.Then, on the conductive layer that is exposed by described a plurality of openings, form a plating seed layer.Form one second pattern mask in the described a plurality of openings of part, so that the parcel plating Seed Layer is covered by second pattern mask.On the plating seed layer that is exposed by second pattern mask, electroplate a metal level.Remove first pattern mask and second pattern mask and expose metal level and plating seed layer.The conductive layer that etching is exposed by metal level and plating seed layer is to form a patterned conductive layer, and wherein patterned conductive layer has a connection pad and a plurality of lead.Form a dielectric layer on basal layer, wherein dielectric layer coats connection pad and these leads.At last, remove part dielectric layer and metal level to expose connection pad.
External connecting pads of the present invention and conducting block are to form integrally formed conductive structure by same plating step, therefore can avoid the situation of external connecting pads and conducting block contraposition skew to take place by same plating step formation external connecting pads and conducting block.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Figure 1A to Fig. 1 N be one embodiment of the invention circuit substrate process analyse and observe flow chart.
Fig. 1 O is the inside connection pad of Figure 1A and the stereogram of conducting block.
Fig. 2 A to Fig. 2 D be another embodiment of the present invention circuit substrate process analyse and observe flow chart.
Fig. 3 is the inside connection pad of Fig. 2 C and the stereogram of conducting block.
Fig. 4 A to Fig. 4 C be further embodiment of this invention circuit substrate process analyse and observe flow chart.
Fig. 5 is the cutaway view of the circuit base plate of yet another embodiment of the invention.
Fig. 6 A to Fig. 6 E be further embodiment of this invention circuit substrate process analyse and observe flow chart.
Description of reference numerals
50,60,360,606: plating seed layer
100,100 ', 200,200 ', 300,400: circuit base plate
110,210,310,610: basal layer
120,220,320,420,630: patterned conductive layer
122,222,322,422: inner connection pad
130,230,330,430,612: dielectric layer
132,232,332,432: the dielectric opening
140: conductive structure
142,242,342,442: conducting block
144,244,344,444: external connecting pads
146,150,620: metal level
160,180,380,602,608: pattern mask
170,270,370: the pattern metal mask
162,172,182,372,382,604,614: opening
190,290,390: coat of metal
124,224,224,324,424: inner lead
600: conductive layer
601a: connection pad
601b: lead
D1, D2, D3, D5, D7, D8, D9, D11: external diameter
D4, D6, D10, D12: internal diameter
L1, L2: live width
Embodiment
Figure 1A to Fig. 1 N be one embodiment of the invention circuit substrate process analyse and observe flow chart.At first, please refer to Figure 1A, a basal layer 110, a patterned conductive layer 120 and a dielectric layer 130 are provided.Basal layer 110 can be line layer, the line layer on the chip support plate or the line layer on the printed circuit board (PCB) on the chip.Patterned conductive layer 120 is configured on the basal layer 110, and patterned conductive layer 120 has an inner connection pad 122.The end structure that this inner connection pad 122 can be connected and be extended out for inner lead 124 as Fig. 1 O illustrate and inner lead 124, and inner connection pad 122 outer diameter D 3 can be greater than the live width L1 of inner lead 124.In addition, on the section of Figure 1A, partially patterned conductive layer 120 for example can be used as inner leads such as holding wire, earth connection, power line 124 and uses.Dielectric layer 130 is configured on the basal layer 110 and overlay pattern conductive layer 120.In another embodiment, dielectric layer 130 is also replaceable is anti-welding (solder mask) material layer (not illustrating).
Then, please refer to 1B and Fig. 1 C, form a plating seed layer 50 on dielectric layer 130, and electroplate a metal level 150 on plating seed layer 50, wherein the material of metal level 150 for example is nickel (Ni), tin (Sn), tin lead (Sn/Pb), magnesium (Mg), zinc (Zn), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W) or other non-Seed Layer metals.In the present embodiment, metal level 150 can be considered mask layer or barrier layer.Please refer to Fig. 1 D, form a pattern mask 160 on metal level 150, wherein pattern mask 160 has an opening 162, and this opening 162 exposes part metals layer 150.In addition, the material of pattern mask 160 is different with the material of metal level 150, with as etching mask.In addition, opening 162 has locational corresponding relation with the inside connection pad 122 of below, and for example: the projection meeting of opening 162 drops on the inner connection pad 122.Please refer to Fig. 1 E, part metals layer 150 that etching openings 162 is exposed and parcel plating Seed Layer 50, to form a pattern metal mask 170, wherein pattern metal mask 170 has an opening 172 and opening 172 exposes part dielectric layer 130.What deserves to be mentioned is, in example of the present invention,, connector (this case is a conducting block) and external connecting pads can be formed in same step, form the structure that is one of the forming by the configuration of pattern metal mask 170.It is described in detail as follows.
Please refer to Fig. 1 F, remove pattern mask 160, and remove the part dielectric layer 130 that opening 172 is exposed, to form a dielectric opening 132 by laser.Because the opening 162 of pattern mask 160, the opening of pattern metal mask 170 172 have locational corresponding relation with the inside connection pad 122 of below, therefore expose inner connection pad 122 by opening 162, opening 172 formed dielectric openings 132.In addition, except removing, also can adopt ion selectivity etching or plasma selective etch with laser-induced thermal etching.Please refer to Fig. 1 G and Fig. 1 H, form a plating seed layer 60 in the inwall of dielectric opening 132, and form a pattern mask 180 on pattern metal mask 170, wherein the material of pattern mask 180 is different with the material of pattern metal mask 170, and pattern mask 180 has an opening 182, this opening 182 exposes partially patterned metal mask 170 and inner connection pad 122, and forms stepped profile on the section of Fig. 1 H.
Please refer to Fig. 1 I, plated conductive structure 140 covers inner connection pad 122, and wherein conductive structure 140 comprises a conducting block 142, an external connecting pads 144 and a metal level 146, and wherein plated conductive structure 140 materials for example are copper.Conducting block 142 is filled dielectric openings 132, external connecting pads 144 filling openings 172, and metal level 146 filling openings 182, and make conductive structure 140 and inner connection pad 122 form one on the section of Fig. 1 I " I " profile of font.Please refer to Fig. 1 J to Fig. 1 L, remove pattern mask 180, metal level 146, pattern metal mask 170 and plating seed layer 50 in regular turn, the mode that wherein removes metal level 146 for example is brushing (brushing), grinding (polishing) or chemico-mechanical polishing (CMP), and only remaining conducting block 142 of conductive structure 140 originally and external connecting pads 144.Inner connection pad 122, conducting block 142 form one with external connecting pads 144 on the section of Fig. 1 L " T " profile of font.Particularly, because conductive structure 140 is different with the material of pattern metal mask 170, therefore when removing the metal level 146 of conductive structure 140, pattern metal mask 170 can not be removed, and can be considered etching mask or barrier layer.In one embodiment; also can form a coat of metal 190 in external connecting pads 144; and finish the making (shown in Fig. 1 M) of circuit base plate 100, wherein the protective layer of coat of metal 190 for example is nickel/gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au), nickel/tin (Ni/Sn), palladium (Pd), gold (Au) or its alloy or organic protection layer (OSP).
Please refer to Fig. 1 M, comprise a basal layer 110, a patterned conductive layer 120, a dielectric layer 130, an external connecting pads 144, a conducting block 142 by the produced circuit base plate 100 of the circuit substrate process of present embodiment.In the present embodiment, comprise that also one covers the coat of metal 190 of external connecting pads 144.Patterned conductive layer 120 is disposed on the basal layer 110 and has an inner connection pad 122, and in one embodiment, partially patterned conductive layer 120 for example can be used as inner leads such as holding wire, earth connection, power line 124 and uses.Dielectric layer 130 is configured on the basal layer 110 and overlay pattern conductive layer 120.External connecting pads 144 is disposed on the dielectric layer 130.Conducting block 142 run through dielectric layer 130 and be connected in external connecting pads 144 and inner connection pad 122 between, wherein external connecting pads 144 and conducting block 142 are integrally formed, and the outer diameter D 1 of external connecting pads 144 equals the outer diameter D 2 of conducting block 142 in fact.
Specifically, please refer to Fig. 1 H and Fig. 1 I, in the circuit substrate process of present embodiment, owing to form pattern metal mask 170, therefore can in same plating step, continue and form conducting block 142 and external connecting pads 144, thereby external connecting pads 144 in Fig. 1 M and conducting block 142 are integrally formed, and the outer diameter D 2 of the outer diameter D 1 of external connecting pads 144 and conducting block 142 can be controlled to be equally in fact, dispose circuit so that dielectric layer 130 surfaces have sufficient space.In addition, can avoid in the past because of external connecting pads 144 and conducting block 142 need be formed by different step respectively by electroplate forming external connecting pads 144 and conducting block 142, and cause the situation generation of the two contraposition skew.And technology cost in the past is also higher.
In another embodiment, after the structure that forms Fig. 1 L, the surface treatment of also can carry out sandblasting (Sandblasting), the particle that wherein sandblasts for example is aluminium oxide (Al 2O 3).When the material that replaces with anti-welding (solder mask) material layer, external connecting pads 144 when dielectric layer 130 is copper, aluminium oxide sandblasts particle can be greater than the abrasion speed of copper for the abrasion speed of anti-welding material, therefore can form half curved surfaces (two concave surfaces as Fig. 1 N, and the element (for example: chip, another circuit base plate) of these half curved surfaces after will helping engages a convex surface).In the present embodiment, after surface treatment, also can form a coat of metal 190, and finish the making of circuit base plate 100 ' in external connecting pads 144.
Please refer to Fig. 1 F, in the present embodiment, the outer diameter D 3 of inner connection pad 122 is greater than the inside diameter D 4 of dielectric opening 132.Right the present invention is as limit, below by Fig. 2 A to Fig. 2 D this illustrated.
Fig. 2 A to Fig. 2 D be another embodiment of the present invention circuit substrate process analyse and observe flow chart.Please refer to Fig. 2 A, the inside connection pad 122 that is illustrated in Figure 1A has bigger outer diameter D 3, the inside connection pad 222 of the patterned conductive layer 220 that present embodiment provided has less outer diameter D 5, that is these inner connection pad 222 meetings and the end structure that is connected and is extended out for inner lead 224 as the inner lead 224 that Fig. 3 illustrated, and inner connection pad 222 outer diameter D 5 equal the live width L2 of inner lead 224 in fact.What deserves to be mentioned is that because inner connection pad 222 has less external diameter, therefore the spacing of the spacing (Pitch) of adjacent two inner connection pads 222 or inner connection pad and adjacent inner lead can be dwindled.Further, consider spacing between the adjacent two inner connection pads, between adjacent two inner leads spacing or when linking to each other spacing between inner connection pad and the inner lead, owing to the inside connection pad with large-size (having outer diameter D 3) that need not consider to be illustrated as Fig. 1 O, only need consider the live width of inner lead, therefore can increase integrated level.Then, can obtain the structure that illustrated as Fig. 2 B by the technology that is similar to Figure 1B to Fig. 1 F, the outer diameter D 5 of wherein inner connection pad 222 is less than the inside diameter D 6 of the dielectric opening 232 of dielectric layer 230, and the metal level 150 that is illustrated in Figure 1B to Fig. 1 F technology still can be used as the use of mask layer or barrier layer in the present embodiment.Afterwards, again by being similar to the technology of Fig. 1 G to Fig. 1 M, the structure fabrication that is illustrated as Fig. 2 B can be become the circuit base plate 200 that is illustrated as Fig. 2 C, wherein inner connection pad 222, conducting block 242 form one with external connecting pads 244 on the section of Fig. 2 C " rectangle " profile.Particularly; in the process of the circuit base plate 200 that the structure fabrication that will be illustrated as Fig. 2 B becomes to be illustrated as Fig. 2 C; (present embodiment does not illustrate owing to conductive structure; it is similar to the conductive structure 140 of Fig. 1 J) different with the material of pattern metal mask 270; therefore (present embodiment does not illustrate at the metal level that removes conductive structure; it is similar to the metal level 146 of Fig. 1 J) time, pattern metal mask 270 can not be removed, and can be considered etching mask or barrier layer.
Please refer to Fig. 2 C, the circuit base plate 200 of present embodiment comprises a basal layer 210, a patterned conductive layer 220, a dielectric layer 230, an external connecting pads 244, a conducting block 242.In the present embodiment, comprise that also one covers the coat of metal 290 of external connecting pads 244.Patterned conductive layer 220 is disposed on the basal layer 210 and has an inner connection pad 222, and in one embodiment, partially patterned conductive layer 220 for example can be used as inner leads such as holding wire, earth connection, power line 224 and uses.Dielectric layer 230 is configured on the basal layer 210 and overlay pattern conductive layer 220.External connecting pads 244 is disposed on the dielectric layer 230.Conducting block 242 run through dielectric layer 230 and be connected in external connecting pads 244 and inner connection pad 222 between.Particularly, by forming pattern metal mask 270 (shown in Fig. 2 B) in the technology, and conducting block 242 and external connecting pads 244 can be formed in same plating step, and have integrally formed structure.Thus, can solve in the past because of conducting block 242 and external connecting pads 244 form respectively at different step, and cause the problem of the two contraposition skew.
It should be noted that compared to the inside connection pad 122 of Fig. 1 M only to be covered by conducting block 142 subregion that the volume of the inside connection pad 222 of present embodiment is less and coated by conducting block 242 fully.Fig. 3 is the inside connection pad of Fig. 2 C and the stereogram of conducting block.Please refer to Fig. 3, specifically, patterned conductive layer 220 (being shown in Fig. 2 C) has an inner lead 224, and the latter end of inner lead 224 constitutes the inside connection pad 222 that is coated by conducting block 242.Particularly, patterned conductive layer 220 its inner connection pads 222 that present embodiment provides have less external diameter, therefore spacing between the adjacent two inner connection pads 222 or the spacing between inner connection pad 222 and the adjacent inner lead 224 can be dwindled, and help the lifting of the integrated level that connects up.
In another embodiment, technology by being similar to Fig. 1 G to Fig. 1 L and the surface of Fig. 1 N sandblast (or spray ceramic particle) handle, the structure fabrication that is illustrated as Fig. 2 B can be become the circuit base plate 200 ' that be illustrated as Fig. 2 D.
The outer diameter D 1 of the external connecting pads 144 of Fig. 1 M equals the outer diameter D 2 of conducting block 142 in fact, and right the present invention is as limit, below by 1F, Fig. 4 A to Fig. 4 C this is illustrated.
Fig. 4 A to Fig. 4 C be further embodiment of this invention circuit substrate process analyse and observe flow chart.Obtain the structure that Fig. 1 F illustrated by technology after as Figure 1A to Fig. 1 F, can carry out etching and make it become the structure that is illustrated as Fig. 4 A pattern metal mask 170, wherein the opening 372 of pattern metal mask 370 exposes the part dielectric layer 330 that dielectric opening 332 reaches around dielectric opening 332, and the metal level 150 that is illustrated in Figure 1B to Fig. 1 F technology still can use as mask layer or barrier layer in present embodiment.Then, by being similar to the technology of Fig. 1 G, form a plating seed layer 360 in the inwall of dielectric opening 332, and form a pattern mask 380 on pattern metal mask 370, wherein pattern mask 380 has different materials with pattern metal mask 370, and in addition, pattern mask 380 has an opening 382, and opening 382 exposes partially patterned metal mask 370 and inner connection pad 322, and forms stepped profile on the section of Fig. 4 B.Afterwards by being similar to the technology of Fig. 1 I to Fig. 1 M, after pattern metal mask 370 is removed, can be with the circuit base plate 300 that the structure fabrication that illustrated as Fig. 4 B becomes as Fig. 4 C be illustrated, wherein inner connection pad 322, conducting block 342 and external connecting pads 344 form one on section " I " profile of font.Particularly; in the process of the circuit base plate 300 that the structure fabrication that will be illustrated as Fig. 4 B becomes to be illustrated as Fig. 4 C; (present embodiment does not illustrate owing to conductive structure; it is similar to the conductive structure 140 of Fig. 1 J) different with the material of pattern metal mask 370; therefore (present embodiment does not illustrate at the metal level that removes conductive structure; it is similar to the metal level 146 of Fig. 1 J) time, pattern metal mask 370 can not be removed, and can be considered etching mask or barrier layer.
Please refer to Fig. 4 C, circuit base plate 300 comprises a basal layer 310, a patterned conductive layer 320, a dielectric layer 330, an external connecting pads 344, a conducting block 342.In the present embodiment, comprise that also one covers the coat of metal 390 of external connecting pads 344.Patterned conductive layer 320 is disposed on the basal layer 310 and has an inner connection pad 322, and in one embodiment, partially patterned conductive layer 320 for example can be used as inner leads such as holding wire, earth connection, power line 324 and uses.Dielectric layer 330 is configured on the basal layer 310 and overlay pattern conductive layer 320.External connecting pads 344 is disposed on the dielectric layer 330.Conducting block 342 run through dielectric layer 330 and be connected in external connecting pads 344 and inner connection pad 322 between.Particularly, by forming pattern metal mask 370 (shown in Fig. 4 B) in the technology, and conducting block 342 and external connecting pads 344 can be formed in same plating step, and have integrally formed structure.Thus, can solve in the past because of conducting block 342 and external connecting pads 344 form respectively at different step, and cause the problem of the two contraposition skew.It should be noted that the outer diameter D 2 that equals conducting block 142 compared to the outer diameter D 1 of the external connecting pads 144 of Fig. 1 M in fact, the outer diameter D 7 of the external connecting pads 344 of present embodiment is greater than the outer diameter D 8 of conducting block 342.
Fig. 5 is the cutaway view of the circuit base plate of yet another embodiment of the invention.Please refer to Fig. 5, compared to the outer diameter D 9 of the inside connection pad 322 of Fig. 4 C inside diameter D 10 greater than the dielectric opening 332 of dielectric layer 330, the outer diameter D 11 of the inside connection pad 422 of present embodiment is less than the inside diameter D 12 of the dielectric opening 432 of dielectric layer 430.Wherein inner connection pad 422, conducting block 442 forms one with external connecting pads 444 on section " T " profile of font.In addition, be similar to the structure that Fig. 3 illustrates, the inside connection pad 422 of Fig. 5 for example is that the latter end of the inner lead of patterned conductive layer 420 constitutes.Particularly, patterned conductive layer 420 its inner connection pads 422 that present embodiment provides have less external diameter (almost the live width with inner lead is identical in fact), therefore spacing between the adjacent two inner connection pads 422 or the spacing between inner connection pad 422 and the adjacent inner lead 424 can be dwindled, and help the lifting of the integrated level that connects up.
In another embodiment, circuit base plate of the present invention also can be taked following technology.Fig. 6 A to Fig. 6 E be further embodiment of this invention circuit substrate process analyse and observe flow chart.Please refer to Fig. 6 A, a basal layer 610 is provided, wherein basal layer 610 for example is line layer, the line layer on the chip support plate or the line layer on the printed circuit board (PCB) on the chip.Then, on basal layer 610, form a conductive layer 600, and on conductive layer 600, form a pattern mask 602 with a plurality of openings 604.Afterwards, on the conductive layer 600 that these openings 604 are exposed, form a plating seed layer 606.Then, please refer to Fig. 6 B, form another pattern mask 608, and electroplate a metal level 620 in being patterned the plating seed layer 606 that mask 602 exposes with cover part plating seed layer 606.Then, please refer to Fig. 6 C, remove pattern mask 608 and pattern mask 602 and expose metal level 620 and plating seed layer 606, and be that mask etching conductive layer 600 forms a patterned conductive layer 630 with plating seed layer 606 with metal level 620, to form a connection pad 601a and a plurality of lead 601b, form a dielectric layer 612 afterwards again, and form the structure of Fig. 6 D.Afterwards, please refer to Fig. 6 E, remove part dielectric layer 612 by brushing, grinding, chemico-mechanical polishing, ionic etching or plasma etching metal level 620 is come out, then remove metal level 620 again and connection pad 601a is come out, and form an opening 614.Particularly, in the present embodiment, form opening 614 by directly removing metal level 620, can avoid in the past etching openings 614 with below the problem of connection pad 601a contraposition skew.
In sum, external connecting pads of the present invention and conducting block are to form integrally formed conductive structure by same plating step, therefore can avoid the situation of external connecting pads and conducting block contraposition skew to take place by same plating step formation external connecting pads and conducting block.In addition, can be to equate with the external diameter of external connecting pads and the outside diameter control of conducting block thus also, so that having sufficient space, the dielectric layer surface disposes circuit.In addition, inner connection pad can be made of the latter end of the inner lead of patterned conductive layer, and make the external diameter of the external diameter of inner connection pad less than conducting block, dwindling spacing between the adjacent two inner connection pads or the spacing between inner connection pad and the adjacent inner lead, and help the lifting of the integrated level that connects up.
In addition, this case also can be carried out the surface treatment of a sandblast after forming external connecting pads, and helps external connecting pads and engaging of element afterwards.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; those of ordinary skill in the technical field under any; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim.

Claims (19)

1. circuit substrate process comprises:
One basal layer, a patterned conductive layer and a dielectric layer are provided, and wherein this patterned conductive layer is configured on this basal layer and has an inner connection pad, and this dielectric layer is configured on this basal layer and cover this patterned conductive layer;
Form a pattern metal and be masked on this dielectric layer, wherein this pattern metal mask has one first opening, and this first opening exposes this dielectric layer of part;
Remove this dielectric layer of part that this first opening is exposed, to form a dielectric opening, wherein this dielectric opening exposes this inside connection pad;
Form one first pattern mask on this pattern metal mask, wherein this first pattern mask has one second opening, and this second opening exposes this inside connection pad;
Form a conductive structure and cover this inside connection pad, wherein this conductive structure comprises a conducting block, an external connecting pads and a first metal layer, this conducting block is filled this dielectric opening, and this external connecting pads is filled this first opening, and this first metal layer is filled this second opening; And
Remove this first pattern mask, this first metal layer and this pattern metal mask.
2. circuit substrate process as claimed in claim 1, the method that wherein forms this pattern metal mask comprises:
Form a plating seed layer on this dielectric layer;
Electroplate one second metal level on this plating seed layer;
Form one second pattern mask on this second metal level, wherein this second pattern mask has one the 3rd opening, and the 3rd opening exposes this second metal level of part;
This second metal level of part that etching the 3rd opening is exposed and this plating seed layer of part are to form this pattern metal mask; And
Remove this second pattern mask.
3. circuit substrate process as claimed in claim 1, the method that wherein forms this conductive structure comprises:
Form the inwall of a plating seed layer in this dielectric opening; And
Electroplate this conductive structure and cover this inside connection pad.
4. circuit substrate process as claimed in claim 1, external diameter that wherein should the inside connection pad is greater than the internal diameter of this dielectric opening.
5. circuit substrate process as claimed in claim 1, external diameter that wherein should the inside connection pad is less than the internal diameter of this dielectric opening.
6. circuit substrate process as claimed in claim 1, wherein the external diameter of this external connecting pads is greater than the external diameter of this conducting block.
7. circuit substrate process as claimed in claim 1, wherein the external diameter of this external connecting pads equals the external diameter of this conducting block.
8. circuit substrate process as claimed in claim 1 also comprises:
Before forming this first pattern mask, this pattern metal mask of etching reaches this dielectric layer of part that centers on this dielectric opening so that this first opening exposes this dielectric opening.
9. circuit substrate process as claimed in claim 1 also comprises:
After removing this pattern metal mask, this external connecting pads is reached this dielectric layer of part that centers on this external connecting pads carry out the processing of sandblasting, and make this external connecting pads curvedly protrude in this dielectric layer, and curvedly cave in respect to this dielectric layer of other parts around this dielectric layer of part of this external connecting pads.
10. circuit base plate comprises:
One basal layer;
One patterned conductive layer is disposed on this basal layer and has an inner connection pad;
One dielectric layer is configured on this basal layer and covers this patterned conductive layer;
One external connecting pads is disposed on this dielectric layer; And
One conducting block, run through this dielectric layer and be connected in this external connecting pads and this inside connection pad between, wherein this external connecting pads and this conducting block are integrally formed.
11. circuit base plate as claimed in claim 10, external diameter that wherein should the inside connection pad be less than the external diameter of this conducting block, and this inside connection pad is coated by this conducting block.
12. circuit base plate as claimed in claim 11, wherein this patterned conductive layer has more an inner lead, and a latter end of this inner lead constitutes this inside connection pad.
13. circuit base plate as claimed in claim 11, wherein the external diameter of this external connecting pads equals the external diameter of this conducting block, and makes this inside connection pad, this conducting block and this external connecting pads form one on section " rectangle " profile.
14. circuit base plate as claimed in claim 11, wherein the external diameter of this external connecting pads is greater than the external diameter of this conducting block, and makes this inside connection pad, this conducting block and this external connecting pads form one on section " T " profile of font.
15. circuit base plate as claimed in claim 10, external diameter that wherein should the inside connection pad is greater than the external diameter of this conducting block.
16. circuit base plate as claimed in claim 15, wherein the external diameter of this external connecting pads equals the external diameter of this conducting block, and makes this inside connection pad, this conducting block and this external connecting pads form one on section " fall T " profile of font.
17. circuit base plate as claimed in claim 15, wherein the external diameter of this external connecting pads is greater than the external diameter of this conducting block, and makes this inside connection pad, this conducting block and this external connecting pads form one on section " I " profile of font.
18. circuit base plate as claimed in claim 10, wherein this external connecting pads curvedly protrudes in this dielectric layer, and curvedly caves in respect to this dielectric layer of other parts around this dielectric layer of part of this external connecting pads.
19. a circuit substrate process comprises:
One basal layer, a conductive layer and one first pattern mask are provided, and wherein this conductive layer is configured on this basal layer, and this first pattern mask is disposed on this conductive layer and has a plurality of openings;
On this conductive layer that is exposed by described a plurality of openings, form a plating seed layer;
Form one second pattern mask in the described a plurality of openings of part, so that this plating seed layer of part is covered by this second pattern mask;
On this plating seed layer that is exposed by this second pattern mask, electroplate a metal level;
Remove this first pattern mask and this second pattern mask and expose this metal level and this plating seed layer;
This conductive layer that etching is exposed by this metal level and this plating seed layer is to form a patterned conductive layer, and wherein this patterned conductive layer has a connection pad and a plurality of lead;
Form a dielectric layer on this basal layer, wherein this dielectric layer coats this connection pad and described a plurality of lead; And
Remove this dielectric layer of part and this metal level to expose this connection pad.
CN 200910221778 2009-11-16 2009-11-16 Circuit substrate and technology thereof Active CN101702400B (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
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CN101847586A (en) * 2010-03-19 2010-09-29 威盛电子股份有限公司 Circuit substrate process and circuit substrate
CN101916732A (en) * 2010-08-06 2010-12-15 威盛电子股份有限公司 Circuit substrate and making process thereof
US8302298B2 (en) 2009-11-06 2012-11-06 Via Technologies, Inc. Process for fabricating circuit substrate
CN102931168A (en) * 2012-11-14 2013-02-13 日月光半导体(上海)股份有限公司 Packaging substrate and manufacturing method thereof
US8549745B2 (en) 2010-07-26 2013-10-08 Via Technologies, Inc. Fabricating process of circuit substrate
US10039184B2 (en) 2016-11-30 2018-07-31 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof

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CN100534263C (en) * 2005-11-30 2009-08-26 全懋精密科技股份有限公司 Circuit board conductive lug structure and making method
CN101534609B (en) * 2008-03-12 2011-11-16 欣兴电子股份有限公司 Circuit structure of circuit board and method for manufacture same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8302298B2 (en) 2009-11-06 2012-11-06 Via Technologies, Inc. Process for fabricating circuit substrate
CN101847586A (en) * 2010-03-19 2010-09-29 威盛电子股份有限公司 Circuit substrate process and circuit substrate
CN101847586B (en) * 2010-03-19 2012-08-22 威盛电子股份有限公司 Circuit substrate process and circuit substrate
US8549745B2 (en) 2010-07-26 2013-10-08 Via Technologies, Inc. Fabricating process of circuit substrate
CN101916732A (en) * 2010-08-06 2010-12-15 威盛电子股份有限公司 Circuit substrate and making process thereof
CN101916732B (en) * 2010-08-06 2013-01-02 威盛电子股份有限公司 Circuit substrate and making process thereof
CN102931168A (en) * 2012-11-14 2013-02-13 日月光半导体(上海)股份有限公司 Packaging substrate and manufacturing method thereof
US10039184B2 (en) 2016-11-30 2018-07-31 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof

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