CN101675348A - 用于补偿mosfet集成电路中工艺诱生性能变化的方法 - Google Patents

用于补偿mosfet集成电路中工艺诱生性能变化的方法 Download PDF

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Publication number
CN101675348A
CN101675348A CN200880014239A CN200880014239A CN101675348A CN 101675348 A CN101675348 A CN 101675348A CN 200880014239 A CN200880014239 A CN 200880014239A CN 200880014239 A CN200880014239 A CN 200880014239A CN 101675348 A CN101675348 A CN 101675348A
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CN
China
Prior art keywords
transistors
array
variations
threshold voltage
drive current
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Pending
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CN200880014239A
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English (en)
Chinese (zh)
Inventor
V·莫罗兹
D·普拉玛尼克
K·辛格哈尔
林锡伟
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Synopsys Inc
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Synopsys Inc
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Publication of CN101675348A publication Critical patent/CN101675348A/zh
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/36Circuit design at the analogue level
    • G06F30/367Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30Devices controlled by electric currents or voltages
    • H10D48/32Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/36Unipolar devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CN200880014239A 2007-06-01 2008-01-17 用于补偿mosfet集成电路中工艺诱生性能变化的方法 Pending CN101675348A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/757,338 US7949985B2 (en) 2007-06-01 2007-06-01 Method for compensation of process-induced performance variation in a MOSFET integrated circuit
US11/757,338 2007-06-01
PCT/US2008/051355 WO2008150555A1 (en) 2007-06-01 2008-01-17 Method for compensation of process-induced performance variation in a mosfet integrated circuit

Publications (1)

Publication Number Publication Date
CN101675348A true CN101675348A (zh) 2010-03-17

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ID=40087455

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200880014239A Pending CN101675348A (zh) 2007-06-01 2008-01-17 用于补偿mosfet集成电路中工艺诱生性能变化的方法

Country Status (7)

Country Link
US (2) US7949985B2 (https=)
EP (1) EP2153239A4 (https=)
JP (1) JP5261479B2 (https=)
KR (1) KR101159305B1 (https=)
CN (1) CN101675348A (https=)
TW (1) TWI392028B (https=)
WO (1) WO2008150555A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104750904A (zh) * 2013-12-31 2015-07-01 德州仪器公司 用以改进晶体管匹配的方法
CN105740572A (zh) * 2016-02-26 2016-07-06 联想(北京)有限公司 一种电子设备

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7949985B2 (en) * 2007-06-01 2011-05-24 Synopsys, Inc. Method for compensation of process-induced performance variation in a MOSFET integrated circuit
US8176444B2 (en) * 2009-04-20 2012-05-08 International Business Machines Corporation Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance
US20120042292A1 (en) * 2010-08-10 2012-02-16 Stmicroelectronics S.A. Method of synthesis of an electronic circuit
US8776005B1 (en) 2013-01-18 2014-07-08 Synopsys, Inc. Modeling mechanical behavior with layout-dependent material properties
US8832619B2 (en) * 2013-01-28 2014-09-09 Taiwan Semiconductor Manufacturing Co., Ltd. Analytical model for predicting current mismatch in metal oxide semiconductor arrays
EP3760196B1 (en) * 2018-02-28 2024-12-18 Petroeuroasia Co., Ltd. Reduced coenzyme q10-containing composition and method for producing same
CN119997585B (zh) * 2025-04-14 2025-07-22 合肥晶合集成电路股份有限公司 一种半导体器件的制作方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3882391A (en) * 1973-06-25 1975-05-06 Ibm Testing the stability of MOSFET devices
US4138666A (en) * 1977-11-17 1979-02-06 General Electric Company Charge transfer circuit with threshold voltage compensating means
US5412263A (en) * 1992-09-30 1995-05-02 At&T Corp. Multiple control voltage generation for MOSFET resistors
KR970001564U (ko) * 1995-06-21 1997-01-21 자동차용 후부차체의 보강구조
US5748534A (en) * 1996-03-26 1998-05-05 Invox Technology Feedback loop for reading threshold voltage
JPH1074843A (ja) * 1996-06-28 1998-03-17 Toshiba Corp 多電源集積回路および多電源集積回路システム
EP0919121A4 (en) * 1996-07-08 2000-11-22 Dnavec Research Inc IN VIVO ELECTROPORATION METHOD FOR ANIMAL EARLY EMBRYONS
US6287926B1 (en) * 1999-02-19 2001-09-11 Taiwan Semiconductor Manufacturing Company Self aligned channel implant, elevated S/D process by gate electrode damascene
JP3324588B2 (ja) * 1999-12-22 2002-09-17 日本電気株式会社 半導体装置及びその製造方法
US6598214B2 (en) * 2000-12-21 2003-07-22 Texas Instruments Incorporated Design method and system for providing transistors with varying active region lengths
US20040038489A1 (en) 2002-08-21 2004-02-26 Clevenger Lawrence A. Method to improve performance of microelectronic circuits
JP4408613B2 (ja) * 2002-09-25 2010-02-03 Necエレクトロニクス株式会社 トランジスタの拡散層長依存性を組み込んだ回路シミュレーション装置およびトランジスタモデル作成方法
US6928635B2 (en) * 2002-09-25 2005-08-09 Numerical Technologies, Inc. Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits
JP4202120B2 (ja) * 2002-12-27 2008-12-24 セイコーインスツル株式会社 集積回路の最適化設計装置
US7487474B2 (en) * 2003-01-02 2009-02-03 Pdf Solutions, Inc. Designing an integrated circuit to improve yield using a variant design element
JP2004241529A (ja) * 2003-02-05 2004-08-26 Matsushita Electric Ind Co Ltd 半導体回路装置及びその回路シミュレーション方法
US7263477B2 (en) * 2003-06-09 2007-08-28 Cadence Design Systems, Inc. Method and apparatus for modeling devices having different geometries
JP2005166741A (ja) * 2003-11-28 2005-06-23 Sharp Corp 半導体記憶素子の特性評価方法及びモデルパラメータ抽出方法
US20050144576A1 (en) * 2003-12-25 2005-06-30 Nec Electronics Corporation Design method for semiconductor circuit device, design method for semiconductor circuit, and semiconductor circuit device
US7174532B2 (en) * 2004-11-18 2007-02-06 Agere Systems, Inc. Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects
JP4833544B2 (ja) * 2004-12-17 2011-12-07 パナソニック株式会社 半導体装置
JP2006178907A (ja) * 2004-12-24 2006-07-06 Matsushita Electric Ind Co Ltd 回路シミュレーション方法および装置
US7441211B1 (en) * 2005-05-06 2008-10-21 Blaze Dfm, Inc. Gate-length biasing for digital circuit optimization
JP2006329824A (ja) * 2005-05-26 2006-12-07 Matsushita Electric Ind Co Ltd 回路シミュレーション方法
US7337420B2 (en) * 2005-07-29 2008-02-26 International Business Machines Corporation Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models
KR100628247B1 (ko) * 2005-09-13 2006-09-27 동부일렉트로닉스 주식회사 반도체 소자
JP2007123442A (ja) * 2005-10-26 2007-05-17 Matsushita Electric Ind Co Ltd 半導体回路装置、その製造方法及びそのシミュレーション方法
US7716612B1 (en) * 2005-12-29 2010-05-11 Tela Innovations, Inc. Method and system for integrated circuit optimization by using an optimized standard-cell library
JP4922623B2 (ja) * 2006-02-22 2012-04-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7321139B2 (en) * 2006-05-26 2008-01-22 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor layout for standard cell with optimized mechanical stress effect
US7761278B2 (en) * 2007-02-12 2010-07-20 International Business Machines Corporation Semiconductor device stress modeling methodology
US7949985B2 (en) 2007-06-01 2011-05-24 Synopsys, Inc. Method for compensation of process-induced performance variation in a MOSFET integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104750904A (zh) * 2013-12-31 2015-07-01 德州仪器公司 用以改进晶体管匹配的方法
US10339251B2 (en) 2013-12-31 2019-07-02 Texas Instruments Incorporated Method to improve transistor matching
CN104750904B (zh) * 2013-12-31 2020-04-14 德州仪器公司 用以改进晶体管匹配的方法
CN105740572A (zh) * 2016-02-26 2016-07-06 联想(北京)有限公司 一种电子设备

Also Published As

Publication number Publication date
US20080297237A1 (en) 2008-12-04
JP2010529649A (ja) 2010-08-26
JP5261479B2 (ja) 2013-08-14
EP2153239A4 (en) 2011-08-17
US8219961B2 (en) 2012-07-10
KR20090133129A (ko) 2009-12-31
EP2153239A1 (en) 2010-02-17
US7949985B2 (en) 2011-05-24
TWI392028B (zh) 2013-04-01
KR101159305B1 (ko) 2012-06-25
WO2008150555A1 (en) 2008-12-11
TW200849408A (en) 2008-12-16
US20110219351A1 (en) 2011-09-08

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Application publication date: 20100317