CN101645432B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN101645432B
CN101645432B CN2009101340546A CN200910134054A CN101645432B CN 101645432 B CN101645432 B CN 101645432B CN 2009101340546 A CN2009101340546 A CN 2009101340546A CN 200910134054 A CN200910134054 A CN 200910134054A CN 101645432 B CN101645432 B CN 101645432B
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silicon wafer
wafer perforation
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CN101645432A (zh
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陈明发
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种形成凸块下金属化层的系统与方法与其所形成的半导体装置，其减少凸块下金属化层(under bump metallization，UBM)、直通硅晶穿孔(throughsilicon via，TSV)与引线的所有覆盖率(footprint)。一优选实施例包括于多个直通硅晶穿孔上形成一凸块下金属化层，而该凸块下金属化层只连接至全部直通硅晶穿孔的部分，且凸块下金属化层位于其上。该凸块下金属化层之下可额外形成连接至直通硅晶穿孔的引线于以于裸片的表面上保留更多空间。

Description

半导体装置
技术领域
本发明涉及一种制造半导体装置的系统与方法，尤其涉及一种制造直通硅晶穿孔的系统与方法。
背景技术
一般而言，如图1所示，经由凸块101可将一半导体裸片100连接至其他裸片或装置。通常借由导电材料层，共同所熟知如，延伸穿过一介电层111的凸块下金属化层103，将这些凸块101连接至半导体裸片100。凸块下金属化层103提供介于凸块101与接触垫105间的连接以电性连接凸块101至形成于半导体裸片100中的金属层107与内连线109。
然而，尽管接触垫105金属层107与内连线109在尺寸上相对为小时，凸块101与其相对的凸块下金属化层103却是非常大。因此于裸片100的表面上凸块103的覆盖率远大于连接至下方的金属层107与内连线109的所需。当装置进一步缩小，多个凸块下金属化层103与其他结构，例如半导体裸片100表面上的引线竞争表面积(valuable real estate)时，此于半导体裸片100表面上的大覆盖率会变成不利条件。
因此，所需为占去较少半导体裸片表面的表面积的凸块下金属化层与直通硅晶穿孔的结合，且其也减少或排除了于半导体裸片表面上的凸块下金属化层与引线间的竞争。
发明内容
借由本发明优选实施例所提供位于凸块下金属化层下的直通硅晶穿孔的结构与形成方法，通常可解决或避免这些或其他问题，且通常可达到技术优点。
本发明一优选实施例提供一种半导体装置，包括一基底，其具有多个直通硅晶穿孔穿过该基底形成。一凸块下金属化层形成于该多个直通硅晶穿孔之上且与该多个直通硅晶穿孔的至少之一电性连接。此外，该多个直通硅晶穿孔的至少之一与该凸块下金属化层电性分离。
本发明另一优选实施例提供一种半导体装置，包括一基底，其具有一或多个接口直通硅晶穿孔与一或多个连接直通硅晶穿孔，其各具有一接触垫。此外，一或多条引线位于基底中且连接至至少一个接触垫，此接触垫连接至连接直通硅晶穿孔之一。一凸块下金属化层位于至少一个连接直通硅晶穿孔之上且与至少一个接口直通硅晶穿孔电性连接，而与至少一个连接直通硅晶穿孔电性分离。
本发明又另一优选实施例提供一种半导体装置，包括一基底，其具有多个直通硅晶穿孔延伸穿过该基底。一凸块下金属化层位于该多个直通硅晶穿孔之上且电性连接至该多个直通硅晶穿孔的至少之一，而与该多个直通硅晶穿孔的至少之一电性分离。一焊料凸块(solder bump)位于该凸块下金属化层之上。
本发明优选实施例的优点为利用凸块下金属化层之下的区域，因此释放出于装置表面上的有用空间。
为了让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举优选实施例，并配合附图，作详细说明如下。
附图说明
图1显示现有技术装置具有一单一接口连接至一凸块下金属化层。
图2-6显示本发明一实施例的凸块下金属化层的形成，其覆盖多个直通硅晶穿孔。
图7A与图7B显示本发明一实施例的一接点于凸块下金属化层之上的形成。
图8A与图8B显示本发明实施例的直通硅晶穿孔的不同布局的俯视图。
图9显示本发明一实施例的于半导体装置上的凸块下金属化层的布局的俯视图
并且，上述附图中的附图标记说明如下：
100～半导体裸片
101～凸块
103～凸块下金属化层
105～接触垫
107～金属层
109～连接
111～介电层
200～裸片
201～基底
203～第一介电层
205～引线
207～基底201的一第一侧
301～第二介电层
303～内连线
305～接口直通硅晶穿孔开口
307～连接直通硅晶穿孔开口
309～导电材料
401～第三介电层
403～接口直通硅晶穿孔接触垫
405～连接直通硅晶穿孔接触垫
501～第四介电层
503～开口
505～凸块下金属化层
601～载体
602～裸片200的第二侧
603～接口直通硅晶穿孔
605～连接直通硅晶穿孔
701～接触凸块
703～接触垫
具体实施方式
本发明于特定内容中以优选实施例来叙述，即为具有相关的直通硅晶穿孔的凸块下金属化层。然而，也可提供本发明至其他形式的电子连接。
参见图2，其显示裸片200的一部分，其包括一基底201与一第一介电层203于基底201上，且引线205形成于第一介电层203中。基底201优选包括一于其上形成有源装置(未示出)的半导体材料与一系列可替换的金属，及预定来自有源装置的内连线与电路的介电层。
第一介电层203优选沿着于有源装置上的基底201的一第一侧207形成于基底201上。第一介电层203优选由一或多个适合的介电材料所制成，例如，氧化硅、氮化硅、低介电常数材料(例如，碳掺杂氧化物)、上述的组合或其类似物。第一介电层203优选借由一工艺，例如化学气相沉积来形成，然而也可利用任何适合的工艺。
引线205优选形成于介电层203中。引线205优选使用来安排电性连接，例如介于有源装置间或甚至介于不同裸片间的输入/输出信号或电源信号。引线205的设计与布局当然依据裸片200的需要，且此种布局完全包含于本实施例范围中。
引线205优选由铝所制成，然而也可使用任何适合的导电材料，例如铝合金、铝铜、铜、上述的组合或其类似物。优选借由使用化学气相沉积工艺与一用以图案化引线的蚀刻来形成引线205。然而也可使用其他适合所用特定材料的方法(例如镶嵌工艺适用于铜)。
图3显示形成一第二介电层301于引线205上与形成内连线303至引线205。第二介电层301可由与对应于图2的上述第一介电层203的相似材料及借由与其相似方法来形成。内连线303优选为铜，且优选借由镶嵌工艺来形成，然而任何适合的材料与方法也可用来形成内连线303至引线。
图3也显示一或多个接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307的形成。优选将接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307彼此同时制成，然而其也可经由分开的工艺来形成。优选借由提供或发展一适合光致抗蚀剂(未示出)且之后蚀刻第二介电层301、第一介电层203与部分基底201来形成接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307。或者，当自基底201向上建构裸片200时，随着个别层(例如介电或金属层)的形成，直通硅晶穿孔开口305与连接直通硅晶穿孔开口307可同时形成。
优选为，形成接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307以便至少较形成于基底201中与其上的电子装置更深入地延伸进入基底，且优选至少至一深度其大于完成的裸片200的最终所需高度。因此，当深度依照裸片200的所有设计时，深度优选为低于基底201上的有源装置下方约1-700μm，优选深度为低于基底201上的有源装置下方约20-250μm。
优选为形成接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307使其直径为约1-100μm，优选直径为约6μm。此外，当接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307关于彼此的距离为依据裸片200的设计时，距离优选为等于或大于约6μm。
一旦形成接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307，优选以导电材料309将接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307填满。导电材料309优选包括一阻障层(例如氮化钛或氮化钽)与铜，然而也可使用其他适合的材料，例如铝、合金、掺杂多晶硅、上述的组合或其类似物。优选借由沉积阻障层与一籽晶层(seed layer)且之后电镀铜于籽晶层上、填满与满出接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307来形成导电材料309。一旦填满了接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307，优选借由磨削工艺(grinding process)，例如，化学机械研磨来移除在接口直通硅晶穿孔开口305与连接直通硅晶穿孔开口307外超出的导电材料309，然而也可使用任何适合的移除工艺。
图4显示一或多个接口直通硅晶穿孔接触垫403与连接直通硅晶穿孔接触垫405的形成。接口直通硅晶穿孔接触垫403连接接口直通硅晶穿孔603(形成自填满的接口直通硅晶穿孔开口305，如下述对应至图6)至引线205且至将被形成的凸块下金属化层(如下所述，对应至图5)。连接直通硅晶穿孔接触垫405连接直通硅晶穿孔605(形成自填满的连接直通硅晶穿孔开口307，如下述对应至图6)至其各自的引线205。接口直通硅晶穿孔接触垫403与连接直通硅晶穿孔接触垫405优选由相同材料，铝，所形成，然而其也可由彼此不同的材料所形成，且也可使用其他材料，例如铝合金、铝铜、铜、上述的组合与其类似物。
接口直通硅晶穿孔接触垫403与连接直通硅晶穿孔接触垫405依据其所使用的材料可由多种方法来形成。例如，若使用铝的话，优选借由形成一铝层于第二介电层301上，且之后使用一适合技术，例如光刻(photolithography)与化学蚀刻以将铝图案化进入接口直通硅晶穿孔接触垫403与连接直通硅晶穿孔接触垫405来形成接口直通硅晶穿孔接触垫403与连接直通硅晶穿孔接触垫405。或者，若使用铜的话，优选借由一开始形成一第三介电层401、形成开口进入第三介电层401、沉积一阻障层与一籽晶层(未示出)、以铜填至满出开口，与之后使用一磨削工艺，例如化学机械研磨以移除位于开口外超出的铜来形成接口直通硅晶穿孔接触垫403与连接直通硅晶穿孔接触垫405。可使用任何适合形成接口直通硅晶穿孔接触垫403与连接直通硅晶穿孔接触垫405的工艺，且所有这些工艺完全包括于本发明范围中。
图5显示一第四介电层501形成于接口直通硅晶穿孔接触垫403与连接直通硅晶穿孔接触垫405之上。第四介电层501优选由相似于第一介电材料203的介电材料(如上所述，对应至图2)所形成，且优选借由与其相似的工艺来形成。一旦形成第四介电层501，制造一或多个开口503穿过第四介电层501以便至少部分露出各接口直通硅晶穿孔接触垫403的部分。开口503优选借由一适合的光刻掩模与蚀刻工艺来形成，然而也可使用任何适合露出接口直通硅晶穿孔接触垫403之工艺。
图5也显示凸块下金属化层505(也熟知为凸块下金属化接点)的形成，凸块下金属化层505穿过第四介电层501而接触接口直通硅晶穿孔接触垫403。一旦开口503露出接口直通硅晶穿孔接触垫403，优选形成凸块下金属化层505于第四介电层501的部分上且穿过开口503以便制造与接口直通硅晶穿孔接触垫403的物理与电性接触。凸块下金属化层505优选由至少三层导电层来形成，例如一层铬、一层铬铜合金与一层铜，与视需要一层金于铜层顶部上。然而，本领域普通技术人员会认可有许多适合的材料与层别的排列，例如钛/钛/钨/铜的排列或铜/镍/金的排列适合凸块下金属化层505的形成。可使用于凸块下金属化层505的任何适合的材料或材料层别完全包含于本申请的范围中。
优选借由形成各层于第四介电层上且进入开口503来形成凸块下金属化层505。优选借由执行使用一化学气相沉积工艺，例如等离子体辅助化学气相沉积(plasma-enhanced chemical vapor deposition，PECVD)来形成各层，然而依据所需的材料也可使用其他形成工艺，例如溅镀、蒸镀或电镀工艺。于凸块下金属化层505中的各层优选具有约10-100μm的厚度，优选厚度为约45μm。一旦形成所需层别，之后优选借由适合的光刻掩模与蚀刻工艺来移除层别的部分以移除不需要的材料而留下图案化的凸块下金属化层505。
优选形成凸块下金属化层505使其不只位于接口开口305上，也位于一或多个连接开口307之上。优选也将凸块下金属化层505形成于至少一条引线205之上。在此方式中，可将连接开口307(且之后被形成连接直通硅晶穿孔605)与引线303整合成三维结构，而取代一般两维结构，因此对于裸片200表面上的所有组成而言，减少了全部的二维覆盖率。
图6显示自接口直通硅晶穿孔开口305形成接口直通硅晶穿孔603与自连接直通硅晶穿孔开口307形成连接直通硅晶穿孔605。优选为，一载体601贴附至裸片200于凸块下金属化层505上。载体601可包括，例如玻璃、氧化硅、氧化铝与其类似物。在一实施例中，可使用一第二粘着剂(未示出)以将载体601粘着至裸片200的顶部表面。第二粘着剂可为任何适合的粘着剂，例如紫外光粘着剂，而当暴露于紫外光时，其会丧失其粘着性。载体的优选厚度为大于约12密尔(mil)。
或者，载体601可优选包括载带(carrier tape)。若使用载带，载带优选为一般熟知的蓝膜片(blue tape)。使用位于载带上的第二粘着剂(未示出)将载带贴附至裸片200优选。
一旦贴附至载体601，接着移除裸片200的一第二侧602的部分以露出位于接口直通硅晶穿孔开口305中的导电材料309以完成接口直通硅晶穿孔603，且也露出位于连接直通硅晶穿孔开口307中的导电材料309以完成连接直通硅晶穿孔605。优选以磨削工艺，例如化学机械研磨来执行移除，然而也可使用其他适合的工艺。移除工艺优选移除裸片200的第二侧的约1-50μm，且优选为移除约20μm的裸片200的第二侧。
如本领域普通技术人员所知，上述包括形成通孔、沉积导体与接着薄化基底201的第二侧602的接口直通硅晶穿孔603与连接直通硅晶穿孔605的形成工艺，只是形成直通硅晶穿孔的方法之一。在另一方法中，可借由蚀刻通孔部分穿过基底201与沉积一介电层于通孔中来形成接口直通硅晶穿孔603与连接直通硅晶穿孔605。在此实施例中，在薄化基底201的背面后，移除位于通孔中的介电层，且再沉积导电材料于通孔中。或者可使用此方法与任何其他适合形成接口直通硅晶穿孔603与连接直通硅晶穿孔605的方法，且这些方法完全包含于本发明范围中。更进一步而言，接口直通硅晶穿孔603与连接直通硅晶穿孔605优选可具有一衬垫，其由介电材料，例如氧化物、氮化物或其类似物所形成。
图7A显示一接触凸块701形成于凸块下金属化层505上。接触凸块701优选包括一材料，例如锡，或其他适合的材料，例如银或铜。在一实施例中，其中接触凸块701为一锡焊料凸块，可借由最初使用一般方法，例如蒸镀、电镀、印刷、焊料转移(solder transfer)、锡球置放(ball placement)等来形成一锡层，以形成接触凸块701至一优选厚度约100μm。一旦锡层形成于此结构上，执行一回流(reflow)以将材料塑造成所需的凸块形状。
图7B显示一替代实施例，其中一接触垫703取代接触凸块701形成于凸块下金属化层505上。在此实施例中，接触垫703优选包括铜，然而也可使用任何适合导电材料，例如铝或钨。在一实施例中，其中接触垫703为铜，接触垫703优选借由一适合的电镀工艺来形成，然而也可使用用于其他材料的其他工艺，例如，化学气相沉积。接触垫703优选形成为矩形，然而也可视需要使用任何适合的形状，例如正方形或八角形。
图8A-图8B显示凸块下金属化层505与其下方的接口直通硅晶穿孔603与连接直通硅晶穿孔605的潜在俯视图。图8A显示优选将凸块下金属化层505图案化成圆形，然而也可使用裸片200的全部设计所需的任何适合形状，例如六角形、八角形或正方形。凸块下金属化层505优选具有约30-400μm的直径，直径优选为80μm。
如图所示，多个接口直通硅晶穿孔603与连接直通硅晶穿孔605优选位于凸块下金属化层505之下，且连接直通硅晶穿孔605的图案也自凸块下金属化层505之下延伸向外。更进一步而言，尽管图2-图7B中显示两个接口直通硅晶穿孔603，位于凸块下金属化层505之下的多数直通硅晶穿孔可被连接至凸块下金属化层505为一接口直通硅晶穿孔603。可使用任何接口直通硅晶穿孔603与连接直通硅晶穿孔605的组合来连接裸片200的组成，且任何组合完全在本申请的范围中。
图8B显示一些替代实施例，其中将凸块下金属化层505形成为八角形，其直径为约160-300μm。如图所示，依据凸块下金属化层505的尺寸，将在凸块下金属化层505下的接口直通硅晶穿孔603与连接直通硅晶穿孔605进行不同布局是可能的。例如，若凸块下金属化层505的直径为约160μm，可利用一接口直通硅晶穿孔603与连接直通硅晶穿孔605的实质正方形的布局，若凸块下金属化层505的直径为约180μm，可利用一十字形图案，且若凸块下金属化层505的尺寸允许，也可使用利用更多直通硅晶穿孔的更复杂的图案。如前所述，可在图案中使用任何接口直通硅晶穿孔603与连接直通硅晶穿孔605的组合。
图9显示于裸片200上的多个凸块下金属化层505的潜在分布，其中所示出的凸块下金属化层505的一显示位于下方的接口直通硅晶穿孔603与连接直通硅晶穿孔605。凸块下金属化层505的此分布优选具有一约60-600μm的距离，优选距离为约150μm。
借由将连接直通硅晶穿孔605与接口直通硅晶穿孔603置于凸块下金属化层505之下，则引线只需占去较少裸片200表面的空间。如此，可将这些裸片间隔得更加紧密地在一起，且当连接时具有较少的所有覆盖率。此减少一般电路组成的尺寸，产生全面较小的装置。
虽然本发明已以优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (15)

1.一种半导体装置，包括：
一基底，其具有一第一侧与一第二侧；
多个直通硅晶穿孔自该第一侧延伸至该第二侧；以及
一凸块下金属化接点位于该多个直通硅晶穿孔之上，其中该凸块下金属化接点电性连接至所述多个直通硅晶穿孔的至少之一，且与该所述多个直通硅晶穿孔的至少之一电性分离。
2.如权利要求1所述的半导体装置，还包括至少一接触垫位于该凸块下金属化接点之下，但不与该凸块下金属化接点接触，该至少一接触垫电性连接至与该凸块下金属化接点电性分离的该直通硅晶穿孔的至少之一。
3.如权利要求2所述的半导体装置，还包括至少一引线位于该至少一接触垫之下，该至少一引线与该至少一接触垫电性连接。
4.如权利要求1所述的半导体装置，其中该凸块下金属化接点电性连接至多于一个该直通硅晶穿孔。
5.如权利要求1所述的半导体装置，其中该凸块下金属化接点包括三层导电材料。
6.一种半导体装置，包括：
一基底，其具有一第一表面与一第二表面，该第二表面位于该第一表面的对面；
多个直通硅晶穿孔自该第一表面延伸至该第二表面；以及
一第一凸块下金属化接点位于所述多个直通硅晶穿孔之上，且与所述多个直通硅晶穿孔的至少之一电性连接，其中所述多个直通硅晶穿孔的至少之一与该第一凸块下金属化接点电性分离。
7.如权利要求6所述的半导体装置，还包括至少一接触垫位于该第一凸块下金属化接点与所述多个直通硅晶穿孔的至少之一之间且与该第一凸块下金属化接点电性连接。
8.如权利要求6所述的半导体装置，还包括引线位于该第一凸块下金属化接点之下且电性连接至该直通硅晶穿孔的至少之一。
9.如权利要求6所述的半导体装置，还包括一接触垫位于该第一凸块下金属化接点之上。
10.如权利要求6所述的半导体装置，还包括多条引线位于该基底中，所述多条引线的至少之一电性连接至该第一凸块下金属化接点，且所述多条引线的至少之一与该第一凸块下金属化接点电性分离。
11.如权利要求6所述的半导体装置，其中该第一凸块下金属化接点与多于一个的所述多个直通硅晶穿孔电性连接。
12.一种半导体装置，包括：
一基底，其具有一第一侧与一相对的第二侧；
一或多个接口直通硅晶穿孔自该第一侧延伸至该第二侧，该一或多个接口直通硅晶穿孔连接至各别的位于该第一侧之上的一或多个接口接触垫；
一或多个连接直通硅晶穿孔自该第一侧延伸至该第二侧，该一或多个连接直通硅晶穿孔连接至各别的位于该第一侧之上的一或多个连接接触垫；以及
一第一凸块下金属化层位于该第一侧之上且该连接直通硅晶穿孔的至少之一之上，该第一凸块下金属化层与连接直通硅晶穿孔的至少之一电性分离，且与该接口直通硅晶穿孔的至少之一电性连接。
13.如权利要求12所述的半导体装置，其中第一凸块下金属化层电性连接至多个该一或多个接口直通硅晶穿孔。
14.如权利要求12所述的半导体装置，还包括一或多条引线位于该第一凸块下金属化层之下且电性连接至一或多个接口接触垫之一。
15.如权利要求12所述的半导体装置，还包括一或多个连接直通硅晶穿孔，其不被该第一凸块下金属化层所覆盖。
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