CN101635279B - Manufacturing method for protecting interval wall of bipolar transistor circuit - Google Patents
Manufacturing method for protecting interval wall of bipolar transistor circuit Download PDFInfo
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- CN101635279B CN101635279B CN200810145560.0A CN200810145560A CN101635279B CN 101635279 B CN101635279 B CN 101635279B CN 200810145560 A CN200810145560 A CN 200810145560A CN 101635279 B CN101635279 B CN 101635279B
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- bipolar transistor
- transistor circuit
- clearance wall
- circuit
- spacer material
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Abstract
The invention relates to a manufacturing method for protecting the interval wall of a bipolar transistor circuit. The bipolar transistor circuit and the grid circuit of an MOS transistor are arranged on the same substrate, and is characterized by comprising the following steps: the first step: depositing a layer of interval-wall material on the substrate; the second step: etching the interval-wall material layer dryly until a thin layer with preset thickness is left; and the third step: etching the thin layer wetly until the bipolar transistor circuit is exposed out. The manufacturing method for protecting the interval wall of the bipolar transistor circuit has the advantages of considering the integrity of the surface of the silicon substrate when removing excessive interval-wall material, improving junction leakage current and increasing the current gain beta of BJT.
Description
Technical field
The present invention relates to a kind of integrated circuit (IC) manufacture method, specifically, is a kind of clearance wall manufacture method of protecting bipolar transistor circuit.
Background technology
In electric current CMOS (Complementary Metal Oxide Semiconductor) (CMOS) manufacturing technology, clearance wall processing procedure (spacer process) is the conventional means that solves hot carrier effect in MOS transistor, yet this processing procedure but causes serious junction leakage current to the bipolar transistor (BJT) being positioned on same silicon substrate.
Typical clearance wall processing procedure is first one, to have on the silicon substrate 14 of gate electrode 10 and deposit all sidedly a spacer material layer 12, for example tetraethoxysilane (Tetra-Ethyl-Ortho-Silicate; TEOS), as shown in Figure 1, Fig. 1 is a schematic diagram of known gap wall processing procedure; Then with dry ecthing procedure etched gap wall material layer 12; Finally leave the clearance wall 16 as Fig. 2, Fig. 2 is another schematic diagram of known gap wall processing procedure.Known gap wall processing procedure can elongate the time of dry ecthing, to guarantee that the spacer material on grid circuit 10 and silicon substrate surface 18 can be etched clean, but dry ecthing than very poor, often damages silicon substrate surface 18 to the selection of TEOS 12 and silicon substrate 14 in etching TEOS 12.
Fig. 3 is that known gap wall processing procedure causes the schematic diagram of damage to BJT, when the silicon substrate damaged surfaces causing when aforementioned clearance wall processing procedure appears at the p-n junction of BJT 28, for example, at the emitter 24 and base stage 22 of BJT 28, or between collector electrode 20 and base stage 22, cause damaged 25 o'clock, just can cause junction leakage current in these junctions.Owing to offering the base current of BJT, generally only have several μ A, and the junction leakage current that surface damage causes also can reach the grade of μ A conventionally, makes the currentgainβ of BJT 28 become very low.
Therefore known clearance wall processing procedure exists above-mentioned all inconvenience and problem.
Summary of the invention
Object of the present invention, is to propose a kind of clearance wall manufacture method of protecting bipolar transistor circuit.
For achieving the above object, technical solution of the present invention is:
Protect a clearance wall manufacture method for bipolar transistor circuit, the grid circuit of described bipolar transistor circuit and a MOS transistor, on same substrate, is characterized in that comprising the following steps:
First step: deposition one spacer material layer is on described substrate;
Second step: described in dry ecthing, spacer material layer is to leaving the thin layer with a preset thickness;
Third step: described in wet etching, thin layer is to exposing described bipolar transistor circuit.
The clearance wall manufacture method of protection bipolar transistor circuit of the present invention can also be further achieved by the following technical measures.
The clearance wall manufacture method of aforesaid protection bipolar transistor circuit, the step of wherein said deposition one spacer material layer on described substrate comprises deposition TEOS.
The clearance wall manufacture method of aforesaid protection bipolar transistor circuit, the step of thin layer comprises described in wherein said wet etching provides hydrofluoric acid.
Adopt after technique scheme, the clearance wall manufacture method of protection bipolar transistor circuit of the present invention has the following advantages:
1. when removing unnecessary spacer material, take into account the complete of silicon substrate surface.
2. improve junction leakage current.
3. improve the currentgainβ of BJT.
Accompanying drawing explanation
Fig. 1 is a schematic diagram of known gap wall processing procedure;
Fig. 2 is another schematic diagram of known gap wall processing procedure;
Fig. 3 is that known gap wall processing procedure causes the schematic diagram of damage to BJT;
Fig. 4 is a structural representation of the embodiment of the present invention;
Fig. 5 is another structural representation of the embodiment of the present invention;
Fig. 6 is the another structural representation of the embodiment of the present invention;
Fig. 7 is a structural representation again of the embodiment of the present invention.
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof, the present invention is illustrated further.
Now refer to Fig. 4～Fig. 7, the structural representation that Fig. 4 is the embodiment of the present invention, another structural representation that Fig. 5 is the embodiment of the present invention, the another structural representation that Fig. 6 is the embodiment of the present invention, the structural representation again that Fig. 7 is the embodiment of the present invention.As shown in the figure, collector electrode 38 and the base stage 36 on described silicon substrate 30 with BJT, and the grid 34 of MOS transistor, at described spacer material layer 32, be deposited on behind the surface of silicon substrate 30, first with electricity slurry or charged particle, spacer material layer 32 is done to iso dry ecthing.As shown in Figure 5, when described spacer material layer 32 is carved into remaining thin layer 40 by dry corrosion, stop dry ecthing, change with wet etching and remove thin layer 40, as shown in Figure 6, because wet etching has good selection ratio, therefore when removing thin layer 40 and forming clearance wall 42, do not damage the surface of silicon substrate 30, thereby improve the junction leakage current between base-emitter or collection-base stage.After described clearance wall 42 forms, then silicon substrate carried out to ion ooze the steps such as assorted, as shown in Figure 7, in the both sides of grid 34, produce as the drain of MOS transistor or the N of source electrode and ooze assorted region 46, and BJT penetrate level 44.
The spacer material that embodiments of the invention are used is TEOS, and carries out wet etching with hydrofluoric acid (FH), and in other embodiments, described spacer material can be photoresistance, and selects applicable wet etching material according to spacer material.
Above embodiment is used for illustrative purposes only, but not limitation of the present invention, person skilled in the relevant technique, without departing from the spirit and scope of the present invention, can also make various conversion or variation.Therefore, all technical schemes that are equal to also should belong to category of the present invention, should be limited by each claim.
Element numbers explanation
10 gate electrodes
12 spacer material layers
14 silicon substrates
16 clearance walls
18 silicon substrate surfaces
20 collector electrodes
22 base stages
24 emitters
25 is damaged
28BJT
30 silicon substrates
32 spacer material layers
34 grids
36 base stages
38 collector electrodes
40 thin layers
42 clearance walls
44 emitters
46N oozes assorted region
Claims (3)
1. protect a clearance wall manufacture method for bipolar transistor circuit, the grid circuit of described bipolar transistor circuit and a MOS transistor, on same substrate, is characterized in that comprising the following steps:
First step: deposition one spacer material layer is on described substrate;
Second step: described in dry ecthing, spacer material layer is to leaving the thin layer with a preset thickness; And
Third step: described in wet etching, thin layer is to exposing described bipolar transistor circuit and form clearance wall on the sidewall of the grid circuit of described MOS transistor, and described clearance wall solves hot carrier effect in described MOS transistor.
2. clearance wall manufacture method as claimed in claim 1, is characterized in that, the step of described deposition one spacer material layer on described substrate comprises deposition TEOS.
3. clearance wall manufacture method as claimed in claim 1, is characterized in that, the step of thin layer comprises described in described wet etching provides hydrofluoric acid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810145560.0A CN101635279B (en) | 2008-07-25 | 2008-07-25 | Manufacturing method for protecting interval wall of bipolar transistor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810145560.0A CN101635279B (en) | 2008-07-25 | 2008-07-25 | Manufacturing method for protecting interval wall of bipolar transistor circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101635279A CN101635279A (en) | 2010-01-27 |
| CN101635279B true CN101635279B (en) | 2014-09-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810145560.0A Expired - Fee Related CN101635279B (en) | 2008-07-25 | 2008-07-25 | Manufacturing method for protecting interval wall of bipolar transistor circuit |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI371085B (en) | 2008-08-12 | 2012-08-21 | Vanguard Int Semiconduct Corp | Fabrication methods for integration cmos and bjt devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070069295A1 (en) * | 2005-09-28 | 2007-03-29 | Kerr Daniel C | Process to integrate fabrication of bipolar devices into a CMOS process flow |
| US20070202642A1 (en) * | 2006-02-24 | 2007-08-30 | Nanda Arun K | Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method |
| CN101145574A (en) * | 2006-09-14 | 2008-03-19 | 台湾类比科技股份有限公司 | High voltage tolerance element and producing method thereof |
-
2008
- 2008-07-25 CN CN200810145560.0A patent/CN101635279B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070069295A1 (en) * | 2005-09-28 | 2007-03-29 | Kerr Daniel C | Process to integrate fabrication of bipolar devices into a CMOS process flow |
| US20070202642A1 (en) * | 2006-02-24 | 2007-08-30 | Nanda Arun K | Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method |
| CN101145574A (en) * | 2006-09-14 | 2008-03-19 | 台湾类比科技股份有限公司 | High voltage tolerance element and producing method thereof |
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| CN101635279A (en) | 2010-01-27 |
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Granted publication date: 20140924 Termination date: 20180725 |