CN101611477B - Method for polishing heterostructures - Google Patents

Method for polishing heterostructures Download PDF

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CN101611477B
CN101611477B CN 200880005163 CN200880005163A CN101611477B CN 101611477 B CN101611477 B CN 101611477B CN 200880005163 CN200880005163 CN 200880005163 CN 200880005163 A CN200880005163 A CN 200880005163A CN 101611477 B CN101611477 B CN 101611477B
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polishing
layer
surface
step
substrate
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CN101611477A (en )
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科琳娜·塞金
米里埃尔·马蒂内
莫尔加纳·洛吉奥
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硅绝缘体技术有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02024Mirror polishing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

A polishing method of a heterostructure (12) comprising at least one relaxed superficial heteroepitaxial layer (121) on a substrate (120) made from a different material from that of said heteroepitaxial layer. The method comprises a first chemical mechanical polishing step of the surface of the heteroepitaxial layer (12) performed with a polishing cloth (14) having a first compressibility ratio and with a polishing solution having a first silica particle concentration. The first chemical mechanical polishing step is followed by a second chemical mechanical polishing step of the surface of theheteroepitaxial layer (121), said second step being performed with a polishing cloth having a second compressibility ratio, higher than said first compressibility ratio, and with a polishing solutionhaving a second silica particle concentration, lower than said first concentration.

Description

用于抛光异质结构的方法 A method for polishing hetero structure

技术领域 FIELD

[0001] 本发明涉及与缓冲层相关的异质结构的领域,该异质结构能够在另一不同材料上获得特定的应变材料。 [0001] related art heterostructure and the buffer layer according to the present invention, the specific heterostructure strained material can be obtained on the other a different material. 这样的异质结构的示例为Si(1_x)Ge(x)结构(χ根据所需的应变度可从20%到100%变化),该Si(1_x)Ge(x)结构包括通过外延附生形成在硅基底上的松散Si(1_x) Ge(x)缓冲层。 Examples of such a heterostructure is Si (1_x) Ge (x) configuration (depending on the desired degree of strain [chi] may vary from 20% to 100%), the Si (1_x) Ge (x) by epitaxy structure comprising is formed on a silicon substrate of bulk Si (1_x) Ge (x) of the buffer layer. 当通过外延附生形成31(1_!£)6〜!£)层时,硅基底与随后的SiGe层之间的晶格失配导致在SiGe缓冲层的表面出现称作“交叉影线”(cross-hatch)的应变晶格。 When the formation 31 (1_! £) 6~! £) layer is formed by epitaxy, the lattice mismatch between the silicon substrate and subsequently cause mismatch SiGe layer called "cross-hatching" appears in the surface of the SiGe buffer layer ( cross-hatch) lattice strain. 该交叉影线增大了松散的SiGe缓冲层的表面粗糙度。 This increases the cross-hatched loose surface roughness of SiGe buffer layer. 然后将松散的SiGe缓冲层的表面抛光,以除去交叉影线并且减小表面粗糙度。 Then the loose surface of the SiGe buffer layer is polished to remove cross-hatching and reduce the surface roughness. 为此,将松散的SiGe缓冲层表面通过化学机械抛光(CMP) (一种公知的抛光技术)而变平,该公知的抛光技术实施到与抛光溶液关联的织物,所述抛光溶液包含能够化学腐蚀所述层的表面的溶剂(例如NH4OH)以及能够机械蚀刻所述表面的研磨颗粒(例如硅石颗粒)。 For this purpose, the loose surface of the SiGe buffer layer flattened by chemical mechanical polishing (the CMP) (a known polishing), the polishing technique known embodiment to the fabric associated with a polishing solution, the polishing solution comprises a chemical capable of etching the layer surface of the solvent (e.g., NH40H) and the surface of the abrasive particles can be mechanical etching (e.g. silica particles).

背景技术 Background technique

[0002] 已提出多个通过CMP除去交叉影线因此降低异质SiGe结构的表面粗糙度的方案。 [0002] CMP has been proposed by a plurality of cross-hatching removed thus reducing the surface roughness of the SiGe structures heterostructure scheme.

[0003] K. Sawano 等人的文献(晶体成长期刊(Journal of Crystal Growth)第251 卷, 第693-696页(2003)) “通过CMP平面化SiGe虚拟基底以及将其应用至应变Si调制掺杂结构(Planarization of SiGe virtual substrate byCMP and its application to strained Si modulation-doped structures),,禾口K. Sawano 等人的文献(材料禾斗学与工程B89第406-409页(2002)) “通过化学机械抛光使SiGe应变松散缓冲层的表面平滑(Surface smoothing ofSiGe strain-relaxed buffer layers by chemical mechanical polishing) ”描述了一种在两个外延附生步骤之间抛光SiGe结构的技术方案,以将表面粗糙度降低到小于1纳米(nm)RMS的值(10X 10 μ m2的扫描面积大约0. 4nm)。然而,通过该方案所获得的抛光速率较慢,通过调整抛光压力参数仅能获得1. 3纳米/秒的最大去除速率。 [0003] K. Sawano et al in the literature (Journal of Crystal Growth (Journal of Crystal Growth), Vol. 251, pp. 693-696 (2003)) "planarized by CMP SiGe virtual substrate and applying it to the modulation-doped strained Si hetero structure (Planarization of SiGe virtual substrate byCMP and its application to strained Si modulation-doped structures) ,, Wo mouth K. Sawano et al document (materials Science and Engineering B89 Wo bucket on pages 406-409 (2002)) "by chemical mechanical polishing the surface of the SiGe buffer layer of loose strained smoothing (surface smoothing ofSiGe strain-relaxed buffer layers by chemical mechanical polishing) "describes a technical solution polishing structure between two SiGe epitaxy step, to surface roughness is reduced to a value less than 1 nm RMS (scanning area 10X 10 μ m2 approximately 0. 4nm) (nm). However, the polishing rate obtained by the program slowly, only by adjusting the polishing pressure to obtain a parameter. the maximum removal rate of 3 nm / sec.

[0004] 文献US 6988936和JP 11197583描述了通过化学机械抛光借助于SmartCut™技术所获得的SOI (绝缘体上硅)的硅层的用于磨光或再循环的方法。 [0004] Documents US 6988936 and JP 11197583 describes a method for finishing or recycling of the silicon layer by means of a SOI (silicon on insulator) SmartCut ™ technology obtained by chemical mechanical polishing. 然而,这些方法不适用于异质SiGe结构。 However, these methods are not suitable for SiGe heterojunction structure. 当包含有SiGe时,通过关于硅的这些方法所获得的抛光速率实际上降低到l/5(Vsi/VSiCe = 5)。 When comprises SiGe, the polishing rate of silicon by these methods on the obtained actually reduced to l / 5 (Vsi / VSiCe = 5).

[0005] 文献WO 2005/120775和WO 2006/032298公开了SiGe层的CMP方法,该方法不仅能够通过“硬的”或“中间的”抛光/平面化织物在单一抛光步骤中实现高的去除速率,而且对于通过原子力显微镜(AFM)测量的10X 10 μ m2的扫描面积,能够获得的小于0. 2纳米(nm)RMS的表面粗糙度。 [0005] Document WO 2005/120775 and WO 2006/032298 disclose a CMP process SiGe layer, which can be only the "hard" or "intermediate" polishing / planarization fabric to achieve a high removal rate in a single polishing step , and the measurement by an atomic force microscope (AFM) scanning area 10X 10 μ m2, and less than 0.2 nanometers (nm) RMS surface roughness can be obtained.

[0006] 虽然在这两个文献中所描述的抛光方法实现了通过AFM所观测的具有较低表面微观粗糙度的异质SiGe结构,但是它们不保证足够的表面宏观粗糙等级来满足组件的不断提高的小型化所需要的新的质量要求,该组件例如待在sSOI结构上制造,该sSOI结构由形成在硅支撑基底上的异质结构(供体基底)构成,借助SiGe缓冲层在该硅支撑基底上形 [0006] While the polishing method described in the literature both achieved SiGe heterojunction structure having a relatively low surface microroughness observed by AFM, but they do not guarantee adequate surface macro-roughness level to meet assembly the new improved quality requirements needed for miniaturization of the components such as the manufacture sSOI structure to stay on the sSOI structure consists heterostructure formed on the silicon support substrate (donor substrate) constituted by a silicon layer on the SiGe buffer formed on the supporting substrate

4成松散SiGe层,应变硅层形成在松散SiGe层上。 4 into a loose layer of SiGe, strained silicon layer is formed on the SiGe layer loose.

[0007] 申请人实际上观测到,通过测量表面光雾度(当晶片或异质结构例如在SPl测量设备中被照亮时,从通过表面缺陷所散播的光产生的低空间频率信号)所确定的表面宏观粗糙度等级是与用以限定结构的表面状态的表面宏观粗糙度等级一样重要的参数。 [0007] Applicant has in fact observed, by measuring the surface haze (or when the wafer is illuminated, for example, the heterostructure SPl measuring device, from a low spatial frequency light generated by the surface defects of the spread signal) is determined macroscopic surface roughness level is an important parameter as with macroscopic surface roughness level to define the surface state of the structure. 由于SiGe异质结构在化学机械抛光之后的表面粗糙度的要求日益严格,所以这些结构的表面特征还必须考虑宏观粗糙度测量。 Since SiGe heterojunction structure of the surface roughness after chemical mechanical polishing required increasingly stringent, the surface characteristics of these structures must also consider the macroscopic roughness measurement. 以低空间频率(即,通过测量表示大范围的表面粗糙度(整个晶片)的表面光雾度)所进行的SiGe异质结构的特征表示表面宏观粗糙度(通过SPl测量的光雾度等级)与产品最终质量之间存在直接相关性。 At low spatial frequencies (i.e., by measuring the surface roughness represents the range (across the wafer) surface haze) wherein SiGe heterostructure represented performed macroscopic surface roughness (haze level measured by SPl) and There is a direct correlation between the quality of the final product. 用于测量晶片上的光雾度等级的技术具体在F. Holsteyns等人的文献(半导体制造,2003IEEE国际专题讨论会, 第378-381页)“利用全部表面光雾度信息的监测和鉴定(Monitoring andQualification Using Comprehensive Surface Haze Information),,中进行了描述。 A haze level of the wafer on the measuring technique in specific literature F. Holsteyns et al (Semiconductor Manufacturing, 2003 IEEE International Symposium on, pp. 378-381), "using all the surface haze and authentication information monitoring (Monitoring described) ,, in andQualification Using Comprehensive Surface Haze Information.

[0008] 因此申请人强调,在CMP后在松散的SiGe层的表面上测量的光雾度等级决定在该层上形成的应变硅层的表面质量,并且因而决定形成的sSOI产品的效率(组件整体性能)。 Efficiency [0008] The applicant hereby emphasized that the haze level on the surface of the SiGe layer of loose measured determines the surface quality strained Si layer is formed on the layer after the CMP, and therefore decided to form sSOI product (component overall performance). 换言之,CMP后的光雾度等级越低,则最终产品的效率越高。 In other words, the lower the haze level after the CMP, the higher the efficiency of the final product. 因此,通过降低CMP后的宏观粗糙度(即,以低空间频率测量的表面粗糙度),可实现所需的表面质量要求,以符合组件和电路的小型化)。 Thus, by reducing the macroscopic roughness after CMP (i.e., low spatial frequency surface roughness measurement), can achieve the desired surface quality to meet the miniaturization of components and circuitry).

[0009] 因此需要提高通过在文献WO 2005/120775和WO 2006/032298中描述的方法所获 [0009] Thus the need to improve by the method described in Document WO 2005/120775 and WO 2006/032298 obtained

得的表面粗糙度等级。 Have a surface roughness level.

发明内容 SUMMARY

[0010] 本发明的目的在于改进上述缺点,并提出一种抛光或平面化方案,借此在异质外延层的表面处存在的粗糙度等级,尤其是宏观粗糙度(光雾度)等级甚至可被进一步降低。 [0010] The object of the present invention to improve the above disadvantages and to propose a polishing or planarization scheme, whereby the roughness class present at the surface of the heteroepitaxial layer, in particular macroscopic roughness (haze) level even It can be further reduced.

[0011] 该目的通过一种包括位于与所述异质外延层的材料不同的基底上的至少一个松散的表面异质外延层的异质结构的抛光方法而得以实现,并通过以下方法来实现,即,其中在所述异质外延层表面的第一化学机械抛光步骤之后进行所述异质外延层表面的第二化学机械抛光步骤,所述第一化学机械抛光步骤通过具有第一压缩比的抛光织物和具有第一硅石颗粒浓度的抛光溶液来进行,所述第二化学机械抛光步骤通过具有比所述第一压缩比高的第二压缩比的抛光织物和具有比所述第一浓度低的第二硅石颗粒浓度的抛光溶液来进行,并且所述异质外延层为硅锗层。 [0011] This object is achieved by a method of polishing at least one loose hetero structure surface of the heteroepitaxial layer is located on the material of the heteroepitaxial layer includes the different substrates is achieved, and is achieved by a method , i.e., in which the first chemical mechanical polishing step after the surface of the hetero-epitaxial layer in the second chemical mechanical polishing step the surface of the heteroepitaxial layer, the first chemical mechanical polishing step is performed by having a first compression ratio polishing solution and a polishing fabric having a first concentration of silica particles is performed, the second chemical mechanical polishing step is performed by a second compression ratio than the first compression ratio and a polishing fabric than the first concentration a second low-concentration silica particles polishing solution is performed, and the heteroepitaxial layer is a silicon germanium layer.

[0012] 当进行所述第一抛光步骤时,优选使用“硬的”抛光织物,例如压缩比包括在2% 至4%之间(尤其为2% )的织物。 [0012] When performing the first polishing step, it is preferable to use "hard" polishing fabric such as a compression ratio comprised between 2-4% (particularly 2%) of the fabric. 虽然这样的硬度(2% )的织物导致比通过具有“中间的”压缩比(例如在文献W02005/120775中所介绍的6%)的织物获得更大的微观粗糙度(AFM40X40 μ m2),但是,根据本发明的该方法的两个步骤的结合能够更有效地去除称为“交叉影线”的应变晶格和称作“光雾度”的微观粗糙度和宏观粗糙度。 Although such a hardness (2%) result in a fabric having greater than that through the micro-roughness (AFM40X40 μ m2) "intermediate" compression ratio (e.g., 6% in the document W02005 / 120775 as described) of the fabric, but the combined two steps of the method of the present invention can be more effectively removed referred to as "cross-hatched" lattice strain and referred to as "haze" microscale roughness and macro-roughness.

[0013] 更准确地是,构成交叉影线的缺陷与晶格对准,并且因此极其稳定且难以变平,然而较容易去除随机布置的微观粗糙度成分。 [0013] More precisely, the defects constituting the lattice is aligned cross-hatched, and therefore extremely stable and difficult to flatten, however, more easily removed component microroughness randomly arranged. 当通过非常硬的织物进行第一抛光步骤时,虽然微观粗糙度整体保持较高(特别是对于其例如与由于抛光变硬的区域对应的随机布置的成分),但交叉影线确实消失。 When the first polishing step is performed by a very stiff fabric, while maintaining a high overall microroughness (for example, for which in particular due to the random arrangement of the components of the polishing region corresponding hardened), but really the cross-hatched disappear. 实际上可观测到随机布置的表面波形式,然而交叉影线清楚地呈现为与晶轴相关。 Wave form actually observed randomly arranged, however, cross-hatching appear clearly related to the crystal axis. 然后在第二抛光步骤中去除随机微观粗糙度,该第二抛光步骤优选包括使用具有例如在5%至9%之间的压缩比(尤其为6%)的中间抛光织物。 Random microroughness then removed in a second polishing step, the second polishing step preferably comprises, for example, having a compression between 5-9% ratio (particularly 6%) of intermediate polishing fabric.

[0014] 而且,当在第一抛光步骤中去除交叉影线时,第二抛光步骤能够使整个微观粗糙度减小到比在直接在单一步骤中用于使微观粗糙度最小的方法的情况下的更低的等级,该单一步骤不能够完全去除交叉影线。 [0014] Further, when removing the cross-hatching in a first polishing step, the second polishing step can be reduced to make the entire micro-roughness in the case of the ratio was used directly in a single step so that a method of minimizing microroughness a lower level, which can not be completely removed in a single step by cross-hatching.

[0015] 根据本发明的一个特征,在第一抛光步骤中,所述抛光溶液的硅石颗粒具有包括在第一值范围内的直径,然而,在第二抛光步骤中,所述抛光溶液的所述硅石颗粒具有至少部分小于所述第一值范围的值的第二值范围内所包括的直径。 [0015] According to one feature of the present invention, in a first polishing step, the polishing solution of silica particles having a range of values ​​included within a first diameter, however, in the second polishing step, the polishing solution said silica particles having a diameter of at least partially within a second range of values ​​smaller than the value of the first value range included. 在所述第一抛光步骤中,所述抛光溶液的所述硅石颗粒可具有包括在70nm至IOOnm之间的直径,而在所述第二抛光步骤中,所述抛光溶液的所述硅石颗粒具有包括在60nm至SOnm之间的直径。 The silica particles in the first polishing step, the polishing solution of the silica particles may have a diameter comprised between 70nm to IOOnm, and in the second polishing step, the polishing solution having including a diameter of between 60nm to SOnm.

[0016] 根据本发明的另一特征,在所述第一抛光步骤中,所述抛光织物具有位于2%至4%之间的第一压缩比,然而,在所述第二抛光步骤中,所述抛光织物具有包括在5%至9% 之间的第二压缩比。 [0016] According to another feature of the present invention, in the first polishing step, the polishing fabric has a first compression ratio located between 2-4%, however, in the second polishing step, comprises a fabric having a polishing said second compression ratio between 5% to 9%.

[0017] 根据本发明的又一特征,在所述第一抛光步骤中,所述抛光溶液具有包括在28% 至30%之间的第一硅石颗粒浓度,然而,在所述第二抛光步骤中,所述抛光溶液具有包括在8%至11%之间的第二硅石颗粒浓度。 [0017] According to a further feature of the present invention, in the first polishing step, the polishing solution comprising a first silica particles having a concentration of between 28-30%, however, in the second polishing step , the polishing solution comprises a second silica particles having a concentration of between 8% and 11%.

[0018] 当所述异质外延层为硅锗层时,具体应用上述参数(压缩率、浓度以及硅石颗粒直径)。 [0018] When the heteroepitaxial layer is a silicon germanium layer, the specific application of the above-described parameters (compression ratio, concentration, and silica particle diameter). 然而,本发明的抛光方法可应用到其它材料,例如应用到砷化镓(GaAs)或氮化镓(GaN)。 However, the polishing method of the present invention may be applied to other materials, for example, be applied to gallium arsenide (GaAs) or gallium nitride (GaN).

[0019] 因此在根据本发明的第一抛光步骤中通过比适用于抛光预定材料的织物的更硬的织物去除交叉阴影,而与通过中间的织物所获得的结果相比的中等微观粗糙度结果无关。 [0019] Thus in a first polishing step of the present invention than by a harder fabric useful in the fabric material removing polishing predetermined cross-hatched, and the middle microroughness compared to the results obtained by the intermediate results based on fabric nothing to do. 然后可在根据本发明的第二抛光步骤通过中间织物去除微观粗糙度和宏观粗糙度。 It can then be removed and the macro-roughness microroughness according to a second polishing step of the present invention by intermediate fabric.

[0020] 这样,无论是什么材料,根据本发明的方法都能够降低上述三种形式的粗糙度, 即,交叉影线、随机微观粗糙度和光雾度。 [0020] Thus, no matter what the material, the method according to the present invention are capable of reducing the above three types of roughness, i.e., cross-hatched, random microroughness and haze.

[0021 ] 根据本发明的一个特征,所述异质外延层为硅锗层。 [0021] According to one feature of the present invention, the heteroepitaxial layer is a silicon germanium layer.

[0022] 在所述第二化学机械抛光步骤之后,对于通过原子力显微镜在2X2 μ m2和IOXlOym2的扫描面积上进行的粗糙度测量,所述硅锗异质外延层具有小于0. Inm RMS的表面微观粗糙度。 [0022] after the second chemical mechanical polishing step for roughness measurement made on the microscope 2X2 μ m2 and the area scanned by an atomic force IOXlOym2, the SiGe heteroepitaxial layer has a surface of less than 0. Inm RMS microroughness.

[0023] 另外,在所述第二化学机械抛光步骤之后,所述硅锗异质外延层具有与小于0. 5ppm的表面光雾度等级对应的表面宏观粗糙度。 [0023] Further, after the second chemical mechanical polishing step, the SiGe heteroepitaxial layer has a macroscopic surface roughness and the haze level of the surface corresponding to less than 0. 5ppm.

[0024] 应注意,根据本发明的方法的第二步骤的抛光通常不用于处理硅锗,而仅用于处理硅,这是由于其具有大约0. 2nm/sec的非常低的抛光去除率。 [0024] It is noted that, according to a second polishing step of the method of the present invention typically are not used silicon germanium, silicon only for processing, since it has about 0. 2nm / sec polishing removal rate is very low.

[0025] 上述本发明的抛光方法可根据已公知的SmartCut™技术有利地用于制造sSOI结构,该制造包括:在属于供体基底的硅锗异质外延层上形成应变硅层;将至少一个原子种类植入在设计形成变弱层的供体基底中;使所述应变硅层的表面与接收基底的表面结合; 并且通过分裂以形成在所述供体基底中的变弱层的等级将与所述接收基底接触的层分离。 [0025] The polishing method of the present invention can be advantageously used in accordance with known techniques for producing the SmartCut ™ sSOI structure, the manufacturing comprising: forming a strained silicon layer on the SiGe heteroepitaxial layer belonging to the donor substrate; at least one implanting atomic species in the donor substrate designed to form weakened layer; the surface of the substrate receiving surface of the strained silicon layer are bonded; and by splitting level to form a weakened layer in the donor substrate will receiving substrate in contact with the layers were separated. 在该情况下,在形成所述应变硅层之前,根据上述抛光方法抛光所述硅锗异质外延层,这能够获得很好质量的sSOI晶片,因此能够降低次品晶片的数量。 In this case, before forming the strained Si layer, according to the polishing method of polishing the SiGe heteroepitaxial layer, it is possible to obtain good quality sSOI wafer, it is possible to reduce the number of defective wafers.

[0026] 根据本发明的一个特征,接收基底包括将其表面等级设计成与应变硅层结合的热氧化层。 [0026] According to one feature of the present invention, the receiving substrate comprises a thermal oxide layer and the surface level of the strained silicon layer is designed to bind. 该氧化层通常在结合之前通过进行复杂的TEOS类型的氧化步骤在供体基底上实现。 The oxide layer is typically performed by prior binding complex TEOS type oxidation step implemented on a donor substrate. 简单的热氧化实际上并不存在将应变硅层的厚度减小太多的缺点,该层的厚度已由临界松驰厚度限定。 Simple thermal oxidation does not really exist in the strained silicon layer is reduced in thickness too much disadvantage, the thickness of the layer defined by the critical relaxation thickness. 与此相反,该氧化层可在结合之前通过松散的硅接收基底的热氧化步骤在接收基底上实现。 In contrast, the oxide layer is a thermal oxidation step prior to the substrate can be received loosely bonded by a silicon implemented on the receiving substrate. 然而,这需要表面状态很好的应变硅和硅锗异质外延层。 However, this requires a good surface state of strained silicon and silicon germanium heteroepitaxial layer. 通过本发明的方法,实现硅锗异质外延层的表面质量,具体为涉及交叉影线和光雾度现象,使应变硅的结合能够直接在包括热氧化层的接收基底上进行。 By the method of the present invention, to achieve the surface quality of the heteroepitaxial SiGe layer, particularly involving cross-hatched and the haze phenomenon, so that the strained silicon can be bound directly on the receiving substrate comprises a thermal oxide layer.

[0027] 本发明还涉及包括位于硅基底上的至少一个松散的硅锗表面层的异质结构,对于通过原子力显微镜在2 X 2 μ m2和10 X 10 μ m2的扫描面积上进行的粗糙度测量,所述异质外延层具有小于0. Inm RMS的表面微观粗糙度。 [0027] The present invention further relates to a silicon substrate positioned on at least one loose SiGe heterostructure of the surface layer, at the scanning microscope an area of ​​2 X 2 μ m2 and 10 X 10 μ m2 for roughness by atomic force measuring the heteroepitaxial layer has less than 0. Inm RMS surface microroughness.

[0028] 所述异质外延层还具有与小于0. 5ppm的表面光雾度等级对应的表面微观粗糙度。 [0028] The heteroepitaxial layer has a further level of surface haze of less than 0. 5ppm corresponding surface microroughness.

[0029] 本发明还涉及设计成用作结晶种的供体基底,用于通过外延附生形成至少一个包括上述异质结构的应变硅层。 [0029] The present invention further relates to the design thereof to be used as the crystalline donor substrate, for forming strained silicon layer comprises at least one of the heterogeneous structure by epitaxy.

附图说明 BRIEF DESCRIPTION

[0030] 图1是可用于实施根据本发明一实施方式的抛光方法的抛光工具的示意图; [0030] FIG. 1 is a schematic view of a polishing tool for polishing method of an embodiment of the present embodiment of the invention;

[0031] 图2是包括通过异质外延生长在硅基底上形成的硅锗层的异质结构的示意剖面图; [0031] FIG. 2 is a schematic cross-sectional view of the silicon germanium heterostructure layers formed by heteroepitaxial growth on a silicon substrate;

[0032] 图3表示在单一步骤中进行的抛光之后以及在根据本发明的两个步骤中进行的抛光之后所获得的光雾度等级的箱形图; [0032] FIG. 3 shows after polishing performed in a single step and in haze levels after polishing box plot obtained for two steps according to the present invention;

[0033] 图4是表示在单一步骤中进行的抛光之后以及在根据本发明的两个步骤中进行的抛光之后所获得的微观粗糙度等级的柱状图; [0033] FIG 4 after polishing is carried out in a single step and microroughness level histogram after polishing steps carried out in accordance with the present invention, the two obtained;

[0034] 图5是表示在根据本发明的两个步骤中进行的抛光之后所获得的微观粗糙度等级的柱状图; [0034] FIG. 5 is a bar graph showing microroughness levels after polishing steps carried out in accordance with the present invention, the two obtained;

[0035] 图6是表示基于供体基底的SiGe层是在单一步骤中进行的抛光还是在根据本发明的两个步骤中进行的抛光而在sSOI晶片上获得的最终次品率的箱形图; [0035] FIG. 6 is a diagram showing the polishing of the SiGe layer of the donor substrate is carried out in a single step or in a box plot of the final defect rate The polishing performed in two steps according to the present invention obtained in the sSOI wafer ;

[0036] 图7是表示在单一步骤中进行的抛光以及在根据本发明的两个步骤中进行的抛光之后所获得的sSOI晶片的质量水平和状态的柱状图。 [0036] FIG. 7 is a bar graph showing the level of quality and the state of polishing performed in a single step and sSOI wafer after polishing is carried out in accordance with the present invention, the two steps are obtained.

具体实施方式 detailed description

[0037] 本发明的抛光方法包括两个连续但在不同操作条件下进行的化学机械抛光步骤(称为CMP)。 Polishing method [0037] according to the present invention comprises two chemical mechanical polishing step carried out continuously, but under different operating conditions (referred to as CMP). 具体地是,通过较“硬”(即具有低压缩比)的抛光织物并通过具有“高”浓度硅石颗粒的抛光溶液进行第一个抛光步骤,硅石颗粒具有包含在“高”值范围内的直径。 Specifically, by relatively "hard" (i.e., having a low compression ratio) of fabric and the first polishing step of polishing by a polishing solution having a "high" concentration of silica particles, silica particles having contained in the "high" range of values diameter.

[0038] 低压缩比意味着与适用于抛光预定材料的织物相比的低比率。 [0038] The low ratio means that the compression ratio is low compared with the predetermined fabric suitable polishing material. 在所有情形中,第一个压缩比与第二个压缩比相比较低,其被认为是“中间值”。 In all cases, the first and second lower compression ratio compared to the compression ratio, which is considered to be "intermediate values." 对于硅锗异质外延层,例如压缩比在2%至4%之间的织物被认为是硬的,而大约6%的压缩率被限定为中间值。 For SiGe heteroepitaxial layer, for example, a compression ratio of between 2-4% of the fabric is considered to be hard, and about 6% of compression rate is defined as an intermediate value.

[0039] 高浓度硅石颗粒意味着与适用于抛光预定材料的抛光溶液相比的高浓度。 [0039] The high concentration means a high concentration of silica particles in comparison with a polishing solution suitable for polishing a predetermined material. 在所有情形中,第一个浓度比第二个浓度高,因此其被认为是“低值”。 In all cases, the first concentration is higher than the second concentration, therefore it is considered "low." 对于硅锗异质外延层,例如小于12%的浓度被认为较低,而大于20%的浓度限定为高浓度。 For SiGe heteroepitaxial layer, for example, a concentration of less than 12% is considered to be low, while the concentration of more than 20% is defined as high concentrations.

[0040] 高值范围意味着比适用于抛光预定材料的抛光溶液高(例如多数值或平均值高) [0040] means that the high range is higher than a predetermined polishing polishing solution suitable material (e.g., a high multi-value or average value)

7的值。 A value of 7. 在所有情形中,虽然不排除部分范围叠加,但第一范围的值基本上高于第二范围的值,因此第二范围的值称为“低值”。 In all cases, although the scope of the superimposed portion does not exclude, but substantially higher than the first range of values ​​of the second range of values, the value of the second range is referred to as "low." 具体溶液的颗粒直径实际上并不完全相同,而且不同溶液的直径分布必定重叠。 Specific particle diameter was not substantially identical, and diameter distribution of the different solutions must overlap. 因此,对于硅锗异质外延层,例如60nm至SOnm之间的值范围被认为是低值范围,而70nm至IOOnm之间的值范围被认为是高值范围。 Thus, for a SiGe heteroepitaxial layer, for example, range between 60nm to SOnm range is considered to be low, and the range between 70nm to IOOnm are considered high values.

[0041] 图1示出了可用于实施根据本发明一实施方式的抛光方法的抛光工具10。 [0041] FIG 1 illustrates a polishing tool may be used to implement the polishing method according to one embodiment of the present invention 10. 工具10 一方面包括抛光头11,具有待抛光的表面粗糙度的异质结构12插在抛光头11中,另一方面工具10包括由抛光织物14覆盖的板13。 The polishing tool 10 includes a head 11 on the one hand, to be polished having a surface roughness of the heterostructure 12 is inserted in a polishing head 11, on the other hand a polishing tool 10 includes a fabric cover 14 of plate 13. 分别旋转驱动抛光头11和板13,以抛光异质结构12的与抛光织物14接触的表面121a。 Driving the polishing head 11 are rotated and the plate 13, to polish heterostructure contact with the polishing surface 12. The fabric 14 121a. 当进行抛光时,另外向头11施加抛光压力Fe和由箭头16表示的平移运动。 When polishing, the polishing pressure applied to Fe and further translational movement represented by arrow 16 to the head 11. 当进行抛光时,由至少一种胶状溶液(例如包含硅石颗粒的NH4OH溶液)形成的研磨抛光溶液另外经由管15注入到研磨头11中,并通过管15分配在抛光织物14上。 When polishing, polishing solution is formed from at least one colloidal solution (e.g., NH4OH solution containing silica particles) is injected via a further pipe 15 to the polishing head 11 and dispensing tube 15 through the fabric 14 on the polishing. 因此通过浸有抛光溶液的抛光织物14对异质结构12的表面121a进行抛光。 Thus polished by the polishing solution is impregnated with a polishing surface of the fabric 14 heterogeneities of 121a 12.

[0042] 异质结构12由形成在由不同材料制成的基底120上的至少一个异质外延层121 形成,异质外延层松散并在其表面处存在需要抛光的应变晶格或交叉影线。 [0042] 12 heterojunction structure formed of at least one heteroepitaxial layer on a substrate made of a different material 120 121, the heteroepitaxial layer and the presence of loose its surface to be polished, or cross-hatched lattice strain . 如图2所示,异质结构12可由松散的Sia_x)Ge(x)缓冲层121形成在硅基底120上,Si(1_x)Ge(x)缓冲层121 包括Si(1_x)Ge(x)渐变层122 (在层的厚度中χ例如从0至0. 2变动)和通过异质外延形成的Si(1_x)Ge(x)均勻层123 (例如χ = 0. 2)。 2, the heterostructure 12 may be loosely Sia_x) Ge (x) a buffer layer 121 is formed on the silicon substrate 120, Si (1_x) Ge (x) a buffer layer 121 comprises Si (1_x) Ge (x) graded layer 122 (χ e.g. from 0 to 0.2 layer thickness variation) and Si (1_x) formed by heteroepitaxial Ge (x) a uniform layer 123 (e.g., χ = 0. 2). 当释放应变时,硅基底与形成在其上的SiGe层之间的晶格失配导致在SiGe层123的与异质结构12的表面121a对应的表面处形成呈交叉影线的松散粗糙度124。 When the strain is released, a silicon substrate with a lattice which is formed between the SiGe layer on the mismatch between the loose in a cross-hatched surface roughness 124 is formed on the surface 12 of the heterostructure SiGe layer 121a corresponding to 123 . 在根据本发明前述的抛光方法去除了交叉影线之后,异质结构12可用于形成应变硅层sSi,该应变硅层sSi然后可转移到例如硅基底的接收基底上,例如利用已公知的SmartCut™技术转移。 In the SmartCut according to the present invention, the polishing method after removing the cross-hatching, the heterostructure 12 may be used to form a strained Si layer sSi, the strained silicon layer sSi may then be transferred to, for example, a receiver substrate of the silicon substrate, for example, using a known per se ™ technology transfer. 在sSi层转移后,异质结构可在抛光异质结构的SiGe 层的断裂表面之后再次根据本发明的方法重复用于形成新的sSi层。 After sSi transfer layer heterostructure according to the invention may again be repeated for the new sSi fracture surface layer is formed after polishing the SiGe layer heterostructure.

[0043] 在第一抛光步骤中,异质结构12的表面经受利用称为“硬”的抛光织物(即压缩比包括在2%至4%之间,优选为2%的织物)进行的化学机构抛光。 [0043] In the first polishing step, the surface of the heterostructure 12 is subjected to polishing by using a fabric called "hard" (i.e., the compression ratio is comprised between 2-4%, preferably 2% of the fabric) for chemical polishing institutions.

[0044] 而且利用称为“侵蚀性的”(即胶状溶液)的抛光溶液进行第一化学机械抛光步骤,该抛光溶液例如为包含至少20%,优选为28%至30%之间的直径在70nm至IOOnm之间的硅石颗粒的NH4OH溶液。 [0044] and the use as "aggressive" (i.e. colloidal solution) to a solution of a first chemical mechanical polishing step of polishing, the polishing solution containing, for example, a diameter of at least 20%, preferably between 28-30% of NH4OH solution silica particles is between 70nm to IOOnm.

[0045] 第一抛光步骤的去除速率优选为3nm/SeC,因此第一步骤的周期大约为2分钟。 [0045] The removal rate of the first polishing step is preferably 3nm / SeC, so the first step of the cycle is approximately 2 minutes.

[0046] 第一化学机械抛光步骤去除了交叉影线,并将表面微观粗糙度降低到0. 2nm RMS, 该粗糙度值为通过原子力显微镜(AFM)对于10 X IOym2所测量的粗糙度值。 [0046] The first chemical mechanical polishing step removes cross-hatching, and to reduce the surface microroughness 0. 2nm RMS, value of the roughness by atomic force microscopy (AFM) 10 X IOym2 roughness values ​​measured for.

[0047] 然而,在该第一抛光步骤之后,异质结构12在其表面121a处具有与所测量的表面光雾度等级对应的大约20ppm的宏观粗糙度等级(例如在SPl测量设备中照亮晶片或异质结构时,来自由表面缺陷散播的光的低空间频率信号)。 [0047] However, after the first polishing step, the heterostructure 12 with macroscopic surface roughness and the haze level measured level corresponds approximately 20ppm (e.g., illuminated wafer SPl measuring device 121a at the surface thereof or heterostructures, the low defect free surface space to spread the frequency of the light signal).

[0048] 根据本发明,进行第二化学机械抛光步骤,以降低在异质结构的表面处存在的宏观粗糙度等级。 [0048] According to the present invention, the second chemical mechanical polishing step, to reduce the roughness of the macro-level present at the surface of the heterostructure.

[0049] 利用称作“中间值”的抛光织物(即,可压缩比在5%至9%之间,优选为6%的织物)来进行异质结构12的表面121a的第二抛光步骤。 [0049] The use referred to as "the middle value" polishing fabric (i.e., between the compressible than 5-9%, preferably 6% fabric) to the second surface 121a of the polishing step 12 of the heterostructure. 在该第二步骤中,抛光织物优选对应于用于在构成SOI (绝缘体上硅)结构中的硅研磨抛光的织物。 In the second step, the polishing fabric is preferably used in a configuration corresponding to the SOI (silicon on insulator) structure of abrasive polishing silicon fabric. 该抛光织物的已知的实施例为由Rohm与Haas供应的SPM3100织物。 The known embodiment of a polishing fabric by Rohm and Haas supplied SPM3100 fabric.

8[0050] 第二化学机械抛光步骤利用比在第一步骤中使用的抛光溶液(即,胶状溶液)“更软”的抛光溶液进行,例如包含的硅石颗粒的百分比大约小于12%、硅石颗粒的直径在60nm 至80nm之间的NH4OH溶液。 8 [0050] The second chemical mechanical polishing step using the "softer" than a polishing solution of the polishing solution used in the first step (i.e., a colloidal solution), for example, the percentage of silica particles comprises less than about 12% silica NH4OH diameter of the particles in a solution of between 60nm to 80nm. 硅石颗粒的百分比优选在8 %至11 %之间。 Percentage of silica particles is preferably between 8-11%.

[0051] 第二抛光步骤的去除速率优选为0. 2nm/sec,因此第二步骤的周期大约为3分钟。 [0051] The removal rate of the second polishing step is preferably 0. 2nm / sec, so the cycle of the second step is about 3 minutes.

[0052] 该第二化学机械抛光步骤能够使表面微观粗糙度减小到小于0. Inm [0052] The second chemical mechanical polishing step of the surface microroughness can be reduced to less than 0. Inm

[0053] RMS的值,该粗糙度值为通过原子力显微镜(AFM)对于2X2 μ m2的扫描面积所测量的粗糙度值。 [0053] The RMS value of the roughness value roughness value for the scan area 2X2 μ m2 as measured by atomic force microscopy (AFM) by. 该第二步骤首先能够在异质结构12的表面121a处获得与通过SPl测量装置所测量的表面光雾度等级对应的大约0. 5ppm的表面宏观粗糙度等级。 The second step is first possible to obtain macroscopic surface roughness of the surface haze level corresponding to the level measured by the measuring device SPl about 0. 5ppm at the surface of the heterostructure 12 of 121a. 与仅通过第一抛光步骤所获得的光雾度等级相比,在上述两个抛光步骤之后所获得的光雾度等级提高40 倍。 Compared with haze levels obtained by only a first polishing step to improve the haze after the above two polishing steps 40 times the level obtained.

[0054] 图3表示在如前所述形成在硅基底上的异质结构12的SiGe层抛光之后所获得的光雾度等级,分别在对应于前述第一抛光步骤的单一步骤中或在对应于前述第一和第二步骤中进行化学机械抛光。 [0054] FIG. 3 shows a single step, the haze level after heterostructure as described above is formed on the silicon substrate 12 is polished SiGe layer obtained, respectively corresponding to the first polishing step or the corresponding chemical mechanical polishing in the first and second steps. 图3中所示的值是在将检测阈值调整为0. 13微米(即可检测颗粒的最小值)的情况下,用SPl测量设备从KLA-Tencor所测得的值。 The values ​​shown in FIG. 3 is a detection threshold is adjusted to 0.13 micron (minimum value of the particles can be detected), the value from KLA-Tencor SPl measured by the measuring device.

[0055] 该图清楚地示出当在根据本发明的两个步骤中进行化学机械抛光时在光雾度等级上所获得的增益。 [0055] The figure clearly shows the gain when the chemical mechanical polishing according to the present invention, the two steps on the obtained level of haze. 因此,在CMP之后光雾度等级因第二抛光步骤而从19ppm的平均值下降到0. 3Ippm的平均值。 Accordingly, the haze level after the CMP polishing step is lowered by the second average value from the average value of 19ppm of 0. 3Ippm.

[0056] 图4表示在单一步骤中以及在根据本发明的两个步骤中进行的CMP之后在SiGe 异质外延层上获得的表面微观粗糙度RMS值。 [0056] FIG. 4 shows the RMS value of surface microroughness and obtained in a single step in the heteroepitaxial layer of SiGe after the CMP conducted in accordance with the present invention in two steps. 所呈现的表面微观粗糙度值是通过原子力显微镜(AFM)对于2 X 2 μ m2禾P 40 X 40 μ m2所测量的值。 Surface microroughness values ​​presented are the values ​​for the 2 X 2 μ m2 Wo P 40 X 40 μ m2 as measured by atomic force microscopy (AFM).

[0057] 图4中所示的值表示,在根据本发明的两个步骤中进行的CMP所获得的表面微观粗糙度对于2X2 μ m2的扫描面积降低2倍,并且对于40X40 μ m2的扫描面积降低1. 5倍。 Values ​​shown in [0057] FIG. 4 shows, the CMP surface microroughness in two steps according to the present invention obtained in the scanning area 2X2 μ m2 of 2-fold decrease, and for scanning the area of ​​40X40 μ m2 decreased 1.5 fold. 因此两个步骤中的CMP之后的微观粗糙度对于2 X 2 μ m2的扫描面积小于0. Inm RMS,这确保例如用于重新进行应变硅外延附生或分子结合的非常好的表面状态。 Thus microroughness two steps after CMP for scanning area 2 X 2 μ m2 is less than 0. Inm RMS, for example, which ensures a very good surface state again strained silicon epitaxy or molecular binding.

[0058] 图5示出除了已在图4中呈现的对于2X2 μ m2的扫描面积以及对于40X40 μ m2 的扫描面积的表面微观粗糙度值之外,在相同SiGe层上利用原子力显微镜(AFM)对于40X40 μ m2的扫描面积所测量的表面微观粗糙度值。 [0058] FIG. 5 shows a scanning area except for 2X2 μ m2 have been presented in FIGS. 4 and surface microroughness values ​​of the scanning area of ​​40X40 μ m2, using an atomic force microscope (AFM) on the same SiGe layer 40X40 μ m2 to the scanning area of ​​the surface microroughness values ​​measured. 该图表示对于2Χ2μπι2的扫描面积所获得的表面微观粗糙度与IOXlOym2的较大扫描面积的粗糙度相似。 The figure shows the scanning area of ​​the surface of the obtained 2Χ2μπι2 microroughness similar large scanning area IOXlOym2 roughness.

[0059] 一个或多个SiGe层(其结果表现在图3至图5中)通过Mirra抛光设备从应用的材料以抛光头的下述旋转速度Vt和板的下述旋转速度Vp进行抛光: [0059] One or more SiGe layer (a result is shown in Figure 3 to 5) at a rotational speed following the rotational speed Vt following the polishing head and the plate material from the polishing Vp applied by Mirra polishing apparatus:

[0060] 第一抛光步骤:Vt包括在75rpm至95rpm之间,优选为87rpm,施加到抛光头的压力包括在5psi至9psi之间,优选为7psi ;Vp包括在85rpm至IOOrpm之间,优选为93rpm ; [0060] The first polishing step: Vt comprised between 75rpm to 95rpm, preferably 87rpm, is applied to the polishing head to a pressure comprised between 5psi 9psi, preferably of 7psi; Vp comprised between 85rpm to IOOrpm, preferably 93rpm;

[0061] 第二抛光步骤:Vt包括在30rpm至45rpm之间,优选为36rpm,施加到抛光头的压力包括在3psi至6psi之间,优选为5psi ;Vp包括在25rpm至40rpm之间,优选为30rpm ; [0061] The second polishing step: Vt comprised between 30rpm to 45rpm, preferably 36rpm, is applied to the polishing head to a pressure comprised between 3psi 6psi, preferably 5psi; Vp comprised between 25rpm to 40rpm, preferably 30rpm;

[0062] 图6表示在由异质结构制成的sSOI (应变硅绝缘体)晶片上所观测到的缺陷等级,该异质结构制成的SiGe层(其作为应变硅层的生长层)经受与前述第一抛光步骤对应的单一步骤或与上述第一和第二抛光步骤对应的两个步骤中进行的CMP。 [0062] FIG. 6 shows the hetero structure made of a sSOI (strained Silicon On Insulator) wafer on the observed defect level, SiGe layer (strained silicon layer as the growth layer) made of the hetero structure is subjected and the first CMP polishing step performed by a single step or in two steps corresponding to the above-described first and second polishing step corresponding.

[0063] 图6中所示的值通过SPl测量设备从KLA-Tencor在将检测阈值调整到0. 4至0. 5 微米(即可检测颗粒的最小尺寸)的情况下进行测量。 Values ​​measured in the case shown in [0063] FIG 6 when the detection threshold is adjusted to from KLA-Tencor SPl measuring apparatus by 0.4 to 0.5 micrometers (the smallest size of the particles can be detected) is. [0064] 图6能够基于是在单一步骤中还是在两个步骤中进行CMP,将倾斜测量(与图6中的所有[DC0](所有缺陷复合倾斜)对应)的整个缺陷(由y轴上所示的缺陷数表示)与垂直测量(与图6中的ALL[DCN](所有缺陷复合正交)对应)的整个缺陷进行对比。 [0064] FIG. 6 is or can be based on the CMP in two steps in a single step, the inclination measurement (in Fig. 6 all [DC0] (all defects composite inclined)) of the entire defect (by the y-axis indicates the number of defects as shown) compared to the vertical measurement (ALL in Fig. 6 [the DCN] (all composite quadrature defect)) of the entire defect. 可观察到,在前述条件下的两个步骤中进行的抛光与在单一步骤中进行的抛光相比(与“中间所有[DC0],,对比)能够使在最终sSOI产品上的缺陷改进20倍。 Can be observed, the polishing carried out in two steps under the conditions of the polishing performed in a single step, as compared to (and "among all [DC0] ,, comparative) enables the defects in the final sSOI product improved 20 times .

[0065] 图7表示归结于sSOI晶片是基于形成异质结构的SiGe层是经受与前述第一抛光步骤对应的单一步骤还是与前述第一和第二步骤对应的两个步骤中的CMP的状态,以SOI 晶片形成异质结构。 [0065] FIG. 7 shows due to the sSOI wafer is formed on the SiGe layer of the heterostructure is a state in two steps with a single step is subjected to the first polishing step or to the corresponding first and second step corresponding to the CMP , SOI wafer to form a heterojunction structure. 在图7中,“最佳”状态对应于晶片的最优等级,根据订货规格,“检测” 状态对应于不太好的质量等级(晶片与用于“最初”等级的晶片相比可交付使用于较小限制的最终规格),并且“降级”状态对应于缺陷过多的废弃晶片。 In FIG. 7, the "best" state corresponds to the optimum level of the wafer, in accordance with the order specification, "detection" state corresponds to a quality level is not good (the wafer used for "initial" wafer level compared deliverable in less restrictive final gauge), and the "degraded" state corresponds to excessive waste wafer defects.

[0066] 在图7中,可清楚地看到在最终晶片成品率上的第二抛光步骤的影响。 [0066] In FIG 7, the second impact can be clearly seen in the final polishing step of the wafer yield. 在单一步骤抛光的情况下,最终成品率实际上为100%的降级晶片,而在两个步骤抛光的情况下,成品率为: In the case of a single polishing step, the final yield of virtually 100% of the wafer is degraded, whereas in the case of two polishing steps, the yield is:

[0067] 18% 的“最佳”, [0067] 18% of the "best",

[0068] 52%的“检测”,以及 [0068] 52% of the "detection", and

[0069] 30%的“降级”,即,是单一步骤中的抛光的1/3。 [0069] 30% of the "degraded", i.e., a single step polishing 1/3.

[0070] 上述用于抛光SiGe异质外延层的抛光方法还能够实施用于抛光砷化镓(GaAs)和氮化镓(GaN)的异质外延层。 [0070] The polishing method for polishing a SiGe heteroepitaxial layer embodiment can also be used to polish gallium arsenide (GaAs) and gallium nitride (GaN) of the heteroepitaxial layer. 针对抛光SiGe层所示的参数(在第一和第二步骤中织物的压缩性、第一和第二步骤中的硅石颗粒浓度/颗粒直径等)也可应用于抛光GaAs或GaN的异质外延层。 For polishing parameters shown SiGe layer (first and second compression step of the fabric, the concentration of silica particles in the first and second steps / particle diameter, etc.) may be applied to polishing of GaAs or GaN heteroepitaxial Floor.

[0071] 因此,通过在前述限定的条件下实施两个抛光步骤,本发明的抛光方法能够使交叉影线、宏观粗糙度(光雾度测量)和表面微观粗糙度(通过原子力显微镜(AMF)测量) 显著减小。 [0071] Thus, by performing two polishing step under the conditions defined in the foregoing, the polishing method of the present invention is capable of cross-hatching, the macroscopic roughness (haze measurement), and surface micro-roughness (by atomic force microscopy (AMF) measurement) significantly reduced. 晶片的表面状态的这种改进具体地确保良好的分子结合以及/或者重新进行应变硅的外延附生。 Specifically, this improved surface state of the wafer to ensure good binding molecules and / or re-strained silicon epitaxy. 还能够在用于制造sSOI晶片的方法结束时得到更好质量的晶片,这是由于产量上的次品晶片的数量减小为1/3,这可显著地提高质量很好的晶片的数量。 Better quality can also be obtained at the end of wafer process for producing sSOI wafer, which is due to the number of defects on the wafer is reduced to 1/3 of the yield, which can significantly increase the number of good quality wafer.

Claims (16)

  1. 一种用于抛光异质结构(12)的方法,所述异质结构包括至少一个位于基底(120)上的松散表面异质外延层(121),该基底由与所述异质外延层不同的材料制成,该方法包括通过具有第一压缩比的抛光织物和具有第一硅石颗粒浓度的抛光溶液对所述异质外延层(121)的表面进行的第一化学机械抛光步骤,其特征在于,在所述第一化学机械抛光步骤之后进行所述异质外延层(121)的表面的第二化学机械抛光步骤,通过具有比所述第一压缩比高的第二压缩比的抛光织物和具有比所述第一浓度低的第二硅石颗粒浓度的抛光溶液进行所述第二步骤;并且所述异质外延层(121)为硅锗层。 A method of polishing heterostructure (12), said heterostructure comprises a loose surface heteroepitaxial layer (121) located in at least a substrate (120) on the substrate by the heteroepitaxial layer and the different made of a material, the method comprising a first step of chemical mechanical polishing of the surface of the heteroepitaxial layer (121) by a first compression ratio of a polishing fabric having a first and a silica particle concentration of the polishing solution, characterized in in that the second chemical mechanical polishing step the surface of heteroepitaxial layer (121) after the first chemical mechanical polishing step, by a second compression ratio than the first compression ratio of a polishing fabric and a second polishing solution having a low concentration of silica particles than the first concentration of the second step is performed; and the heteroepitaxial layer (121) is a silicon germanium layer.
  2. 2.根据权利要求1所述的方法,其特征在于,在所述第一抛光步骤中,所述抛光溶液的所述硅石颗粒具有包括在第一值范围内的直径,在所述第二抛光步骤中,所述抛光溶液的所述硅石颗粒具有包括在至少部分小于所述第一值范围的第二值范围内的直径。 2. The method according to claim 1, wherein, in the first polishing step, the polishing solution of the silica particles having a diameter comprised within a first range of values, the second polishing step, the polishing solution comprising the silica particles having a diameter of at least part of the first value is less than the range of the second value range.
  3. 3.根据权利要求1或2所述的方法,其特征在于,在所述第一抛光步骤中,所述抛光织物具有包括在2%至4%之间的第一压缩比。 3. The method of claim 1 or claim 2, wherein, in the first polishing step, the polishing comprising a first web having a compression ratio of between 2% to 4%.
  4. 4.根据权利要求1或2所述的方法,其特征在于,在所述第二抛光步骤中,所述抛光织物具有包括在5%至9%之间的第二压缩比。 4. The method of claim 1 or claim 2, wherein, in the second polishing step, the polishing comprising a second fabric having a compression ratio of between 5% to 9%.
  5. 5.根据权利要求1或2所述的方法,其特征在于,在所述第一抛光步骤中,所述抛光溶液具有包括在28%至30%之间的第一硅石颗粒浓度。 5. The method of claim 1 or 2, wherein, in the first polishing step, the polishing solution comprising a first silica particles having a concentration of between 28-30% of.
  6. 6.根据权利要求1或2所述的方法,其特征在于,在所述第二抛光步骤中,所述抛光溶液具有包括在8%至11%之间的第二硅石颗粒浓度。 6. A method according to claim 1 or 2, wherein, in the second polishing step, the polishing solution comprises a second silica particles having a concentration of between 8% and 11%.
  7. 7.根据权利要求2所述的方法,其特征在于,在所述第一抛光步骤中,所述抛光溶液的所述硅石颗粒具有包括在70nm至IOOnm之间的直径。 7. The method according to claim 2, wherein, in the first polishing step, the polishing solution of the silica particles having a diameter comprised between 70nm to IOOnm of.
  8. 8.根据权利要求2所述的方法,其特征在于,在所述第二抛光步骤中,所述抛光溶液的所述硅石颗粒具有包括在60nm至SOnm之间的直径。 8. The method according to claim 2, wherein, in the second polishing step, the polishing solution of the silica particles having a diameter comprised between 60nm to SOnm of.
  9. 9.根据权利要求1所述的方法,其特征在于,在所述第二化学机械抛光步骤之后,所述硅锗异质外延层通过原子力显微镜进行的粗糙度测量在2X2 μ m2和IOX 10 μ m2的扫描面积上具有小于0. Inm RMS的表面微观粗糙度。 9. The method according to claim 1, wherein, after the second chemical mechanical polishing step, the SiGe heteroepitaxial layer roughness measurement by AFM in the 10 μ 2X2 μ m2 and IOX 0. Inm RMS surface of the scanning area is less than m2 microroughness.
  10. 10.根据权利要求1或9所述的方法,其特征在于,在所述第二化学机械抛光步骤之后, 所述硅锗异质外延层具有与小于0. 5ppm的表面光雾度等级对应的表面宏观粗糙度。 10. The method of claim 1 or claim 9, wherein, after the second chemical mechanical polishing step, the SiGe heteroepitaxial layer having a haze level of a surface corresponding to the surface of less than 0. 5ppm macro-roughness.
  11. 11.根据权利要求1所述的方法,其特征在于,在包括抛光头(11)和板(13)的抛光工具(10)中进行所述第一和第二化学机械抛光步骤,所述异质结构(12)布置在所述抛光头中,所述板由与所述待抛光的异质外延层表面接触的抛光织物(14)覆盖,由所述抛光头分配所述抛光溶液。 11. The method according to claim 1, characterized in that, for the first and second chemical mechanical polishing step comprises polishing head (11) and the plate (13) a polishing tool (10), said iso chromatin structure (12) disposed in said polishing head, the polishing plate covered with a fabric (14) in contact with the surface of the heteroepitaxial layer to be polished by said polishing head dispensing the polishing solution.
  12. 12. —种sSOI结构的制造方法,该方法包括:在属于供体基底的硅锗异质外延层上形成应变硅层;将至少一个原子种类植入在设计形成变弱层的供体基底中;使所述供体基底的表面与接收基底的表面结合;以及通过分裂以形成在所述供体基底中的变弱层的等级将与所述接收基底接触的层分离,其特征在于,在形成所述应变硅层之前,通过根据权利要求1至12中任一项所述的抛光方法抛光所述硅锗异质外延层。 12. - sSOI structure manufacturing method, the method comprising: forming a strained silicon layer on the SiGe heteroepitaxial layer belonging to the donor substrate; at least one atomic species implanted in the donor substrate design weakened layer is formed ; body surface of the substrate and the surface of the receiver substrate for binding; and by splitting to form a weakened layer was separated level in the donor layer of the substrate in contact with the receiving substrate, characterized in that before forming the strained silicon layer, by a polishing method according to any one of 12 claims polishing the SiGe heteroepitaxial layer.
  13. 13.根据权利要求12所述的sSOI结构的制造方法,其特征在于,所述接收基底包括位于结合表面上的热氧化层。 The manufacturing method according to sSOI structure according to claim, wherein said receiving substrate comprises a thermal oxide layer on the surface of the binding.
  14. 14. 一种异质结构(12),该异质结构包括位于硅基底(120)上的至少一个松散的硅锗表面异质外延层(121),其特征在于,通过根据权利要求1至9中任一项所述的抛光方法抛光所述硅锗表面异质外延层(121),并且对于通过原子力显微镜在2 X 2 μ m2和10 X 10 μ m2的扫描面积上进行的粗糙度测量,所述异质外延层(121)具有小于0. Inm RMS的表面微观粗糙度。 14. A heterostructure (12), the heterostructure comprises a silicon substrate (120) at least one surface of the loose SiGe heteroepitaxial layer (121), characterized by the claims 1 to 9 the polishing method according to any one of the polished surface of the SiGe heteroepitaxial layer (121), and the roughness measurements in the scanning microscope an area of ​​2 X 2 μ m2 and 10 X 10 μ m2 for by atomic force, the heteroepitaxial layer (121) of less than 0. Inm RMS surface microroughness.
  15. 15.根据权利要求14所述的异质结构,其特征在于,所述异质外延层(121)具有与小于0. 5ppm的表面光雾度等级对应的表面宏观粗糙度。 15. A heterostructure according to claim 14, wherein said heteroepitaxial layer (121) having a macroscopic surface roughness and the haze level of the surface corresponding to less than 0. 5ppm.
  16. 16. 一种设计成用作结晶种的供体基底,所述结晶种用于通过外延附生形成至少一个应变硅层,其特征在于,其包括根据权利要求14或15所述的异质结构(12)。 16. A crystalline kind designed for use as the donor substrate, at least one kind of the crystalline strained silicon layer is formed by epitaxy, characterized in that it comprises a heterostructure according to claim 14 or 15 (12).
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