CN101572545B - Phase-locked loop circuit and control method thereof - Google Patents

Phase-locked loop circuit and control method thereof Download PDF

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Publication number
CN101572545B
CN101572545B CN200910052964.XA CN200910052964A CN101572545B CN 101572545 B CN101572545 B CN 101572545B CN 200910052964 A CN200910052964 A CN 200910052964A CN 101572545 B CN101572545 B CN 101572545B
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phase
resistance
circuit
locked loop
output
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CN200910052964.XA
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CN101572545A (en
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任铮
胡少坚
周伟
唐逸
王勇
曹永峰
叶红波
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上海集成电路研发中心有限公司
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Abstract

The invention relates to a phase-locked loop circuit and a control method thereof. The phase-locked loop circuit comprises a phase frequency detector, a charge pump, a current lens circuit, a loop filter, a loop filter resistance adjusting circuit, a voltage controlled oscillator, and a frequency divider which are connected with each other in turn, wherein the input end of the current lens circuitreceives control current outputted by the charge pump and adjusts the size of the control current; and the loop filter resistance adjusting circuit adjusts a resistance parameter of the loop filter a ccording to digital signals divided by the frequency divider. The phase-locked loop circuit adjusts the loop bandwidth and the damping coefficient of the phase-locked loop circuit through the current lens circuit and the loop filter resistance adjusting circuit, so that the stability of the phase-locked loop circuit is improved.

Description

Phase-locked loop circuit and control method thereof

Technical field

The present invention relates to a kind of phase-locked loop circuit and control method thereof.

Background technology

Since phase-locked concept is suggested, at electronics and communication field, be widely used.Phase-locked loop (Phase Lock Loop, PLL) circuit is widely used in clock forming circuit and Electronic Circuit of Communication.Although the development of Phase Lock Technique experience decades has obtained very ripe application, complicated and diversified along with electronic product, has proposed one and another challenge to the application of phase-locked loop.Wherein, a major challenge of Design of PLL is exactly: how to allow phase-locked loop be applicable to different peripheral circuits.Conventionally, phase-locked loop adopts the outer low-frequency crystal oscillator of sheet as input clock, by regulating the divider ratio of feedback divider to reach the object that regulates phase-lock-ring output frequency.Like this, by feedback divider is carried out to programming Control, just realize control output frequency able to programme, thereby reached the range of application that expands this phase-locked loop.

Said method is proved to be the reference frequency output that can effectively expand phase-locked loop in many application, but such way can cause the problem that some VCO effective frequency ranges change.Wherein, topmost problem is, because the change of output frequency and feedback factor can cause the variation of the whole loop parameter of phase-locked loop, and the variation of loop parameter can affect the loop shake inhibition of (jitter) and the stability of whole loop to phase-locked loop.The loop parameter of phase-locked loop mainly comprises following three: loop bandwidth, and the corresponding rate of this parametric description phase-locked loop, conventionally value is reference frequency 1/20; Damping coefficient, the stability of the loop of description phase-locked loop, value is about one conventionally; Third level limit, can reduce the dither cycle of output frequency, and value should be about 1/2 of reference frequency.These parameters depend on some parameters of phase-locked loop circuit, such as charge pump current, and loop filter value etc.

Refer to Fig. 1, Fig. 1 is a kind of block diagram of phase-locked loop circuit of prior art.This phase-locked loop circuit 10 comprises phase frequency detector (phase detector) 11, charge pump (charge pump) 12, loop filter (loop filter) 13, voltage controlled oscillator (V oltage Controlled Oscillator, VCO) 14, the frequency divider 15 connecting successively.This phase frequency detector 11, this charge pump 12, this loop filter 13, voltage controlled oscillator 14, frequency divider 15 are connected to form a loop.

The transfer function of this phase-locked loop circuit 10 is:

H ( s ) = I CH K VCO 2 π C 1 ( RC 1 s + 1 ) s 2 + I CH K VCO 2 πN Rs + I CH 2 π C 1 · K VCO N - - - ( 1 )

Kvco represents the gain of 14 pairs of input voltages of voltage controlled oscillator, I cHrepresent that this current pump 12 is input to the electric current of this loop filter 13, above-mentioned transfer function can be write as the expression formula of the damping coefficient in control theory, so just obtains the loop parameter of whole the two poles of the earth phase-locked loop;

H ( s ) = ω n 2 s 2 + 2 ζ ω n s + ω n 2 - - - ( 2 )

Wherein, loop bandwidth:

ω n = I CH 2 π C 1 · K VCO N - - - ( 3 )

Damping coefficient:

ζ = R 2 I CH C 1 2 π · K VCO N - - - ( 4 )

From formula (3) (4), in order to adjust the output frequency of this voltage controlled oscillator 14, after having changed the divider ratio N of this frequency divider 15, bandwidth in the loop parameter of this phase-locked loop circuit 10 and damping coefficient all will change, thereby affect the stability of whole phase-locked loop circuit 10.

Summary of the invention

In order to solve phase-locked loop circuit of the prior art, owing to changing the divider ratio of frequency divider, affect the technical problem of the stability of whole phase-locked loop circuit, be necessary to provide a kind of phase-locked loop circuit that can increase stability.

The present invention also provides a kind of control method of phase-locked loop circuit.

A phase-locked loop circuit, for generation of an output signal, comprises frequency divider, and for receiving this output signal, and the frequency of adjusting this output signal is to provide feedback signal; Phase frequency detector, receives reference signal and this feedback signal, and output is used to indicate the phase signal of this reference signal and this feedback signal phase difference; For receiving this phase signal output, control the charge pump of electric current; For generation of the loop filter of controlling voltage; For adjusting the voltage controlled oscillator of the output signal frequency of this phase-locked loop circuit; For receiving and adjust the current mirroring circuit of the control electric current of this charge pump output, this loop filter filters control electric current after this adjustment to produce this control voltage; For according to the divider ratio signal of this frequency divider, adjust the loop filtering resistance Circuit tuning of the resistance parameter of this loop filter, this control voltage is input to this voltage controlled oscillator via this loop filtering resistance Circuit tuning.

Wherein, this current mirroring circuit is inverse ratio programmable current mirror circuit.This current mirroring circuit comprises the first transistor and at least one serial transistor unit, this serial transistor unit receives the control electric current of this charge pump output, and control the control electric current after this first transistor output is adjusted, the conducting number of this serial transistor unit is controlled electric current with the amplification of this first transistor output and is inversely proportional to.

Each serial transistor unit comprises transistor seconds and the 3rd transistor, the source ground of this transistor seconds, the grid of this transistor seconds connects the grid of this first transistor, the drain electrode of this transistor seconds connects the 3rd transistorized source electrode, the 3rd transistorized grid receives controls bias voltage, the 3rd transistorized drain electrode connects the grid of this first transistor and receives the control electric current of this charge pump output, the source ground of this first transistor, the control electric current after this adjustment of drain electrode output.This control bias voltage is used for controlling the 3rd transistorized conducting and cut-off, and then adjusts the control electric current of this current mirroring circuit input and the proportionate relationship between the control electric current of output.

This loop filtering resistance Circuit tuning comprises for receiving the input of the control voltage of this loop filter output, for exporting the output that controls voltage to this voltage controlled oscillator, the first resistance, the second resistance, the 4th transistor and the 5th transistor, this is first years old, the second resistance is connected in parallel between this input and output, the highest order of the divider ratio signal of this frequency divider and a time high position are input to respectively the 4th, the 5th transistorized grid, by controlling the 4th, the 5th transistorized conducting and cut-off adjust this first, the resistance of the second resistance parallel circuits.

Four, the 5th transistorized drain electrode connects one end of this second resistance, and the other end of this second resistance is connected this input with one end of this first resistance, and the other end of the 4th, the 5th transistorized source electrode and this first resistance is connected this output.

This loop filtering resistance Circuit tuning also comprises power end, the 3rd resistance and first, second, third electric capacity, the 3rd resistance is connected between the 4th, the 5th transistorized source electrode and this output, this first electric capacity is connected between this power end and this input, this the second electric capacity is connected in the common port of this power end and this first, second resistance, and the 3rd resistance is connected between this power end and this output.

A phase-locked loop circuit, for generation of an output signal, comprises frequency divider, and for receiving this output signal, and the frequency of adjusting this output signal is to provide feedback signal; Phase frequency detector, receives reference signal and this feedback signal, and output is used to indicate the phase signal of this reference signal and this feedback signal phase difference; For receiving this phase signal output, control the charge pump of electric current; For producing according to the control electric current of this charge pump output the loop filter of controlling voltage; For adjusting the voltage controlled oscillator of the output signal frequency of this phase-locked loop circuit; For according to the divider ratio signal of this frequency divider, adjust the loop filtering resistance Circuit tuning of the resistance parameter of this loop filter, this control voltage is input to this voltage controlled oscillator via this loop filtering resistance Circuit tuning.

A control method for phase-locked loop circuit, comprises the steps: to receive reference signal and feedback signal, the output signal that this feedback signal is this phase-locked loop circuit; Output is used to indicate the phase signal of this reference signal and this feedback signal phase difference; According to this phase signal, by charge pump output, control electric current; According to the loop bandwidth of this phase-locked loop circuit and damping coefficient, adjust the size that electric current is controlled in this output; Control electric current after adjusting according to this produces controls voltage; According to the divider ratio signal of the frequency divider of this phase-locked loop circuit, adjust the resistance parameter of the loop filter of this phase-locked loop circuit, and then adjust this control voltage; According to this control voltage, adjust the output signal frequency of this phase-locked loop circuit.

Compared with prior art, phase-locked loop circuit of the present invention comprises this current mirroring circuit, by adjustment, be input to the control bias voltage of this current mirroring circuit, adjust the current ratio relation of input and the output of this current mirroring circuit, adjust loop bandwidth and the damping coefficient of this phase-locked loop circuit, thereby improve the stability of this phase-locked loop circuit.Phase-locked loop circuit of the present invention also can comprise this loop filtering resistance Circuit tuning, this loop filtering resistance Circuit tuning is according to the resistance parameter of this loop filter of divider ratio signal controlling of this frequency divider, by adjustment, be input to the control voltage of this voltage controlled oscillator, thereby adjust the loop bandwidth of this phase-locked loop circuit and the stability that damping coefficient improves this phase-locked loop circuit.

Accompanying drawing explanation

Fig. 1 is a kind of block diagram of phase-locked loop circuit of prior art.

Fig. 2 is the block diagram of the phase-locked loop circuit of first embodiment of the invention.

Fig. 3 is the internal circuit schematic diagram of the current mirroring circuit shown in Fig. 2.

Fig. 4 is the internal circuit schematic diagram of the loop filtering resistance Circuit tuning shown in Fig. 2.

Fig. 5 is the block diagram of the phase-locked loop circuit of second embodiment of the invention.

Fig. 6 is the amplitude frequency curve figure of the phase-locked loop circuit shown in Fig. 5.

Fig. 7 is the phase frequency curve figure of the phase-locked loop circuit shown in Fig. 5.

Fig. 8 is the block diagram of the phase-locked loop circuit of third embodiment of the invention.

Fig. 9 is the amplitude frequency curve figure of the phase-locked loop circuit shown in Fig. 8.

Figure 10 is the phase frequency curve figure of the phase-locked loop circuit shown in Fig. 8.

Embodiment

For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the present invention is described in further detail.

Refer to Fig. 2, Fig. 2 is the block diagram of the phase-locked loop circuit of first embodiment of the invention.This phase-locked loop circuit 20 comprises phase frequency detector 21, charge pump 22, current mirroring circuit 23, loop filter 24, loop filtering resistance Circuit tuning 25, voltage controlled oscillator 26, the frequency divider 27 connecting successively.This phase frequency detector 21, this charge pump 22, this current mirroring circuit 23, this loop filter 24, this loop filtering resistance Circuit tuning 25, this voltage controlled oscillator 26, this frequency divider 27 form a loop.

The divider ratio of this frequency divider 27 can be preset, and the divider ratio of this frequency divider 27 is looked the design requirement of this phase-locked loop circuit 20 by the outside input control of this phase-locked loop circuit 20.For example, when the divider ratio of this frequency divider 27 is 32, the outside divider ratio signal that needs input one 5bit.This frequency divider 27 receives the output signal of this phase-locked loop circuit 20, and the frequency of adjusting these phase-locked loop circuit 20 output signals is to provide feedback signal to this phase frequency detector 21.This phase frequency detector 21 is for receiving a reference signal and this feedback signal, and output is used to indicate the phase signal of this reference signal and this feedback signal phase difference.This charge pump 22 is for receiving the phase signal of these phase frequency detector 21 outputs and exporting a control electric current.The input 231 of this current mirroring circuit 23 receives this and controls electric current, and adjusts the size of this control electric current.This loop filter 24 is for filtering control electric current after this adjustment to produce a control voltage.This loop filtering resistance Circuit tuning 25, according to the divider ratio signal of this frequency divider 27, is adjusted the resistance parameter of this loop filter 24.This voltage controlled oscillator 26 changes the frequency of these phase-locked loop circuit 20 output signals according to this control voltage.

See also Fig. 3, Fig. 3 is the internal circuit schematic diagram of the current mirroring circuit 23 shown in Fig. 2.This current mirroring circuit 23 is inverse ratio programmable current mirror circuits.This current mirroring circuit 23 comprises the first transistor Q1 and five serial transistor unit 233 that circuit structure is identical.This serial transistor unit 233 receives the control electric current of these charge pump 22 outputs, and adjust according to the conducting number of this serial transistor unit 233 the control electric current that this first transistor Q1 exports, the conducting number of this serial transistor unit 233 is inversely proportional to the control electric current of this first transistor Q1 output.

Each serial transistor unit 233 includes a transistor seconds Q2 and one the 3rd transistor Q3, the source ground of this transistor seconds Q2, the grid of this transistor seconds Q2 connects the grid of this first transistor Q1, the drain electrode of this transistor seconds Q2 connects the source electrode of the 3rd transistor Q3, the grid of the 3rd transistor Q3 receives controls bias voltage, the drain electrode of the 3rd transistor Q3 and the input 231 of this current mirroring circuit 23 are all connected the grid of this first transistor Q1, the source ground of this first transistor Q1, drain electrode connects the output 232 of this current mirroring circuit 23.The i.e. source electrode of the transistor seconds Q2 of these five serial transistor unit 233 ground connection respectively, the drain electrode of the 3rd transistor Q3 of these five serial transistor unit 233 all links together to receive the control electric current of these charge pump 22 outputs, the grid of the 3rd transistor Q3 of these five serial transistor unit 233 receives respectively five and controls bias voltage, control bias voltage for controlling the conducting number of these five the 3rd transistor Q3, and then control the proportionate relationship between the input 231 of this current mirroring circuit 23 and the control electric current of output 232 for these five.For example: in order to increase the electric current of the output 232 of this current mirroring circuit 23, can change the control bias voltage that is input to this serial transistor unit 233, thereby reduce the conducting number of the 3rd transistor Q3 in this serial transistor unit 233.

Referring again to Fig. 4, Fig. 4 is the internal circuit schematic diagram of the loop filtering resistance Circuit tuning 25 shown in Fig. 2.This loop filtering resistance Circuit tuning comprise 25 comprise one for the input 251, that receives the control voltage of this loop filter 24 outputs for exporting output 252, a power end VDD who controls voltage to this voltage controlled oscillator 26.

Four, the drain electrode of the 5th transistor Q4, Q5 connects one end of the second resistance R 2, and the other end of this second resistance R 2 is connected the power end of this loop filtering resistance Circuit tuning 25 with one end of the first resistance R 1 via one second capacitor C 2.Four, the source electrode of the 5th transistor Q4, Q5 and the other end of this first resistance R 1 are connected the input 251 of this loop filtering resistance Circuit tuning 25.The grid of the 4th transistor Q4 receives the highest order of the divider ratio signal of this frequency divider 27, and the grid of the 5th transistor Q5 receives a time high position for the divider ratio signal of this frequency divider 27.The 3rd resistance R 3 is connected between the source electrode of the 4th, the 5th transistor Q4, Q5 and the output 252 of this loop filtering resistance Circuit tuning 25, the first capacitor C 1 is connected between this power end and the input 251 of this loop filtering resistance Circuit tuning 25, and the 3rd capacitor C 3 is connected between this power end and the output 252 of this loop filtering resistance Circuit tuning 25.In the present embodiment, the resistance value of this first, second resistance R 1, R2 equates.The 4th transistor Q4 is PMOS transistor, and the 5th transistor Q5 is nmos pass transistor.

When the highest order of the divider ratio signal of this frequency divider 27 and a time high position change and while making one of them conducting of the 4th, the 5th transistor Q4, Q5 of this loop filtering resistance Circuit tuning 25, the second resistance R 2 of this loop filtering resistance Circuit tuning 25 is connected in parallel with this first resistance R 1, and the resistance of this loop filtering resistance Circuit tuning 25 is less.

When the highest order of the divider ratio signal of this frequency divider 27 and a time high position change and when the 4th, the 5th transistor Q4, the Q5 of this loop filtering resistance Circuit tuning 25 are all ended, the second resistance R 2 of this loop filtering resistance Circuit tuning 25 is cancelled with the relation in parallel of this first resistance R 1, and the resistance of this loop filtering resistance Circuit tuning 25 increases.

The operation principles of this phase-locked loop circuit 20 is as follows:

The input 211 of this phase frequency detector 21 receives reference signal, and from these frequency divider 27 receiving feedback signals, this phase frequency detector 21 is by relatively phase place output dropping signal (Down) or the rising signals (Up) of this reference signal and this feedback signal, and this dropping signal and rising signals have been expressed the phase difference between this reference signal and this feedback signal.When the phase lag of feedback signal is during in the phase place of reference signal, these phase frequency detector 21 output phase error rising signals.When the phase place of the leading reference signal of phase place of feedback signal, these phase frequency detector 21 output phase error dropping signals.

This charge pump 22 is controlled electric current according to the dropping signal of these phase frequency detector 21 outputs and rising signals output, and this control electric current is current impulse.When this reference signal and this feedback signal have identical phase place, the current impulse of these charge pump 22 outputs has equal width.When the phase place of this reference signal and this feedback signal is not identical, one of current impulse of these charge pump 22 outputs is elongated, with phase calibration.

The input 231 of this current mirroring circuit 23 receives the control electric current of these charge pump 22 outputs, by setting, be input to the control bias voltage of this serial transistor unit 233, control the conducting number of the 3rd transistor Q3 in this serial transistor unit 233, and then adjust the current ratio relation of input 231 with the output 232 of this current mirroring circuit 23.From formula (3), (4), when the loop bandwidth of this phase-locked loop circuit 20 and damping coefficient change, by adjustment, be input to the control bias voltage of this serial transistor unit 233, can adjust and be input to the size that this loop filter 24 is controlled electric current, thereby adjust loop bandwidth and the damping coefficient of this phase-locked loop circuit 20, and then improve the stability of this phase-locked loop circuit 20.

Control electric current after the adjustment of output 232 outputs of these loop filter 24 these current mirroring circuits 23 of reception, and producing this one for controlling the control voltage of this voltage controlled oscillator 26 according to the control electric current after this adjustment, this control voltage is for controlling the frequency of these voltage controlled oscillator 26 output signals.

When the loop bandwidth of this phase-locked loop circuit 20 and damping coefficient change, the output frequency of this voltage controlled oscillator 26 changes, the highest order of the divider ratio signal of this frequency divider 27 and a time high position change, thereby control the 4th, the 5th transistor Q4 of this loop filtering resistance Circuit tuning 25, conducting or the cut-off of Q5, and then control the resistance parameter of this loop filter 24.By controlling the resistance parameter of this loop filter 24, can adjust the control voltage that is input to this voltage controlled oscillator 26, and then can adjust the gain of 26 pairs of input voltages of this voltage controlled oscillator, from formula (3), (4), by adjusting the gain of this voltage controlled oscillator 26, can adjust loop bandwidth and the damping coefficient of this phase-locked loop circuit 20, thereby improve the stability of this phase-locked loop circuit 20.

Compared with prior art, phase-locked loop circuit 20 of the present invention comprises this current mirroring circuit 23 and this loop filtering resistance Circuit tuning 25, by adjusting the control bias voltage of this current mirroring circuit 23, adjust the current ratio relation of input 231 with the output 232 of this current mirroring circuit 23, thereby adjust loop bandwidth and the damping coefficient of this phase-locked loop circuit 20.This loop filtering resistance Circuit tuning 25, according to the resistance parameter of this loop filter 24 of divider ratio signal controlling of this frequency divider 27, is input to the control voltage of this voltage controlled oscillator 26 by adjustment, adjust loop bandwidth and the damping coefficient of this phase-locked loop circuit 20.Phase-locked loop circuit 20 of the present invention is adjusted loop bandwidth and the damping coefficient of this phase-locked loop circuit 20 by this current mirroring circuit 23 and this loop filtering resistance Circuit tuning 25, improved the stability of this phase-locked loop circuit 20.

Refer to Fig. 5, Fig. 5 is the block diagram of the phase-locked loop circuit of second embodiment of the invention.The structural similarity of the phase-locked loop circuit 20 of this phase-locked loop circuit 50 and the first execution mode, this phase-locked loop circuit 50 comprises phase frequency detector 51, charge pump 52, current mirroring circuit 53, loop filter 54, voltage controlled oscillator 56, the frequency divider 57 connecting successively.This phase frequency detector 51, this charge pump 52, this current mirroring circuit 53, this loop filter 54, this voltage controlled oscillator 56, this frequency divider 57 form a loop.

This frequency divider 57, for receiving this output signal, and the frequency of adjusting this output signal is to provide feedback signal.This phase frequency detector 51, receives reference signal and this feedback signal, and output is used to indicate the phase signal of this reference signal and this feedback signal phase difference.This charge pump 52 is for receiving this phase signal and controlling electric current according to this phase signal output.This current mirroring circuit 53 is for receiving and adjust the control electric current of these charge pump 52 outputs.This loop filter 54 is for producing and control voltage according to the control electric current of these current mirroring circuit 53 outputs.This voltage controlled oscillator 56 is adjusted the frequency of these phase-locked loop circuit 50 output signals for the control voltage producing according to this loop filter 54.

The internal circuit configuration of this current mirroring circuit 53 is all identical with internal circuit configuration and the operation principles of the current mirroring circuit 23 of the first execution mode.

This current mirroring circuit 53 is inverse ratio programmable current mirror circuits.This current mirroring circuit 53 comprises the first transistor and a plurality of serial transistors unit.This serial transistor unit receives the control electric current of these charge pump 52 outputs, and adjust according to the conducting number of this serial transistor unit the control electric current that this first transistor is exported, the conducting number of this serial transistor unit is inversely proportional to the control electric current of this first transistor output.

Each serial transistor unit includes a transistor seconds and one the 3rd transistor, the source ground of this transistor seconds, the grid of this transistor seconds connects the grid of this first transistor, the drain electrode of this transistor seconds connects the 3rd transistorized source electrode, the 3rd transistorized grid receives controls bias voltage, the input of the 3rd transistorized drain electrode and this current mirroring circuit is all connected the grid of this first transistor, the source ground of this first transistor, drain electrode connects the output of this current mirroring circuit 53.

See also Fig. 6, Fig. 7, Fig. 6 is the amplitude frequency curve figure of the phase-locked loop circuit 50 shown in Fig. 5, and wherein, abscissa represents the frequency of these phase-locked loop circuit 50 output signals, and ordinate represents the gain of these phase-locked loop circuit 50 output signals.When curve 61 represents not adopt this current mirroring circuit 53, the amplitude frequency curve of this phase-locked loop circuit 50, when curve 62 represents that present embodiment adopts this current mirroring circuit 53, makes after the current doubles of these charge pump 52 outputs the amplitude frequency curve of this phase-locked loop circuit 50.Fig. 7 is the phase frequency curve figure of the phase-locked loop circuit 50 shown in Fig. 5, and wherein, abscissa represents the frequency of these phase-locked loop circuit 50 output signals, and ordinate represents the phase place of these phase-locked loop circuit 50 output signals.As seen from the figure, after the phase-locked loop circuit 50 of present embodiment utilizes this current mirroring circuit 53 that the electric current of these charge pump 52 outputs is doubled, the phase place of these phase-locked loop circuit 50 output signals does not change.During zero point, signal frequency is increased to 372KHz from 213KHz, and gain is increased to 577mdB from 535mdB, and phase margin is increased to 62 ° from 52 °, has improved the stability of this phase-locked loop circuit 50.

Refer to Fig. 8, Fig. 8 is the block diagram of the phase-locked loop circuit of third embodiment of the invention.The structural similarity of the phase-locked loop circuit 20 of this phase-locked loop circuit 80 and the first execution mode, this phase-locked loop circuit 80 comprises phase frequency detector 81, charge pump 82, loop filter 84, loop filtering resistance Circuit tuning 85, voltage controlled oscillator 86, the frequency divider 87 connecting successively.This phase frequency detector 81, this charge pump 82, this loop filter 84, this loop filtering resistance Circuit tuning 85, this voltage controlled oscillator 86, this frequency divider 87 form a loop.

This frequency divider 87 is for receiving this output signal, and the frequency of adjusting this output signal is to provide feedback signal.This phase frequency detector 81, receives reference signal and this feedback signal, and output is used to indicate the phase signal of this reference signal and this feedback signal phase difference.This charge pump 82 is for receiving this phase signal and controlling electric current according to this phase signal output.This loop filter 84 is for producing and control voltage according to the control electric current of these charge pump 82 outputs.This loop filtering resistance Circuit tuning 85, according to the divider ratio signal of this frequency divider 87, is adjusted the resistance parameter of this loop filter 84.This control voltage is input to this voltage controlled oscillator 86 via this loop filtering resistance Circuit tuning 85.

The internal circuit configuration of this loop filtering resistance Circuit tuning 85 is all identical with internal circuit configuration and the operation principles of the loop filtering resistance Circuit tuning 25 of the first execution mode.

This loop filtering resistance Circuit tuning comprises that 85 comprise that one controls voltage to output, a power end of this voltage controlled oscillator 86 for exporting for receiving the input, of the control voltage of these loop filter 84 outputs.

Four, the 5th transistorized drain electrode connects one end of the second resistance, and the other end of this second resistance is connected the power end of this loop filtering resistance Circuit tuning with one end of the first resistance via one second electric capacity.Four, the other end of the 5th transistorized source electrode and this first resistance is connected the input of this loop filtering resistance Circuit tuning.The 4th transistorized grid receives the highest order of the divider ratio signal of this frequency divider, and the 5th transistorized grid receives a time high position for the divider ratio signal of this frequency divider.The 3rd resistance is connected between the 4th, the 5th transistorized source electrode and the output of this loop filtering resistance Circuit tuning 85, the first electric capacity is connected between this power end and the input of this loop filtering resistance Circuit tuning 85, and the 3rd electric capacity is connected between this power end and the output of this loop filtering resistance Circuit tuning 85.

When the highest order of the divider ratio signal of this frequency divider 87 and a time high position change and while making one of them conducting of the 4th, the 5th transistor 8 of this loop filtering resistance Circuit tuning 85, the second resistance of this loop filtering resistance Circuit tuning 85 and this first resistance are connected in parallel, and the resistance of this loop filtering resistance Circuit tuning 85 is less.

When the highest order of the divider ratio signal of this frequency divider 87 and a time high position change and when the 4th, the 5th transistor of this loop filtering resistance Circuit tuning 85 is all ended, the second resistance of this loop filtering resistance Circuit tuning 85 is cancelled with the relation in parallel of this first resistance, and the resistance of this loop filtering resistance Circuit tuning 85 increases.

See also Fig. 9, Figure 10, Fig. 9 is the amplitude frequency curve figure of the phase-locked loop circuit 80 shown in Fig. 8, and wherein, abscissa represents the frequency of these phase-locked loop circuit 80 output signals, and ordinate represents the gain of these phase-locked loop circuit 80 output signals.Figure 10 is the phase frequency curve figure of the phase-locked loop circuit 80 shown in Fig. 8, abscissa represents the frequency of these phase-locked loop circuit 80 output signals, ordinate represents the phase place of these phase-locked loop circuit 80 output signals, wherein, when curve 101 represents not adopt this loop filtering resistance Circuit tuning 85, the phase frequency curve of phase-locked loop circuit output signal, curve 102 represents to adopt after this loop filtering resistance Circuit tuning 85, when this second resistance does not access this loop filtering resistance Circuit tuning 85, the phase frequency curve of these phase-locked loop circuit 80 output signals.As seen from the figure, the phase-locked loop circuit 80 of present embodiment utilizes this loop filtering resistance Circuit tuning 85 to adjust the resistance parameter of this loop filter 84, before and after adjusting, the gain of these phase-locked loop circuit 80 output signals remains unchanged, but the filter zero point being determined by the resistance parameter of this loop filter 84, the positive direction to abscissa moved, by 148KHz ,-290mdB, be increased to 215KHz ,-157mdB, thereby make its phase margin rise to 61 degree by the degree of 41 before adjusting, thereby improved the stability of this phase-locked loop circuit 80.

Phase-locked loop circuit of the present invention is controlled the 4th, the 5th transistorized conducting and cut-off of this loop filtering resistance Circuit tuning according to the highest order of the divider ratio signal of this frequency divider and a time high position, and then adjust the resistance parameter of this loop filter, also can according to other figure places of the divider ratio signal of this frequency divider, control the 4th, the 5th transistorized conducting and cut-off of this loop filtering resistance Circuit tuning, be not limited to described in above-mentioned execution mode.Phase-locked loop circuit of the present invention can also pass through the transistorized number of adjustment loop filter resistance Circuit tuning, adjustment is linked into the number of the resistance of this loop filtering resistance Circuit tuning, when the figure place of the divider ratio signal of this frequency divider is N, this loop filtering resistance Circuit tuning can produce 2 nindividual resistance parameter, the span of the figure place N of the divider ratio signal of this frequency divider is 4~20.For example, when the divider ratio of this frequency divider is 32, the outside divider ratio signal that needs input one 5bit, the divider ratio signal of this 5bit can be adjusted 5 transistorized conductings and cut-off, thereby control this loop filtering resistance Circuit tuning, produces 2 5individual resistance parameter, and then realize the meticulous adjusting to the resistance parameter of the loop filter of phase-locked loop circuit.

Without departing from the spirit and scope of the present invention in the situation that, can also form many embodiment that have very big difference.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in specification.

Claims (19)

1. a phase-locked loop circuit, for generation of an output signal, comprising:
Frequency divider, for receiving this output signal, and the frequency of adjusting this output signal is to provide feedback signal;
Phase frequency detector, receives reference signal and this feedback signal, and output is used to indicate the phase signal of this reference signal and this feedback signal phase difference;
Charge pump, for receiving this phase signal output control electric current;
Loop filter, for generation of controlling voltage;
Voltage controlled oscillator, for adjusting the output signal frequency of this phase-locked loop circuit, is characterized in that, this phase-locked loop circuit also comprises:
Current mirroring circuit, for receiving and adjust the control electric current of this charge pump output, this loop filter filters control electric current after this adjustment to produce this control voltage;
Loop filtering resistance Circuit tuning, for according to the divider ratio signal of this frequency divider, adjusts the resistance parameter of this loop filter, and this control voltage is input to this voltage controlled oscillator via this loop filtering resistance Circuit tuning, this loop filtering resistance Circuit tuning comprises for receiving the input of the control voltage of this loop filter output, for exporting the output that controls voltage to this voltage controlled oscillator, the first resistance, the second resistance, the 4th transistor and the 5th transistor, this is first years old, the second resistance is connected in parallel between this input and output, the highest order of the divider ratio signal of this frequency divider and a time high position are input to respectively the 4th, the 5th transistorized grid, by controlling the 4th, the 5th transistorized conducting and cut-off adjust this first, the resistance of the second resistance parallel circuits.
2. phase-locked loop circuit as claimed in claim 1, is characterized in that: this current mirroring circuit is inverse ratio programmable current mirror circuit.
3. phase-locked loop circuit as claimed in claim 1, it is characterized in that: this current mirroring circuit comprises the first transistor and at least one serial transistor unit, this serial transistor unit receives the control electric current of this charge pump output, and control the control electric current after this first transistor output is adjusted, the conducting number of this serial transistor unit is inversely proportional to the control electric current of this first transistor output.
4. phase-locked loop circuit as claimed in claim 3, it is characterized in that: each serial transistor unit comprises transistor seconds and the 3rd transistor, the source ground of this transistor seconds, the grid of this transistor seconds connects the grid of this first transistor, the drain electrode of this transistor seconds connects the 3rd transistorized source electrode, the 3rd transistorized grid receives controls bias voltage, the 3rd transistorized drain electrode connects the grid of this first transistor and receives the control electric current of this charge pump output, the source ground of this first transistor, control electric current after this adjustment of drain electrode output.
5. phase-locked loop circuit as claimed in claim 4, is characterized in that: this control bias voltage is used for controlling the 3rd transistorized conducting and cut-off, and then adjusts input and the proportionate relationship of exporting the control electric current of this current mirroring circuit.
6. phase-locked loop circuit as claimed in claim 1, it is characterized in that: four, the 5th transistorized drain electrode connects one end of this second resistance, the other end of this second resistance is connected this input with one end of this first resistance, and the other end of the 4th, the 5th transistorized source electrode and this first resistance is connected this output.
7. phase-locked loop circuit as claimed in claim 6, it is characterized in that: this loop filtering resistance Circuit tuning also comprises power end, the 3rd resistance and first, second, third electric capacity, the 3rd resistance is connected between the 4th, the 5th transistorized source electrode and this output, this first electric capacity is connected between this power end and this input, this the second electric capacity is connected in the common port of this power end and this first, second resistance, and the 3rd resistance is connected between this power end and this output.
8. phase-locked loop circuit as claimed in claim 1, is characterized in that: the resistance value of this first, second resistance is identical.
9. phase-locked loop circuit as claimed in claim 1, it is characterized in that: the 4th transistor is PMOS transistor, the 5th transistor is nmos pass transistor, the divider ratio signal of this frequency divider is digital signal, the 4th transistorized grid receives the highest order of the divider ratio signal of this frequency divider, and the 5th transistorized grid receives a time high position for the divider ratio signal of this frequency divider.
10. a phase-locked loop circuit, for generation of an output signal, comprising:
Frequency divider, for receiving this output signal, and the frequency of adjusting this output signal is to provide feedback signal;
Phase frequency detector, receives reference signal and this feedback signal, and output is used to indicate the phase signal of this reference signal and this feedback signal phase difference;
Charge pump, for receiving this phase signal output control electric current;
Loop filter, for producing and control voltage according to the control electric current of this charge pump output;
Voltage controlled oscillator, for adjusting the output signal frequency of this phase-locked loop circuit, is characterized in that, this phase-locked loop circuit also comprises:
Loop filtering resistance Circuit tuning, for according to the divider ratio signal of this frequency divider, adjusts the resistance parameter of this loop filter, and this control voltage is input to this voltage controlled oscillator via this loop filtering resistance Circuit tuning, this loop filtering resistance Circuit tuning comprises for receiving the input of the control voltage of this loop filter output, for exporting the output that controls voltage to this voltage controlled oscillator, the first resistance, the second resistance, the 4th transistor and the 5th transistor, this is first years old, the second resistance is connected in parallel between this input and output, the highest order of the divider ratio signal of this frequency divider and a time high position are input to respectively the 4th, the 5th transistorized grid, by controlling the 4th, the 5th transistorized conducting and cut-off adjust this first, the resistance of the second resistance parallel circuits.
11. phase-locked loop circuits as claimed in claim 10, it is characterized in that: four, the 5th transistorized drain electrode connects one end of this second resistance, the other end of this second resistance is connected this input with one end of this first resistance, and the other end of the 4th, the 5th transistorized source electrode and this first resistance is connected this output.
12. phase-locked loop circuits as claimed in claim 11, it is characterized in that: this loop filtering resistance Circuit tuning also comprises power end, the 3rd resistance and first, second, third electric capacity, the 3rd resistance is connected between the 4th, the 5th transistorized source electrode and this output, this first electric capacity is connected between this power end and this input, this the second electric capacity is connected in the common port of this power end and this first, second resistance, and the 3rd resistance is connected between this power end and this output.
13. phase-locked loop circuits as claimed in claim 12, it is characterized in that: the 4th transistor is PMOS transistor, the 5th transistor is nmos pass transistor, the divider ratio signal of this frequency divider is digital signal, the 4th transistorized grid receives the highest order of the divider ratio signal of this frequency divider, and the 5th transistorized grid receives a time high position for the divider ratio signal of this frequency divider.
The control method of 14. 1 kinds of phase-locked loop circuits, comprises the steps:
Receive reference signal and feedback signal, the output signal that this feedback signal is this phase-locked loop circuit;
Output is used to indicate the phase signal of this reference signal and this feedback signal phase difference;
According to this phase signal, by charge pump output, control electric current;
According to the loop bandwidth of this phase-locked loop circuit and damping coefficient, adjust the size that electric current is controlled in this output;
Control electric current after adjusting according to this produces controls voltage;
According to the divider ratio signal of the frequency divider of this phase-locked loop circuit, adjust the resistance parameter of the loop filter of this phase-locked loop circuit, and then adjust this control voltage; Be specially:
According to the signal level of the highest order of the divider ratio signal of the frequency divider of this phase-locked loop circuit and a time high position, adjust the resistance parameter of the loop filter of this phase-locked loop circuit;
According to this control voltage, adjust the output signal frequency of this phase-locked loop circuit.
The control method of 15. phase-locked loop circuits as claimed in claim 14, is characterized in that: utilize a current mirroring circuit to adjust the size of this control electric current.
The control method of 16. phase-locked loop circuits as claimed in claim 15, is characterized in that: by adjustment, be input to the control bias voltage of this current mirroring circuit, adjust the proportionate relationship of the input of this current mirroring circuit and the control electric current of output.
The control method of 17. phase-locked loop circuits as claimed in claim 16, is characterized in that: this current mirroring circuit is inverse ratio programmable current mirror circuit.
The control method of 18. phase-locked loop circuits as claimed in claim 14, is characterized in that: the figure place of the divider ratio signal of the frequency divider of this phase-locked loop circuit is N, and the loop filter of this phase-locked loop circuit can produce 2N resistance parameter.
The control method of 19. phase-locked loop circuits as claimed in claim 18, is characterized in that: the scope of the figure place N of this divider ratio signal is 4~20.
CN200910052964.XA 2009-06-12 2009-06-12 Phase-locked loop circuit and control method thereof CN101572545B (en)

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US9722617B2 (en) * 2014-11-14 2017-08-01 Mediatek Singapore Pte. Ltd. Phase locked loop and associated method for loop gain calibration
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