CN101567214B - Line selector applicable to reading and wiring functions of nine-transistor memory unit - Google Patents

Line selector applicable to reading and wiring functions of nine-transistor memory unit Download PDF

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CN101567214B
CN101567214B CN 200910072234 CN200910072234A CN101567214B CN 101567214 B CN101567214 B CN 101567214B CN 200910072234 CN200910072234 CN 200910072234 CN 200910072234 A CN200910072234 A CN 200910072234A CN 101567214 B CN101567214 B CN 101567214B
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input
gate
read
line
row
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CN 200910072234
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CN101567214A (en
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白旭
许秉时
赵慧卓
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哈尔滨工业大学
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Abstract

A line selector applicable to reading and wiring functions of a nine-transistor memory unit belongs to the field of digital electronics and aims at solving the problem that the nine-transistor memory unit can not directly control and select a line needing to be read or written through a decoding line. The line selector comprises a three-input AND gate, a two-input AND gate and an NON gate. The first input end of the three-input AND gate is a write control signal input end; the third input end of the three-input AND gate is a NON gate end; the output end of the three-input AND gate is a line selection write enabling signal output end and connected with a WR wire of the nine-transistor memory unit; the second input end of the three-input AND gate and the first input end of the two-input ANDgate are line address signal input ends; the second input end of the two-input AND gate and the input end of the NON gate are read control signal input ends; the output end of the NON gate is connected with the NON gate end of the tree-input AND gate; and the output end of the two-input AND gate is a line selection read enabling signal output end and is connected with an RD wire of the nine-transistor memory unit. The line selector is applied to line selection of a memory used for the nine-transistor memory unit.

Description

适应九管存储单元读写功能的行选择器 Adaptation nine read or write memory row selector function

技术领域 FIELD

[0001] 本发明涉及一种适应九管存储单元读写功能的行选择器,属于数字电子领域。 [0001] The present invention relates to a storage unit adapted to read and write nine row selector function, belonging to the field of digital electronics. 背景技术 Background technique

[0002] 现有存储器一般以传统的六管结构作为其存储单元(如图1),六管存储单元具有速度快,面积小等诸多优点。 [0002] In the conventional memory conventional six general structure as the memory cell (FIG. 1), six memory cell has high speed, and small area of ​​advantages. 但是其单元结构中数据节点通过门控管(N3,N4)直接与位线WL相连,在读周期中由于反相器和门控管的分压使数据节点中存储的数据更易受到外界噪声的影响,这导致了其读稳定性和噪声容限的下降,而为了满足一定读稳定性的要求,就要求其交叉耦合反相器中的下拉晶体管(Ni,N2)的尺寸要相应的加大,这就导致了静态功耗的增加。 However, the data unit which is directly connected to the node structure via the bit line WL Controls gate (N3, N4), in the read cycle since the inverter and the partial pressure of the door so Controls data stored in the data node is more susceptible to external noise , which leads to decreased stability and its read noise margin, and in order to meet the requirements of certain read stability, which requires that the size of cross-coupled inverters in the pull-down transistor (Ni, N2) to respective increase, This leads to an increase in static power.

[0003] 九管存储单元的结构(如图2)能够提高存储单元的读稳定性和降低功耗,克服六管存储单元存在的缺点。 [0003] The structure of nine memory cells (FIG. 2) can improve the memory cell stability and reduce power consumption reading, to overcome the shortcomings of the six memory cells. 在读周期中,不失一般性的假设Nodel中存储了数据“1”,BL被预充至高电平,WR信号保持在低电平,RD提升至高电平开始读取。 In the read cycle, without loss of generality in assuming Nodel data is stored "1", BL is pre-charged to a high level, WR signal is at a low level, high level up to the RD to start reading. 此时N5、N7开启,BL通过N5、N7放电,此过程中数据节点Nodel与位线完全隔离,使其读稳定性大为提高。 At this time, N5, N7 turn, BL through N5, N7 discharge process data node Nodel completely isolated from the bit line, so that stability is greatly improved read. 由于其读稳定性大为提高,则九管存储单元的晶体管的尺寸可以最小化而不用为读稳定性考虑,这就降低了功耗。 Because of its greatly improved read stability, the size of the transistor nine memory cells can be minimized by not considering the read stability, which reduces power consumption.

[0004] 对于传统的六管存储单元,读写过程中只有位线WL —个信号控制,读写周期中WL 均为高电平。 [0004] For a conventional six memory cells during read and write bit lines WL only - control signals, read and write cycle WL are high. 因此译码线可直接与位线WL相连以达到选择当前行的目的。 Thus decode line may be directly connected to the bit line WL selected to achieve the purpose of the current line. 而在改进的九管存储单元中,用到了WR和RD两个信号。 In the improved nine storage unit, it uses two signals WR and RD. 在写周期中,WR信号为高,RD信号为低,在读周期中,WR信号为低,RD信号为高。 In the write cycle, WR signal is high, RD signal is low, the read cycle, WR signal is low, RD signal is high. 这使得译码线无法直接控制选择需要被读写的行。 This enables the decode line direct control of the selected row to be read.

发明内容 SUMMARY

[0005] 本发明的目的是解决九管存储单元无法通过译码线直接控制选择需要被读写的行的问题,提供了一种适应九管存储单元读写功能的行选择器。 Objective [0005] The present invention is to solve row nine storage units can not directly control the select line is read by decoding, there is provided a storage unit adapted to read and write nine row selector function.

[0006] 本发明包括三输入与门、二输入与门和非门,三输入与门的第一输入端为写控制信号输入端,三输入与门的第三输入端为非门端,三输入与门的输出端为行选择写使能信号输出端;三输入与门的第二输入端和二输入与门的第一输入端为行地址信号输入端,二输入与门的第二输入端和非门的输入端为读控制信号输入端,非门的输出端和三输入与门的非门端相连,二输入与门的输出端为行选择读使能信号输出端。 [0006] The present invention comprises a three-input AND gate, two-input NAND gate and AND gate, a first input of a 3-input AND gate as a write control signal input terminal, a third input terminal of the three-input AND gate of the non-door side, tris and the output of the input gate for the row select write enable signal output terminal; a second input terminal of the three-input aND gate and a first input terminal of two-input aND gate is a row address signal input terminal, a second input of the two-input aND gate and an input terminal of the NAND gate terminal of the read control signal input terminal, an output terminal of the NAND gate and a three-input NAND gate is connected to the gate terminal, an output terminal of a two-input aND gate for row read enable selection signal output terminal.

[0007] 本发明的优点:本发明提出一种行选择器结构。 Advantages [0007] of the present invention: The present invention provides a row selector structure. 其输入端分别接收读写控制信号和由译码线输出的行地址信号,其输出端分别与WR线、RD线相连。 An input terminal which receives a row address signal and a write control signal outputted from the decode line, and its output terminals are connected to the WR line, the RD line. 通过地址信号的译码结果和读写控制信号来选择当前需要进行读写的行,并正确的进行读写操作。 Selecting the current row need to be read by the decoding result of the read address signal and the control signal and the correct read and write operations.

附图说明 BRIEF DESCRIPTION

[0008] 图1是六管存储单元结构示意图, 图2是九管存储单元结构示意图,图3是本发明行选择器的结构示意图, [0008] FIG. 1 is a schematic view of six memory cell structure, FIG. 2 is a schematic view of nine memory cell structure, FIG. 3 is a schematic view of the present invention, the row selector,

图4是本发明所述行选择器的具体电路图, FIG 4 is a detailed circuit diagram of the present invention, the row selector,

图5是应用本发明方法的九管存储单元的效果仿真图。 FIG 5 is a simulation of the effect of the nine memory cells applied the method of the present invention.

具体实施方式 Detailed ways

[0009] 具体实施方式一:下面结合图3至图5说明本实施方式,本实施方式包括三输入与门1、二输入与门2和非门3,三输入与门1的第一输入端为写控制信号输入端,三输入与门1的第三输入端为非门端,三输入与门1的输出端为行选择写使能信号输出端;三输入与门1的第二输入端和二输入与门2的第一输入端为行地址信号输入端,二输入与门2的第二输入端和非门3的输入端为读控制信号输入端,非门3的输出端和三输入与门1的非门端相连,二输入与门2的输出端为行选择读使能信号输出端。 [0009] DETAILED DESCRIPTION a: below in connection with FIGS. 3 to 5 according to the present embodiment described embodiment, the present embodiment includes a three-input AND gates, two 2-input AND gate and a NAND gate 3, a first input terminal of the three-input gate 1 write control signal input terminal, a third input terminal of the three-input aND gate 1 is a non-door side, three input and output terminals 1 for row selection gate write enable signal output terminal; a second input terminal of the three-input aND gate 1 and two-input gate to the first input terminal 2 of the row address signal input terminal, a second input terminal and the second input gate and a 2 input NAND gate 3 to a read control signal input terminal, an output terminal of the NAND gate and three 3 input NAND gate is connected to an aND gate, two input and output terminals 2 for row selection gate read enable signal output terminal.

[0010] 参见图3所示本发明的结构,行地址信号输入端接入的信号为行地址信号Row, 是译码器的结果,如当前行的译码结果为高电平,则行地址信号Row为高电平,即当前行为有效行,代表该行被选中;写控制信号输入端接入的信号为写控制信号Write,高电平时有效;读控制信号输入端接入的信号为读控制信号Read,高电平时有效;如果要对该行进行写操作,则让写控制信号Write置高电平,读控制信号Read置低电平;如果要对该行进行读操作,则让读控制信号Read置高电平,写控制信号Write置低电平;选择写使能信号输出端接九管存储单元的WR线接,高电平时有效,行选择读使能信号输出端接九管存储单元的RD 线高电平时有效,WR高、RD低代表对当前选中行进行写操作,WR低、RD高代表对当前选中行进行读操作。 [0010] Referring to the structure shown in FIG. 3 of the present invention, the row address signal input terminal of the access signal is a row address signal Row, is a result of the decoder, such as a decoding result of the current row high level, the row address row signal is high, i.e. the behavior of the current active line, representing the row is selected; write signal input of the access control signal is a write control signal write, active high; read control signal input of the read access signal read control signal, active high; to the write line, the write is set high so that the write control signal, read control signal read is set low; If you want to read the line, so that the read read control signal is set high, the write control signal write is set low; selecting a write enable signal WR line output end of the nine memory cells connected, active high, the read enable signal line select nine output termination when the memory cell line RD active-high, high WR, RD low current representative of a selected row is written, the low WR, RD high current representative of a selected row read operation.

[0011] 下面结合一个具体的实施例说明其工作原理,用九管存储单元构成的存储器中包括有m行九管存储单元,m为自然数,每行都接有本发明所述的行选择器,每行的地址由译码器的结果确定,本发明所述行选择器中行地址信号Row接译码器的结果,如当前行的译码结果为高电平,即当前行为有效行,代表该行被选中,对该行进行读写操作。 The row selector [0011] following embodiment in conjunction with a specific embodiment of how it works, with nine memory storage units includes m rows of nine memory cells, m being a natural number, each line connected with the present invention , each row address decoder is determined from the results, the results of the present invention is the selection of rows in the row address signal contact row decoder, such as a decoding result of the current line is high, i.e., the current active line behavior, representative of the row is selected, the row read and write operations.

[0012] 对选中行进行写操作的分析,三输入与门1的三个输入端分别为: [0012] The analysis of the selected row write operation, the three three-input gate input terminal 1 are:

[0013] 第一输入端(写控制信号输入端)、写控制信号Write高电平; [0013] a first input terminal (the write control signal input terminal), a write control signal Write high;

[0014] 第二输入端(行地址信号输入端)、行地址信号Row高电平,因为高电平有效,高电平表示当前行被选中; [0014] a second input terminal (input row address signal), a row address Row a high level signal, since the active high, a high level indicates that the current row is selected;

[0015] 第三输入端(非门端)、读控制信号Read低电平,经非门3后变成高电平接非门端。 [0015] The third input terminal (non-gate terminal), a read control signal Read low level, the NAND gate connected to a NAND gate 3 becomes the high level side.

[0016] 即三输入与门1的三个输入端都为高电平,则行选择写使能信号输出端输出结果为高电平,即九管存储单元的WR线接高电平,进行写操作。 Three inputs [0016] i.e., a three-input AND gate are high, the write enable row selection result signal output terminal is high, i.e., WR line nine memory cells connected to high level, for write operation.

[0017] 二输入与门2的两个输入端分别为: [0017] The two input AND gate input terminals 2, respectively:

[0018] 第一输入端(行地址信号输入端)、行地址信号Row高电平,因为高电平有效,高电平表示当前行被选中; [0018] a first input terminal (input row address signal), a row address Row a high level signal, since the active high, a high level indicates that the current row is selected;

[0019] 第二输入端(读控制信号输入端)、读控制信号Read低电平。 [0019] a second input terminal (a read control signal input terminal), a read control signal Read low.

[0020] 即二输入与门2的两个输入端分别为高电平和低电平,行选择读使能信号输出端输出结果为低电平,即九管存储单元的RD线接低电平,不进行读操作。 [0020] i.e. two input AND gate input terminals 2, respectively, an enable signal output terminal outputs high and low, low read row selection, i.e., RD ​​line nine memory cells connected to low level not read.

[0021] 通过本发明所述的行选择器,使应用九管存储单元的存储器能对选中的行进行正确的写操作,未被选中的行即使此时写控制信号为高电平也不进行任何操作,分析如下: [0021] by the row selector according to the present invention, the application of the memory storage unit is nine to allow for correct operation on a selected write line, the unselected rows even when the write control signal is high at this time is not performed any operation, as follows:

[0022] 如当前行未被选中,则行地址信号Row低电平,结合上述各端口电平的分析,三输入与门1的输入端一低两高,则输出结果为低电平,即九管存储单元的WR线接低电平;二输入与门2的输入端两个低电平,则输出结果为低电平,即九管存储单元的RD线接低电平,未被选中的行不进行读或写的操作。 [0022] The current line is not selected, the row address Row a low level signal, the port binding assay described above each level, three-input gate and the input terminal 1 of the two high and one low, then the output is low, i.e., WR line nine memory cells connected to low level; input of two input aND gate 2 is low, the output is low, i.e., RD ​​line nine memory cells connected to low level, the unselected the line does not read or write operation.

[0023] 对选中行进行读操作的分析和写操作的分析相似,三输入与门1的三个输入端分别为: [0023] analysis and analysis of the selected row write operation is similar to a read operation, the three three-input gate input terminal 1 are:

[0024] 第一输入端(写控制信号输入端)、写控制信号Write低电平; [0024] a first input terminal (the write control signal input terminal), a write control signal Write low;

[0025] 第二输入端(行地址信号输入端)、行地址信号Row高电平,因为高电平有效,高电平表示当前行被选中; [0025] a second input terminal (input row address signal), a row address Row a high level signal, since the active high, a high level indicates that the current row is selected;

[0026] 第三输入端(非门端)、读控制信号Read高电平,经非门3后变成低电平接非门端。 [0026] The third input terminal (non-gate terminal), a read control signal Read high level, the NAND gate 3 becomes a low potential end connected to the NAND gate.

[0027] 即三输入与门1的三个输入端两个为高电平,一个为低电平,则输出结果为低电平,即九管存储单元的WR线接低电平,不进行写操作。 Three inputs [0027] i.e., three two-input AND gate 1 is at a high level, a low level, the output is low, i.e., WR line nine memory cells connected to low level, without write operation.

[0028] 二输入与门2的两个输入端分别为: [0028] The two input AND gate input terminals 2, respectively:

[0029] 第一输入端(行地址信号输入端)、行地址信号Row高电平,因为高电平有效,高电平表示当前行被选中; [0029] a first input terminal (input row address signal), a row address Row a high level signal, since the active high, a high level indicates that the current row is selected;

[0030] 第二输入端(读控制信号输入端)、读控制信号Read高电平。 [0030] a second input terminal (a read control signal input terminal), a high level reading control signal Read.

[0031] 即二输入与门2的两个输入端都为高电平,输出结果为高电平,即九管存储单元的RD线接高电平,进行读操作。 [0031] i.e., two two-input and 2 input of AND gate are high, the output is high, i.e., RD ​​line nine memory cells connected to high level, read operation.

[0032] 通过本发明所述的行选择器,使应用九管存储单元的存储器能对选中的行进行正确的读操作,未被选中的行即使读控制信号为高电平也不进行任何操作,分析如下: [0032] by the row selector according to the present invention, the application of the memory storage unit is nine to allow for correct operation of the selected read line, the unselected row read control signal is high, even if not performed any operation ,analyse as below:

[0033] 如当前行未被选中,则行地址信号Row低电平,结合上述电平的分析,三输入与门1的输入端三低,则输出结果为低电平,即九管存储单元的WR线接低电平;二输入与门2的输入端一低一高,则输出结果为低电平,即九管存储单元的RD线接低电平,未被选中的行不进行读或写的操作。 [0033] The current line is not selected, the row address Row a low level signal, the level of binding assay, three-input gate and the input terminal 1 - low, then the output is low, i.e., nine memory cells the WR line connected to low level; input aND gate 2, an input terminal of a high-low, then the output is low, i.e., RD ​​line nine memory cells connected to low level, non-selected rows are not read or write operations.

[0034] 综上所述,通过本发明所述行选择器的设计,实现了对由九管存储单元组成的存储阵列的行的正确选择以及对存储单元的控制信号的正确逻辑的获得。 [0034] In summary, the present invention is the design of the selected row, to achieve the correct selection of the correct logic row from the memory array of nine storage units and a control signal to the storage unit.

[0035] 给出一个实现本发明所述行选择功能的具体的电路图如图4所示。 Specific circuit [0035] of the present invention to achieve a given row select function is shown in Fig.

[0036] 下面结合图5所示的实验仿真效果图,证明由九管存储单元的存储器应用本发明所述行选择器的正确性。 [0036] The simulation results shown in Figure 5 in conjunction with FIG proved by the present invention, the memory means stores nine correctness of applying the row selector.

[0037] 以九管存储单元为核心搭建一个8K大小的完整存储器,将本发明应用其中并对其进行了读写功能测试,测试结果如下: [0037] In nine memory cells as the core to build a complete memory size of 8K, the present invention is applied wherein the read and write functions and its test results are as follows:

[0038] 图中所述输入数据为8位的十六进制数据,Row为行地址信号,Write为写控制信号,Read为读控制信号,读出数据为8位的十六进制数据,应与输入数据相同,elk为时钟信号。 [0038] FIG said input data is 8-bit hexadecimal data, Row to row address signals, Write write control signal, the Read is a read control signal, readout data is 8-bit hexadecimal data, It should be identical to the input data, elk clock signal. 由图看出,4ns时写入数据1,19ns时读出数据1 ;28ns和40ns时连续写入数据7和f,55ns和63ns时分别读出7和f。 Seen from the figure, when data is read out write data 1,19ns 1 4ns; 7 and write data continuously during 28ns and 40ns f, and f, respectively when read 7 55ns and 63ns. 说明了本发明的正确性和可用性。 To illustrate the validity and the availability of the present invention.

Claims (2)

1.适应九管存储单元读写功能的行选择器,其特征在于,它包括三输入与门(1)、二输入与门(2)和非门(3),三输入与门(1)的第一输入端为写控制信号输入端,三输入与门(1)的第三输入端为非门端,三输入与门(1)的输出端为行选择写使能信号输出端;三输入与门(1)的第二输入端和二输入与门(2)的第一输入端为行地址信号输入端,二输入与门(2)的第二输入端和非门(3)的输入端为读控制信号输入端,非门⑶的输出端和三输入与门⑴的非门端相连,二输入与门⑵的输出端为行选择读使能信号输出端。 1. accommodate nine read and write functions of the memory cell row selector, characterized in that it comprises a three-input AND gate (1), a two-input AND gate (2) and a non-door (3), three-input AND gate (1) a first input terminal of the write control signal input terminal, a third input terminal of three-input aND gate (1) a non-gate terminal of the three-input aND gate (1) to the output terminal of the row select write enable signal output terminal; third a second aND gate input terminal (1) and a first input terminal of two-input aND gate (2) is a row address signal input terminal, a two-input aND gate (2) and a second input terminal of the NAND gate (3) input of the read control signal input terminal, an output terminal of the NAND gate ⑶ three-input aND gate and a NAND gate ⑴ terminal coupled to the output terminal of two-input aND gate for row selection ⑵ read enable signal output terminal.
2.根据权利要求1所述的适应九管存储单元读写功能的行选择器,其特征在于,写控制信号输入端、行地址信号输入端和读控制信号输入端都是高电平有效。 According to claim 1 adapted to read or write memory nine row selector function, wherein the write control signal input terminal, a row address signal input terminal and a read control signal input terminal is active high.
CN 200910072234 2009-06-10 2009-06-10 Line selector applicable to reading and wiring functions of nine-transistor memory unit CN101567214B (en)

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CN1524271A (en) 2001-01-31 2004-08-25 摩托罗拉公司 Content addressable magnetic random access memory
CN1561522A (en) 2001-09-28 2005-01-05 睦塞德技术公司 Circuit and method for performing variable width searches in a content addressable memory
US6657878B2 (en) 2002-02-27 2003-12-02 Integrated Device Technology, Inc. Content addressable memory (CAM) devices having reliable column redundancy characteristics and methods of operating same
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