CN101546602B - Nonvolatile memory device using variable resistance element - Google Patents

Nonvolatile memory device using variable resistance element Download PDF

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CN101546602B
CN101546602B CN 200810131440 CN200810131440A CN101546602B CN 101546602 B CN101546602 B CN 101546602B CN 200810131440 CN200810131440 CN 200810131440 CN 200810131440 A CN200810131440 A CN 200810131440A CN 101546602 B CN101546602 B CN 101546602B
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write
bit line
local
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CN101546602A (en
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崔炳吉
赵栢衡
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三星电子株式会社
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Abstract

一种非易失性存储器设备,包括多个存储器组,每个存储器组包括多个非易失性存储器单元。 A nonvolatile memory device comprising a plurality of memory banks, each memory group including a plurality of nonvolatile memory cells. 每个单元包括可变电阻元件,所述可变电阻元件具有根据存储的数据而变化的电阻。 Each cell includes a variable resistive element, said resistive element having a variable resistance based on the stored data varies. 包括多个全局位线,每个全局位线被多个存储器组共享。 Comprising a plurality of global bit lines, each global bit line is shared by a plurality of memory banks. 多个主字线对应于多个存储器组中的一个排列。 A plurality of main word lines are arranged corresponding to a plurality of memory banks.

Description

使用可变电阻元件的非易失性存储器设备 Variable resistor element of a nonvolatile memory device

技术领域 FIELD

[0001] 本发明的示例实施例涉及使用可变电阻元件的非易失性存储器设备。 Example [0001] Example embodiments of the present invention relates to a nonvolatile memory device using the variable resistor element.

背景技术 Background technique

[0002] 使用电阻材料的非易失性半导体存储设备分为NOR闪存设备、NAND闪存设备、相变随机存取存储器(PRAM)设备等。 [0002] The use of resistive material nonvolatile semiconductor memory device is divided into a NOR flash memory devices, NAND flash memory devices, phase change random access memory (PRAM) devices. 然而,动态随机存取存储器(DRAM)设备或闪存设备使用电荷写数据,相变随机存取存储器(PRAM)使用例如硫合金的相变材料存储数据,由于加热后的冷却所造成的温度改变,所述相变材料进入晶态或非晶态(amorphous state)。 However, a dynamic random access memory (DRAM) device or a flash device using a charge write data, phase change random access memory (PRAM) using a phase change material for storing data, for example, sulfur alloy, the temperature of the cooling after the heating caused by the change, the phase change material into the crystalline or amorphous (amorphous state).

[0003] 换言之,由于多数处于晶态的相变材料的电阻低,而非晶态相变材料的电阻高,因此,晶态被称为设定态或“O”态,而非晶态称为复位态或“I”态。 [0003] In other words, since the majority of the low resistance crystalline state phase change material, and the resistance of the amorphous phase change material is high, thus, the crystalline state is referred to as a set state or a "O" state, and said amorphous reset state or a "I" state. PRAM设备通过使用将设定脉冲或复位脉冲应用到相变材料所产生的焦耳热来写数据。 PRAM devices by using a set pulse or reset pulse is applied to the phase change material, Joule heat generated to write data. 详细地,通过使用复位脉冲将PRAM单元的相变材料加热到高于其熔点、并快速冷却相变材料以使相变材料的状态变为非晶态,或者通过将相变材料加热到低于其结晶点、维持得到的温度预定时间量、并冷却相变材料以使相变材料的状态变为晶态,向PRAM单元写数据。 In detail, by using a reset pulse to the phase change material PRAM cell is heated above its melting point and rapidly cooling the phase change material in the phase change material becomes the amorphous state, or by heating to below the phase change material crystallization point, to maintain the amount of time to give a predetermined temperature and cooling the phase change material in the phase change material changes to the state of crystalline state, write data to the PRAM unit.

[0004] 图1和图2是用于说明传统的非易失性存储器设备的排列的电路图。 [0004] FIG. 1 and FIG. 2 is a circuit diagram for explaining the arrangement of a conventional nonvolatile memory device. 为方便说明,图1和图2示出传统的非易失性存储器设备包括8个存储器组,但其也可包括不同数量的存储器组。 For convenience of illustration, FIGS. 1 and 2 show a conventional nonvolatile memory device comprises eight memory banks, but it may also include different numbers of memory banks.

[0005] 参考图1,传统的非易失性存储器设备包括多个存储器组10_1到10_8、全局列选择电路30_1到30_8、全局读出放大器(amp)电路40_1到40_8、和/或全局写驱动器电路50_1到50_8。 [0005] Referring to FIG 1, a conventional nonvolatile memory device comprising a plurality of memory banks 10_1 to 10_8, 30_1 to the global column select circuit 30_8, the global sense amplifier (amp) circuits 40_1 to 40_8, and / or global write driver circuits 50_1 to 50_8. 具有更高容量和更高集成密度的非易失性存储器设备可使用分级位线结构和分级字线结构来实现,在所述分级位线结构中,多个局部位线连接到每个全局位线,在所述分级字线结构中,多个子字线耦合到每个主字线。 The nonvolatile memory device having a higher capacity and higher integration density with a hierarchical bit line structure and a hierarchical word line structure is achieved, the hierarchical bit line structure, a plurality of local bit lines coupled to each global bit line in the hierarchical word line structure, a plurality of sub-word line is coupled to each of the main word line. 如图1所示,全局位线GBL对应于多个存储器组10_1到10_8中的每个来排列。 As shown, the global bit line GBL are arranged corresponding to each one of the plurality of memory banks 10_1 to 10_8. 主字线方向对应于多个存储器组10_1到10_8来排列。 A main word line direction corresponding to the plurality of memory groups are arranged 10_1 to 10_8.

[0006] 当全局位线GBL对应于多个存储器组10_1到10_8中的每个来排列时,传统的非易失性存储器设备具有如图2所示的核心架构。 [0006] When the global bit line GBL 10_1 corresponding to the plurality of memory groups are arranged in each 10_8, conventional nonvolatile memory device having a core architecture shown in FIG. 参考图2,多个主字线解码器20_1到20_8和多个冗余存储器单元阵列12_1到12_8对应于多个存储器组10_1到10_8来排列。 Referring to FIG 2, a plurality of main word line decoder 20_1 to 20_8 and a plurality of redundant memory cell arrays 12_1 to 12_8 corresponding to the plurality of memory groups are arranged 10_8 to 10_1.

[0007] 在同步脉冲读操作期间,根据正被预取的字的数量,具有图2所示的核心架构的传统的非易失性存储器设备需要全局读出放大器电路401到408中的读出放大器的数量的显著增长。 [0007] The read operation during the synchronization pulses, according to the number of words being prefetched, with a conventional nonvolatile memory device shown in FIG. 2 core architecture requires global sense amplifier in the read circuit 401 to 408 a significant increase in the number of amplifiers. 例如,如果要从一个存储器组(例如10_1)内读取并预取的字的数量为4,那么在一个全局读出放大器电路(例如40_1)内所需的读出放大器的数量是64 (I字(16位)X 4)。 For example, if the number of words read from the one memory group (e.g., 10_1), and prefetching is 4, then in a global sense amplifier circuit (e.g., 40_1) required to read the number of the amplifier is 64 (I word (16-bit) X 4). 这样,在8个全局读出放大器电路40_1到40_8中,需要512(64X8)个读出放大器。 Thus, the eight global sense amplifier circuit 40_1 to 40_8 in the required 512 (64X8) sense amplifiers. 若从一个存储器组中预取8个字,则需要1024个读出放大器。 If the prefetch eight words from one memory group in the 1024 sense amplifiers. 若从一个存储器组中预取16个字,则需要2048个读出放大器。 If the prefetch memory 16 words from a group, the 2048 sense amplifiers required. 也就是说,随着要预取的字的数量增加,核心架构的面积相应增加。 In other words, as the number of words to be prefetched, a corresponding increase in the area of ​​core architecture.

[0008] 测试操作期间,也难以在一个存储器组(例如101)中写入大量的数据位。 During the test. [0008], it is difficult to set in a memory (e.g., 101) to write large amounts of data bits. 假设在将复位数据写到一个非易失性存储器单元时、流过一个非易失性存储器单元的复位电流约为1mA,则每次将16位数据写入存储器组101可能需要约16mA的复位电流。 When the reset is assumed that data is written to a nonvolatile memory cell, a reset current flowing through the non-volatile memory units is about 1mA, each time the 16-bit data written in the memory 101 may need to reset groups of about 16mA current. 也就是说,由于过高级别的复位电流流入到存储器组10_1 (窄空间),因此,难以每次写入大量数据位。 That is, since the high level of reset current flows to the memory group 10_1 (narrow space), and therefore, a large amount of data each time it is difficult to write bits. 这样,因为在测试操作期间每次应当写入少量数据位,所以需要大量测试时间。 Thus, as should be written in small data bit during a test operation, it requires a lot of testing time.

[0009] 进一步地,因为对应于多个存储器组10_1到10_8排列多个主字线解码器20_1到20_8,所以增加了核心架构的面积。 [0009] Further, since the plurality of memory groups corresponding to 10_1 to 10_8 are arranged a plurality of main word line decoders 20_1 to 20_8, it increases the area of ​​the core architecture. 因为存储器组10_1到10_8内的非易失性存储器单元和冗余存储器单元阵列12_1到12_8内的冗余存储器单元共享同一字线WL,所以对应于多个存储器组10_1到10_8来排列多个冗余存储器单元阵列12_1到12_8,所以,进一步增加了核心架构的面积。 Because the memory 10_1 group nonvolatile memory cells and the redundant memory cell array 10_8 to 12_1 to 12_8 in the redundant memory cells share the same word line WL, so that the plurality of memory groups corresponding to 10_1 to 10_8 are arranged in a plurality of redundant it 12_1 to 12_8 memory cell array, so further increasing the area of ​​the core architecture.

发明内容 SUMMARY

[0010] 本发明涉及一种非易失性存储器设备及其构成方法。 [0010] The present invention relates to a nonvolatile memory device and a method of configuration.

[0011] 该非易失性存储器设备包括多个存储器组,每个存储器组包括多个非易失性存储器单元。 [0011] The nonvolatile memory device comprises a plurality of memory banks, each memory group including a plurality of nonvolatile memory cells. 每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件。 Each unit comprises a resistor having a variable resistance element based on the stored data varies. 包括多个全局位线,并且每个全局位线被多个存储器组共享。 Comprising a plurality of global bit lines, and each global bit line is shared by a plurality of memory banks. 对应于多个存储器组中的一个来排列多个 Corresponding to the plurality of memory groups are arranged in a plurality of

主字线。 Main word line.

附图说明 BRIEF DESCRIPTION

[0012] 通过参考附图来详细说明示例实施例,本发明的上述及其它特征和优点将更明显,附图中: [0012] described in detail by reference to the drawings exemplary embodiments, the above and other features and advantages of the invention will become apparent drawings in which:

[0013] 图1和图2是用于说明传统的非易失性存储器设备的排列的电路图; [0013] FIG. 1 and FIG. 2 is a circuit diagram for explaining an arrangement of a conventional nonvolatile memory device;

[0014] 图3是用于说明根据本发明实施例的非易失性存储器设备的方框图; [0014] FIG. 3 is a block diagram showing a nonvolatile memory device according to an embodiment of the present invention for explaining;

[0015] 图4是根据本发明实施例的非易失性存储器设备的方框图; [0015] FIG. 4 is a block diagram showing a nonvolatile memory device according to an embodiment of the present invention;

[0016] 图5是用于更详细说明图4中的非易失性存储器设备的概念电路图; [0016] FIG. 5 is a more detailed circuit diagram of the concept of FIG. 4 in the nonvolatile memory device;

[0017] 图6是用于说明根据本发明实施例的非易失性存储器设备的读写操作的概念电路图; [0017] FIG. 6 is a circuit diagram for explaining a concept of write nonvolatile memory device according to an embodiment of the present invention operate;

[0018] 图7A-7D是局部列选择电路的示例图;以及 [0018] Figures 7A-7D are exemplary diagrams of a local column selection circuit; and

[0019] 图8A和图SB是根据本发明实施例的非易失性存储器设备的示例性横截面图。 [0019] FIGS. 8A and SB is a cross-sectional view of an exemplary nonvolatile memory device according to an embodiment of the present invention. 具体实施方式 Detailed ways

[0020] 通过参考以下示例实施例和附图的具体说明,可更容易理解本发明的优点和特征及其实现方法。 DETAILED DESCRIPTION OF THE DRAWINGS Examples and [0020] by reference to the following exemplary embodiments may be more readily understood advantages and features of the present invention and its implementation. 但是,本发明可以不同形式实现,并且不应仅解释为限制于此处描述的实施例。 However, the present invention can be implemented in different forms and should not be construed as limited to only the embodiments described herein. 而是,提供了这些实施例,使得本公开将是完整和彻底的,并且将对本领域技术人员完全传达本发明的观念,同时本发明将仅由权利要求所限定。 Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the person skilled in the concept of the present invention, while the present invention will be limited only by the claims. 遍及说明书,相同的标号表示相同的元件。 Throughout the specification, like reference numerals denote like elements.

[0021] 将理解,当某个元件或层被称为“连接到”或“耦合到”另一元件时,它可直接连接或耦合到另一元件或层,或者可存在中间元件。 [0021] It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or layer, or intervening elements may be present. 相反地,当某个元件被称为“直接连接到”或“直接耦合到”另一元件时,不存在中间元件。 In contrast, when an element is referred to as being "directly connected to" or "directly coupled" to another element, there are no intervening elements present. 遍及全文相同的标号表示相同的元件。 Throughout the text the same reference numerals denote the same elements. 如此处使用的,术语“和/或”包括一个或多个相关联列出的项目的任何和所有的组合。 As used herein, the term "and / or" includes one or more of the associated listed items any and all combinations. [0022] 虽然在下面的不同部分中或基于一个实施例接实施例地分别说明示例实施例,但除非指明,各描述并非互不相关。 [0022] Although in different portions or below based on one embodiment, the ground Example illustrate exemplary embodiments, unless specified, each description is not unrelated. 它们全部或部分地是彼此的变体,并且有时一个描述是另一描述的详细或补充形式。 They are wholly or partially variants of each other, and sometimes a further description is described in greater detail or supplement form. 在下述示例实施例中,即使当为元件指示特定数字符号(量、数值、数量、范围等),也不限制为所指示的特定数字符号,除非另有指明或理论上限定到该特定数字符号;应当理解它可以大于或小于特定的数字符号。 In the following exemplary embodiment, even when a number indicating a particular symbol (amount, numerical value, quantity, range and the like) of elements, not limited to a particular number of symbols indicated, unless otherwise indicated or defined theoretically to the specific digital symbols ; it should be understood that it may be greater or less than a specified number sign. 在下述实施例中,元件(包括元件步骤)并非总是必要的,除非另外指明或清楚地认为是必要的。 Embodiment, the elements (including element steps) are not always necessary in the following examples, unless otherwise specified or clearly considered necessary. 同样地,当在下述实施例中指示元件的形状或位置时,认为也包括与之基本相等或类似的形状或位置,除非另外指明或清楚地认为并非如此。 Likewise, when the shape or position of the elements indicated in the following examples, that also includes a position or a shape similar thereto, or substantially equal, unless otherwise indicated or clearly do not think so. 这对上述数字符号和范围保持成立。 This holds true for the digital symbols and scope. 在图示示例实施例的所有附图中,具有相同功能的元件被指定相同的参考标号;并且这些元件的说明不再重复。 In all drawings illustrate exemplary embodiments, elements having the same functions are assigned the same reference numerals; and descriptions of these elements will not be repeated.

[0023] 将理解,虽然术语第一、第二和其他在此可用于描述不同的元件,但这些元件不应被这些术语所限定。 [0023] It will be understood that although the terms first, second, and others may be used herein to describe various elements, these elements should not be limited by these terms. 这些术语仅用于将一个元件与另一个元件区分。 These terms are only used to distinguish one element from another element. 这样,在不违背本发明教导的情况下,下述第一元件可称为第二元件。 Thus, without departing from the teachings of the present invention, following a first element could be termed a second element.

[0024] 如“在......之下”,“在......下面”,“低于”,“在上面”,“上面的”等的空间相 [0024] such as "beneath ......", "at ...... below," "lower," space "above", "upper" and the like with

关的术语在此可用来方便描述,以描述如附图所示的一个元件或特征与(多个)另外的元件或(多个)特征的关系。 Related term used to the convenience of description, as shown in the drawings to describe one element or feature's relationship (s) or additional element (s) features. 将理解,空间相关的术语意在包括除图中的方向外使用或操作中的设备的不同方向。 It will be understood that the spatially relative terms are intended to encompass different orientations of the use or operation of the apparatus in addition to the direction of FIG. 例如,如果图中的设备被反转,则描述为“在其他元件或特征下面”或“在其他元件或特征之下”的元件将朝向在其他元件或特征的“上面”。 For example, if the device in the figures is inverted, elements described as "the other elements or features below" or "beneath other elements or features" will be towards the other elements or features "above." 这样,示例性术语 Thus, the exemplary term

“在......下面”可包括在上面和在下面的两个方向。 "In ...... below" can encompass both directions above and below. 设备可另有朝向(旋转90度或在其 Another device may be oriented (rotated 90 degrees or at its

他方向),并且在此使用的空间相关的术语相应地解释。 He direction), and the terms used herein in the space associated with a corresponding explanation.

[0025] 此后,将关于PRAM描述本发明的示例性实施例。 [0025] Thereafter, the exemplary embodiments of the present invention is described with respect to PRAM. 然而,本领域技术人员将显而易见,本发明也可应用于使用电阻材料的非易失性半导体存储器设备,如相变RAM(PRAM),磁RAM(MRAM)等。 However, it will be apparent to those skilled in the art, the present invention is also applicable to a nonvolatile semiconductor memory device using resistance material, phase change RAM (PRAM), magnetic RAM (MRAM) and the like.

[0026] 图3是用于说明根据本发明实施例的非易失性存储器设备的方框图。 [0026] FIG. 3 is a block diagram showing a nonvolatile memory device according to an embodiment of the present invention to be described. 为了说明方便,图3示出具有8个存储器组的非易失性存储器设备,但它也可包括不同数量的存储器组。 For convenience of explanation, FIG. 3 shows a nonvolatile memory device having 8 memory banks, but it may also include different numbers of memory banks.

[0027] 参考图3,非易失性存储器设备包括多个存储器组110_1到110_8、全局列选择电路130、全局读出放大器(amp)电路140、和/或全局写驱动器电路150、冗余存储器单元阵列112和主字线解码器120。 [0027] Referring to FIG 3, the nonvolatile memory device comprises a plurality of memory banks 110_1 to 110_8, global column select circuit 130, the global sense amplifier (amp) circuit 140, and / or global write driver circuit 150, the redundant memory cell array 112 and a main word line decoder 120.

[0028] 虽然图3中未显示,但存储器组110_1到110_8的每个包括多个非易失性存储器单元,每个单元包括可变电阻元件和存取元件,可变电阻元件具有根据存储的数据变化的电阻,存取元件控制流过可变电阻元件的电流。 [0028] Although not shown in FIG. 3, but the memory bank 110_1 to 110_8 each include a plurality of nonvolatile memory cells, each cell comprising a variable resistive element and an access element, having a variable resistive element according to a stored resistance change data, the access element controls the current flowing through the variable resistive element. 可变电阻元件可由各种种类的材料构成,如二元(2个元素)化合物(例如,GaSb> InSb、或InSe),三元(3个元素)化合物(例如,GeSbTe、GaSeTe、InSbTe、SnSb2Te4 或InSbGe),或四元(4 个元素)化合物(例如,AglnSbTe、(GeSn) SbTe,GeSb (SeTe)或Te81Ge15Sb2S2)。 The variable resistive element may be formed of various kinds of materials, such as glycols (element 2) compound (e.g., GaSb> InSb, or an InSe), three yuan (three elements) of the compound (e.g., GeSbTe, GaSeTe, InSbTe, SnSb2Te4 or InSbGe), or quaternary (four elements) compound (e.g., AglnSbTe, (GeSn) SbTe, GeSb (SeTe) or Te81Ge15Sb2S2). 最常用的材料是GeSbTe。 The most commonly used material is GeSbTe. 存取元件可包括二极管、场效应(FET)晶体管、NPN双极晶体管、PNP双极晶体管或其他半导体设备。 Access member may include a diode, a field effect (FET) transistor, the NPN bipolar transistor, the PNP bipolar transistors or other semiconductor devices.

[0029] 更高容量和更高集成密度的非易失性存储器设备可使用分级位线结构和分级字线结构实现,在所述分级位线结构中,多个局部位线连接到每个全局位线,在所述分级字线结构中,多个子字线耦合到每个主字线。 [0029] The higher capacity and higher integration density of a nonvolatile memory device may use the hierarchical bit line structure and a hierarchical word line structure implemented in the hierarchical bit line structure, a plurality of local bit lines coupled to each global bit line in the hierarchical word line structure, a plurality of sub-word line is coupled to each of the main word line. 参考图3,多个全局位线GBLO到GBLn+Ι中的每个对应于多个存储器组110_1到110_8来排列。 Referring to Figure 3, a plurality of global bit lines GBLO GBLn + Ι to each of the plurality of memory groups corresponding to 110_1 to 110_8 are arranged. 多个主字线中的每个对应于多个存储器组110_1到110_8之一而提供。 A plurality of main word lines each corresponding to one of the plurality of memory banks 110_1 and 110_8 provided.

[0030] 全局读出放大器电路140耦合到多个全局位线GBLO到GBLn+Ι,并且通过多个全局位线GBLO到GBLn+Ι,从多个存储器组110_1到110_8内的非易失性存储器单元中读取数据。 [0030] global sense amplifier circuit 140 is coupled to the plurality of global bit lines GBLO GBLn + Ι, and GBLO to GBLn + Ι by a plurality of global bit lines, from the plurality of memory banks 110_1 to 110_8 of the non-volatile memory unit to read data. 全局写驱动器电路150耦合到多个全局位线GBLO到GBLn+Ι,并且通过多个全局位线GBLO到GBLn+Ι,向多个存储器组110_1到110_8内的非易失性存储器单元写入数据。 Global write driver circuit 150 is coupled to the plurality of global bit lines GBLO GBLn + Ι, and GBLO to GBLn + Ι by a plurality of global bit lines, a plurality of write data to memory banks 110_1 in the nonvolatile memory cells to 110_8 .

[0031] 主字线解码器120耦合到多个主字线,并且选择性地选择多个主字线,每个主字线对应于多个存储器组110_1到110_8中的一个来提供。 [0031] The main word line decoder 120 is coupled to a plurality of main word lines, and a plurality of selectively selecting main word lines, each master word line corresponding to a plurality of memory banks 110_1 to 110_8 provided. 这样,因为多个存储器组110_1到110_8共享主字线解码器120和冗余存储器单元阵列112,所以减小了核心架构的面积。 Thus, since a plurality of memory banks 110_1 to 110_8 shared main word line decoder 120 and the redundant memory cell array 112, thus reducing the area of ​​the core architecture.

[0032] 图4是根据本发明实施例的非易失性存储器设备的方框图。 [0032] FIG. 4 is a block diagram showing a nonvolatile memory device according to an embodiment of the present invention.

[0033] 参考图4,每个全局位线包括写全局位线(WGBL)和读全局位线(RGBL),写全局位线(WGBL)用于向多个存储器组110_1到110_8写入数据,读全局位线(RGBL)用于从多个存储器组110_1到110_8中读取数据。 [0033] Referring to FIG 4, each global bit line comprises a write global bit line (WGBL) and the read global bit line (RGBL), the write global bit lines (WGBL) for writing data to a plurality of memory banks 110_1 to 110_8, a read global bit line (RGBL) for reading data from the plurality of memory banks 110_1 to 110_8. 具有该配置的非易失性存储器设备可容易地在写操作期间执行读操作(例如,当写入时读取)。 The nonvolatile memory device having this configuration can easily be performed in a read operation during a write operation (e.g., when the read write).

[0034] 在根据本发明的非易失性存储器设备中,多个存储器组110_1到110_8的每个被分为多个子块SO到S7。 [0034] In the plurality of sub-blocks SO nonvolatile memory device according to the present invention, the plurality of memory banks 110_1 to 110_8 are each divided into S7. 全局读出放大器电路(例如图3中的140)包括分别对应于多个子块SO到S7的第一到第八读出放大器电路140_1到140_8。 Global sense amplifier circuit (e.g., 140 in FIG. 3) comprises a plurality of respectively corresponding to SO to the first to eighth sub-blocks of the read amplifier circuit S7 140_1 to 140_8. 全局写驱动器电路(例如图3中的150)包括分别对应于多个子块SO到S7的第一到第八全局写驱动器电路150_1到150_8。 Global write driver circuit (e.g., 150 of FIG. 3) comprises a plurality of respectively corresponding to the first to eighth sub-blocks SO through S7 global write driver circuit 150_1 to 150_8. 全局列选择电路(例如图3中的130)包括分别对应于多个子块SO到S7的第一到第八全局列选择电路130_1到130_8。 Global column selection circuit (e.g., 130 in FIG. 3) comprises first to eighth global corresponding to a plurality of sub-blocks SO through S7 column selection circuit 130_1 to 130_8.

[0035] 图5是用于更详细说明图4中的非易失性存储器设备的概念电路图。 [0035] FIG. 5 is a more detailed circuit diagram of the concept of FIG. 4 in a non-volatile memory device.

[0036] 参考图5,非易失性存储器设备包括在写操作期间使用的多个独立的写全局位线WGBLO到WGBLn、以及在读操作期间使用的多个独立的读全局位线RGBLO到RGBLn。 [0036] Referring to FIG 5, the nonvolatile memory device comprises a plurality of individual write global bit line WGBLO to WGBLn, and a plurality of independent read global bit line for use during a read operation for use during a write operation to RGBLO RGBLn.

[0037] 这样,全局列选择电路130响应于写全局列选择信号WGYO到WGYn和读全局选择信号RGYO到RGYn,分别选择多个写全局位线WGBLO到WGBLn和多个读全局位线RGBLO到RGBLn。 [0037] Thus, global column select circuit 130 in response to a write to a global column select signal WGYO WGYn selection signal and a read global RGYO to RGYn, were selected plurality of write global bit lines and a plurality of read WGBLn WGBLO to the global bit line to RGBLn RGBLO . 也就是说,选择晶体管被布置到每个读全局位线RGBLO到RGBLn和每个写全局位线WGBLO到WGBLn中。 That is, the selection transistor is disposed to each of the read global bit line RGBLO RGBLn to write global bit line and each WGBLO to the WGBLn. 读全局位线RGBLO到RGBLn中的选择晶体管在其栅极处接收读全局列选择信号RGYO到RGYn中各自的一个,并且写全局位线WGBLO到WGBLn中的选择晶体管在其栅极处接收写全局列选择信号WGYO到WGYn中各自的一个。 RGBLO to read global bit line selection transistor RGBLn at its gate receives a read global column selection signal RGYO RGYn to a respective one of the write global bit line and the WGBLO WGBLn selection transistor receives at its gate a write global WGYO WGYn column select signal to a respective one.

[0038] 响应于写局部列选择信号WLYO到WLYn,局部列选择电路155选择性地稱合多个局部位线LBLO到LBLn与相应的写全局位线WGBLO到WGBLn。 [0038] In response to a write to the local column select signal WLYO WLYn, the local column selection circuit 155 for selectively closing said plurality of local bit lines LBLO to LBLn the write global bit line corresponding to WGBLO WGBLn. 响应于读局部列选择信号RLYO到RLYn,局部列选择电路155选择性地耦合到多个局部位线LBLO到LBLn与相应的读全局位线RGBLO到RGBLn。 The local response to the read column select signal to RLYO RLYn, the local column selection circuit 155 selectively coupled to the plurality of local bit lines LBLO to LBLn corresponding to the read global bit line RGBLO to RGBLn. 局部列选择电路155的示例性配置将在下面参考图7A到7D详细说明。 Local column selection circuit 155 of the exemplary configuration. 7A to 7D described in detail below with reference to FIG.

[0039] 图6是用于说明根据本发明实施例的非易失性存储器设备的读写操作的概念电路图。 [0039] FIG. 6 is a conceptual circuit diagram of the read and write non-volatile memory device of the present embodiment of the invention operation.

[0040] 参考图6,读出放大器的数量随要在同步脉冲读操作期间预取的字的数量变化。 6, the number of changes with the number of sense amplifiers to the sync pulse during a read operation of the prefetch word [0040] Referring to FIG. 例如,如果要从一个存储器组读取并预取的字的数量为4,则全局读出放大器电路140需要64(I字(16位)X4)个读出放大器。 For example, if the number of words from a set of read memory and a prefetch is 4, then the global sense amplifier circuit 140 requires 64 (I word (16 bits) X4) sense amplifiers. 若从一个存储器组中预取8个和16个字,则全局读出放大器电路140可分别包括128个和256个读出放大器。 If the prefetch 8 and 16 words from one memory group in the global sense amplifier circuit 128 and 140 may include sense amplifiers 256, respectively. [0041] 进一步,为了写nXm组数据(η和m是大于I的整数),根据本实施例的非易失性存储器设备可在测试操作期间同时向η个子块中写入m组数据。 [0041] Further, in order to write data nXm group ([eta] and m is an integer of I), m sets of data can be simultaneously written to the [eta] th sub-block during a test operation of a nonvolatile memory device according to the present embodiment.

[0042] 例如,如图6所示,为向一个存储器组(例如110_1)中写入16(例如8X2)组数据,可在测试操作期间向8个子块中同时写入两组数据。 [0042] For example, as shown in Figure 6, it is a (e.g., 110_1) is written into a memory bank 16 (e.g. 8X2) set of data, two sets of data can be written simultaneously into 8 sub-blocks during a test operation. 在正常操作期间,两组数据可被重复8次写入一个子块(例如S0)中。 During normal operation, the two sets of data may be repeated eight times to write a sub-block (e.g., S0) in. 也就是说,因为通过测试器施加写入电流,所以测试操作期间可同时写入16组数据。 That is, since the write current is applied by the tester, it is possible to simultaneously write data set 16 during a test operation. 因为对电流驱动能力的限制,所以在正常操作期间非易失性存储器设备向一个子块中重复写入数据,而非向多个子块SO到S7中同时写入数据。 Since current drive capability limit, the nonvolatile memory device during normal operation is written to a duplicate data sub-block, rather than a plurality of sub-blocks SO through S7 to simultaneously write data. 但是,在正常操作期间,具有足够电流驱动能力的非易失性存储器设备可向多个子块中同时写入数据。 However, during normal operation, the nonvolatile memory device having a sufficient current driving capability of the data can be written simultaneously to a plurality of sub-blocks. 因为设定/复位电流可流入多个子块SO到S7 (即,在宽区域中),所以在测试期间可每次写入16组数据。 Because the set / reset current may flow into a plurality of sub-blocks SO to S7 (i.e., in a wide region), so that during the test group 16 may each write data. 也就是说,因为测试期间可同时写入大量数据,所以测试时间可显著降低。 That is, since large amounts of data can be written at the same time during the test, the test time can be significantly reduced.

[0043] 图7A-7D是局部列选择电路155的示例性电路图。 [0043] Figures 7A-7D are circuit diagram of an exemplary local column selection circuit 155.

[0044] 参考图7A-7D,图5的局部列选择电路155包括(多个)写局部列选择电路(图7A或图7B中的170_1和170_2、或者图7C或图7D中的170)和(多个)读局部列选择电路(图7A或图7B中的160_1和160_2、或图7C或图7D中的160)。 [0044] with reference to FIGS. 7A-7D, FIG. 5 is a partial column selecting circuit 155 comprises a (plurality of) partial write column select circuit (FIG. 7A or FIG. 7B 170_1 and 170_2, or FIG. 7C 170 7D or in FIG.) And (s) reading the local column select circuit (FIG. 7A or FIG. 7B 160_1 and 160_2, or in FIG. 7C or Fig 7D 160). 在写操作期间,响应于写局部列选择信号WLYO到WLY7,(多个)写局部列选择电路耦合局部位线LBLO到LBL7与写全局位线WGBL。 During a write operation, in response to a write to the local column select signal WLYO WLY7, (a plurality of) partial write column select circuit coupled to the local bit lines LBLO LBL7 the write global bit line WGBL. 在读操作期间,响应于读局部选择信号RLYO到RLY7,(多个)读局部列选择电路耦合局部位线LBLO到LBL7与读全局位线RGBL。 During a read operation, in response to the read to the local selection signal RLYO RLY7, (a plurality of) partial read column select circuit coupled to the local bit lines LBLO LBL7 read global bit line RGBL. 存储器单元阵列包括位于子块(图4中的SO到S7)内并耦合到局部位线LBLO到LBL7的多个非易失性存储器单元。 The memory cell array includes a sub-block (SO 4 to FIG S7) and coupled to the local bit lines LBLO to LBL7 plurality of nonvolatile memory cells.

[0045] 如图7A的实施例所示,写局部列选择电路170_1和170_2布置在单元阵列的任一侦U。 As shown in Example [0045] FIG. 7A, a partial write column selection circuit 170_1 and 170_2 are arranged in either a cell array investigation U. 写局部列选择电路170_1和170_2的每个包括在数量上对应于单元阵列的局部位线的多个选择晶体管。 170_1 partial write column selection circuit and a plurality of select transistors each comprising a cell array corresponding to the number of bit lines 170_2 Board. 每个选择晶体管被连接在写全局位线WGBL和局部位线LBLO到LBL7中各自的一个之间;并且接收写局部列选择信号WLYO到WLY7中各自的一个。 Each selection transistor being connected between a respective LBL7 a WGBL write global bit line and local bit lines LBLO to; and receiving the write column select signal WLYO local WLY7 to a respective one. 读局部列选择电路160_1和160_2也布置在单元阵列的任一侧。 Local read column select circuit 160_2 and 160_1 are also arranged on either side of the cell array. 但是,读局部列选择电路1601仅包括对应于偶数编号的局部位线的选择晶体管,而读位列选择电路1602包括对应于奇数编号的局部位线的选择晶体管。 However, the local read only column selection circuit 1601 comprises a transistor corresponding to the selected bit lines of even-numbered Bureau, ranked read circuit 1602 includes a selection corresponding to the odd-numbered local bit line selection transistor. 特别地,读局部列选择电路1601的选择晶体管被连接在读全局位线RGBL和局部位线LBLO、LBL2、LBL4和LBL6中各自的一个之间;并在其栅极分别接收读局部选择信号RLY0、RLY2、RLY4和RLY6。 In particular, the local column selection circuit 1601 reads the selection transistors are connected RGBL read global bit line and local bit lines LBLO, LBL2, LBL4 and LBL6 between a respective one; partial selection signal and receiving a read RLY0 respectively at their gates, RLY2, RLY4 and RLY6. 读局部列选择电路1602包括选择晶体管,该选择晶体管被连接在读全局位线RGBL和局部位线LBL1、LBL3、LBL5和LBL7之间,并在其栅极接收读局部选择信号RLY1、RLY3、RLY5和RLY7。 Local read column selection circuit 1602 includes a selection transistor, the selection transistor is connected to the read global bit lines and local bit lines LBL1 RGBL, between LBL3, LBL5 and LBL7, and a gate receiving a read partial selection signal RLY1, RLY3, RLY5 and RLY7.

[0046] 在图7B的实施例中,写局部列选择电路170_1和170_2布置在单元阵列的任一侦U。 [0046] In the embodiment of FIG. 7B, a partial write column selection circuit 170_1 and 170_2 are arranged in either a cell array investigation U. 该写局部列选择电路中的每个包括用于单元阵列内的一半局部位线的选择晶体管。 The write column selection transistor for selecting the local bit lines of each circuit includes a cell array within a half innings. 特别地,写局部列选择电路170_1包括选择晶体管,该选择晶体管被连接在写全局位线WGBL和局部位线LBL0、LBL2、LBL4和LBL6之间;且这些选择晶体管在其栅极分别接收写局部选择信号WLYO,WLY2、WLY4和WLY6。 In particular, the local write column selection circuit 170_1 includes a selection transistor, the selection transistor is connected between the write global bit lines and local bit lines WGBL LBL0, LBL2, LBL4 and LBL6; and these partial write select transistor receives at its gate, respectively selection signal WLYO, WLY2, WLY4 and WLY6. 写局部列选择电路170_2包括选择晶体管,该选择晶体管被连接在写全局位线WGBL和局部位线LBLl、LBL3、LBL5和LBL7之间;且这些选择晶体管在其栅极分别接收写局部选择信号WLY1、WLY3、WLY5和WLY7。 Partial write column selection circuit 170_2 includes a selection transistor, the selection transistor is connected between the write global bit lines and local bit lines WGBL LBLl, LBL3, LBL5 and LBL7; and these select transistors respectively receive the partial write select signal at its gate WLY1 , WLY3, WLY5 and WLY7. 在该实施例中,读局部列选择电路160_1和160_2布置在单元阵列的任一侧。 In this embodiment, the local read column selection circuit 160_2 and 160_1 are arranged at either side of the cell array. 读局部列选择电路160_1和160_2都包括与每个局部位线相关联的选择晶体管。 Local read column select circuit 160_2 and 160_1 include associated with each local bit line selection transistor. 特别地,这些读局部列选择电路包括选择晶体管,该选择晶体管被连接在读全局位线RGBL和局部位线LBLO到LBL7中各自的一个之间。 In particular, the local column selection circuit comprises a read select transistor, the selection transistor is connected to the read global bit lines and local bit lines LBLO RGBL LBL7 to a respective one between. 选择晶体管在其栅极也分别接收每个读局部选择信号RLYO到RLY7。 Selection transistor and its gate receives a selection signal for each local read RLYO to RLY7.

[0047] 在图7C的实施例中,单独的读局部列选择电路160布置在单元阵列的一侧,而单独的写局部列选择电路170布置在单元阵列的另一侧。 [0047] In the embodiment of FIG. 7C, a separate local read column select circuit 160 is arranged on one side of the cell array, separate write and the other side of the local column selection circuit 170 is disposed in the cell array. 写局部列选择电路170与图7A中的写局部列选择电路170_2相同,并且读列选择电路160与图7B的读列选择电路160_1相同。 Partial write column select write circuit 170 in FIG. 7A same local column select circuit 170_2, and the read column select circuit 160 of FIG. 7B and the read column selection circuit 160_1 same.

[0048] 如将从上面的讨论意识到的,对每个单元阵列重复关于图7A-7C讨论的上述排列。 [0048] As appreciated from the discussion above, the arrangement is repeated for each cell array on the discussion of Figure 7A-7C. 关于图7D的实施例,对每对单元阵列重复该实施例。 The embodiment of Fig. 7D, the cell array is repeated for each of the embodiments. 在图7D中,图示了示例单元阵列I和2。 In FIG. 7D, an example of the cell array, and I 2. 这些单元阵列共享局部位线LBL0-LBL7。 These cell arrays share the local bit lines LBL0-LBL7. 写局部列选择电路170和读局部列选择电路160布置在单元阵列I和2之间。 Partial write column selection circuit 170 and a read column select circuit 160 partially disposed between the cell arrays and I 2. 写局部列选择电路170和读局部列选择电路160中的每个包括选择晶体管,该选择晶体管在数量上等于单元阵列I和2的相关联部分中的局部位线。 Local column selection circuit 170 write and read each of the local column select circuit 160 includes select transistors in the cell array selection transistor is equal to I and the associated local bit line of the portion 2 in number. 特别地,读局部列选择电路160包括选择晶体管,该选择晶体管被连接在读全局位线RGBL和局部位线LBLO到LBL7之间,且选择晶体管在它们的栅极分别接收读局部选择信号RLO到RL7。 In particular, local read column select circuit 160 includes a selection transistor, the selection transistor is connected to the read global bit lines and local bit lines LBLO RGBL between LBL7, and the read select transistor receives partial selection signal RLO respectively at their gates to RL7 . 类似地,写局部选择电路170的选择晶体管被连接在写全局位线WGBL和局部位线LBLO到LBL7之间,并且选择晶体管分别接收写局部选择信号WLYO到WLY7。 Similarly, a partial write selection circuit 170 select transistors are connected between the write global bit lines and local bit lines LBLO WGBL to LBL7, and the selection transistor receives a write selection signal WLYO to local WLY7.

[0049] 写局部列选择电路和读局部列选择电路可具有不同于图7A-7D中图示的配置的各种其他配置。 [0049] The partial write column selection circuit and a read column selection circuit may partially have various configurations illustrated in FIGS. 7A-7D is different from other configurations.

[0050] 图8A和图SB是根据本发明实施例的非易失性存储器设备的示例性横截面图。 [0050] FIGS. 8A and SB is a cross-sectional view of an exemplary nonvolatile memory device according to an embodiment of the present invention.

[0051] 参考图8A和图SB,根据本实施例的非易失性存储器设备包括P型半导体衬底110,该P型半导体衬底110具有通过在其上形成器件隔离区所限定的活动区域。 [0051] FIG. 8A and SB, nonvolatile memory device according to the present embodiment includes a P-type semiconductor substrate 110, the P-type semiconductor substrate 110 having formed thereon defined by the device isolation region on the active region .

[0052] 在半导体衬底110内形成N+型子字线N+SWL。 [0052] an N + N + type sub-word line SWL in the semiconductor substrate 110.

[0053] 第一绝缘层130在半导体衬底110上形成。 [0053] The first insulating layer 130 is formed on the semiconductor substrate 110. 包括N-和P+型半导体模式132和134的多个单元二极管D,与N+型子字线N+SWL相接触地在第一绝缘层130中形成。 Including N- and P + -type semiconductor pattern and a plurality of cell diodes D 132 134, the N + N + type sub-word line SWL is formed in contact with the first insulating layer 130.

[0054] 第二绝缘层140在第一绝缘层130上形成,并且多个底电极触点(BEC) 142在第二绝缘层140内形成。 [0054] The second insulating layer 140 is formed on the first insulating layer 130, and a plurality of bottom electrode contacts (BEC) 142 formed in the second insulating layer 140. 每个BEC142与单元二极管D各自的一个接触。 Each cell diode D BEC142 with a respective one of the contact.

[0055] 多个可变电阻材料152在第二绝缘层140上形成以耦合到多个BEC 142,并且多个顶电极触点(TEC) 154在多个可变电阻材料152上形成。 [0055] a plurality of variable resistive material 152 is formed to be coupled to a plurality of BEC 142, and a plurality of top electrode contacts (TEC) 154 is formed on a plurality of variable resistive material 152 on the second insulating layer 140.

[0056] 非易失性存储器设备进一步包括在第二绝缘层140上形成的第三绝缘层150,该第三绝缘层150具有分别耦合到多个TEC 154的多个位线触点156。 [0056] The nonvolatile memory device further includes a third insulating layer 150 is formed on the second insulating layer 140, the third insulating layer 150 having a TEC coupled to the plurality of bit lines 154 of the plurality of contacts 156. 多个局部位线LBL在第三绝缘层150上形成,并分别耦合到多个位线触点156。 A plurality of local bit lines LBL on the third insulating layer 150 is formed, and a plurality of bit lines coupled to the contacts 156. 绝缘层160在多个位线LBL上形成。 Insulating layer 160 is formed on the plurality of bit lines LBL.

[0057] 参考图8A,子字线SWL在绝缘层160上的多个局部位线LBL上形成。 [0057] 8A, the sub-word line SWL is formed on a plurality of local bit lines LBL on the insulating layer 160. 绝缘层170在子字线SWL上形成。 Insulating layer 170 is formed on the sub-word line SWL. 写全局位线WGBL和读全局位线RGBL在绝缘层170上的子字线SWL上形成。 WGBL write global bit line and a read global bit line RGBL formed on the sub-word lines SWL on the insulating layer 170. 绝缘层180在读全局位线RGBL和写全局位线WGBL上形成。 Insulating layer 180 RGBL read global bit line and the write global bit line is formed on WGBL. 主字线MWL在绝缘层180上的写全局位线WGBL和读全局位线RGBL上形成。 Main word line MWL WGBL write global bit line and a read global bit line is formed on the insulating layer on RGBL 180. 虽然图8A中未显示,但是子字线SWL与在半导体衬底110内形成的N+-型子字线N+SWL耦合。 Although not shown in FIG. 8A, but the sub-word line SWL and N formed in the semiconductor substrate 110 + - N + type sub-word line SWL coupling.

[0058] 进一步,写全局位线WGBL和读全局位线RGBL选择性地与多个局部位线LBL (图8A中的8个LBL)耦合。 [0058] Further, the write global bit line and a read global bit line WGBL RGBL selectively (8 LBL FIG. 8A) is coupled to the plurality of local bit lines LBL. 特别地,图8A示出写全局位线WGBL和读全局位线RGBL位于同一层(level)的示例。 In particular, FIG. 8A shows the write global bit line and a read global bit line WGBL RGBL same layer positioned example (Level) a. 此外,虽然图8A中未显示,但是主字线MWL与子字线SWL选择性地耦合。 Furthermore, although not shown in FIG. 8A, but the main word line MWL and sub-word line coupled selectively SWL. [0059] 图SB表示非易失性存储器设备的示例,在该非易失性存储器设备中,写全局位线WGBLO和WGBLl与读全局位线RGBLO和RGBLl位于不同的层。 [0059] FIG. SB shows an example of a nonvolatile memory device, the nonvolatile memory device, the write global bit line and WGBLl WGBLO read global bit line and RGBLl RGBLO in different layers. 参考图8B,主字线MWL和子字线SWL在绝缘层160上形成。 8B, the main word line MWL and sub-word line SWL is formed on the insulating layer 160. 绝缘层170'在主字线MWL和子字线SWL上形成。 Insulating layer 170 'is formed on the main word line MWL and sub-word line SWL. 各自的第一读全局位线和第二读全局位线RGBLO和RGBLl在绝缘层170'上形成,并且另一绝缘层180'在第一读全局位线和第二读全局位线RBGLl和RGBL2上形成。 Respective first read global bit line and a second read global bit line and RGBLl RGBLO insulating layer 170 'is formed, and another insulating layer 180' is first read global bit line and a second read global bit line and RGBL2 RBGLl the form. 写全局位线WGBLO和WGBLl可在绝缘层180'上的读全局位线RGBLO和RGBLl上形成。 And a write global bit line WGBLO WGBLl global bit line can be read on RGBLl RGBLO and on the insulating layer 180 'is formed. 虽然图8B中未显示,但是读全局位线RGBLO和写全局位线WGBLO选择性地与多个局部位线LBL (图8B中左边4个LBL)耦合,而读全局位线RGBLl和写全局位线WGBLl选择性地与剩余的多个局部位线LBL (图8B中的右边4个LBL)耦合。 Although not shown in FIG. 8B, but the read global bit lines and the write global bit lines RGBLO WGBLO selectively with the LBL plurality of local bit lines (FIG. 8B left 4 LBL) coupled to read global bit lines and the write global bit RGBLl WGBLl line selectively with the rest of the LBL plurality of local bit lines (right side of FIG. 8B four LBL) coupling. 读全局位线RGBLO和RGBLl以及写全局位线WGBLO和WGBLl可以各种其他方式与多个局部位线LBL耦合。 RGBLO read global bit line and global bit lines and the write RGBLl WGBLO and WGBLl LBL can be coupled with a variety of other forms a plurality of local bit lines. 此外,虽然图8B示出了主字线MWL和子字线SWL在同一层上形成,但它们可以以其他方式排列。 Further, while FIG 8B shows a main word line MWL and sub-word line SWL are formed in the same layer, but they may be arranged in other ways. 例如,主字线MWL可在写全局位线WGBLO和WGBLl上形成。 For example, the main word line MWL can write global bit line and WGBLl WGBLO formed.

[0060] 如上所述,本发明提供了一种具有降低的核心架构的大小的非易失性存储器设备。 [0060] As described above, the present invention provides a nonvolatile memory device having a reduced size core architecture.

[0061] 虽然已经参照本发明的示例性实施例具体示出和描述了本发明,但本领域普通技术人员将理解,可进行形式和细节上的各种变化,而不脱离如权利要求所定义的本发明的精神和范围。 [0061] Although exemplary embodiments with reference to exemplary embodiments of the present invention is particularly shown and described the present invention, those of ordinary skill in the art will be understood that various changes in form and detail without departing from the as defined in the claims the spirit and scope of the present invention.

Claims (19)

1.一种非易失性存储器设备,包括: 多个存储器组,每个存储器组包括多个非易失性存储器单元,每个单元包括可变电阻元件,所述可变电阻元件具有根据存储的数据而变化的电阻; 多个全局位线,每个全局位线被多个存储器组共享并且包括写全局位线和读全局位线,所述写全局位线用于向多个存储器组写入数据,所述读全局位线用于从多个存储器组读取数据;以及多个主字线,每个主字线对应于多个存储器组中的一个排列; 至少一组局部位线,每组局部位线与至少一个存储器组的存储器单元相关联; 与每组局部位线相关联的多个写局部列选择电路,并且在写操作期间,将至少部分局部位线组与一个写全局位线耦合;以及与每组局部位线相关联的多个读局部列选择电路,并且在读操作期间,将至少部分局部位线组与一个读全局位线耦合, 其中第 1. A nonvolatile memory device, comprising: a plurality of memory banks, each memory group including a plurality of nonvolatile memory cells, each cell comprising a variable resistive element the resistance element, according to the variable memory having data varies resistance; a plurality of global bit lines, each global bit line is shared by a plurality of memory banks and comprising a write global bit line and global bit line is read, the write global bit line for writing to a plurality of memory banks into data, said read global bit line for reading data from a plurality of memory groups; and a plurality of main word lines, a main word lines are arranged corresponding to each of the plurality of memory banks; at least a set of local bit lines, Board with each bit line group of at least one memory associated with memory cells; a plurality of local bit lines associated with each local write column selection circuit, and during a write operation, at least part of a local bit line group and the global write bit line coupling; and a plurality of local bit lines and each set of associated local read column selection circuit, and during a read operation, at least part of a local bit line group and the global read bit line coupling, wherein the first 写局部列选择电路和第二写局部列选择电路位于存储器单元阵列的任一侧,且第一读局部列选择电路和第二读局部列选择电路位于存储器单元阵列的任一侧,并且第一写局部列选择电路和第一读局部列选择电路中的一个包括用于单元阵列中的一半局部位线的选择晶体管。 Write column selection circuit and a second local partial write column selection circuit located on either side of the memory cell array, and the first partial readout column selection circuit and the second partial readout column selection circuit on either side of the memory cell array, and the first partial write column selection circuit and the first read partial column selection circuit comprises a transistor for selecting a local bit line half cell array.
2.如权利要求1的设备,其中至少一个存储器组包括共享局部位线的第一存储器单元阵列和第二存储器单元阵列;以及` 写局部列选择电路和读局部列选择电路位于第一存储器单元阵列和第二存储器单元阵列之间。 2. The apparatus of claim 1, wherein the at least one memory cell array including a first memory group and a second memory cell array sharing the local bit lines; and write 'and a read column selection circuit topical local column select circuit a first memory cell located array and between the second memory cell array.
3.如权利要求1的设备,其中多个存储器组的每个包括多个子块,每个子块具有多个非易失性存储器单元。 3. The apparatus as claimed in claim 1, wherein each of the plurality of memory banks comprises a plurality of sub-blocks, each sub-block having a plurality of nonvolatile memory cells.
4.如权利要求3的设备,其中当η和m是大于I的整数时,在测试操作期间,配置全局位线和主字线使得m组数据同时写到η个子块,以便写入nXm组数据。 4. The apparatus of claim 3, wherein when η and m is an integer greater than I, during a test operation, the global bit line configuration and the main word line set such that data is simultaneously written η m sub-blocks, to write nXm group data.
5.如权利要求3的设备,其中当η和m是大于I的整数时,在正常操作期间,配置全局位线和主字线使得m组数据被重复写入I个子块η次,以便写入nXm组数据。 5. The apparatus of claim 3, wherein when η I and m is an integer greater than one, during normal operation, the global bit line configuration and the main word lines such that m sets of data is repeatedly written to the I sub-blocks η times to write nXm the set of data.
6.如权利要求1的设备,还包括: 耦合到多个全局位线的全局写驱动器电路和/或读出放大器电路,该全局写驱动器电路和/或读出放大器电路通过多个全局位线向多个存储器组写入数据,并且通过多个全局位线从多个存储器组中读取数据。 6. The apparatus of claim 1, further comprising: coupling a plurality of global bit lines to the global write driver circuit and / or the sense amplifier circuit, the global write driver circuit and / or a plurality of global bit lines by the sense amplifier circuit writing data to a plurality of memory banks, and reads data from the plurality of memory banks through the plurality of global bit lines.
7.如权利要求1的设备,还包括: 主解码器,所述主解码器耦合到多个主字线并选择多个主字线,每个主字线对应于多个存储器组的一个排列。 7. The apparatus of claim 1, further comprising: a main decoder, said decoder coupled to the plurality of main word lines and selecting a plurality of primary main word lines, each master word line arranged corresponding to a plurality of memory banks .
8.如权利要求1的设备,还包括: 由多个存储器组共享的冗余存储器单元阵列。 8. The apparatus as claimed in claim 1, further comprising: a redundant cell array of memory shared by a plurality of memory banks.
9.如权利要求1的设备,其中非易失性存储器单元是相变存储器单元。 9. The apparatus of claim 1, wherein the non-volatile memory cells are phase change memory cells.
10.一种非易失性存储器设备,包括: 多个存储器组,每个存储器组包括多个非易失性存储器单元,每个单元包括可变电阻元件,所述可变电阻元件具有根据存储的数据而变化的电阻; 多个写全局位线,用于向多个存储器组写入数据; 多个读全局位线,用于从多个存储器组读取数据; 全局写驱动器和/或读出放大器电路,耦合到多个写全局位线和多个读全局位线; 至少一组局部位线,每组局部位线与至少一个存储器组的存储器单元相关联; 与每组局部位线相关联的多个写局部列选择电路,并且在写操作期间,将至少部分局部位线组耦合到多个写全局位线中的一个;以及与每组局部位线相关联的多个读局部列选择电路,并且在读操作期间,将至少部分局部位线组耦合到多个读全局位线中的一个, 其中第一写局部列选择电路和第二写局部列选择电路位 10. A nonvolatile memory device, comprising: a plurality of memory banks, each memory group including a plurality of nonvolatile memory cells, each cell comprising a variable resistive element the resistance element, according to the variable memory having data varies resistance; a plurality of write global bit lines, for writing data to a plurality of memory banks; plurality of read global bit lines, for reading data from a plurality of memory banks; global write driver and / or reading amplifier circuit, coupled to the plurality of write global bit lines and the plurality of read global bit lines; at least a set of local bit lines, each local bit line and the at least one memory group associated with memory cells; associated with each local bit line associated plurality of local write column selection circuit, and during a write operation, at least a portion of the local bit line groups are coupled to a plurality of write global bit lines; and a plurality of local bit line associated with each of the local column read selection circuit, and during a read operation, at least a portion of the local bit line groups are coupled to a plurality of read global bit lines, wherein the first partial write column selection circuit and the second write bit partial column selection circuit 存储器单元阵列的任一侧,且第一读局部列选择电路和第二读局部列选择电路位于存储器单元阵列的任一侧,并且第一写局部列选择电路和第一读局部列选择电路中的一个包括用于单元阵列中的一半局部位线的选择晶体管。 On either side of the memory cell array, and the first partial readout column selection circuit and a second local read column selecting circuit located on either side of the memory cell array, and the first partial write column selection circuit and the first read partial column selection circuit half of the select transistor comprises a local bit line for the cell array.
11.如权利要求10的设备,其中多个存储器组共享多个写全局位线的每个和多个读全局位线的每个。 11. The apparatus of claim 10, wherein each of the plurality of memory groups to share each of the plurality of read global bit lines and a plurality of write global bit line.
12.如权利要求10的设备,其中多个存储器组的每个包括多个子块,每个子块具有多个非易失性存储器单元。 12. The apparatus of claim 10, wherein each of the plurality of memory banks comprises a plurality of sub-blocks, each sub-block having a plurality of nonvolatile memory cells.
13.如权利要求12的设备,其中当η和m是大于I的整数时,在测试操作期间,配置全局位线和主字线使得m组数据被同时写入η个子块,以便写入nXm组数据。 13. The apparatus of claim 12, wherein when η and m is an integer greater than I, during a test operation, the global bit line configuration and the main word line set such that data is written η m sub-blocks simultaneously, to write nXm set of data. ` `
14.如权利要求12的设备,其中当η和m是大于I的整数时,在正常操作期间,配置全局位线和主字线使得m组数据被重复写入一个子块η次,以便写入nXm组数据。 14. The apparatus of claim 12, wherein when η I and m is an integer greater than one, during normal operation, the global bit line configuration and the main word lines such that m sets of data is repeatedly written to η times a sub-block, to write nXm the set of data.
15.如权利要求11的设备,还包括: 由多个存储器组共享的冗余存储器单元阵列。 15. The apparatus of claim 11, further comprising: a redundant cell array of memory shared by a plurality of memory banks.
16.如权利要求11的设备,其中非易失性存储器单元是相变存储器单元。 16. The apparatus of claim 11, wherein the non-volatile memory cells are phase change memory cells.
17.一种非易失性存储器设备,包括: 半导体衬底; 至少一组局部位线,在半导体衬底上形成并耦合到多个相变存储器单元; 写全局位线和读全局位线,在至少一组局部位线上形成并选择性地耦合到至少部分局部位线组; 与每组局部位线相关联的多个写局部列选择电路,并且在写操作期间,将至少部分局部位线组与一个写全局位线耦合;以及与每组局部位线相关联的多个读局部列选择电路,并且在读操作期间,将至少部分局部位线组与一个读全局位线耦合, 其中第一写局部列选择电路和第二写局部列选择电路位于存储器单元阵列的任一侧,且第一读局部列选择电路和第二读局部列选择电路位于存储器单元阵列的任一侧,并且第一写局部列选择电路和第一读局部列选择电路中的一个包括用于单元阵列中的一半局部位线的选择晶体管。 17. A nonvolatile memory device comprising: a semiconductor substrate; a plurality of local bit lines formed at least on the semiconductor substrate and coupled to a plurality of phase change memory cells; write global bit line and a read global bit line, forming at least one set of local bitlines selectively coupled to and at least partially set of local bit lines; and a plurality of local bit lines associated with each set of partial write column selection circuit, and during a write operation, at least a portion of the local bit line group and a write global bit line coupling; and a plurality of local bit lines and read each associated local column selection circuit, and during a read operation, at least part of a local bit line group and the global read bit line coupling, wherein the first a write column selection circuit and a second local partial write column selecting circuit located on either side of the memory cell array, and the first partial readout column selection circuit and a second local read column selecting circuit located on either side of the memory cell array, and the first a partial write column selection circuit and the first read partial column selection circuit comprises a transistor for selecting a local bit line half cell array.
18.如权利要求17的设备,其中写全局位线和读全局位线位于同一层。 18. The apparatus of claim 17, wherein the write global bit line and a read global bit line in the same layer.
19.如权利要求17的设备,其中写全局位线位于与读全局位线不同的层。 19. The apparatus of claim 17, wherein the write global bit lines and the read global bit lines located in different layers.
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