CN101533821A - Chip carrier enhancing heat sinking efficiency and chip packaging structure thereof - Google Patents
Chip carrier enhancing heat sinking efficiency and chip packaging structure thereof Download PDFInfo
- Publication number
- CN101533821A CN101533821A CN 200810086433 CN200810086433A CN101533821A CN 101533821 A CN101533821 A CN 101533821A CN 200810086433 CN200810086433 CN 200810086433 CN 200810086433 A CN200810086433 A CN 200810086433A CN 101533821 A CN101533821 A CN 101533821A
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- chip
- perforation
- flexible substrate
- packaging structure
- substrate layer
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 26
- 230000002708 enhancing effect Effects 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000004519 grease Substances 0.000 claims description 11
- 239000004642 Polyimide Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229920000728 polyester Polymers 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 10
- 238000003466 welding Methods 0.000 description 5
- 238000004804 winding Methods 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- -1 PI) Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 230000001737 promoting effect Effects 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000011469 building brick Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a chip carrier enhancing heat sinking efficiency and a chip packaging structure thereof. Furthermore, the chip carrier comprises a flexible substrate layer and a plurality of conductive circuits. The flexible substrate layer has a first surface and a second surface that is opposite to the first surface and the conductive circuits are formed on the first surface. In particular, at least one punched hole is formed by the flexible substrate layer at a position corresponding to at least one conductive circuit among the conductive circuits, and the punched hole prevents the first surface from being electrically connected with the second surface and is completely covered by the conductive circuit.
Description
Technical field
The invention relates to a kind of chip carrier and chip-packaging structure, particularly about a kind of chip carrier and the chip-packaging structure that can promote heat sinking benefit.
Background technology
(circuit complexity and the density of chip internal increase fast for integrated circuit, IC) development of technologies, so the heat energy that chip is produced when running also rises gradually along with integrated circuit.With present common electronic installation, as PC, mobile phone, display unit etc., the ic core sector-meeting of its inner high integration (integration) produces a large amount of heat energy when running.In order to make chip can keep normal operation and to avoid the too high usefulness that causes of temperature to descend or damage, knowing this technical field personage must propose to keep the solution of chip normal working temperature in the lump when the chip of the high complexity/density of design.
In prior art, chip mainly can engage (wire bonding by routing, WB) (flip chip, FC) technology or winding engage (tape automated bonding, TAB) technology and chip carrier (carrier) electric connection automatically for technology, chip bonding.Because the automatic joining technique of winding has: can on the flexible substrate layer, directly carry out testing electrical property; Can utilize the flexible substrate layer to finish the solid assembling of electronic building brick; And can make slim, can dynamically link and the advantages such as chip packing-body of tool flexibility, therefore be widely used in the encapsulation of the chip of electronic products such as PC, LCD/TV, storage card.
As shown in Figure 1, the chip-packaging structure 7 with the automatic joining technique manufacturing of winding mainly comprises flexible substrate layer 70, conducting wire layer 72, welding resisting layer 74, chip 76, fin 77 and adhesive body 78 in the known technology.Flexible substrate layer 70 is rewinding type flexible substrates; This conducting wire layer 72 is formed at a upper surface 702 of this flexible substrate layer 70; And 74 of this welding resisting layers are formed on this conducting wire layer 72, produce short circuit to prevent conducting wire layer 72 because of pollution.Chip 76 has an active face 762 and a back side 764, and this active face 762 is provided with a plurality of projections 766, and those projections 766 can be engaged to conducting wire layer 72, to finish the electric connection of chip 76 and conducting wire layer 72.
In addition, fin 77 can adhere to the back side 764 of chip 76 by thermal grease 79.78 of adhesive bodies are formed between flexible substrate layer 70 and the chip 76, to cover and to fix those projections 766.
Yet, though fin 77 can increase the radiating rate of chip 76, but the integral thickness of chip-packaging structure 7 can increase, the weight of fin 77 also may make flexible substrate layer 70 produce crooked or distortion, influence the normal operation of chip 76, and the thermal source of chip 76 mainly results from active face 762 and conduct to the conducting wire layer 72 that couples with chip 76, this fin 77 is the back side 764 that adheres to chip 76, its conducting path is far away, and radiating effect is relatively poor.
Summary of the invention
Therefore, a purpose of the present invention is to provide a kind of chip carrier of promoting heat sinking benefit, to solve the problem in the prior art.
A kind of chip carrier is provided according to an aspect of the present invention, and it comprises a flexible substrate layer and a plurality of conducting wire.This flexible substrate layer has a first surface and with respect to a second surface of this first surface, and these conducting wires are formed on this first surface.Especially, the position of at least one conducting wire of this flexible substrate layer in corresponding these conducting wires forms at least one perforation, and this perforation can not make this first surface and this second surface form and electrically connect, and this perforation is covered fully by this conducting wire.
Another object of the present invention is to provide a kind of chip-packaging structure, it has the good heat radiating effect, and can solve the problem in the prior art.
A kind of chip-packaging structure is provided according to a further aspect of the invention, and it comprises a flexible substrate layer, a plurality of conducting wire and a chip.This flexible substrate layer has a first surface and with respect to a second surface of this first surface, comprises a chip bonding area on this first surface.These conducting wires are formed on this first surface, and stretch out in this chip bonding area certainly.In addition, this chip is arranged in this chip bonding area, and comprises a plurality of contacts and couple these conducting wires respectively.Especially, the position of at least one conducting wire of this flexible substrate layer in corresponding these conducting wires forms at least one perforation, and this perforation can not make this first surface and this second surface form and electrically connect, and this perforation is covered fully by this conducting wire.
Description of drawings
Can be further understood by the detailed description of the Invention of following conjunction with figs. about the advantages and spirit of the present invention preferred embodiment of the present invention, wherein:
Fig. 1 is the profile of the chip-packaging structure in the prior art.
Fig. 2 A is the chip carrier schematic diagram of a specific embodiment of the present invention.
Fig. 2 B is the chip carrier profile of a specific embodiment of the present invention.
Fig. 3 A is the chip carrier profile of a specific embodiment of the present invention.
Fig. 3 B is the chip carrier profile of a specific embodiment of the present invention.
Fig. 4 A is the chip-packaging structure schematic diagram of a specific embodiment of the present invention.
Fig. 4 B is the chip-packaging structure profile of a specific embodiment of the present invention.
Embodiment
The invention provides a kind of chip carrier and chip-packaging structure of promoting heat sinking benefit.
See also Fig. 2 A and Fig. 2 B, Fig. 2 A is the chip carrier schematic diagram according to a specific embodiment of the present invention; Fig. 2 B then is the profile that illustrates according to the chip carrier of a specific embodiment of the present invention.The disclosed chip carrier 1 of this specific embodiment is to be applied to winding to engage (tape automatedbonding, TAB) the belt flexible base plate of technology automatically.
Shown in Fig. 2 A and Fig. 2 B, chip carrier 1 can comprise flexible substrate layer 10 and a plurality of conducting wire 12.Flexible substrate layer 10 can be by polyimides (Polyimide, PI), polyesters compound (polyethylene terephthalate, PET) or other suitable material made, and it has first surface 102 and opposing second surface 104, and be formed with chip bonding area 108 on this first surface 102, for the fixing usefulness of chip join.In addition, conducting wire 12 can be formed on the first surface 102 by etching or other suitable mode patterning by Copper Foil.Further, flexible substrate layer 10 forms at least one perforation 106 and is through to second surface 104 from first surface 102 in the position of at least one conducting wire 12 of correspondence.Especially, these perforation 106 can not make first surface 102 form with second surface 104 and electrically connect (in other words, different in the perforation that chip carrier of the present invention comprised and the known technology) in order to the hole of conducting first surface and second surface, and perforation 106 can be covered fully by conducting wire 12.
In addition, shown in Fig. 2 B, chip carrier 1 of the present invention can further comprise welding resisting layer 18, and its local these conducting wires 12 that cover produce short circuit to prevent conducting wire 12 because of pollution.
See also Fig. 3 A and Fig. 3 B, Fig. 3 A and Fig. 3 B all are chip carrier profiles according to a particular embodiment of the invention.Compared to the chip carrier of aforementioned specific embodiment, the chip carrier 1 that Fig. 3 A is illustrated further comprises thermal grease 14, and it is coated on the second surface 104 and fills up perforation 106.Note that thermal grease 14 can use any suitable material.And in practice, thermal grease 14 not necessarily to fill up the perforation 106, and can only cover the perforation 106 or with suitably insert in various degree the perforation 106 in.
In addition, compared to the chip carrier of aforementioned specific embodiment, the chip carrier 1 that Fig. 3 B is illustrated further comprises radiating component 16, and it is arranged on the second surface 104 and covers perforation 106.Note that radiating component 16 can use any suitable material to make.And in practice, radiating component 16 also can be for covering the relatively large solid memder of some perforation 106 simultaneously.In addition, radiating component 16 can be radiating fin (heat-dissipating fin), heat pipe (heat pipe), thermal conductance post (heat column) or other form that is fit to.
In practical application, perforation might not be through to second surface from first surface, and can adjust its degree of depth and pore size according to circumstances.In addition, produce the more zone of heat more perforation can be set, produce the less zone of heat and a small amount of perforation then is set or perforation must not be set.In addition, in practical application, aforesaid thermal grease and radiating component also can be arranged in pairs or groups mutually and be used in chip carrier of the present invention.
Please in the lump referring to Fig. 4 A and Fig. 4 B, Fig. 4 A is the chip-packaging structure schematic diagram that illustrates according to a specific embodiment of the present invention, and Fig. 4 B then is the profile that illustrates according to the chip-packaging structure of a specific embodiment of the present invention.
Shown in Fig. 4 A and Fig. 4 B, except aforesaid flexible substrate layer 30 and conducting wire 32, chip-packaging structure 3 also can comprise chip 34.Flexible substrate layer 30 can (Polyimide, PI), polyesters compound (PET) or other suitable material be made, and it has first surface 302 and opposing second surface 304 by polyimides.In addition, comprise chip bonding area 308 on the first surface 302.In addition, conducting wire 32 can be formed on the first surface 302 by etching or other suitable mode patterning by Copper Foil, and stretches out in chip bonding area 308.34 of chips are arranged in the chip bonding area 308, and comprise a plurality of contacts (not being illustrated among the figure) and corresponding a plurality of projection (bump) 342 to couple conducting wire 12 respectively.In practical application, projection 342 can use gold, copper, aluminium, nickel or other suitable material made.
Further, shown in Fig. 4 B, chip-packaging structure 3 of the present invention also can comprise welding resisting layer 38 and adhesive body 39.As previously mentioned, welding resisting layer 38 local these conducting wires 32 that cover produce short circuit to prevent conducting wire 32 because of pollution.39 of adhesive bodies are formed between chip 34 and the flexible substrate layer 30, sealing those projections 342, and provide suitable packaging protection to prevent electrical short circuit and dust pollution.
Especially, as mentioned above, flexible substrate layer 30 forms at least one perforation 306 in the position of each these conducting wire 32 of correspondence, and it can not make first surface 302 and second surface 304 form electric connection.Perforation 306 can be covered fully by each conducting wire 32.
In practical application, chip and flexible substrate layer can by winding carrying encapsulation (Tape carrierpackage, TCP), cover brilliant thin-film package (Chip-on-film package, COF) or other suitable encapsulation technology encapsulate.
As mentioned above, the also visual demand of chip-packaging structure of the present invention adds aforesaid thermal grease and/or radiating component, to promote radiating efficiency.In addition, in practical application, perforation might not be through to second surface from first surface, and can adjust its degree of depth and pore size according to circumstances.In addition, produce the more zone of heat more perforation can be set, produce the less zone of heat and a small amount of perforation then is set or perforation must not be set.
Compared to known technology, chip carrier of the present invention and chip-packaging structure can reach the purpose of promoting radiating effect by perforation, and with thermal grease and/or auxiliary its radiating efficiency of radiating component.In addition, the setting of perforation can be carried out the design of position and density according to situations such as chip type, flexible substrate layer type and heat distribution, therefore has bigger elasticity on making.
By the above detailed description of preferred embodiments, be to wish to know more to describe feature of the present invention and spirit, and be not to come category of the present invention is limited with above-mentioned disclosed preferred embodiment.On the contrary, its objective is that hope can contain in the category of claim of being arranged in of various changes and tool equality institute of the present invention desire application.
Claims (10)
1. chip carrier comprises:
One flexible substrate layer has a first surface and with respect to a second surface of this first surface; And
A plurality of conducting wires are formed on this first surface;
Wherein the position of at least one conducting wire of this flexible substrate layer in corresponding these conducting wires forms at least one perforation, and this perforation can not make this first surface and this second surface form and electrically connect, and this perforation is covered fully by this conducting wire.
2. chip carrier according to claim 1 is characterized in that further comprising:
One thermal grease is coated on this second surface, and this perforation is filled and covered to this thermal grease.
3. chip carrier according to claim 1 is characterized in that further comprising:
One radiating component is arranged on this second surface, and this radiating component covers this perforation.
4. chip carrier according to claim 1 is characterized in that this flexible substrate layer is made by polyimides or polyesters compound.
5. chip-packaging structure comprises:
One flexible substrate layer has a first surface and with respect to a second surface of this first surface, comprises a chip bonding area on this first surface;
A plurality of conducting wires are formed on this first surface, and stretch out in this chip bonding area certainly; And
One chip is arranged in this chip bonding area, and this chip comprises a plurality of contacts and couples these conducting wires respectively;
Wherein the position of at least one conducting wire of this flexible substrate layer in corresponding these conducting wires forms at least one perforation, and this perforation can not make this first surface and this second surface form and electrically connect, and this perforation is covered fully by this conducting wire.
6. chip-packaging structure according to claim 5 is characterized in that further comprising:
One thermal grease is coated on this second surface, and this perforation is filled and covered to this thermal grease.
7. chip-packaging structure according to claim 5 is characterized in that further comprising:
One radiating component is arranged on this second surface, and this radiating component covers this perforation.
8. chip-packaging structure according to claim 5 is characterized in that this flexible substrate layer is made by polyimides or polyesters compound.
9. chip-packaging structure according to claim 5 is characterized in that respectively comprising a projection respectively on these a plurality of contacts.
10. chip-packaging structure according to claim 9, the material that it is characterized in that this projection comprise and one of are selected from the group that is made up of gold, copper, aluminium and nickel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810086433 CN101533821A (en) | 2008-03-13 | 2008-03-13 | Chip carrier enhancing heat sinking efficiency and chip packaging structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810086433 CN101533821A (en) | 2008-03-13 | 2008-03-13 | Chip carrier enhancing heat sinking efficiency and chip packaging structure thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101533821A true CN101533821A (en) | 2009-09-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810086433 Pending CN101533821A (en) | 2008-03-13 | 2008-03-13 | Chip carrier enhancing heat sinking efficiency and chip packaging structure thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101533821A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517912A (en) * | 2013-09-30 | 2015-04-15 | 南茂科技股份有限公司 | Thin film flip chip packaging structure |
-
2008
- 2008-03-13 CN CN 200810086433 patent/CN101533821A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517912A (en) * | 2013-09-30 | 2015-04-15 | 南茂科技股份有限公司 | Thin film flip chip packaging structure |
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Open date: 20090916 |