CN101510034B - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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CN101510034B
CN101510034B CN 200910126411 CN200910126411A CN101510034B CN 101510034 B CN101510034 B CN 101510034B CN 200910126411 CN200910126411 CN 200910126411 CN 200910126411 A CN200910126411 A CN 200910126411A CN 101510034 B CN101510034 B CN 101510034B
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memory capacitance
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subpixel
liquid crystal
post
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CN101510034A (en
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下敷领文一
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Sharp Corp
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Sharp Corp
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Abstract

A liquid crystal display of the invention includes a plurality of pixels each of which has a liquid crystal layer and a plurality of electrodes for applying a voltage to the liquid crystal layer and which are arranged in a matrix of rows and columns, wherein: each of the plurality of pixels has a first sub-pixel and a second sub-pixel which can apply mutually different voltages to the liquid crystal layer, where the first sub-pixel has a higher brightness than the second sub-pixel in certain gradations; the first sub-pixel and the second sub-pixel each has: a liquid crystal capacitor formed by a counter electrode and a sub-pixel electrode opposing the counter electrode via the liquid crystal layer, and a storage capacitor formed by a storage capacitor electrode connected electrically to the sub-pixel electrode, an insulating layer, and a storage capacitor counter electrode opposing the storage capacitor electrode via the insulating layer; the counter electrode is a single electrode shared by the first sub-pixel and the second sub-pixel, and the storage capacitor counter electrodes of the first sub-pixel and the second sub-pixel are electrically independent of each other; and the storage capacitor counter electrode of the first sub-pixel in any of the plurality of pixels and the storage capacitor counter electrode of the second sub-pixel of a pixel adjacent to any of the pixelsin the column direction are electrically independent of each other.

Description

Liquid crystal display
The application is to be on Dec 3rd, 2004 applying date, and application number is 200410099783X, and what " liquid crystal display " by name applied for divides an application.
Technical field
The present invention relates to a kind of structure and/or driving method that can reduce the view angle dependency of γ characteristic in liquid crystal display.
Background technology
Liquid crystal display is a kind of superperformance flat-panel monitor of (comprising high resolving power, less thickness, lighter weight and lower power consumption) that has.Along with the raising of display performance and output and the price advantage of comparing with other types of display, its market share is also in rapid expansion.
Usually the conventional twisted nematic type of using liquid crystal molecule from positive dielectric anisotropy to (TN) liquid crystal display that have, liquid crystal molecule with its major axis orientation approximate be parallel to substrate surface and reverse the mode of 90 ° along the thickness direction of liquid crystal layer be distributed between the substrate of up and down.When liquid crystal layer was applied voltage, liquid crystal molecule began to be parallel to electric field, discharged twisted arrangement.Light transmission capacity is controlled in the change that the TN liquid crystal display utilizes the orientation of the liquid crystal molecule that voltage causes to change the rotary polarization that causes.
The TN liquid crystal display allows very wide manufacturing tolerance limit and high output.On the other hand, it also has the problem of display performance, especially viewing angle characteristic.Specifically, when looking side ways the display surface of TN liquid crystal display, the display comparison degree descends quite severely.Therefore, even when seeing from the dead ahead, clear image ground presents from black to white a plurality of gray scales, but the luminance difference between gray scale also seems extremely unintelligible when stravismus.In addition, also there is the phenomenon that when seeing from the dead ahead, aobvious dark part highlights when stravismus.
In order to improve the viewing angle characteristic of TN liquid crystal display, recently some liquid crystal display have been developed, comprise that coplanar switching (IPS) type liquid crystal display, the Japan described in Japanese Laid-Open Patent JP63-21907 treat that multidomain homeotropic alignment (MVA) type liquid crystal display, the Japan described in publication treat the little box of axial symmetry (ASM) escope of describing in publication JP10-186330, and Japan treats the liquid crystal display described in publication JP2002-55343.
Adopt the liquid crystal display of above-mentioned arbitrary novel pattern (wide field-of-view mode) to solve the particular problem of viewing angle characteristic.Especially they are less than the contrast that shows when looking side ways the display surface of TN liquid crystal display or the remarkable problem that descends of display gray scale.
In the improved situation of the display quality of liquid crystal display, face again the new problem of viewing angle characteristic, namely the view angle dependency of γ characteristic, this means to have the γ property difference when watching display and stravismus display from the dead ahead.Just go wrong when showing image (such as photo) or show television broadcasting etc. like this.
The view angle dependency of γ characteristic ratio in MVA pattern and ASM pattern is more outstanding in the IPS pattern.On the other hand, more be difficult to than MVA or ASM plate high yield ground making has higher contrast when the dead ahead is seen IPS plate.Thereby hope reduces the view angle dependency of the γ characteristic of MVA pattern or ASM pattern.
Produced in view of the above problems the present invention.Fundamental purpose of the present invention is to provide a kind of liquid crystal display with the γ characteristic view angle dependency that reduces.
Summary of the invention
To achieve these goals, a first aspect of the present invention provides a kind of liquid crystal display of normal black pattern, it comprises a large amount of pixels, each pixel has liquid crystal layer and is used for applying a large amount of electrodes of voltage to liquid crystal layer, and it is characterized in that: each of a large amount of pixels comprises the first subpixel and second subpixel that can apply to liquid crystal layer separately mutually different voltage; And (wherein gk and gn are not less than zero integer when the gray scale gk of 0≤gk≤gn is satisfied in each demonstration of a large amount of pixels, and the higher value of gk is corresponding to higher brightness), if suppose Δ V12 (gk)=V1 (gk)-V2 (gk), satisfy at least relationship delta V12 (gk)＞0V and Δ V12 (gk)＞Δ V12 (gk+1) in the scope of 0＜gk≤n-1, wherein, V1 (gk) and V2 (gk) are the r.m.s. voltage that is applied to respectively the liquid crystal layer of the first subpixel and the second subpixel.By the way, " pixel " herein represents the minimum display unit on liquid crystal display, in the situation that color monitor, it is corresponding to showing single color (typically being R, G or B) " picture dot (or point) " of planting.
Liquid crystal display can be constructed like this: each in a large amount of pixels comprises can apply to its liquid crystal layer the 3rd subpixel of the voltage that is different from the first subpixel and the second subpixel; With each the display gray scale gk when a large amount of pixels, and during Δ V13 (gk)=V1 (gk)-V3 (gk), if the r.m.s. voltage that applies to the liquid crystal layer of the 3rd subpixel is V3 (gk), satisfies and concern 0V＜Δ V13 (gk)＜Δ V12 (gk).
The r.m.s. voltage that preferably is applied to liquid crystal layer satisfies relationship delta V12 (gk) 〉=Δ V12 (gk+1) at least in the scope of 0＜gk≤n-1.
Preferably when each pixel has the 3rd subpixel, satisfy at least relationship delta V12 (gk) 〉=Δ V12 (gk+1) and Δ V13 (gk) 〉=Δ V13 (gk+1) in the scope of 0＜gk≤n-1.
In a preferred embodiment, the first subpixel and the second subpixel each comprise: by counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode; And by the memory capacitance that is electrically connected to the subpixel electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with storage capacitor electrode; And counter electrode is the single electrode of sharing with the first subpixel and the second subpixel, and the memory capacitance counter electrode of the first subpixel and the second subpixel is electrically insulated from each other.Typically, counter electrode is arranged in relative substrate (sometimes being called " public electrode "), but in the IPS pattern, counter electrode is arranged in the substrate identical with the subpixel electrode.By the way, " through the liquid crystal layer counter electrode relative with the subpixel electrode " needn't be relative every the thickness of liquid crystal layer with the subpixel electrode.In the IPS liquid crystal display, it is placed in liquid crystal layer relative every liquid crystal layer with the subpixel electrode.
In a preferred embodiment, liquid crystal display comprises that two are respectively the on-off elements that the first subpixel and the second subpixel arrange, and it is characterized in that two on-off elements open and close by the scanning-line signal voltage of supplying with the common scanning line; When two on-off elements were opened, display voltage was applied on each subpixel electrode and storage capacitor electrode of the first subpixel and the second subpixel from common signal line; After two on-off elements were closed, the voltage of each memory capacitance counter electrode of the first subpixel and the second subpixel changed; And the variable quantity difference between the first subpixel and the second subpixel that is limited by the size and Orientation that changes.Herein not only about size (absolute value), and about the variable quantity of direction definition memory capacitance counter electrode.For example, the absolute value of the voltage variety of the memory capacitance counter electrode of the first subpixel and the second subpixel equates, opposite in sign.In brief, if the voltage of one of them memory capacitance counter electrode raises and the voltage drop of another memory capacitance counter electrode after on-off element disconnects, the absolute value that changes can equate.
Preferred liquid crystal layer is the liquid crystal layer of homeotropic alignment, and comprise have negative dielectric anisotropic row mutually to liquid crystal material.
Each liquid crystal layer of preferred the first subpixel and the second subpixel is included in four farmlands of about 90 ° of being separated by on azimuth direction, and liquid crystal molecule just tilts when applying voltage in four farmlands.
Preferred the first subpixel and the second subpixel are placed on the opposition side of common signal line; Each has a large amount of protruding ribs to liquid crystal layer in counter electrode one side for the first subpixel and the second subpixel, and a large amount of ribs is included in the upwardly extending first rib of first party and approximately perpendicular to the upwardly extending second rib of the second party of first direction; And the first subpixel and the second subpixel in each first rib and second rib be symmetrical arranged with respect to the center line that is parallel to the common scanning line, and the first and second subpixel one of in the distribution of first rib and second rib with respect to other subpixel in being distributed symmetrically of first rib and second rib.
The center line that preferably is parallel to the common scanning line in the first subpixel and the second subpixel in each arranges with array of scan lines spacing in being approximately equal to the first subpixel and the second subpixel half interval.
The area of preferred the first subpixel is equal to or less than the area of the second subpixel.When each of a large amount of pixels had three or more subpixel, the subpixel area that preferably is applied in maximum r.m.s. voltage was not more than the area of other subpixel.
In liquid crystal display according to a further aspect of the invention: be applied to that in a large amount of pixels, the direction of an electric field on liquid crystal layer reverses between each vertical-scan period; And when showing intermediate gray-scale, in the situation of any row pixel, direction of an electric field is gone up periodic inversion in the row direction, in the situation of arbitrary row pixel, and the direction of an electric field of each pixel counter-rotating on column direction.
According to an embodiment, in the situation of any row pixel, the direction of an electric field of each pixel counter-rotating on line direction.
According to an embodiment, in the situation of any row pixel, the direction of an electric field of every two pixels counter-rotating on line direction.
According to the liquid crystal display of an embodiment with normal black work pattern; It is characterized in that at least two subpixel comprise two subpixel SPa (p, q) and SPb (p, q); And (wherein gk and gn are not less than zero integer when the gray scale gk of 0≤gk≤gn is satisfied in each demonstration of a large amount of pixels, and larger gk value is corresponding to higher brightness), if suppose Δ V12 (gk)=V1 (gk)-V2 (gk), satisfy at least relationship delta V12 (gk)＞0V and Δ V12 (gk) 〉=Δ V12 (gk+1) in the scope of 0＜gk≤n-1, wherein, V1 (gk) and V2 (gk) are the r.m.s. voltage that is applied to respectively on the liquid crystal layer of the first subpixel and the second subpixel.
According to an embodiment, satisfy at least relationship delta V12 (gk) 〉=Δ V12 (gk+1) in the scope of 0＜gk≤n-1.
According to an embodiment, SPa (p, q) and SPb (p, q) each comprises: by counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode, with by the storage capacitor electrode that is electrically connected to the subpixel electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with memory capacitance; And counter electrode is SPa (p, q) and the shared single electrode of SPb (p, q), and the memory capacitance counter electrode of SPa (p, q) and SPb (p, q) is electrically insulated from each other.
According to an embodiment, liquid crystal display comprises and is respectively two on-off elements that SPa (p, q) and SPb (p, q) arrange, and it is characterized in that these two on-off elements open and close by the scanning-line signal voltage of supplying with the common scanning line; When these two on-off elements were opened, display voltage was applied on each subpixel electrode and storage capacitor electrode of SPa (p, q) and SPb (p, q) from common signal line; After these two on-off elements were closed, the voltage of each memory capacitance counter electrode of SPa (p, q) and SPb (p, q) just changed; And different between SPa (p, q) and SPb (p, q) by the variable quantity that the size and Orientation that changes limits.Specifically, when these two on-off elements are opened, voltage just is applied on each memory capacitance counter electrode of VSpa (on) and VSpb (on), thereby make when these two on-off elements disconnect, the electromotive force of each memory capacitance counter electrode will change, for example become VSpa (off) and VSpb (off) from VSpa (on) and VSpb (on) respectively, and each variable quantity " VSpa (off)-VSpa (on) " and " VSpb (off)-VSpb (on) " are with different.
According to an embodiment, the change in voltage of SPa (p, q) and SPb (p, q) memory capacitance counter electrode equates on amount, and is opposite on direction.
According to an embodiment, the voltage of the memory capacitance counter electrode of SPa (p, q) and SPb (p, q) is the oscillating voltage that 180 ° of phase differential are arranged each other.Oscillating voltage can be square wave, sine wave or triangular wave.
According to an embodiment, each has the cycle that is approximately equal to a horizontal scanning period oscillating voltage of the memory capacitance counter electrode of SPa (p, q) and SPb (p, q).
According to an embodiment, each has the cycle that is shorter than a horizontal scanning period oscillating voltage of the memory capacitance counter electrode of SPa (p, q) and SPb (p, q).
According to an embodiment, if average within the cycle, the oscillating voltage of the memory capacitance counter electrode of SPa (p, q) and SPb (p, q) approximately equal in any horizontal scanning period.
According to an embodiment, be half of a horizontal scanning period oscillation period.
According to an embodiment, oscillating voltage is that dutycycle is the square wave of 1: 1.
According to an embodiment, SPa (p, q) and SPb (p, q) have different areas, and little area belongs to and has SPa (p, q) or the SPb (p, q) that is applied to the larger r.m.s. voltage on its liquid crystal layer.
According to an embodiment, the area of SPa (p, q) and SPb (p, q) is in fact equal.
A third aspect of the present invention provides a kind of liquid crystal display, it comprises: a large amount of pixels, each pixel has liquid crystal layer and a large amount of electrode that is used for applying voltage to liquid crystal layer, electrode is the ranks matrix distribution, it is characterized in that: each of a large amount of pixels has can apply the first subpixel and second subpixel of mutually different voltage to liquid crystal layer, and the first subpixel has the brightness higher than the second subpixel under definite gray scale; Each comprises the first subpixel and the second subpixel: by counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode, with by the storage capacitor electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with storage capacitor electrode that are electrically connected on the subpixel electrode; Counter electrode is the single electrode of being shared by the first subpixel and the second subpixel, and the memory capacitance counter electrode of the first subpixel and the second subpixel is electrically insulated from each other; The memory capacitance counter electrode of the second subpixel of the pixel that on the memory capacitance counter electrode of first subpixel of a large amount of pixels in any and column direction, any pixel is adjacent is electrically insulated from each other.
According to an embodiment, the first subpixel of any pixel be scattered in column direction on second subpixel of adjacent image point of any pixel adjacent.
According to an embodiment, in each of a plurality of pixels, the first subpixel is scattered on column direction adjacent with the second subpixel.
According to an embodiment, liquid crystal display comprises a large amount of memory capacitance posts that are electrically insulated from each other, and it is characterized in that each memory capacitance post is electrically connected on any memory capacitance counter electrode of the first subpixel in a large amount of pixels and the second subpixel through storage capacitance line.
According to an embodiment, the quantity of the memory capacitance post that is electrically insulated from each other in a large amount of memory capacitance posts (trunk) is L, and the memory capacitance inverse voltage of being supplied with by each memory capacitance post is oscillating voltage, and be L times of horizontal scanning period oscillation period.
According to an embodiment, a large amount of memory capacitance posts that are electrically insulated from each other are, form the even number memory capacitance post of paired memory capacitance post, supply with the memory capacitance inverse voltage of the vibration that 180 ° of phase differential are arranged each other.
According to an embodiment, the quantity of the memory capacitance post that is electrically insulated from each other is than large 8 times of the share of dividing a horizontal scanning period acquisition by the CR time constant, and wherein the CR time constant is near the maximum load impedance of storage capacitance line.
According to an embodiment, the quantity of the memory capacitance post that is electrically insulated from each other is than dividing large 8 times of the share that a horizontal scanning period obtains by the CR time constant, and is even number, and wherein the CR time constant is near the maximum load impedance of storage capacitance line.
According to an embodiment, a large amount of memory capacitance posts comprises the first memory capacitance post and the second memory capacitance post that is electrically insulated from each other; And if the storage capacitance line of memory capacitance counter electrode that is connected to the first subpixel of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form is made as CSBL_A_n, if the storage capacitance line that is connected on the memory capacitance counter electrode of the second subpixel is made as CSBL_B_n, and if k is natural number (comprising 0), CSBL_A_n+k just is connected on the first memory capacitance post, and CSBL_B_n just is connected on the second memory capacitance post.
According to an embodiment, are twices of horizontal scanning period the oscillation period of the first and second memory capacitance inverse voltages of supplying with by the first and second memory capacitance posts respectively.
According to an embodiment, the second memory capacitance inverse voltage is than the phase differential of a horizontal scanning period of the first memory capacitance inverse voltage hysteresis.
According to an embodiment, liquid crystal display comprises that two are respectively the on-off elements that the first subpixel and the second subpixel arrange, and it is characterized in that these two on-off elements open and close by the scanning-line signal voltage of supplying with the common scanning line; When these two on-off elements were opened, display voltage was applied on the electrode of subpixel separately and storage capacitor electrode of the first subpixel and the second subpixel from common signal line; After these two on-off elements were closed, the voltage of the counter electrode of memory capacitance separately of the first subpixel and the second subpixel just changed; And if Td represent these two on-off elements close after the first memory capacitance inverse voltage change the required time in the very first time, Td greater than 0 horizontal scanning period less than a horizontal scanning period.
According to an embodiment, Td is approximately equal to 0.5 times of horizontal scanning period.
according to an embodiment, a large amount of memory capacitance posts comprise the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post and the 4th memory capacitance post that is electrically insulated from each other, be made as CSBL_A_n and if be connected to the storage capacitance line of the first subpixel memory capacitance counter electrode of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the second subpixel memory capacitance counter electrode, and if k is natural number (comprising 0), CSBL_A_n+4*k and CSBL_B_n+2+4*k just are connected on the first memory capacitance post, CSBL_B_n+4*k and CSBL_A_n+2+4*k just are connected on the second memory capacitance post, CSBL_A_n+1+4*k and CSBL_B_n+3+4*k just are connected on the 3rd memory capacitance post, CSBL_B_n+1+4*k and CSBL_A_n+3+4*k just are connected on the 4th memory capacitance post.
According to an embodiment, be 4 times of horizontal scanning period the oscillation period of the first to fourth memory capacitance inverse voltage of supplying with by first to fourth memory capacitance post respectively.
According to an embodiment, the second memory capacitance inverse voltage is than the phase differential of the first stagnant latter two horizontal scanning period of memory capacitance inverse voltage, the 3rd memory capacitance inverse voltage is than the phase differential of three horizontal scanning periods of the first memory capacitance inverse voltage hysteresis, and the 4th memory capacitance inverse voltage is than the phase differential of a horizontal scanning period of the first memory capacitance inverse voltage hysteresis.
According to an embodiment, liquid crystal display comprises that two are respectively the on-off elements that the first subpixel and the second subpixel arrange, and it is characterized in that these two on-off elements open and close by the scanning-line signal voltage of supplying with the common scanning line; When these two on-off elements were opened, display voltage was applied on each subpixel electrode and storage capacitor electrode of the first subpixel and the second subpixel from common signal line; When two on-off elements were closed, the voltage of each memory capacitance counter electrode of the first subpixel and the second subpixel changed; And if Td represent two on-off elements close after the first memory capacitance inverse voltage change the required time in the very first time, Td greater than 0 horizontal scanning period less than two horizontal scanning periods.
According to an embodiment, Td is approximately equal to a horizontal scanning period.
according to an embodiment, a large amount of memory capacitance posts comprise the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post and the 6th memory capacitance post that is electrically insulated from each other, be made as CSBL_A_n and if be connected to the storage capacitance line of the first subpixel memory capacitance counter electrode of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the second subpixel memory capacitance counter electrode, and if k is natural number (comprising 0), CSBL_A_n+3*k just is connected on the first memory capacitance post, CSBL_B_n+3*k just is connected on the second memory capacitance post, CSBL_A_n+1+3*k just is connected on the 3rd memory capacitance post, CSBL_B_n+1+3*k just is connected on the 4th memory capacitance post, CSBL_A_n+2+3*k just is connected on the 5th memory capacitance post, CSBL_B_n+2+3*k just is connected on the 6th memory capacitance post.
According to an embodiment, be 6 times of horizontal scanning period the oscillation period of the first to the 6th memory capacitance inverse voltage of supplying with by the first to the 6th memory capacitance post respectively.
according to an embodiment, a large amount of memory capacitance posts comprise the first memory capacitance post of being electrically insulated from each other, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post ... (L-3) memory capacitance post, (L-2) memory capacitance post, (L-1) memory capacitance post and L memory capacitance post etc. are L memory capacitance post altogether, and when 1/2 of the quantity L of the memory capacitance post of electrical isolation is odd number, namely work as L=2, 6, 10, Deng the time, be made as CSBL_A_n if be connected to the storage capacitance line of the first subpixel memory capacitance counter electrode of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the second subpixel memory capacitance counter electrode, and if k is natural number (comprising 0), CSBL_A_n+ (L/2) * k just is connected on the first memory capacitance post, CSBL_B_n+ (L/2) * k just is connected on the second memory capacitance post, CSBL_A_n+1+ (L/2) * k just is connected on the 3rd memory capacitance post, CSBL_B_n+1+ (L/2) * k just is connected on the 4th memory capacitance post, CSBL_A_n+2+ (L/2) * k just is connected on the 5th memory capacitance post, CSBL_B_n+2+ (L/2) * k just is connected on the 6th memory capacitance post, CSBL_A_n+ (L/2)-2+ (L/2) * k just is connected on (L-3) memory capacitance post, CSBL_B_n+ (L/2)-2+ (L/2) * k just is connected on (L-2) memory capacitance post, CSBL_A_n+ (L/2)-1+ (L/2) * k just is connected on (L-1) memory capacitance post, CSBL_B_n+ (L/2)-1+ (L/2) * k just is connected on L memory capacitance post.
According to an embodiment, respectively by first to L memory capacitance post supply with first to the L that is horizontal scanning period oscillation period of L memory capacitance inverse voltage doubly.
According to an embodiment, a large amount of memory capacitance posts comprise the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post, the 7th memory capacitance post and the 8th memory capacitance post that is electrically insulated from each other; be made as CSBL_A_n and if be connected to the storage capacitance line of the first subpixel memory capacitance counter electrode of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the second subpixel memory capacitance counter electrode, and if k is natural number (comprising 0), CSBL_A_n+8*k and CSBL_B_n+4+8*k just are connected on the first memory capacitance post, CSBL_B_n+8*k and CSBL_A_n+4+8*k just are connected on the second memory capacitance post, CSBL_A_n+1+8*k and CSBL_B_n+5+8*k just are connected on the 3rd memory capacitance post, CSBL_B_n+1+8*k and CSBL_A_n+5+8*k just are connected on the 4th memory capacitance post, CSBL_A_n+2+8*k and CSBL_B_n+6+8*k just are connected on the 5th memory capacitance post, CSBL_B_n+2+8*k and CSBL_A_n+6+8*k just are connected on the 6th memory capacitance post, CSBL_A_n+3+8*k and CSBL_B_n+7+8*k just are connected on the 7th memory capacitance post, CSBL_B_n+3+8*k and CSBL_A_n+7+8*k just are connected on the 8th memory capacitance post.
According to an embodiment, be 8 times of horizontal scanning period the oscillation period of the first to the 8th memory capacitance inverse voltage of supplying with by the first to the 8th memory capacitance post respectively.
according to an embodiment, a large amount of memory capacitance posts comprise the first memory capacitance post of being electrically insulated from each other, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post, the 7th memory capacitance post, the 8th memory capacitance post ... (L-3) memory capacitance post, (L-2) memory capacitance post, (L-1) memory capacitance post and L memory capacitance post etc. are L memory capacitance post altogether, and when 1/2 of the quantity L of the memory capacitance post of electrical isolation is even number, namely work as L=4, 8, 12, Deng the time, if be connected to be arranged in the ranks matrix arbitrarily the storage capacitance line of the first subpixel memory capacitance counter electrode of the pixel of the row n of the nominated bank infall that forms of row and a large amount of pixels be made as CSBL_A_n, be made as CSBL_B_n if be connected to the storage capacitance line of the second subpixel memory capacitance counter electrode, and if k is natural number (comprising 0), CSBL_A_n+L*k and CSBL_B_n+ (L/2)+L*k just is connected on the first memory capacitance post, CSBL_B_n+L*k and CSBL_A_n+ (L/2)+L*k just is connected on the second memory capacitance post, CSBL_A_n+1+L*k and CSBL_B-n+ (L/2)+1+L*k just is connected on the 3rd memory capacitance post, CSBL_B_n+1+L*k and CSBL_A_n+ (L/2)+1+L*k just is connected on the 4th memory capacitance post, CSBL_A_n+2+L*k and CSBL_B_n+ (L/2)+2+L*k just is connected on the 5th memory capacitance post, CSBL_B_n+2+L*k and CSBL_A_n+ (L/2)+2+L*k just is connected to the 6th memory capacitance post, CSBL_A_n+3+L*k and CSBL_B_n+ (L/2)+3+L*k just is connected on the 7th memory capacitance post, CSBL_B_n+3+L*k and CSBL_A_n+ (L/2)+3+L*k just is connected on the 8th memory capacitance post, CSBL_A_n+ (L/2)-2+L*k and CSBL_B_n+L-2+L*k just are connected on (L-3) memory capacitance post, CSBL_B_n+ (L/2)-2+L*k and CSBL_A_n+L-2+L*k just are connected on (L-2) memory capacitance post, CSBL_A_n+ (L/2)-1+L*k and CSBL_B_n+L-1+L*k just are connected on (L-1) memory capacitance post, and CSBL_B_n+ (L/2)-1+L*k and CSBL_A_n+L-1+L*k just are connected on L memory capacitance post.
According to an embodiment, respectively by first to L memory capacitance post supply with first to the L that is horizontal scanning period oscillation period of L memory capacitance inverse voltage doubly.
A fourth aspect of the present invention provides a kind of liquid crystal display, it comprises a large amount of pixels, each pixel has liquid crystal layer and is used for liquid crystal layer is executed alive a large amount of electrodes with the ranks matrix distribution, and each that it is characterized in that a large amount of pixels has can apply to liquid crystal layer the first subpixel and second subpixel of mutually different voltage; This is in determines that the first subpixel under gray scale has the brightness higher than the second subpixel; Each comprises the first subpixel and the second subpixel: by counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode, with by the storage capacitor electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with storage capacitor electrode that are electrically connected on the subpixel electrode; Counter electrode is the single electrode of being shared by the first subpixel and the second subpixel, and the memory capacitance counter electrode of the first subpixel and the second subpixel is electrically insulated from each other; Liquid crystal display also comprises the memory capacitance post that is electrically insulated from each other in a large number, each memory capacitance post is electrically connected on any memory capacitance counter electrode of the first subpixel and the second subpixel in a large amount of pixels through storage capacitance line, and on column direction, the memory capacitance counter electrode of first subpixel of one of two adjacent image points is connected on the equipotential storage capacitance line of memory capacitance counter electrode of the second subpixel with another; And the quantity of the memory capacitance post that is electrically insulated from each other in a large amount of memory capacitance posts is L or larger (L is even number), the memory capacitance inverse voltage of being supplied with by each memory capacitance post is oscillating voltage, and be 2*K*L (K is positive integer) times of horizontal scanning period oscillation period.
According to an embodiment, if the storage capacitance line of the memory capacitance counter electrode of the first subpixel of the pixel of the row nominated bank year infall that is connected to that the pixel that is arranged in any row and a large amount of ranks matrix distribution forms is made as CSBL_ (n) A, the storage capacitance line that is connected to the memory capacitance counter electrode of the second subpixel is made as CSBL_ (n) B, and the CS bus that is connected to the memory capacitance post of L electrical isolation satisfies following relationship:
CSBL_(p+2*(1-1))B，(p+2*(1-1))+1)A，
CSBL_(p+2*(2-1))B，(p+2*(2-1))+1)A，
CSBL_(p+2*(3-1))B，(p+2*(3-1))+1)A，
…
CSBL_ (p+2* (K-1)) B, (p+2* (K-1))+1) A, and
CSBL_(p+2*(1-1)+K*L+1)B，(p+2*(1-1))+K*L+2)A，
CSBL_(p+2*(2-1)+K*L+1)B，(p+2*(2-1))+K*L+2)A，
CSBL_(p+2*(3-1)+K*L+1)B，(p+2*(3-1))+K*L+2)A，
…
CSBL_(p+2*(K-1)+K*L+1)B，(p+2*(3-1))+K*L+2)A，
Or
CSBL_(p+2*(1-1)+1)B，(p+2*(1-1)+2)A，
CSBL_(p+2*(2-1)+1)B，(p+2*(2-1)+2)A，
CSBL_(p+2*(3-1)+1)B，(p+2*(3-1)+2)A，
…
CSBL_(p+2*(K-1)+1)B，(p+2*(K-1)+2)A，
With
CSBL_(p+2*(1-1)+K*L)B，(p+2*(1-1)+K*L+1)A，
CSBL_(p+2*(2-1)+K*L)B，(p+2*(2-1)+K*L+1)A，
CSBL_(p+2*(3-1)+K*L)B，(p+2*(3-1)+K*L+1)A，
…
CSBL_(p+2*(K-1)+K*L)B，(p+2*(K-1)+K*L+1)A，
Herein, p=1,3,5 etc., or p=0,2,4 etc.
According to an embodiment, K be 1 or 2, L be any one in 6,8,10 and 12.
According to an embodiment, preferred storage capacitance line is placed on column direction between two adjacent pixels.
According to an embodiment, liquid crystal display comprises: two on-off elements that are respectively the first subpixel and the configuration of the second subpixel; Jointly be connected to two sweep traces on on-off element, it is characterized in that the common scanning line is placed between the first subpixel and the second subpixel.
According to an embodiment, a large amount of memory capacitance posts are supplied with the memory capacitance inverse voltage for forming the even number memory capacitance post of paired memory capacitance post, and the vibration of inverse voltage has the phase differential of 180 ° each other.
According to an embodiment, in any two adjacent image points of column direction, the memory capacitance counter electrode of the memory capacitance counter electrode of the first subpixel of a pixel and the second subpixel of another pixel is connected on common storage electric capacity line
According to an embodiment, the dutycycle of memory capacitance inverse voltage is 1: 1.
According to an embodiment, the first subpixel in arbitrary pixel be arranged to column direction on the second subpixel of the adjacent pixel of arbitrary pixel adjacent, and in each of a large amount of pixels, the first subpixel be arranged to column direction on the second subpixel adjacent.
According to an embodiment, the first subpixel and the second subpixel area approximation equate.
According to an embodiment, the area of the second subpixel is greater than the area of the first subpixel.
A first aspect of the present invention can reduce the view angle dependency of γ characteristic in liquid crystal display.Particularly, can there be the liquid crystal display at wide visual angle such as the γ characteristic of MAV or ASV liquid crystal display to realize high display quality by improvement.
A second aspect of the present invention can reduce by the flicker that exchanges on electrically driven (operated) liquid crystal display.Reduce flicker by merging a first aspect of the present invention and second aspect, can providing a kind of, improved the viewing angle characteristic of γ characteristic and the liquid crystal display of high display quality.
A third aspect of the present invention can increase the oscillation period of the voltage (oscillating voltage) that is applied to memory capacitance counter electrode in liquid crystal display according to second aspect.Thereby, a kind of such liquid crystal display can be provided, and this display is suitable for improving greatly or the viewing angle characteristic of the liquid crystal display of high-resolution by a pixel being divided into two or more subpixel and with different luminance levels, subpixel being thrown light on.
A fourth aspect of the present invention can also utilize common storage electric capacity line (CS bus) to supply with oscillating voltage to the subpixel of adjacent image point on column direction except the oscillation period that can increase the voltage (oscillating voltage) that is applied to the memory capacitance counter electrode the same as the third aspect.Therefore, if storage capacitance line is placed between adjacent image point on column direction, also can be used as black matrix" (BM).Thereby fourth aspect has advantages of can increase the pixel aperture ratio, and it can save, and the black matrix" that provides separately is provided in the liquid crystal display situation of the third aspect, and has reduced the quantity of CS bus than the third aspect.
Description of drawings
Fig. 1 is the pixel structure schematic diagram according to the liquid crystal display 100 of first aspect present invention embodiment;
Fig. 2 A～2C is the structural representation according to the liquid crystal display of the embodiment of the present invention;
Fig. 3 A～3C means the structural representation of conventional liquid crystal display 100 ';
Fig. 4 A～4C is the display characteristic sketch of MVA liquid crystal display, and wherein Fig. 4 A is transmissivity and executes alive relation curve, and Fig. 4 B is the perspective rate figure about Fig. 4 A after transmissivity normalization under white mode, and Fig. 4 C means the sketch of γ characteristic;
Fig. 5 A～5D means the sketch of the state A～D of the voltage that is applied to the liquid crystal layer by dividing the subpixel that pixel obtains;
Fig. 6 A～6B means the γ family curve that obtains under voltage status A shown in Figure 5～D, wherein Fig. 6 A represents the visual angle γ characteristic on 60 °, right side, and Fig. 6 B means the visual angle γ characteristic of 60 ° of upper right sides;
Fig. 7 means white mode transmissivity (facing) curve that obtains under voltage status A～D;
Fig. 8 A～8B means that according to the curve of the embodiment of the present invention in the Area Ratio between subpixel under voltage status C and γ characteristic, wherein Fig. 8 A represents the visual angle γ characteristic on 60 °, right side, and Fig. 8 B means the visual angle γ characteristic of 60 ° of upper right sides;
Fig. 9 is at the relation curve between white mode transmissivity (facing) and subpixel Area Ratio under voltage status C according to the embodiment of the present invention;
Figure 10 A～10B means the curve according to embodiment of the present invention γ characteristic of subpixel under voltage status B, and wherein Figure 10 A represents the visual angle γ characteristic on 60 °, right side, and Figure 10 B means the visual angle γ characteristic of 60 ° of upper right sides;
Figure 11 means according to the relation curve of the embodiment of the present invention between white mode transmissivity under voltage status B and subpixel number;
Figure 12 is the pixel structure schematic diagram of liquid crystal display 200 according to another embodiment of the present invention;
Figure 13 means the equivalent circuit schematic of the pixel of liquid crystal display 200;
Figure 14 is the sketch for the various voltage waveforms (a)-(f) that drive liquid crystal display 200;
Figure 15 is the sketch that concerns that is applied in liquid crystal display 200 between the voltage of liquid crystal layer of subpixel;
Figure 16 A～16B means the γ characteristic sketch of liquid crystal display 200, and wherein Figure 16 A represents the visual angle γ characteristic on 60 °, right side, and Figure 16 B means the visual angle γ characteristic of 60 ° of upper right sides;
Figure 17 means the pixel distribution schematic diagram according to the liquid crystal display of second aspect present invention;
Figure 18 has the sketch of various voltages (signal) waveforms (a)-(j) of the liquid crystal display of structure shown in Figure 17 for driving;
Figure 19 means the pixel distribution schematic diagram of liquid crystal display according to another embodiment of the present invention;
Figure 20 has the sketch of various voltages (signal) waveforms (a)-(j) of the liquid crystal display of structure shown in Figure 19 for driving;
Figure 21 A is the pixel distribution schematic diagram of liquid crystal display according to another embodiment of the present invention, and Figure 21 B means the schematic diagram of the layout of storage capacitance line and storage capacitor electrode;
Figure 22 is the equivalent circuit schematic according to the specific region of the liquid crystal display of second aspect present invention;
Figure 23 A means oscillation period and the phase place sketch of the oscillating voltage that is applied to the CS bus with regard to the voltage waveform of grid bus, also represents the voltage of the subpixel electrode of liquid crystal display shown in Figure 22;
Figure 23 B means oscillation period and the phase place of supplying with the oscillating voltage of CS bus with regard to the voltage waveform of grid bus, and the voltage (voltage that is applied to liquid crystal layer has the polarity opposite with Figure 23 A) of the subpixel in liquid crystal display shown in expression Figure 22
Figure 24 A means the driving condition schematic diagram (adopting the voltage shown in Figure 23 A herein) of liquid crystal display shown in Figure 22;
Figure 24 B means the driving condition schematic diagram (adopting the voltage shown in Figure 23 B herein) of liquid crystal display shown in Figure 22;
Figure 25 A means the structural representation that is used for the oscillating voltage of supply liquid crystal display CS bus according to the embodiment of second aspect present invention, and Figure 25 B means the equivalent electrical circuit near the liquid crystal display electrical load resistance;
Figure 26 represents that the subpixel electrode does not have the blunt nosed oscillating voltage waveform (a)～(e) of CS voltage waveform;
Figure 27 represents that the subpixel electrode is not corresponding to the blunt nosed oscillating voltage waveform (a)～(e) of the CS voltage waveform of " 0.2H " CR time constant;
Figure 28 means the relation curve of the oscillation period of the oscillating voltage mean value of calculating based on waveform in Figure 26 and 27 and effective value and CS bus voltage;
Figure 29 is the equivalent voltage schematic diagram according to the liquid crystal display of third aspect present invention embodiment;
Figure 30 A means oscillation period and the phase place of supplying with the oscillating voltage of CS bus with regard to the voltage waveform of grid bus, and represents the voltage of the subpixel in liquid crystal display shown in Figure 29;
Figure 30 B means oscillation period and the phase place of supplying with the oscillating voltage of CS bus with regard to the voltage waveform of grid bus, and the voltage (voltage that is applied to liquid crystal layer has the polarity opposite with Figure 30 A) of the subpixel in liquid crystal display shown in expression Figure 22
Figure 31 A means the driving condition sketch (adopting the voltage shown in Figure 30 A herein) of liquid crystal display shown in Figure 29;
Figure 31 B means the driving condition sketch (adopting the voltage shown in Figure 30 B herein) of liquid crystal display shown in Figure 29;
Figure 32 is the equivalent voltage schematic diagram according to the liquid crystal display of third aspect present invention embodiment;
Figure 33 A means oscillation period and the phase place of supplying with the oscillating voltage of CS bus with regard to the voltage waveform of grid bus, and represents the voltage of the subpixel in liquid crystal display shown in Figure 32;
Figure 33 B means oscillation period and the phase place of supplying with the oscillating voltage of CS bus with regard to the voltage waveform of grid bus, and the voltage (voltage that is applied to liquid crystal layer has the polarity opposite with Figure 33 A) of the subpixel in liquid crystal display shown in expression Figure 32;
Figure 34 A means the driving condition sketch (adopting the voltage shown in Figure 33 A herein) of liquid crystal display shown in Figure 32;
Figure 34 B means the driving condition sketch (adopting the voltage shown in Figure 33 B herein) of liquid crystal display shown in Figure 32;
Figure 35 A represents according to the profile schematic diagram of black matrix" between CS bus and pixel in the liquid crystal display of third aspect present invention embodiment, and Figure 35 B means also the total line profile of CS as black matrix" between pixel in the liquid crystal display of fourth aspect present invention embodiment;
Figure 36 A means the driving condition sketch according to the liquid crystal display of fourth aspect present invention embodiment;
Figure 36 B means the driving condition sketch according to the liquid crystal display of fourth aspect present invention embodiment, wherein is applied to the opposite direction of driving condition shown in the electric field of liquid crystal layer and Figure 33 A;
Figure 37 means according to the matrix structure of the liquid crystal display of fourth aspect present invention embodiment (the connection pattern of CS bus) schematic diagram;
Figure 38 means the drive signal waveform schematic diagram of liquid crystal display shown in Figure 37;
Figure 39 means according to the matrix structure of the liquid crystal display of another embodiment of fourth aspect present invention (the connection pattern of CS bus) schematic diagram;
Figure 40 means the schematic diagram of the drive signal waveform of liquid crystal display shown in Figure 39;
Figure 41 means according to the matrix structure of the liquid crystal display of another embodiment of fourth aspect present invention (the connection pattern of CS bus) schematic diagram;
Figure 42 means the schematic diagram of the drive signal waveform of liquid crystal display shown in Figure 41;
Figure 43 means according to the matrix structure of the liquid crystal display of another embodiment of fourth aspect present invention (the connection pattern of CS bus) schematic diagram;
Figure 44 means the schematic diagram of the drive signal waveform of liquid crystal display shown in Figure 43;
Figure 45 means according to the matrix structure of the liquid crystal display of another embodiment of fourth aspect present invention (the connection pattern of CS bus) schematic diagram;
Figure 46 means the schematic diagram of the drive signal waveform of liquid crystal display shown in Figure 45;
Figure 47 means according to the matrix structure of the liquid crystal display of another embodiment of fourth aspect present invention (the connection pattern of CS bus) schematic diagram;
Figure 48 means the schematic diagram of the drive signal waveform of liquid crystal display shown in Figure 47;
Figure 49 means according to the matrix structure of the liquid crystal display of another embodiment of fourth aspect present invention (the connection pattern of CS bus) schematic diagram;
Figure 50 means the schematic diagram of the drive signal waveform of liquid crystal display shown in Figure 49
Embodiment
Structure and the operation of the liquid crystal display in first aspect present invention embodiment are described below with reference to accompanying drawing.
At first referring to Fig. 1,2A, 2B and 2C.Fig. 1 means the schematic diagram according to distribution of electrodes in the pixel of the liquid crystal display 100 of the embodiment of the present invention.Fig. 2 A is the general structure schematic diagram of liquid crystal display 100, and Fig. 2 B is the schematic diagram of electrode structure in pixel, and Fig. 2 C is along the sectional view of 2C-2C ' in Fig. 2 B.For the purpose of reference, Fig. 3 A, 3B and 3C represent respectively distribution of electrodes in the pixel of conventional liquid crystal display 100 ', electrode structure and along the sectional view of 3C-3C '.
Deceive work pattern according to the liquid crystal display 100 of the present embodiment with normal, and comprise that a large amount of pixels, each pixel have liquid crystal layer and are used for liquid crystal layer is executed alive a large amount of electrode.Although this sentences the TFT liquid crystal display is example, also can replace with other on-off element (as the MIM element).
Liquid crystal display 100 has a large amount of pixels 10 with matrix distribution.Each of a large amount of pixels 10 has liquid crystal layer 13.In addition, pixel has pixel capacitors 18 and the counter electrode 17 of oneself, to apply voltage to liquid crystal layer 13.Typically, counter electrode 17 is single electrodes public to all pixels 10.
In the liquid crystal display 100 according to the present embodiment, each of a large amount of pixels 10 has the first subpixel 10a and the second subpixel 10b that can apply mutually different voltage, as shown in Figure 1.
0≤gk≤gn (herein when demonstration is satisfied, gk and gn are not less than zero integer, and larger gk value is corresponding to higher brightness) gray scale the time, each of a large amount of pixels is to satisfy at least Δ V12 (gk)＞0V and Δ V12 (gk) in the scope of 0＜gk≤n-1 " mode of Δ V12 (gk+1) drives, wherein, Δ V12 (gk)=V1 (gk)-V2 (gk) is r.m.s. voltage V2 (gk) poor that is applied to the r.m.s. voltage V1 (gk) of the first subpixel 10a liquid crystal layer and is applied to the liquid crystal layer of 10 ones of the second subpixel.
The subpixel quantity that each pixel 10 has (sometimes being called the quantity that pixel is divided) is not limited to two.Each pixel 10 can also have the 3rd subpixel (not shown), and it is applied the voltage that is different from the first subpixel 10a and the second subpixel 10b.In this case, if pixel design becomes hypothesis Δ V13=V1 (gk)-V3 (gk), the r.m.s. voltage of V3 (gk) for the liquid crystal layer of the 3rd subpixel is applied herein, and Δ V13 (gk) satisfies 0V＜Δ V13 (gk)＜Δ V12 (gk) for the r.m.s. voltage and r.m.s. voltage poor that imposes on the 3rd subpixel liquid crystal layer of the liquid crystal layer that imposes on the first subpixel
The r.m.s. voltage that preferably is applied to the subpixel liquid crystal layer satisfies relationship delta V12 (gk)＞Δ V12 (gk+1) at least in the scope of 0＜gk≤n-1.Thereby preferred grey level becomes higher, and the difference that is applied to the r.m.s. voltage of the first subpixel 10a and the second subpixel 10b liquid crystal layer becomes less.In other words, preferably along with grey level's step-down (near black), the difference that is applied to the r.m.s. voltage of the first subpixel 10a and the second subpixel 10b liquid crystal layer becomes larger.In addition, if each pixel has the 3rd subpixel, preferably satisfy at least relationship delta V12 (gk)＞Δ V12 (gk+1) and Δ V13 (gk)＞Δ V13 (gk+1) in the scope of 0＜gk≤n-1.
The area of the first subpixel 10a is equal to or less than the area of the second subpixel 10b.If each of a large amount of pixels has three or more subpixel, the area (being the first subpixel in the case) that preferably is applied in the subpixel of the highest r.m.s. voltage is not more than subpixel (being the second subpixel in the case) area that is applied in minimum r.m.s. voltage.Specifically, if each pixel 10 have a large amount of subpixel SP1, SP2 ... and SPn, and the r.m.s. voltage that is applied to liquid crystal layer be V1 (gk), V2 (gk) ... and Vn (gk), preferably satisfy V1 (gk)＞V2 (gk)＞...＞Vn (gk).In addition, if the area of subpixel be SSP1, SSP2 ... and SSPn, preferably satisfy SSP1≤SSP2≤...≤SSPn.
If at least for all gray scales (that is, in the scope of 0＜gk≤n-1) except the highest gray scale and minimum gray scale satisfy V1 (gk)＞V2 (gk)＞...＞Vn (gk), can realize the present invention.But, also can implement a kind of structure that all gray scales (that is, in the scope of 0≤gk≤n) is satisfied this relational expression.
In this way, if each pixel is divided into a large amount of subpixel, and the liquid crystal layer of subpixel is applied different voltage, obtain the mixing of different γ characteristics, thereby, the view angle dependency of γ characteristic can be reduced.In addition, because the r.m.s. voltage difference of low gray scale arranges greatlyr, so greatly reduce at normal view angle dependency of deceiving black side (low brightness levels) the γ characteristic of pattern.This is very effective aspect the raising display quality.
Can apply r.m.s. voltage in the mode that satisfies the above-mentioned relation formula to the liquid crystal layer of subpixel 10a and 10b with different structures.
For example, liquid crystal display 100 can consist of as shown in Figure 1.Specifically, in conventional liquid crystal display 100 ', pixel 10 only has a pixel capacitors 18 to be connected on signal wire 14 through TFT 16, and liquid crystal display 100 has two sub-pixel capacitors 18a and 18b to be connected on different signal wire 14a and 14b through TFT 16a and 16b respectively.
Because subpixel 10a and 10b form a pixel 10, so the grid of TFT16a and 16b is connected on common scanning line (gate line) 12, and opens and close by the common scanning signal.Signal wire (source bus line) 14a and 14b are supplied with the signal voltage (grayscale voltage) that satisfies above-mentioned relation.The gate configuration of preferred TFT16a and 16b becomes public grid.
perhaps, each comprises by the storage capacitor electrode that is electrically connected to the subpixel electrode in the first subpixel and the second subpixel, in the structure of insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with storage capacitor electrode (back description), the first subpixel of being electrically insulated from each other and the memory capacitance counter electrode of the second subpixel preferably are provided, and the voltage (being called the memory capacitance counter electrode voltage) of supplying with the memory capacitance counter electrode by change changes the r.m.s. voltage that is applied to the first subpixel liquid crystal layer and the r.m.s. voltage that is applied to the second subpixel liquid crystal layer.By the value of regulating memory capacitance and the voltage swing of supplying with the memory capacitance counter electrode, can control the size of the r.m.s. voltage that is applied to the subpixel liquid crystal layer.
In this structure, because do not need antithetical phrase pixel capacitors 18a and 18b to apply different signal voltages, so TFT three 16a and 16b can be connected on common signal line, and can supply with identical signal voltage to them.Therefore, the quantity of signal wire is in the situation that conventional liquid crystal display 100 ' shown in Figure 3 is identical, and can utilize the signal-line driving circuit that same structure is arranged with conventional liquid crystal display 100 '.Certainly, because TFT three 16a and 16b are connected on same sweep trace, thus preferred the same with the situation of above-mentioned example, share public grid.
Preferred the present invention is applied to the liquid crystal display of the liquid crystal layer that adopts homeotropic alignment, and wherein liquid crystal layer comprises the nematic liquid crystal material with negative dielectric anisotropic.Particularly, preferably the liquid crystal layer of each subpixel comprises four and separates the farmland of about 90 ° at azimuth direction, just inclination (MVA) of liquid crystal molecule when applying voltage.Perhaps, the liquid crystal layer of each subpixel is kept when applying voltage and is axially arranged symmetrically (ASM).
Under regard to MVA liquid crystal display 100 embodiments of the present invention will be described in more detail, wherein the liquid crystal layer of each subpixel comprises four and separates the farmland of about 90 ° at azimuth direction, liquid crystal molecule just tilts when applying voltage.
As shown in Fig. 2 A, MVA liquid crystal display 100 comprises liquid crystal board 10A, (the typically being the phase difference compensation plate) 20a that is arranged on the phase difference compensating element of liquid crystal board 10A both sides and 20b, polaroid 30a and 30b and backlight assembly 40 that compensating plate is clipped in the middle.The axis of homology of polaroid 30a and 30b (also referred to as polarization axle) orthogonal (Niccol distribution) is to such an extent as to aobvious black when the liquid crystal layer (not shown) of liquid crystal board 10A is not applied voltage (homeotropic alignment state).Provide phase difference compensating element 20a and 20b improving the viewing angle characteristic of liquid crystal display, and utilize the known technology optimal design.Specifically, optimize (gk=0) poor minimum that is kept to of brightness (black level) for top view with arbitrary orientation angle stravismus the time.When optimizing by this way phase difference compensating element 20a and 20b, the present invention can produce larger visual field effect.
In fact, form common scanning line 12, signal wire 14a and 14b and TFT16a and 16b (seeing Fig. 1) on substrate 11a, to apply prearranged signal voltage at schedule time antithetical phrase pixel capacitors 18a and 18b respectively.In addition, form as required circuit etc. to drive these elements.In addition, on another substrate 11b, colored filter etc. is set as required.
Below with reference to Fig. 2 A～2C, pixel structure in MVA liquid crystal display 100 is described.For example treat to have described in publication application JP11-242225 structure and the work of MVA liquid crystal display in Japan.
As described in reference to figure 1, the pixel 10 in MVA liquid crystal display 100 has two subpixel 10a and 10b, and the subpixel 10a in subpixel has subpixel electrode 18a, and subpixel 10b has subpixel electrode 18b.As shown in Fig. 2 C, the subpixel electrode 18a (with subpixel electrode 18b (not shown)) that is formed on substrate of glass 11a has slit 18s, and forms tilting electric field with being placed to subpixel electrode 18a together with the relative counter electrode 17 of liquid crystal layer 13.In addition, in the arrangement of substrate of glass 11b protruding rib 19 to liquid crystal layer 13 is set on the surface of counter electrode 17.Liquid crystal layer 13 is made by the nematic liquid crystal material with negative dielectric anisotropic.When not applying voltage, it is by covering the homeotropic alignment film (not shown) near vertical ground arrangement of counter electrode 17, rib 19 and subpixel electrode 18a and 18b.The liquid crystal molecule of homeotropic alignment is laid on predetermined direction restfully by rib 19 surfaces (dip plane) and tilting electric field.
As shown in Fig. 2 C, the mode wherein heart inclination of rib 19 to form an angle.The liquid crystal molecule near vertical is arranged in ground, dip plane.Thereby rib 19 determines inclination angle (angle that is formed by the major axis of substrate surface and the liquid crystal molecule) distribution of liquid crystal molecules.Slit 18s changes the direction of the electric field that is applied to liquid crystal layer regularly.Therefore, when applying electric field, liquid crystal molecule provides vertical and viewing angle characteristic horizontal symmetrical, good by rib 19 and slit 18 four direction shown in arrow---upper right, upper left, lower-left and bottom right---arrangement in the drawings.The rectangle display surface of liquid crystal board 10A is placed with its long scale level and the axis of homology of polaroid 30a is parallel to longer yardstick and places typically and be orientated.On the other hand, pixel 10 typically is orientated with the longer yardstick that its longer yardstick is orthogonal to liquid crystal board 10A, as shown in Fig. 2 B.
Preferably, as shown in Fig. 2 B, the area of the first subpixel 10a and the second subpixel 10b is in fact equal, each subpixel is included in first rib that first direction extends and at the upwardly extending second rib of second party, first rib in each subpixel and second rib are placed with respect to the center line that is parallel to sweep trace 12 is symmetrical, and the distribution of the rib in one of them subpixel is symmetrical with respect to the center line that is orthogonal to sweep trace 12 with the rib distribution in another subpixel.This kind distribution causes liquid crystal molecule---upper right, upper left, lower-left and bottom right---the upper distribution at four direction in each subpixel, and make the area on liquid crystal farmland in the whole pixel that comprises the first subpixel and the second subpixel in fact equal, vertical and horizontal symmetrical and good viewing angle characteristic are provided.In addition, the center line that preferably is parallel to the common scanning line in each subpixel is placed to be approximately equal to array of scan lines spacing half interval.
Next, work and display characteristic according to the liquid crystal display 100 of the embodiment of the present invention are described.
At first, referring to Fig. 4, to having the display characteristic of the MVA liquid crystal display of identical electrodes structure to describe with conventional liquid crystal display 100 ' shown in Figure 3.By the way, the liquid crystal layer according to subpixel 10a and 10b in the liquid crystal display 100 of the embodiment of the present invention (being subpixel electrode 18a and 18b) is applied the display characteristic that display characteristic that identical r.m.s. voltage obtains is approximately equal to conventional liquid crystal display.
Fig. 4 A be from the front side (N1), right side 60 ° (L1) and from the upper right 60 ° (LU1) watch when showing transmissivity with execute alive dependence.Fig. 4 B is that to use transmissivity that the highest grayscale voltage (voltage that display white is required) obtains be three transmittance graphs shown in Fig. 4 A after 100% normalization.Under three kinds of conditions of its expression: the transmissivity of facing state (N2), right side 60 ° (L2) and 60 ° of (LU2) normalization from the upper right with execute alive relation: face state (N2), right side 60 ° (L2) and from the upper right 60 ° (LU2).By the way, " 60 ° " refer to press from both sides with the display surface normal angle of 60 °.
As can be seen from Figure 4B, the display characteristic of facing is different from the display characteristic of 60 ° of 60 °, right side and upper right sides.This shows that the γ characteristic depends on direction of observation.
Fig. 4 C more clearly represents the difference of γ characteristic.in order clearly to represent the difference of γ characteristic, transverse axis representative (facing the transmissivity of normalization/100) ^ (1/2.2), and vertical axes represents N3, gamma characteristic under L3 and LU3 state: face gamma characteristic=(facing the transmissivity of normalization/100) ^ (1/2.2), 60 °, right side visual angle gamma characteristic=(transmissivity of the 60 ° of normalization in right side/100) ^ (1/2.2), 60 ° of upper right sides visual angle gamma characteristic=(transmissivity of the 60 ° of normalization in upper right side/100) ^ (1/2.2), "-" represents index herein, the inverse of index is corresponding to the γ value.In typical liquid crystal display, the γ value of facing gamma characteristic is made as 2.2.
Referring to Fig. 4 C, under state (N3), abscissa value overlaps with ordinate value facing, thereby the gamma characteristic under this state (N3) is linear.On the other hand, the 60 ° of visual angle gamma characteristics in the 60 ° of visual angle gamma characteristics in right side (L3) and upper right side (LU3) are curve.The deviation of facing state (N3) lower curve (L3 and LU3) and straight line represents each deviation of γ characteristic quantitatively, i.e. the deviation (difference) of gray scale demonstration.
The present invention is intended to reduce this deviation in normal black liquor crystal display.Desirable situation is to represent that the curve (L3 and LU3) of the 60 ° of visual angle gamma characteristics in the 60 ° of visual angle gamma characteristics in right side (L3) and upper right side (LU3) overlaps with the straight line that gamma characteristic (N3) is faced in representative.Assessment improves the effect of γ characteristic below with reference to the accompanying drawings, and wherein accompanying drawing represents the difference of γ characteristic, as the situation shown in Fig. 4 C.
Referring to Fig. 4 B, how the below will can describe by the first subpixel and the second subpixel being set in each pixel and the liquid crystal layer of subpixel being applied the cardinal principle that different r.m.s. voltage reduces the deviation of γ characteristic the present invention.Suppose that the first subpixel and the second subpixel have identical area herein.
For the liquid crystal display 100 ' of routine, represented that by a NA voltage place that is facing transmissivity, 60 °, right side visual angle transmissivity are represented by a LA, its mid point LA represents 60 °, the right side visual angle transmissivity with the identical voltage of NA.About the present invention, obtain with put NA identical face transmissivity, the transmissivity of facing of the first subpixel and the second subpixel can be separately positioned on a NB1 and NB2.Because the transmissivity of facing at some NB2 place is approximately zero, and the first subpixel and the second subpixel have identical area, so the transmissivity of facing at NB1 place is the twice that some NA place faces transmissivity.The difference of the r.m.s. voltage between some NB1 and NB2 is Δ V12.In addition, for the present invention, 60 °, right side visual angle transmissivity is by some P representative, and it is as 60 °, the right side visual angle transmissivity LB1 at voltage identical with NB2 with a NB1 respectively place and the mean value of LB2.
For liquid crystal display according to the present invention, the some P ratio that represents the 60 ° of visual angle transmissivities in right side represents that the some LA of the 60 ° of visual angle transmissivities in right side of conventional liquid crystal display 100 ' is more approaching and represents the corresponding some NA that faces transmissivity.The deviation that this means the γ characteristic reduces.
As can be seen from the above, approaching zero the fact of 60 °, the right side visual angle transmissivity (seeing a LB2) of the second subpixel has strengthened effect of the present invention.Thereby, strengthen effect of the present invention, the preferred increase of controlling transmissivity when looking side ways blank screen.From. this viewpoint, phase difference compensating element 20a and 20b as shown in Fig. 2 A preferably are installed as required, thus the increase of transmissivity when controlling the stravismus blank screen.
Liquid crystal display 100 according to the present invention applies different r.m.s. voltage by two liquid crystal layers to each subpixel 10a and 10b in each pixel 10 and improves the γ characteristic.When doing like this, the difference Δ V12 (gk)=V1 (gk) V2 (gk) of r.m.s. voltage that is applied to each liquid crystal layer of subpixel 10a and 10b is arranged to satisfy Δ V12 (gk)＞0V and Δ V12 (gk) 〉=Δ V12 (gk+1).The below will be described in the situation that satisfies above-mentioned relation in the gamut of 0＜gk≤n.
Fig. 5 A～5D represent to be applied to pixel 10 shown in Figure 1 the first subpixel 10a liquid crystal layer r.m.s. voltage V1 (gk) and be applied to multiple relation between the r.m.s. voltage V2 (gk) of liquid crystal layer of the second subpixel 10b.
Apply under state A at the voltage shown in Fig. 5 A, apply identical voltage (V1=V2) to the liquid crystal layer of two sub-pixel 10a and 10b.Thereby, Δ V12 (gk)=0V.
Under the voltage status B shown in Fig. 5 B, keep concerning V1＞V2, and V12 is the constant irrelevant with the V1 value.Thereby, under voltage status B, any gray scale gk is satisfied relationship delta V12 (gk)=Δ V12 (gk+1).This embodiment adopts Δ V12 (gk)=1.5V as representative value, certainly, also can adopt other value.Larger Δ V12 (gk) value has strengthened effect of the present invention, but causes the problem of the brightness (transmissivity) that reduces in white mode.In addition, when the value of Δ V12 (gk) surpassed the threshold voltage (being the Vth shown in Fig. 4 B) of transmissivity of liquid crystal display, the brightness (transmissivity) of black pattern increased, and the display comparison degree reduces, and this is a problem.Therefore, Δ V12 (gk)≤Vth preferably.
Under the voltage status C shown in Fig. 5 C, keep concerning V1＞V2, and Δ V12 reduces along with the increase of V1.Thereby, under voltage status C, any gray scale gk is satisfied relationship delta V12 (gk)＞Δ V12 (gk+1).
This embodiment adopts Δ V12 (0)=1.5V and Δ V12 (n)=0V as representative value, certainly, also can adopt other value.Yet, as mentioned above, preferably light Δ V12 (gk)≤Vth from the setting of display comparison degree during looking side ways, preferably Δ V12 (n)=0V is lighted in the setting of brightness from white mode.
Under the voltage status D shown in Fig. 5 D, keep concerning V1＞V2, and Δ V12 increases with the increase of V1.Thereby, under voltage status D, any gray scale gk is kept Δ V12 (gk)＜Δ V12 (gk+1).
The present embodiment adopts Δ V12 (0)=0V and Δ V12 (n)=1.5V as representative value.
In the liquid crystal display 100 according to the embodiment of the present invention, the liquid crystal layer of subpixel 10a and 10b is applied voltage, make and will satisfy voltage status B or voltage status C.By the way, although satisfy Δ V12 (gk)＞0 for all gray scales in Fig. 5 B and Fig. 5 C, in the situation that optimum gradation or the highest gray scale Δ V12=0 all set up.
The gamma characteristic of MVA liquid crystal display under voltage status A～D is described below with reference to Fig. 6.Transverse axis in Fig. 6 A and 6B representative (facing the transmissivity of normalization/100) ^ (1/2.2), vertical axes representative (transmissivity of the 60 ° of normalization in right side/100) ^ (1/2.2) in Fig. 6 A, vertical axes representative (transmissivity of the 60 ° of normalization in the upper right side/100) ^ (1/2.2) in Fig. 6 B.Also show representative in figure and face the straight line of gamma characteristic in the lump for reference.
Under voltage status A, the liquid crystal layer of subpixel 10a and 10b is applied identical voltage (Δ V12 (gk)=0).As shown in Fig. 6 A and 6B, the same with conventional liquid crystal display shown in Fig. 4, the γ characteristic greatly departs from.
Voltage status D is on the impact of the view angle dependency that reduces the γ characteristic situation less than voltage status B and C.For example, the voltage status of the pixel divided corresponding to the conventional capacity that utilizes Japan to treat to describe in publication application JP6-332009 of voltage status D.Although influential to improving viewing angle characteristic under normal white mode, the view angle dependency that reduces the γ characteristic under normal black pattern is not had a great impact.
As mentioned above, preferred voltage state B or C are used for reducing often to deceive the view angle dependency of γ characteristic under pattern.
Next, referring to Fig. 7, the variation to white mode transmissivity in voltage status, when namely applying the highest grayscale voltage is described.
Transmissivity in white mode is natural in the situation under voltage status A under voltage status B and D.Under voltage status C, the transmissivity of white mode equals the transmissivity under voltage status A.In this regard, preferably voltage status B and D of voltage status C.Thereby, consider the view angle dependency of γ characteristic and the transmissivity in white mode, can say that voltage status C is more superior.
Next the preferred Area Ratio between the descriptor pixel.
According to the present invention, if be applied to subpixel SP1, SP2 ... with the r.m.s. voltage of the liquid crystal layer of SPn be V1, V2 ... Vn, if the area of subpixel be SSP1, SSP2 ... and SSPn, and if keep concerning V1＞V2＞... Vn preferably satisfies SSP1≤SSPn.Will there be description the back.
Suppose that SSP1 and SSP2 are the areas of subpixel 10a and 10b in pixel 10 shown in Figure 1.Fig. 8 has compared the (SSP1: the γ characteristic between SSP2)=(1: 3), (1: 2), (1: 1), (2: 1), (3: 1) of Area Ratio under voltage status C.Fig. 8 A represents the γ characteristic at visual angle, right side, and Fig. 8 B represents the γ characteristic at visual angle, upper right side.Fig. 9 represents the transmissivity of facing of different Xia Sew ratios.
As can be seen from Figure 8, be applied in high voltage subpixel (10a) Area Ratio reduce the view angle dependency that reduces the γ characteristic more effective.
(SSP1: the transmissivity in the time of SSP2)=(1: 1) in white mode is got maximal value, and along with Area Ratio becomes inhomogeneous and reduces when Area Ratio.This is because if Area Ratio becomes inhomogeneous, no longer can obtain good multidomain homeotropic alignment, thereby has reduced the area of the first subpixel and the second subpixel.This trend is concluded in having the high-resolution liquid crystal display of little elemental area.Thereby, although preferred Area Ratio is 1: 1, considering the impact of view angle dependency, the transmissivity in white mode and the utilization of liquid crystal display etc. that reduce the γ characteristic, can regulate as required.
Next the number of partitions of pixel will be described.
Although for liquid crystal display shown in Figure 1 100, pixel 10 is comprised of two subpixel (10a and 10b), the invention is not restricted to this, the quantity of subpixel can be for three or more.
The γ characteristic that Figure 10 comparison obtains under three kinds of voltage statuss: pixel is divided into two subpixel; Pixel is divided into four subpixel; Be not divided with pixel.Figure 10 A represents the γ characteristic at visual angle, right side, and Figure 10 B represents the visual angle γ characteristic of upper right side.Figure 11 represents the corresponding transmissivity of liquid crystal display in white mode.The constant area of pixel, and adopted voltage status B.
As can be seen from Figure 10, the increase of subpixel quantity has increased the effect of proofreading and correct the deviation in the γ characteristic.Compare with not dividing pixel, the effect a when pixel is divided into two subpixel is especially affirmed.When the quantity of dividing rose to four from two, although there is no very large difference on the deviation of γ characteristic, characteristic was improved with regard to the smooth change of the deviation relevant with grey scale change.But as can be seen from Figure 11, the transmissivity in white mode (facing) descends with the increase of division numbers.Especially when being increased to four from two, the quantity of dividing descends very large.The main cause of this very large decline is that the area of each subpixel reduces as described above greatly.More do not divide and transmissivity reduces when being divided into two state main cause is to have adopted voltage status B.Thereby, consider the impact on the view angle dependency that reduces the γ characteristic, transmissivity in white mode and employing of liquid crystal display etc., the quantity that can regulate as required division.
As can be seen from above, the view angle dependency of the shape distortion of the deviation of γ characteristic, deviation and γ characteristic increases with the increase of pixel division numbers.These effects are particularly remarkable when more not dividing pixel and pixel and be divided into the state of two (two subpixel).Thereby, consider the decline of the white mode transmissivity that the decline by the increase of subpixel quantity and manufacturability causes, preferably a pixel is divided into two subpixel.
In liquid crystal display shown in Figure 1 100, subpixel 10a and 10b are connected on TFT16a and TFT 16b independently of one another.The source electrode of TFT 16a and TFT16b is connected respectively on signal wire 14a and 14b.Thereby, liquid crystal display 100 allows any r.m.s. voltage to be applied on each liquid crystal layer of subpixel, but requiring is the twice (signal wire 14a and 14b) of signal wire 14 of conventional liquid crystal display 100 ' shown in Figure 3, also needs the signal-line driving circuit more than twice.
On the contrary, liquid crystal display 200 has the signal wire with conventional liquid crystal display 100 ' equal number according to another embodiment of the present invention, but can under the voltage status of above-mentioned voltage status C, the liquid crystal layer to subpixel 10a and 10b applies mutually different r.m.s. voltage being similar to.
Figure 12 represents the circuit structure of liquid crystal display 200 according to another embodiment of the present invention.Have with the element of liquid crystal display 100 identical functions shown in Figure 1 and adopt the label identical with counter element and save description.
Pixel 10 is divided into subpixel 10a and 10b, and these subpixel are connected respectively on TFT 16a and TFT16b and memory capacitance (CS) 22a and 22b.The gate electrode of TFT16a and TFT16b is connected on sweep trace 12, and the source electrode is connected on common signal line 14. Memory capacitance 22a and 22b are connected respectively on storage capacitance line (CS bus) 24a and 24b.Memory capacitance 22a and 22b are formed by the insulation course (not shown) that is electrically connected to the memory capacitance on subpixel electrode 18a and 18b, the memory capacitance counter electrode that is electrically connected to storage capacitance line 24a and 24b and be formed at therebetween respectively.The memory capacitance counter electrode of memory capacitance 22a and 22b is independent of one another, and is supplied with mutually different memory capacitance inverse voltage through storage capacitance line 24a and 24b.
Next, with reference to accompanying drawing, how liquid crystal display 200 is described the principle that the liquid crystal layer of subpixel 10a and 10b applies different r.m.s. voltage.
Figure 13 represents the equivalent electrical circuit of a pixel of liquid crystal display 200.In equivalent electrical circuit, the liquid crystal layer of subpixel 10a and 10b represents with label 13a and 13b.The liquid crystal capacitance that is formed by subpixel electrode 18a and 18b, liquid crystal layer 13a and 13b and counter electrode 17 ( subpixel 10a and 10b share) represents with Clca and Clcb.
Suppose that liquid crystal capacitance Clca and Clcb have identical capacitance CLC (V).The value of CLC (V) depends on the r.m.s. voltage of the liquid crystal layer that imposes on subpixel 10a and 10b.The memory capacitance 22a and the 22b that are connected to independently of one another on the liquid crystal capacitance of subpixel 10a and 10b are represented by Ccsa and Ccsb, and suppose that their capacitance is CCS.
The electrode of one of the liquid crystal capacitance Clca of subpixel 10a and memory capacitance Ccsa is connected on the drain electrode of TFT 16a with driven element pixel 10a.Other electrode of liquid crystal capacitance Clca is connected on counter electrode, and another electrode of memory capacitance Ccsa is connected on storage capacitance line 24a.The electrode of one of the liquid crystal capacitance Clcb of subpixel 10b and memory capacitance Ccsb is connected on the drain electrode of TFT 16b with driven element pixel 10b.Another electrode of liquid crystal capacitance Clcb is connected on counter electrode, and another electrode of memory capacitance Ccsb is connected on storage capacitance line 24b.The gate electrode of TFT16a and TFT16b is connected on sweep trace 12, and the source electrode is connected on signal wire 14.
Figure 14 represents to use chronogram for the voltage that drives liquid crystal display 200.
In Figure 14, waveform (a) is the voltage waveform Vs of signal wire 14, waveform (b) is the voltage waveform Vcsa of storage capacitance line 24a, waveform (c) is the voltage waveform Vcsb of storage capacitance line 24b, waveform (d) is the voltage waveform Vg of sweep trace 12, waveform (e) is the voltage waveform V1ca of the subpixel electrode 18a of subpixel 10a, and waveform (f) is the voltage waveform V1cb of the subpixel electrode 18b of subpixel 10b.Dotted line in figure represents the voltage waveform COMMON (Vcom) of counter electrode 17.
The work of the equivalent electrical circuit in Fig. 3 is described with reference to Fig. 4.
At T1 constantly, when voltage Vg changes to VgH from VgL, TFT16a and TFT16b conducting simultaneously, and voltage Vs is transferred to subpixel electrode 18a and the 18b of subpixel 10a and 10b from signal wire 14, cause subpixel 10a and 10b to change.Similarly, the memory capacitance Csa of each subpixel and Csb charge from signal wire.
At moment T2, when the voltage Vg of sweep trace 12 became VgL from VgH, TFT 16a and TFT16b ended simultaneously.Therefore, subpixel 10a and 10b and memory capacitance Csa and Csb end with signal wire 14.The pulling effect that causes due to the stray capacitance of TFT 16a and TFT 16b, afterwards, the voltage V1ca of each subpixel and the V1ca approximately uniform voltage Vd that namely descends becomes:
V1ca＝Vs-Vd
V1cb＝Vs-Vd
At this moment, the voltage Vcsa of each storage capacitance line and Vcsb are:
Vcsa＝Vcom-Vad
Vcsb＝Vcom+Vad
At moment T3, the voltage Vcsa that is connected to the storage capacitance line 24a on memory capacitance Csa becomes " Vcom+Vad " from " Vcom-Vad ", and the voltage Vcsb that is connected to the storage capacitance line 24b on memory capacitance Csb changes the Vad of twice to " Vcom-Vad " from " Vcom+Vad ".The result that storage capacitance line 24a and 24b voltage change is that voltage V1ca and the V1cb of each subpixel become:
V1ca＝Vs-Vd+2*Kc*Vad
V1cb＝Vs-Vd-2*Kc*Vad
Herein, Kc=CCS/ (CLC (V)+CCS))
At moment T4, Vcsa becomes " Vcom-Vad " from " Vcom+Vad ", and Vcsb becomes " Vcom+Vad " from the Vad that " Vcom-Vad " changes twice.Therefore, V1ca and V1cb from:
V1ca＝Vs-Vd+2*Kc*Vad
V1cb＝Vs-Vd-2*Kc*Vad
Become:
V1ca＝Vs-Vd
V1cb＝Vs-Vd
At moment T5, Vcsa changes the Vad of twice from " Vcom-Vad ", become " Vcom+Vad ", and Vcsb becomes " Vcom-Vad " from the Vad that " Vcom+Vad " changes twice.Therefore, V1ca and V1cb from:
V1ca＝Vs-Vd
V1cb＝Vs-Vd
Become:
V1ca＝Vs-Vd+2*Kc*Vad
V1cb＝Vs-Vd-2*Kc*Vad
Vcsa, Vcsb, V1ca and V1cb change above-mentioned variation at T4 and the T5 moment with the interval of the integral multiple of level write time 1H.Be used for to change the interval integer 1,2 or 3 ... driving method (method of reversal of poles etc.) and the display condition (flicker, granularity etc.) that can consider liquid crystal display arrange afterwards as required.These replacement cycles repeat to pixel 10 always and are re-written to next constantly, that is, until equal the moment of T1.Therefore, the effective value of the voltage V1ca of subpixel and V1cb is
V1ca＝Vs-Vd+Kc*Vad
V1cb＝Vs-Vd-Kc*Vad
Thereby, be applied to the liquid crystal layer 13a of subpixel 10a and 10b and r.m.s. voltage V1 and the V2 of 13b and be:
V1＝V1ca-Vcom
V2＝V1cb-Vcom
As a result,
V1＝Vs-Vd+Kc*Vad-Vcom
V2＝Vs-Vd-Kc*Vad-Vcom
Therefore, be applied to the r.m.s. voltage of the liquid crystal layer 13a of subpixel 10a and 10b and 13b difference Δ V12 (=V1-V2) be Δ V12=2*Kc*Vad (Kc=CCS/ (CLC (V)+CCS)), herein.This means and to apply mutually different voltage.
Be shown in Figure 15 according to the V1 of Figure 12 to 14 illustrated embodiment and the relation between V2.
As can be seen from Figure 15, in the liquid crystal display 200 according to the present embodiment, the V1 value is less, and Δ V12 value is just larger.The result that obtains under this and above-mentioned voltage status C is similar.The fact that Δ V12 value changes according to V1 or V2 is owing to the capacitance CLC (V) of liquid crystal capacitance.
Be shown in Figure 16 according to the γ characteristic of the liquid crystal display 200 of the present embodiment.For the ease of relatively, the γ characteristic that obtains when subpixel 10a and 10b are applied identical voltage also is shown in Figure 16.As can be seen from the figure, also improve according to γ characteristic in the liquid crystal display of the present embodiment.
As mentioned above, embodiments of the invention can improve the γ characteristic of normal black liquor crystal display, especially MVA liquid crystal display.But, the invention is not restricted to this, also can be applied in the IPS liquid crystal display.
Next, the liquid crystal display according to second aspect present invention embodiment is described.
The below describes the distribute preferred form of (sub-pixel array) of the driving method that can reduce " flicker " on liquid crystal display or pixel, in pixel distributes, and the subpixel that when each pixel has at least two to show middle gray, brightness differs from one another.Although this structure and operation of sentencing the liquid crystal display of the present embodiment are described as the liquid crystal display example that has according to the division pixel structure of first aspect present invention embodiment, but the restriction that pixel distribution produce an effect is not divided by pixel, and also can adopt the liquid crystal display with another kind of pixel partition structure.
At first " flicker " problem on liquid crystal display is described.
From reliability, typical liquid crystal display is designed so that with alternating voltage as the voltage (sometimes also referred to as " ac drives method ") that is applied to the pixel liquid crystal layer.The magnitude relationship of the electromotive force between pixel capacitors and counter electrode is reversed at a certain time interval, and the direction of an electric field (line of electric force) that therefore is applied to each liquid crystal layer is also with this time interval counter-rotating.Be placed in exemplary lcd on different base for counter electrode and pixel capacitors, the direction of an electric field that is applied to each liquid crystal layer is reversed to the direction of observer-light source from light source-observer's direction.
Typical situation is, the direction of an electric field returing cycle that is applied to each liquid crystal layer be the twice of Frame cycle (as 16.667ms) (as, 33.333ms).In other words, in liquid crystal display, be applied to direction of an electric field counter-rotating when each demonstration image (frame image) changes of each liquid crystal layer.Thereby, when showing still image, if inaccurately mate in the electric field intensity (voltage that applies) of alternating direction, if namely electric field intensity changes when each direction of an electric field changes, the brightness of pixel changes with the change of electric field intensity, thereby causes showing flicker.
In order to prevent flicker, electric field intensity (voltage that applies) is equated.But, for industrial liquid crystal display, be difficult to make electric field intensity to equate on alternating direction.Therefore, reduce flicker, the opposite pixel of direction of an electric field is close to place, the spatially brightness of average pixel thus.Usually, the method is known as " some counter-rotating " or " row counter-rotating ".The capable counter-rotating of 1-) and the reversal of poles of every two row and every row various " counter-rotating drive " method can be arranged, comprise that one by one (reversal of poles by column line by line: the counter-rotating of the 1-point) counter-rotating of lineament pattern on pixel, counter-rotating line by line (are reversed: line by line.Select as required wherein a kind of.
as mentioned above, realize high-quality demonstration, preferably satisfy following three conditions: (1) adopts ac to drive, make the direction of an electric field that imposes on each liquid crystal layer with the specific time interval such as each Frame periodic reversal, (2) voltage that imposes on each liquid crystal layer on the alternating electric field direction (or be stored in liquid crystal capacitance the quantity of electric charge) is equated with the quantity of electric charge in being stored in memory capacitance, (3) in each vertical-scan period (as the Frame cycle), that pixel is opposite each other by being arranged to the direction of an electric field that is applied to liquid crystal layer (sometimes being called " polarity of voltage ").By the way, " vertical-scan period " can be defined as and choose scan line after until choose again the cycle of this scan line.Scan period equal in noninterlace driving situation a Frame cycle and corresponding to a field duration in staggered driving situation.In addition, in each vertical-scan period, choose the moment of a scan line and choose again poor (cycle) in the moment of this scan line and be known as horizontal scanning period (1H).
The above embodiment of the present invention is by being divided into each pixel at least two subpixel and making each other different demonstrations that realize good viewing angle characteristic of brightness (transmissivity).The inventor finds, when each pixel is divided into the different subpixel of a large amount of brightness, preferably also satisfies the 4th condition about the subpixel distribution except above-mentioned three conditions.Specifically, the preferred different subpixel of brightness is placed randomly with the order of any brightness.With regard to display quality, most preferably not the identical subpixel of brightness be placed to be expert at or column direction on adjacent.In other words, most preferably the identical subpixel of brightness distributes with tessellated pattern.
The below distributes driving method, the pixel that description is suitable for the above embodiment of the present invention and the subpixel distribution.Below with reference to Figure 17 and 18, the driving method example that is used for according to the liquid crystal display of the embodiment of the present invention is described.
Quote such example as proof in following description, pixel is with multirow (1～rp) and multiple row (1～cq) matrix form (rp, cq) distribute, each pixel is expressed as P (p, q) (1≤p≤rp and 1≤q≤cq) herein, and have two subpixel SPa (p, q) and SPb (p at least, q), as shown in figure 17.Figure 17 mean the schematic diagram of a kind of relative distribution (8 row * 6 row): signal wire S-C1, the S-C2 in the liquid crystal display of the present embodiment,, S-C3,, S-C4, ... S-Ccq; Sweep trace G-L1, G-L2, G-L3 ..., G-Lrp; Storage capacitance line CS-A and CS-B; Pixel P (p, q); With the subpixel SPa (p, q) and the SPb (p, q) that form pixel.
As shown in figure 17, a pixel P (p, q) has the subpixel SPa (p, q) and the SPb (p, q) that are similar to horizontal spread centered by pixel on sweep trace G-Lp either side.Subpixel SPa (p, q) and SPb (p, q) are distributed on the column direction of each pixel.The storage capacitor electrode (not shown) of subpixel SPa (p, q) and SPb (p, q) is connected respectively on adjacent storage capacitance line CS-A and CS-B.Supply with signal wire S-Ccq vertical distribution between pixel of signal voltage according to the image that shows to pixel P (p, q), supply with signal voltage with the TFT element (not shown) of the subpixel on the signal wire right side.According to structure shown in Figure 17, a storage capacitance line or a sweep trace are shared by two subpixel.This is the benefit that increases the pixel aperture opening ratio.
Figure 18 represents to have for driving the oscillogram of various voltages (signal) of the liquid crystal display of structure shown in Figure 17.The voltage that has voltage waveform shown in Figure 180 (a)-(j) by use drives the liquid crystal display with structure shown in Figure 17, can satisfy above-mentioned four conditions.
Next, how the liquid crystal display of describing according to the present embodiment is satisfied above-mentioned four conditions.Simple in order to explain, suppose that all pixels all show with intermediate gray-scale.
In Figure 18, waveform (a) be supply with signal wire S-C1, S-C3,, S-C5 ... the display voltage waveform (source signal voltage waveform) of (the odd number signal line group also is known as S-O sometimes); Waveform (b) be supply with signal wire S-C2,, S-C4,, S-C6 ... the display voltage waveform of (the odd number signal line group also is known as S-E sometimes); Waveform (c) is the memory capacitance inverse voltage waveform of supplying with storage capacitance line CS-A; Waveform (d) is the memory capacitance inverse voltage waveform of supplying with CS-B; Waveform (e) is the scanning voltage waveform of supplying with sweep trace G-L1; Waveform (f) is the scanning voltage waveform of supplying with sweep trace G-L2; Waveform (g) is the scanning voltage waveform of supplying with sweep trace G-L3; Waveform (h) is the scanning voltage waveform of supplying with sweep trace G-L4; Waveform (i) is the scanning voltage waveform of supplying with sweep trace G-L5; Waveform (j) is the scanning voltage waveform of supplying with sweep trace G-L6.Sweep trace voltage consists of a horizontal scanning period (1H) from the cycle that low-level (VgL) became between the time of high level (VgH) and next sweep trace voltage becomes VgH from VgL time.The cycle that the voltage of sweep trace remains on high level (VgH) is called sometimes chooses cycle PS.
Because all pixels show with intermediate gray-scale, so all display voltage (waveform in Figure 18 (a) and (b)) has the waveform of fixed amplitude.In addition, be two horizontal scanning periods (2H) oscillation period of display voltage.Display voltage be waveform and signal wire S-O (S-C1, S-C3 ...) and signal wire S-E (S-C2, S-C4 ...) voltage waveform the reason of 180 ° of aberrations is arranged is to satisfy above-mentioned the 3rd condition.Usually in TFT drives, be subjected to the variable effect (sometimes being called pull-in phenomena) of scanning voltage waveform to the line voltage signal of pixel capacitors through the TFT element transmission.Consider pull-in phenomena, after the line voltage signal waveform was delivered to pixel capacitors, inverse voltage was close to the center that is positioned at the line voltage signal waveform.In Figure 18, the pixel capacitors voltage waveform is higher than the inverse voltage part, and signal voltage is with "+" number expression, and the pixel capacitors voltage waveform is lower than the inverse voltage part, and signal voltage is with "-" number expression."+" and "-" is number corresponding to the direction of an electric field that is applied to liquid crystal layer.Direction of an electric field is opposite when "+" number and "-" number.
As described in referring to Figure 12～15, when the scanning voltage of sweep trace is VgH, be connected to the TFT conducting on sweep trace, cause display voltage supply company to be connected to the subpixel of TFT.Then, when the scanning voltage of sweep trace became VgL, the memory capacitance inverse voltage changed.Because the variation of memory capacitance inverse voltage (comprising the change of direction and symbol) is different between two subpixel, so r.m.s. voltage is applied to subpixel.
In example shown in Figure 180, the amplitude of oscillation of memory capacitance inverse voltage and cycle (waveform (c) and (d)) are got identical value between storage capacitance line CS-A and CS-B; For example, be respectively Vad (seeing Figure 14) and the 1H of two times.In addition, if one of them phase shift is 180 °, the waveform of CS-A and CS-B is with overlapping.That is, their phase differential is 0.5H.If the voltage of corresponding sweep trace becomes VgL the first change in voltage increase of corresponding stored electric capacity line afterwards from VgH, the average voltage of each subpixel is the display voltage of the respective signal line in the cycle when being present in corresponding sweep trace and being in the VgH attitude, if but the first change in voltage of corresponding stored electric capacity line reduces, lower than the display voltage of the respective signal line in the cycle that is present in corresponding sweep trace and is in the VgH attitude.
Therefore, if the display voltage shown in Figure 18 (waveform (a) or (b)) with "+" number mark, to be in the r.m.s. voltage that is applied to liquid crystal layer when higher than decline state just higher when the change in voltage of storage capacitance line.On the other hand, if the display voltage shown in Figure 18 (waveform (a) or (b)) with "-" number mark, to be in the r.m.s. voltage that is applied to liquid crystal layer when higher than decline state just lower when the change in voltage of storage capacitance line.
Figure 17 represents the state of vertical-scan period (being in this example the Frame cycle) middle pixel P (p, q) and subpixel SPa (p, q) and SPb (p, q).The below is with respect to the state of three symbolic representation subpixel of the sweep trace symmetry of each subpixel.
The first symbol H or L represent to be applied to the magnitude relationship of the r.m.s. voltage of subpixel, and symbol H represents that the r.m.s. voltage that applies is very high, and symbol L represents that the r.m.s. voltage that applies is very low.Voltage swing relation between second symbol "+" and "-" expression counter electrode and subpixel electrode, in other words, its expression is applied to the direction of an electric field of liquid crystal layer.The voltage of symbol "+" expression subpixel electrode is higher than the voltage of counter electrode, and the voltage of symbol "-" expression subpixel electrode is lower than the voltage of counter electrode.The 3rd symbol A or B represent that suitable storage capacitance line is CS-A or CS-B.
For example, the state of the subpixel SPa (1,1) of pixel P (1,1) and SPb (1,1).From waveform shown in Figure 180 (a)～(e) see, in the cycle (scanning voltage is the cycle PS of VgH) of selecting GL-1, display voltage is "+".When the scanning voltage of GL-1 became VgL from VgH, the voltage of the storage capacitance line of each subpixel (waveform (c) and (d)) was in the state of arrow shown in Figure 180 (from first arrow on a left side) expression.Thereby after VgH became VgL, the first change in voltage of the memory capacitance inverse voltage of SPa (1,1) was increase (with " U " in waveform (c) expression) shown in Figure 180 at the scanning voltage of GL-1.On the other hand, the scanning voltage of GL-1 is after VgH becomes VgL, and the first change in voltage of the memory capacitance inverse voltage of SPa (1,1) is shown in Figure 180 reducing (with " D " in waveform (d) expression).Therefore, the r.m.s. voltage of SPa (1,1) increases, and the r.m.s. voltage of SPb (1,1) reduces.So the r.m.s. voltage of the SPa that applies (1,1) is higher than the r.m.s. voltage of SPb (1,1), and symbol H is attached to SPa (1,1), and symbol L is attached to SPb (1,1).
According to waveform shown in Figure 180 (b), in the cycle of selecting GL-1, being used for the SPa (1,1) of P (1,1) and the display voltage of SPb (1,1) is "-".When the scanning voltage of GL-1 became VgL from VgH, the voltage of the storage capacitance line of each subpixel (waveform (c) and (d)) was in the state shown in arrow in Figure 18 (first arrow on the left side).Thereby after VgH became VgL, the first change in voltage of the memory capacitance inverse voltage of SPa (1,2) increased (" U "), as shown in figure 18 at the scanning voltage of GL-1.On the other hand, the scanning voltage of GL-1 is after VgH becomes VgL, and the first change in voltage of the memory capacitance inverse voltage of SPb (1,2) reduces (" D "), as shown in figure 18.Therefore, the r.m.s. voltage of SPa (1,2) reduces and the r.m.s. voltage increase of SPb (1,2).So the r.m.s. voltage of the SPa that applies (1,2) is higher than the r.m.s. voltage of SPb (1,2), and symbol L is attached to SPa (1,2), and symbol H is attached to SPb (1,2).
According to waveform shown in Figure 180 (a), in selecting the cycle of GL-2, it is "-" that the S that is used for P (2,1) criticizes the display voltage that a (2,1) and S criticize b (2,1).When the scanning voltage of GL-2 became VgL from VgH, the voltage of the storage capacitance line of each subpixel (waveform (c) and (d)) was in the state shown in arrow in Figure 18 (second arrow on the left side).Thereby after VgH became VgL, the first change in voltage of the memory capacitance inverse voltage of SPa (2,1) reduced (" D "), as shown in Figure 18 D at the scanning voltage of GL-2.On the other hand, the scanning voltage of GL-2 is after VgH becomes VgL, and the first change in voltage of the memory capacitance inverse voltage of SPb (2,1) increases (" D "), as shown in Figure 18 C.Therefore, the r.m.s. voltage of SPa (2,1) increases and the r.m.s. voltage of SPb (2,1) reduces.So the r.m.s. voltage of the SPa that applies (2,1) is higher than the r.m.s. voltage of SPb (2,1), and symbol H is attached to SPa (2,1), and symbol L is attached to SPb (2,1).State shown in Figure 17 occurs by this way.
Can drive in this mode that satisfies first condition according to the liquid crystal display of the present embodiment.
Because whether Figure 17 and the state of 18 expression Frame in the cycle satisfy so can not assess first condition from figure.But 180 °, the phase place by moving the upper voltage waveform of every signal line (S-O (Figure 18 A) or S-E (Figure 18 B)) by Frame can be carried out ac and drive, and wherein is applied to each Frame periodic reversal of direction of an electric field of each liquid crystal layer.
In addition, in the liquid crystal display according to the present embodiment, the brightness order (relative position in Figure 17 " H " and " L ") that is subpixel in display screen for the magnitude relation of the subpixel that prevents pixel changes by Frame, and the voltage waveform of phase place on signal wire of the upper voltage waveform of storage capacitance line CS-A and CS-B changes 180 ° when changing.Therefore, be suitable for symbol "+" and "-" in Figure 17 reverse in next Frame (for example (+, H) (, H), and (+, L) (, L)).Above-mentioned first condition can satisfy in this way.
Below we will check whether satisfy second condition, namely the liquid crystal layer of each subpixel (memory capacitance of subpixel) is charged to par at different field directions.In the liquid crystal display according to the present embodiment, different r.m.s. voltage is applied to the liquid crystal layer of the subpixel in each pixel, display quality for example glimmer be subjected to the very high subpixel of brightness, be the decisive influence of the subpixel of symbol in Figure 17 " H " expression.Thereby second condition especially affects the subpixel of symbol " H " expression.
Below with reference to voltage waveform shown in Figure 180, second condition is described.
Be to liquid crystal capacitance and the memory capacitance charging of subpixel in cycle (selection cycle PS) of VgH at the voltage of corresponding sweep trace.The quantity of electric charge that is stored in liquid crystal capacitance depends on the display voltage of signal wire in selection cycle and the voltage difference between inverse voltage (not shown in Figure 18), depends on voltage difference between the display voltage of signal wire in selection cycle and the voltage of storage capacitance line (memory capacitance inverse voltage) and be stored in the quantity of electric charge on memory capacitance.
As shown in figure 18, the display voltage in each selection cycle can be a kind of in two classes of "+" or "-" number expression in figure.In any situation, in each selection cycle, voltage does not change.No matter the inverse voltage (not shown) how, all subpixel all applied the identical dc voltage that does not change in time.
Two class storage capacitance line CS-A and CS-B are arranged.The voltage waveform of CS-A is all identical in the selection cycle of any sweep trace.Similarly, the voltage waveform of CS-B is all identical in the selection cycle of any sweep trace.In other words, the DC composition of the voltage of storage capacitance line (DC level) is got identical value in the selection cycle of any sweep trace.
Thereby, can satisfy second condition by the DC composition (DC level) of regulating following voltage: the display voltage of each sweep trace, the voltage of counter electrode and the voltage of each storage capacitance line.
Next, we will confirm whether the 3rd condition is satisfied, and whether the pixel of opposite direction is placed with in per frame period and gets together on the spot.In the liquid crystal display according to the present embodiment, different r.m.s. voltage is applied to the liquid crystal layer of subpixel in each pixel, and the 3rd condition is applied to the subpixel that is provided identical r.m.s. voltage and the relation between pixel.The particularly important is, the subpixel of the 3rd condition by high brightness, be that the subpixel of symbol in Fig. 17 " H " expression is met, as the situation of second condition.
As shown in figure 17, "+" and "-" that represents each pixel polarity (direction of an electric field) (horizontal direction) every two pixels (two row) in the row direction changes once, as (+,-), (+,-), (+,-), change once at every two pixels of column direction (vertical direction) (two row), as (+,-), (+,-), (+,-), (+,-).See according to pixel one by one, show a counter-rotating, satisfy the 3rd condition.
Next, the subpixel of our high brightness, the i.e. subpixel of symbol " H " expression in Figure 17.
Referring to Figure 17, there is not reversal of poles in line direction shown in the figure, for example on the first row about subpixel SPa+H ,+H ,+H, but polarity transformation once for every two pixels of column direction shown in the figure (two row), as in first row (+H ,-H), (+H ,-H), (+H,-H), (+H ,-H).The state that is known as row counter-rotating can be observed at the level place of the high brightness subpixel that is even more important, and this means that their satisfy the 3rd condition.The subpixel that is represented by symbol L also distributes with the pattern of rule, satisfies the 3rd condition.
Next, we will discuss the 4th condition.The 4th condition needs the identical subpixel of brightness in subpixel should be by placing, and this makes brightness change to some extent.
According to the present embodiment, the subpixel that brightness changes, namely be applied to the different subpixel of the r.m.s. voltage of its liquid crystal layer with the symbol " H " in Figure 17 or " L " expression.
In Figure 17, if subpixel be divided into that two sub-pixels by two subpixel of line direction and column direction form four groups is (as SPa (1,1), SPb (1,1), SPa (1,2) and SPb (1,2)), whole matrix is formed by the subpixel group, wherein H and L from left to right distribute in the row of top, and L and H are distributed in the row of bottom.Thereby in Figure 17, symbol " H " and " L " distribute with the gridiron pattern pattern in the subpixel level, satisfy the 4th condition.
Matrix, in the pixel level, correspondence between the position of the subpixel that distributes on the brightness order of subpixel and column direction in each pixel in the pixel situation of any row goes up in the row direction periodically and changes (each pixel), but in the situation that the pixel of row is constant arbitrarily.Thereby in the pixel P (p, q) that goes arbitrarily, the brightest subpixel (using in this example the subpixel of " H " expression) is SPa (p, q) when q is odd number, is SPb (p, q) when q is even number.Otherwise when q is odd number, the brightest subpixel is SPb (p, q), and q is SPa (p, q) when being even number.On the other hand, in the pixel P (p, q) of any row, the brightest subpixel always SPa (p, q) or SPb (p, q) in same row, no matter p is odd number or even number.Herein SPa (p, q) or SPb (p, q) mean alternately no matter p is odd number or even number, and in odd column, the brightest subpixel is SPa (p, q), and no matter p is odd number or even number, in even number line, the brightest subpixel is SPb (p, q).
, satisfy above-mentioned four conditions according to the liquid crystal display of the present embodiment, and thereby can realize high-quality demonstration with reference to as shown in figure 17 and 18 as above-mentioned.
Next, utilization is described to the liquid crystal display of another embodiment of the different driving method of pixel and subpixel with reference to Figure 19 and 20.Figure 19 and 20 is corresponding to Figure 17 and 18.
As shown in figure 20, in the liquid crystal display according to the present embodiment, the every 2H vibration of display voltage and memory capacitance inverse voltage once.Thereby be 4H (four level write times) oscillation period.The oscillating phase potential difference of the signal voltage of odd number signal wire S-O (S-C1, S-C3, S-C5...) and even signal line S-E (S-C2, S-C4, S-C6...) is 180 degree (being 2H take the time).The voltage oscillation phase differential of storage capacitance line CS-A and CS-B is also 180 degree (being 2H take the time).In addition, the voltage oscillation of signal wire is than voltage oscillation phase place hysteresis 45 degree (1/8 cycle, i.e. H/2) of storage capacitance line CS-A.By the way, the phase differential of 45 degree are used for preventing that the change in voltage of the VgH-VgL change in voltage of sweep trace and storage capacitance line is overlapping, and the value that herein adopts is not to be strict with, and also can adopt as required other value.
For the liquid crystal display according to the present embodiment, each pixel is changed by two brightness and is comprised of the subpixel of " H " or " L " expression.In addition, as shown in figure 19, the subpixel that is represented by symbol " H " or " L " distributes with the gridiron pattern pattern, this means and satisfies the 4th condition, and is the same with top embodiment.About first condition, can utilize the reversal process the same with employing in above-mentioned Figure 17 and 18 illustrated embodiments to satisfy.
But the embodiment shown in Figure 19 and 20 can not satisfy above-mentioned second condition.
Refer now to pixel P (1,1), P (2,1), P (3 shown in first to fourth row of first row in Figure 19,1) and P (4,1) than transom pixel Pa (1,1), Pa (2,1), Pa (3,1) and Pa (4,1).When being recharged, namely when selecting G-L1, the polarity sign of respective signal line is "+" as Pa (1,1).When being recharged, namely when selecting G-L3, the polarity sign of respective signal line is "-" as Pa (3,1).In addition, when being recharged, namely when selecting G-L1, the voltage waveform of corresponding stored electric capacity line CS-A begins staged and descends in the center near selection cycle as Pa (1,1).When being recharged, namely when selecting G-L3, the voltage waveform of corresponding stored electric capacity line CS-A begins staged and rises in the center near selection cycle as Pa (3,1).Thereby the phase place of the voltage waveform signal by accurate control store electric capacity line CS-B and sweep trace can make the memory capacitance counter electrode be recharged and Pa (3,1) has identical DC level when being recharged at Pa (1,1).By DV being horizontally disposed with Pa (1, the voltage of memory capacitance counter electrode when 1) being recharged (equaling the voltage of subpixel electrode) and Pa (3, the mean value of the voltage of memory capacitance counter electrode when 1) being recharged (equaling the voltage of subpixel electrode), can make and be stored in Pa (1,1) equal with the quantity of electric charge in Pa (3,1).Next at Pa (2,1) locate, in the cycle of correspondence, namely when selecting G-L2, the polarity sign of respective signal line is that "-" is (with above-mentioned Pa (3,1) situation is identical), the voltage of corresponding stored electric capacity line is got fixed value (not being the waveform as above-mentioned).Thereby, by making corresponding to the magnitude of voltage of the storage capacitance line of Pa (2,1) and above-mentioned DC level about Pa (1,1) and Pa (3,1) identical, can make to be stored in Pa (1,1), the quantity of electric charge in Pa (2,1) and Pa (3,1) is identical.But, due to underlying cause, can not make the quantity of electric charge that is stored in Pa (4,1) identical with the quantity of electric charge that is stored in Pa (1,1), Pa (2,1) and Pa (3,1).The polarity sign of the signal wire of Pa (4,1) and Pa's (1,1) is identical, and whatsoever constantly, the voltage of corresponding stored electric capacity line is got fixed value (not being waveform as above).Therefore, need to make Pa (4, the magnitude of voltage of storage capacitance line 1) (above-mentioned fixed value) and DC level are about Pa (1,1) and Pa (3,1) identical, with Pa (2,1) situation is identical, namely equal Pa (4,1) and for the magnitude of voltage (above-mentioned fixed value) of the storage capacitance line of Pa (2,1).But, this is impossible, because can find out from Figure 19 and 20, for Pa (2,1) and Pa (4,1) storage capacitance line is CS-B, and their regular waveform is at Pa (2,1) select the maximal value of waveform in selection cycle, and select the minimum value of waveform in the selection cycle of Pa (4,1), make two voltages inevitable different.
In addition, with regard to the subpixel of distribution identical polar so that its as much as possible with regard to the 3rd condition not adjacent one another are, the present embodiment is inferior to the above-described embodiment shown in Figure 17 and 18.
Referring to Figure 19, we by larger voltage be applied to its liquid crystal layer the subpixel that forms pixel, be the reversal of poles of the subpixel that represents of symbol H.In Figure 19, there is not reversal of poles in line direction shown in the figure, as in the first row for subpixel SPa+H ,+H ,+H (as Figure 17), but every four pixel reversal of poles of column direction shown in the figure are as the (+H in first row,-H,-H ,+H), (+H ,-H,-H ,+H).In referring to Figure 17 and 18 described embodiment, a reversal of poles occurs in every two pixels, and the reversal of poles cycle of the present embodiment is 1/2.In other words, in referring to Figure 17 and 18 described embodiment, the reversal of poles frequency is above twice referring to Figure 19 and 20 described embodiment.At this on the one hand, the present embodiment (referring to Figure 19 and 20 described) is inferior to referring to Figure 17 and 18 described embodiment.
In fact display quality compares between the driving method of the driving method of implementing the last embodiment that pixel shown in Figure 17 distributes and the present embodiment, and finds out difference in display quality.Specifically, for example when observing 64/255 gray scale demonstration with fixing sight line, two kinds of driving methods do not see that obvious difference is arranged, and wherein this gray scale is producing larger luminance difference for the subpixel that changes brightness.But, when observing demonstration by mobile sight line, see horizontal clause (Figure 19) in the driving method of the present embodiment, and the driving method of last embodiment (Figure 17) does not have these problems.Can believe, described difference is by due to the difference in above-mentioned reversal of poles cycle.Because the brightness of two subpixel that comprise in each pixel is more remarkable, so preferably make minimum than the reversal of poles cycle of transom pixel.Each pixel is divided into two subpixel in above-mentioned example, but also can be divided into three or more subpixel, and the subpixel that preferably distributes in this manner namely, makes the reversal of poles cycle of transom pixel minimum.Much less, preferably other all subpixel all has the identical reversal of poles cycle with transom pixel.
Next, referring to Figure 21 A and 21B, the following examples are described, in this embodiment, even observe demonstration by mobile sight line, utilize the above-mentioned horizontal clause in shorter reversal of poles cycle also than more not obvious in embodiment shown in Figure 17.
According to embodiment shown in Figure 17, although form pixel than transom pixel (with symbol " H " expression) (+,-), (+,-), reverse on the column direction shown in (+,-) and (+,-), but+,+,+, + ,+,+or-,-,-,-,-,-shown in direction nonreversible.On the contrary, according to embodiment shown in Figure 21, than "+" and "-" of transom pixel not only (+,-), (+,-), reverse on the column direction shown in (+,-), (+,-), and reverse on the line direction shown in (+,-), (+,-).Thereby embodiment shown in Figure 20 adopted than the short reversal of poles cycle embodiment illustrated in fig. 17.In this regard, embodiment shown in Figure 20 more is better than embodiment shown in Figure 17.
Even in the embodiment shown in Figure 21, in the subpixel that forms pixel, the 4th condition is satisfied in distributing with the gridiron pattern pattern than the transom pixel of symbol " H " expression.
Pixel shown in can following enforcement Figure 21 A distributes.
As shown in Figure 21 B, every two row of memory capacitance counter electrode that are used for subpixel in every row alternately are connected to storage capacitance line CS-A or CS-B.This structural change can be clear that by the previous embodiment shown in the present embodiment more shown in Figure 21 and Figure 17 or 18.Specifically, this can find out by checking the storage capacitance line that line direction subpixel place chooses.For example, at subpixel SPa (1,1)～SPa (1,6) in the row, be SPa (1,1) choosing " A " from the memory capacitance counter electrode of symbol " A " or " B " expression, for SPa (1,2) choosing " B ", be SPa (1,4) and SPa (1,5) choosing " A ", be SPa (1,6) choosing " B ", as shown in figure 21, and to all subpixel SPa shown in Figure 17 or 18 (1,1)～SPa (1,6) selects " A ".
According to embodiment shown in Figure 21, the voltage waveform shown in Figure 18 (a)～(j) can be as the voltage waveform of supplying with the wire that comprises storage capacitance line CSA and CS-B.But, because the every two row conversions of display voltage once, therefore the display voltage that has a waveform shown in Figure 180 (a) offer S-C1, S-C2, S-C5, S-C6 ... as shown in Figure 21 A, and the display voltage with waveform shown in Figure 20 (b) offer the S-C3 shown in Figure 21 A, S-C4, S-C7 (not shown), S-C8 (not shown) ...
Although in the above-described embodiments, the memory capacitance inverse voltage of supplying with storage capacitance line is that dutycycle is the square wave oscillation voltage of 1: 1, and the present invention can not be the square wave of 1: 1 with duty-cycle yet.In addition, can also use other waveform, for example sine wave or triangular wave.In this case, when the TFT that is connected to a plurality of sub-pixels closed, the variation that produces in the voltage of supplying with sub-pixel memory capacitance counter electrode can change according to sub-pixel.But the amount of charge that is stored in different subpixel (liquid crystal capacitance and memory capacitance) and the voltage root mean square that is applied on different subpixel easily equate to use square wave to make.
And, although above-mentioned with reference to Figure 17 and 21 described embodiment in, be 1H oscillating voltage oscillation period of supplying with storage capacitance line (waveform (c) and (d)), as shown in figure 18, but can be also 1H by the mark of natural number except resulting 1H, 1/1H for example, 1/2H, 1/3H, 1/4H etc.But, because oscillating voltage shortens oscillation period, therefore be difficult to consist of the power consumption increase of driving circuit or driving circuit.
Next, the embodiment of third aspect present invention is described.
The embodiment of third aspect present invention relates to by the sub-pixel that each pixel is divided into a plurality of different brightness and improves viewing angle characteristic, especially improves large or high-resolution liquid crystal display and its driving method of display comparison degree.
As mentioned above, the embodiment of first aspect present invention improves liquid crystal display or the driving method of viewing angle characteristic, especially display comparison degree by the sub-pixel that each pixel is divided into a plurality of different brightness.Such demonstration and driving refer to that here many pixel demonstrations, many pixel drivers, Area Ratio gray shade scale show or the Area Ratio gray shade scale drives.Also have, the embodiment of second aspect present invention has the liquid crystal display of the array of sub-pixels that can reduce demonstration " flicker " or its driving method, and suitably makes up with first aspect embodiment.
In the liquid crystal display according to second aspect present invention embodiment, the oscillating voltage (memory capacitance inverse voltage) that is applied to CS bus (storage capacitance line) equals or be shorter than a horizontal scanning period oscillation period.If the oscillating voltage with short oscillation period is applied on the CS bus by this way, increase resolution and the size of display board, make the short oscillation period of resulting oscillating voltage clapp oscillator circuit difficult (costliness) to build, increase power consumption, or increase the impact of the waveform passivation that is caused by CS bus electrical load resistance.
Compare with the liquid crystal display according to second aspect embodiment, describe the liquid crystal display according to third aspect present invention embodiment, again describe concrete structure and operation according to the liquid crystal display of second aspect present invention embodiment here.The below is by being set as the example that a horizontal scanning period is realized above-mentioned Area Ratio gray shade scale the oscillation period with CS bus oscillating voltage.With reference to accompanying drawing, concentrate and describe following 3 points.First structure that relates to liquid crystal display centers around the memory capacitance counter electrode of the memory capacitance of connexon pixel and the connection pattern between the CS bus.Second point relates to CS bus oscillation period and the phase place according to the grid bus voltage waveform.The driving and the show state that thirdly relate to sub-pixel.
Figure 22 is the equivalent circuit diagram of certain area with liquid crystal display of pel array shown in Figure 17.Liquid crystal display has the pixel that row and column is arranged in matrix.Each pixel has two sub-pixels (representing with symbol A and B).Each sub-pixel comprises liquid crystal capacitance CLCA_n, m or CLCB_n, m and memory capacitance CCSA_n, m or CCSB_n, m.Each liquid crystal capacitance is comprised of pixel electrode, counter electrode ComLC and the liquid crystal layer that is clipped between them.Each memory capacitance is comprised of storage capacitor electrode, dielectric film and memory capacitance counter electrode (ComCSA_n or ComCSB_n).Two sub-pixels are through each TFTA_n, and m and TFTB_n, m are connected on common signal line (power bus) SBL_m.Come opening and closing TFTA_n, m and TFTB_n, m by the scanning voltage signal that is applied on common scanning line (grid bus) GBL_n.When two TFT opened, monitor signal voltage was supplied with the storage capacitor electrode of each pixel electrode and two sub-pixels through common signal line.Through CS bus (CSBL), the memory capacitance counter electrode of one of two pixel electrodes is connected on memory capacitance main line (CS main line) CSVtypeR1, and the memory capacitance counter electrode of other sub-pixel is connected on memory capacitance main line (CS main line) CSVtypeR2.
Should note sharing electric public CS bus at the sub-pixel of Figure 22 column direction neighbor.Have CLCB_n in capable especially for n, the CS bus CSBL of the sub-pixel of m and be used for the column direction adjacent lines and have CLCA_n+1, the CS bus CSBL electricity of the sub-pixel of m pixel shares.
Figure 23 A and 23B illustrate with regard to the voltage waveform of grid bus and shown in supply with oscillation period and the phase place of the oscillating voltage of CS bus with regard to pixel electrode voltage.Liquid crystal display usually reverse (with specific time interval) be applied to the direction of an electric field of each pixel liquid crystal layer, therefore, need to consider two type driving voltage waveform of corresponding direction of an electric field.In Figure 23 A and Figure 23 B, the driving condition of two types is shown respectively.
In Figure 23 A and 23B, VSBL_m represents to supply with the waveform of the display voltage (power supply signal voltage) of m row power bus SBL_m, and simultaneously VGBL_n represents to supply with the waveform of scanning voltage signal (signal voltage) of the grid bus GBL_n of n row.VCSVtypeR1 and VCSVtypeR2 represent respectively to supply with the waveform of the oscillating voltage of CS main line CSVtypeR1 and CSVtypeR2, as the memory capacitance inverse voltage.VPEA_m, n and VPEB_m, n represent the voltage waveform of each sub-pixel liquid crystal capacitance.
Note in Figure 23 A and 23B first is all to equal oscillation period of the voltage VCSVtypeR1 of CSVtypeR1 and CSVtypeR2 and VCSVtypeR2 a horizontal scanning period (1H).
The second point of noting in Figure 23 A and 23B is that the phase place of VCSVtypeR1 and VCSVtypeR2 is as follows.At first, observe the phase differential between the CS main line, it is 0.5H that VCSVtypeR2 falls behind VCSVtypeR1.Next, observe the voltage of CS main line and grid bus, the voltage-phase of CS main line and grid bus is as follows.Can find out the time consistency at flat arrival their center of the grid bus voltage of corresponding each CS main line becomes VgL from VgH time and CS rail voltage from Figure 23 A and 23B.In other words, the Td value in Figure 23 A and 23B is 0.25H.But Td can be greater than 0H but less than any value of 0.5H.
Although with reference to voltage-phase and cycle that Figure 23 A and 23B have described the CS main line, the voltage waveform of CS main line is not limited to this, the CS main line can be any waveform, as long as satisfy one of following two conditions.First condition is after the voltage of corresponding grid bus becomes HgL from VgH, and it is that voltage increases that first of voltage VCSVtypeR1 changes, and after the voltage of corresponding grid bus became HgL from VgH, it was that voltage reduces that first of voltage VCSVtypeR2 changes.Second condition is after the voltage of corresponding grid bus becomes HgL from VgH, and it is that voltage reduces that first of voltage VCSVtypeR1 changes, and after the voltage of corresponding grid bus became HgL from VgH, it was that voltage increases that first of voltage VCSVtypeR2 changes.
The driving condition of Figure 24 A and 24B general introduction liquid crystal display.According to a plurality of driving voltages of the sub-pixel of Figure 23 A and 23B example shown, the driving condition of liquid crystal display also is divided into two types.The driving voltage waveform of the driving condition corresponding diagram 23A of Figure 24 A, and the driving voltage waveform of the driving condition corresponding diagram 23B of Figure 24 B.
Figure 24 A and 24B are shown schematically in the pixel driver state of " capable of 8 capable row of n+7 from n " in a plurality of pixels of arranging by matrix * " being listed as 6 row of m+5 row from m ".Each pixel has the sub-pixel of different brightness.Namely be expressed as the sub-pixel and the sub-pixel that is expressed as " d (secretly) " of " b (bright) ".Figure 24 A is basically identical with Figure 17 with 24B.
The lime light of Figure 24 A and Figure 24 B is whether to satisfy the requirement of Area Ratio gray shade scale plate.Area Ratio gray shade scale plate has five requirements.
First requirement is that each pixel is comprised of a plurality of pixels of different brightness when showing the middle gray grade.
The second requirement is not consider the time, and the sub-pixel intensity level of different brightness is constant.
The 3rd requirement is that the sub-pixel of different brightness is arranged fine.
The 4th requirement is that the pixel of opposite polarity in all frames is arranged fine.
The 5th requirement is that the sub-pixel of identical polar, same luminance level (particularly the brightest sub-pixel) in all frames is arranged fine.
Verify according to first requirement.Here, each pixel is comprised of the sub-pixel of two different brightness.Particularly, for example in Figure 24 A, the pixel of the capable and m row of n is by the high brightness subpixel that is expressed as " b (bright) " and be expressed as the low-light level sub-pixel of " d (secretly) " and form.Therefore, satisfy first requirement.
Require to verify according to second.Liquid crystal display replaces two kinds of show states of different driving state with time interval of rule.Figure 24 A and 24B represent to meet corresponding to the driving condition of two kinds of show states the position of high brightness subpixel and low-light level sub-pixel.Therefore, satisfy the second requirement.
Require to verify according to the 3rd.In Figure 24 A and 24B, the sub-pixel of different intensity levels (that is, being expressed as the sub-pixel and the sub-pixel that is expressed as " d (secretly) " of " b (bright) ") is arranged by lineament.The visible observation of liquid crystal display does not have to occur such as using different brightness sub-pixels to reduce the demonstration problem of resolution.Therefore, satisfy the 3rd requirement.
Require to check according to the 4th.The Pixel arrangement of opposite polarity becomes lineament in Figure 24 A and 24B.Particularly, for example in Figure 24 A, the pixel at n+2 in capable and m+2 row has "+" polarity.From this pixel, follow direction and column direction and change polarity every a pixel between "-" and "+".For not satisfying the 4th liquid crystal display that requires, think to change to synchronize between "+" and "-" with the driving polarity of pixel to see flashing of display.But, just can't see when the liquid crystal display of sight check embodiment and flash.Therefore, satisfy the 4th requirement.
Require to check according to the 5th.In Figure 24 A and 24B, the sub-pixel of observing same luminance level drives polarity, and every two row sub-pixels (that is, every a pixel wide) counter-rotating drives polarity.Particularly, for example in the n_B of Figure 24 A was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "-".In n+1_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "-".In n+1_B was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "+".In n+2_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "+".For not satisfying the 5th liquid crystal display that requires, think to change to synchronize between "+" and "-" with the driving polarity of pixel to see flashing of display.But, just can't see during according to liquid crystal display of the present invention when sight check and flash.Therefore, satisfy the 5th requirement.
When observing liquid crystal display by the amplitude VCSpp that changes CS voltage, during oblique view, raising along with the display comparison degree, viewing angle characteristic just improves, because the amplitude VCSpp of CS voltage begins to increase (0V is used for the general liquid crystal display of support except the liquid crystal display according to the present invention) from 0V.Although as if slightly different according to the raising of the image aspects characteristic that shows, when VCSpp be set as make VLCaddpp value the 0.5-2 of the liquid crystal display threshold voltage of common drive pattern (VCSpp is 0V) doubly within the time, the raising of realization the best.
Therefore, improve viewing angle characteristic by applying oscillating voltage according to the liquid crystal display of second aspect present invention embodiment on the memory capacitance counter electrode, realize that thus many pixels show, wherein be applied to oscillating voltage on the memory capacitance counter electrode and equal oscillation period or be shorter than a horizontal scanning period.But, when the oscillation period that is applied to the oscillating voltage on the CS bus in short-term, with regard to difficult to realize that many pixels show on the display of the high-resolution liquid crystal display of the high capacity electric capacity of CS bus and the large liquid crystal display of resistance, short horizontal scanning period or high-speed driving and short vertical, horizontal scanning period.
This problem is described with reference to Figure 25-28.
Figure 25 A means in the liquid crystal display according to second aspect present invention embodiment, be used for oscillating voltage supply with the CS bus structural representation.A plurality of CS buses that oscillating voltage arranges LCD panel from the CS mains supply.Oscillating voltage is supplied with the CS main line through tie point ContP1 and ContP2 and process ContP3 and ContP4 from CS bus voltage generator circuit.Due to the size that increases LCD panel, therefore the distance from the pixel at display board center to tie point ContP1 and ContP2 increases, and makes it can not ignore loaded impedance between center pixel and tie point.The main element of loaded impedance comprises liquid crystal capacitance (CLC) and memory capacitance (CCS), the resistance R CS of CS bus and the resistance R trunk of CS main line of pixel.The low-pass filter that the first approximation of loaded impedance can be comprised of the above-mentioned electric capacity shown in Figure 25 B and resistance.The value of loaded impedance is the function of liquid crystal display Board position.For example, it is the function apart from tie point ContP1, ContP2, ContP3 and ContP4 distance.Particularly, loaded impedance increases with the increase of distance join point distance, reducing and reduce with distance join point distance.
That is to say, be subjected to the impact of the approximate CS bus load of CR low-pass filter by the CS bus voltage of oscillating voltage generator circuit generation, the CS bus is through the position of waveform passivation change on flat board.
As described in the embodiment of first aspect present invention, oscillating voltage imposes on the CS bus, in order to consist of each pixel of two or more sub-pixels and change the brightness of sub-pixel.That is, use such structure and driving method according to the liquid crystal display of the embodiment of the present invention: form the voltage waveform of pixel electrode according to the oscillating voltage of CS bus, and change effective voltage according to the waveform of CS bus.Therefore, if CS bus voltage waveform changes to another position from a position, the effective voltage of pixel electrode is also like this.In other words, if the waveform passivation of CS bus voltage changes the position, display brightness is also with change in location, thereby obtains irregular display brightness.
Advantage according to the third aspect present invention liquid crystal display by proofreading and correct the irregular ability of display brightness the oscillation period that increases the CS bus.The below will lay down a definition.
Figure 26 and 27 is shown schematically in the oscillating voltage waveform of the situation pixel electrode that the CS load remains unchanged.Figure 26 and 27 be the voltage of supposition pixel electrode when the CS bus voltage is not oscillating voltage for " 0V ", and be the schematic diagram of " 1V " by the amplitude of the pixel electrode voltage of the generation of vibration of CS bus.Waveform in Figure 26 (a)-(e) expression CS voltage does not have the waveform of waveform passivation, namely, the CR time constant of CR low-pass filter is " 0H ", and the waveform passivation of waveform (a)-(e) expression when the CR of CR low-pass filter time constant is " 0.2H " in Figure 27.Figure 26 and 27 schematically shows the voltage waveform of pixel electrode voltage when the CR of CR low-pass filter time constant is respectively " 0H " and " 0.2H ", and be changed the oscillation period of CS bus oscillating voltage.Ripple in Figure 26 and 27 (a)-(e) the expression oscillating waveform cycle is respectively the situation of 1H, 2H, 4H, 8H.
When Figure 26 and 27 compares, can find out that waveform difference in Figure 26 and 27 reduces with the increase of oscillation period.This trend quantificational expression in Figure 28.
Figure 28 represents based on the waveform of Figure 27 (corresponding horizontal scanning period of one-period: the mean value of the oscillating voltage that 1H) calculates and the relation of effective value oscillation period than CS bus voltage.As can be seen from Figure 28, when the CR time constant is 0H and the CR time constant when being 0.2H between the deviation of average voltage and effective voltage reduce with the increase of CS bus oscillation period.Can find out, can reduce largely the impact of waveform passivation, particularly when oscillation period of CS bus oscillating voltage during greater than 8 times of the CR time constant (approximate value of loaded impedance) of CS bus.
Like this, by increasing the oscillation period of CS bus oscillating voltage, may reduce the display brightness that the passivation of CS bus waveform causes irregular.Can reduce largely the impact of waveform passivation, particularly when oscillation period of CS bus oscillating voltage during greater than 8 times of the CR time constant (approximate value of loaded impedance) of CS bus.
Because the liquid crystal display according to second aspect present invention has the problems referred to above, therefore a third aspect of the present invention is proposed.This aspect provides preferred structure and the method for liquid crystal display, and it can increase the oscillation period that is applied to the oscillating voltage on the CS bus.
In the liquid crystal display according to third aspect present invention embodiment, the CS bus of electrical isolation is used at the same column of matrix driving liquid crystal display and sub-pixel (for example, the first sub-pixel and the second sub-pixel) along the column direction different intensity levels of sub-pixel adjacent one another are.Be electrically insulated from each other especially for the CS bus of capable the first sub-pixel of n and the CS bus of capable the second sub-pixel of n+1.Here, the pixel in matrix driving liquid crystal display same column is by the pixel of same signal line (being generally power bus) driving.And, the pixel of the scanning line driving of being selected by adjacent time point in the sweep trace (being generally grid bus) by the time shaft select progressively in the column direction of matrix driving liquid crystal display pixel adjacent one another are.In addition, supposing has L group CS main line electrical isolation, and the vibration period of CS bus can be L times of horizontal scanning period.As mentioned above, 8 times of the business that obtains divided by the CR time constant that is approximately equal to the impedance of CS bus maximum load greater than a horizontal scanning period of the quantity of preferred CS main line.And as hereinafter described, preferably this numerical value is except greater than 8 multiples or even number.At this, the quantity of CS main line electrical isolation group (L group) can represent with the quantity of the CS main line (L main line) of electrical isolation.If the CS main line of electrical equivalent is arranged on plate both sides, the quantity of the CS main line of electrical equivalent is constant.
With reference to the accompanying drawings, describe according to the liquid crystal display of third aspect present invention embodiment and its driving method.
At first, with reference to Figure 29-31B, describe liquid crystal display and realize that by being set as 4 times of horizontal scanning period the oscillation period with the oscillating voltage of CS bus the Area Ratio gray shade scale shows.Description concentrates on following points, and provides with reference to accompanying drawing.First relates to liquid crystal display device structure, centers around the connection pattern between the memory capacitance counter electrode that is connected to the memory capacitance on sub-pixel and CS bus.Second point relates to oscillation period and the oscillation phase according to the CS bus of grid bus voltage waveform.Thirdly relate to driving and show state according to the sub-pixel of the present embodiment.
Figure 29 is the schematic equivalent circuit according to the liquid crystal display of third aspect present invention embodiment, corresponding Figure 22.The element identical with Figure 22 Reference numeral/symbolic representation identical with Figure 22, it describes omission.Liquid crystal display in Figure 29 is different from the liquid crystal display in Figure 22, and wherein it has CS main line CSVtypeA1-CSVtypeA4 and the connection status between CS main line and CS bus of four electrical isolations.
First that will note in Figure 29 is: the CS bus of the adjacent subpixels of pixel in the column direction adjacent lines (for example, corresponding CLCB_n, m and CLCA_n+1, the sub-pixel of m) is electrically insulated from each other.Particularly, for example be used for the capable sub-pixel CLCB_n of n, the CS bus CSBL_B_n of m and be used for the sub-pixel CLCA_n+1 of column direction adjacent lines pixel, the bus CSBL_A_n+1 of m is electrically insulated from each other.
The second point that will note in Figure 29 is: each CS bus (CSBL) is connected on one of four CS main lines (CSVtypeA1, CSVtypeA2, CSVtypeA3 and CSVtypeA4) of dull and stereotyped end.That is, in the liquid crystal display according to the present embodiment, the CS main line of four groups of electrical isolations is arranged.
What will note in Figure 29 is thirdly: the connection status between CS bus and four CS main lines, that is, and along the distribution of the CS bus of column direction electrical isolation.According to the concatenate rule of CS bus in Figure 29 and CS main line, be connected to bus on CS main line CSVtypeA1, CSVtypeA2, CSVtypeA3 and CSVtypeA4 shown in table 1.
[table 1]
The CS main line Be connected to the CS bus on the CS main line The general symbol(s) of the CS bus that draw on the left side
CSVtypeA1 CSBL_A_n， CSBL_B_n+2， CSBL_A_n+4， CSBL_B_n+6， CSBL_A_n+8， CSBL_B_n+10， CSBL_A_n+12， CSBL_B_n+14， … CSBL_A_n+4·k， CSBL_B_n+2+4·k (k＝0，1，2，3，…)
CSVtypeA2 CSBL_B_n， CSBL_A_n+2， CSBL_B_n+4， CSBL_A_n+6， CSBL_B_n+8， CSBL_A_n+10， CSBL_B_n+12， CSBL_A_n+14， … CSBL_B_n+4·k， CSBL_A_n+2+4·k (k＝0，1，2，3，…)
CSVtypeA3 CSBL_A_n+ 1， CSBL_B_n+3， CSBL_A_n+5， CSBL_B_n+7， CSBL_A_n+9， CSBL_B_n+11， CSBL_A_n+13， CSBL_B_n+15， … CSBL_A_n+1+4·k， CSBL_B_n+3+4·k (k＝0，1，2，3，…)
CSVtypeA4 CSBL_B_n+ 1， CSBL_A_n+3， CSBL_B_n+5， CSBL_A_n+7， CSBL_B_n+9， CSBL_A_n+11， CSBL_B_n+13， CSBL_A_n+15， … CSBL_B_n+1+4·k， CSBL_A_n+3+4·k (k＝0，1，2，3，…)
The CS bus of four groups of electrical isolations is connected respectively on four CS main lines shown in above-mentioned table 1.
Figure 30 A and 30B represent CS bus oscillation period and the phase place according to the voltage waveform of grid bus, and the voltage of expression pixel electrode.The corresponding above-mentioned Figure 23 A of Figure 30 A and 30B and 23B.Element with Figure 23 A with the 23B identical Reference numeral/symbolic representation identical with 23B with Figure 23 A omitted at this and described.Liquid crystal display generally is applied to direction of an electric field on the liquid crystal layer of each pixel with the counter-rotating of time interval of rule, therefore, needs to consider the driving voltage waveform of two types corresponding to direction of an electric field.Represent respectively this driving condition of two types in Figure 30 A and 30B.
First that will note in Figure 30 A and 30B is: be all 4 times (4H) of horizontal scanning period the oscillation period of voltage VCSVtypeA1, VCSVtypeA2, VCSVtypeA3 and the VCSVtypeA4 of CSVtypeA1, CSVtypeA2, CSVtypeA3 and CSVtypeA4.
The second point that will note in Figure 30 A and 30B is: the phase place of VCSVtypeA1, VCSVtypeA2, VCSVtypeA3 and VCSVtypeA4 is as follows.At first, compare the phase place in the CS main line, VCSVtypeA2 is than the backward 2H of VCSVtypeA1, and VCSVtypeA3 is than the backward 3H of VCSVtypeA1, and VCSVtypeA4 is than the backward 1H of VCSVtypeA1.Next, observe the voltage of CS main line and the voltage of grid bus, the phase place of CS bus voltage and grid bus voltage is as follows.As shown in Figure 30 A and 30B, the flat that becomes time of VgL and CS main line from VgH corresponding to the voltage of the grid bus of each CS main line arrives the time consistency at their centers.In other words, the Td value in Figure 30 A and 30B is 1H.But the Td value is any greater than the value of 0H less than 2H.
Here, the grid bus corresponding to each Cs main line is that the CS bus is connected CS main line and the grid bus of identical pixel electrode through auxiliary capacitor CS with the TFT element.According to Figure 29, corresponding to expression in the grid bus of each the CS main line in this liquid crystal display and CS bus table 2 below.
[table 2]
The CS main line Corresponding grid bus Corresponding CS bus
CSVtypeA1 GBL_n，GBL_n+2，GBL_n+4， GBL_n+6，GBL_n+8，… ........................ [GBL_n+2·k (k＝0，1，2，3，…)] CSBL_A_n，CSBL_B_n+2，CSBL_A_n+4， CSBL_B_n+6，CSBL_A_n+8，… ........................ [CSBL_A_n+4·k，CSBL_B_n+2+4·k (k＝0，1，2，3，…)]
CSVtypeA2 GBL_n，GBL_n+2，GBL_n+4， GBL_n+6，GBL_n+8，… ....................... [GBL_n+2·k (k＝0，1，2，3，…)] CSBL_B_n，CSBL_A_n+2，CSBL_B_n+4， CSBL_A_n+6，CSBL_B_n+8，… ....................... [CSBL_B_n+4·k，CSBL_A_n+2+4·k (k＝0，1，2，3，…)]
CSVtypeA3 GBL_n+ 1，GBL_n+3，GBL_n+5， GBL_n+7，GBL_n+9，… ........................ [GBL_n+1+2·k (k＝0，1，2，3，…)] CSBL_A_n+1，CSBL_B_n+3， CSBL_A_n+5， CSBL_B_n+7，CSBL_A_n+9，… ............................. [CSBL_A_n+1+4·k，CSBL_B_n+3+4·k (k＝0，1，2，3，…)]
CSVtypeA4 GBL_n+ 1，GBL_n+3，GBL_n+5， GBL_n+7，GBL_n+9，… ........................ [GBL_n+1+2·k (k＝0，1，2，3，…)] CSBL_B_n+1，CSBL_A_n+3， CSBL_B_n+5， CSBL_A_n+7，CSBL_B_n+9，… ................... [CSBL_B_n+1+4·k，CSBL_A_n+3+4·k (k＝0，1，2，3，…)]
Although described cycle and the phase place of CS rail voltage with reference to Figure 30 A and 30B, the voltage waveform of CS main line is not limited to this.The CS main line can be other waveform that satisfies following two conditions.
First condition is: it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA1 after VgL changes, it is lower voltage that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA2 after VgL changes, it is lower voltage that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA3 after VgL changes, and it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA4 after VgL changes.Driving voltage waveform shown in Figure 30 A satisfies this condition.
Second condition is: it is lower voltage that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA1 after VgL changes, it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA2 after VgL changes, it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA3 after VgL changes, and it is lower voltage that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA4 after VgL changes.Driving voltage waveform shown in Figure 30 B satisfies this condition.
But, for the reason that the following describes, preferably use the waveform shown in Figure 30 A and 30B.
In Figure 30 A and 30B, be constant oscillation period.This can simplify signal generator circuit.
And in Figure 30 A and 30B, the vibration dutycycle is constant.May keep like this amplitude of oscillation constant, and when oscillating voltage was used as the CS bus voltage, the voltage variety that is applied to liquid crystal display layer depends on amplitude and the dutycycle of vibration, therefore simplify signal generator circuit.Therefore, the vibration dutycycle remains unchanged, and just may make the amplitude of vibration constant.For example, dutycycle is set as 1: 1.
And, in Figure 30 A and 30B, for any CS oscillating voltage, there is the oscillating voltage (oscillating voltage of opposite phase) that exceeds 180 degree phase places.That is, four electrical isolation CS main lines form the CS main line to (two pairs), and it supplies with the oscillating voltage that exceeds 180 degree phase places mutually.This just may make the magnitude of current that flows through the memory capacitance counter electrode minimum, therefore simplifies the driving circuit that connects counter electrode.
The driving condition of Figure 31 A and 31B general introduction the present embodiment liquid crystal display.According to the polarity of sub-pixel driving voltage, the driving condition of liquid crystal display also is divided into two types, the situation as shown in Figure 30 A and 30B.Driving condition in Figure 31 A is corresponding to the driving voltage waveform of Figure 30 A, and simultaneously, the state in Figure 31 B is corresponding to the driving condition of Figure 30 B driving voltage waveform.Figure 31 A and 31B are corresponding to above-mentioned Figure 24 A and 24B.
Lime light in Figure 31 A and 31B is whether to satisfy the requirement of Area Ratio gray shade scale plate.Five requirements according to following Area Ratio gray shade scale plate are verified.
First requirement is that each pixel is comprised of a plurality of different brightness sub-pixels when showing the middle gray grade.
Second no matter to require be the time, and the different sub-pixel intensity level of brightness is constant.
The 3rd requirement is that the sub-pixel of different brightness is arranged fine.
The 4th requirement is that the pixel of opposite polarity in all frames is arranged fine.
The 5th requirement is that the sub-pixel of identical polar, same luminance level (especially the brightest sub-pixel) in all frames is arranged fine.
Verify according to first requirement.In Figure 31 A and 31B, each pixel is comprised of two different sub-pixels of brightness.Particularly, for example in Figure 31 A, the pixel of the capable and m row of n is by the high brightness subpixel that is expressed as " b (bright) " and be expressed as the low-light level sub-pixel of " d (secretly) " and form.Therefore, satisfy first requirement.
Require to verify according to second.Liquid crystal display replaces two kinds of show states of different driving state with the rule time interval.Figure 31 A and 31B represent to meet corresponding to the driving condition of two show states the position of high brightness subpixel and low-light level sub-pixel.Therefore, satisfy the second requirement.
Require to verify according to the 3rd.In Figure 31 A and 31B, the sub-pixel of different intensity levels (that is, being expressed as the sub-pixel and the sub-pixel that is expressed as " d (secretly) " of " b (bright) ") is arranged by lineament.The demonstration problem is not seen in the visualization of liquid crystal display, for example because different brightness sub-pixels reduce resolution.Therefore, satisfy the 3rd requirement.
Require to verify according to the 4th.In Figure 31 A and 31B, the Pixel arrangement of opposite polarity becomes lineament.Particularly, for example in Figure 31 A, the pixel at n+2 in capable and m+2 row has "+" polarity.From this pixel, follow direction and column direction and change polarity every a pixel between "-" and "+".For not satisfying the 4th liquid crystal display that requires, think to change to synchronize between "+" and "-" with the driving polarity of pixel to see flashing of display.But, can't see when the liquid crystal display of sight check embodiment and flash.Therefore, satisfy the 4th requirement.
Require to verify according to the 5th.In Figure 31 A and 31B, the sub-pixel of observing same luminance level drives polarity, and every two row sub-pixels (that is, every a pixel wide) counter-rotating drives polarity.Particularly, for example in n_B was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "-".In n+1_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "-".In n+1_B was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "+".In n+2_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "+".For not satisfying the 5th liquid crystal display that requires, think to change to synchronize between "+" and "-" with the driving polarity of pixel to see flashing of display.But, can't see during according to liquid crystal display of the present invention when sight check and flash.Therefore, satisfy the 5th requirement.
When the liquid crystal display of observing by the amplitude VCSpp that changes CS voltage according to the present embodiment, during oblique view, inhibition (surpressed) along with the display comparison degree, viewing angle characteristic improves, because the amplitude VCSpp of CS voltage increases (0V is used for the common liquid crystals display of support except the liquid crystal display according to the present invention) from 0V.Although as if according to the image that shows, the raising of viewing angle characteristic is slightly different, when setting VCSpp so that VLCaddpp value the 0.5-2 of the liquid crystal display threshold voltage of common drive pattern (VCSpp is 0V) doubly within the time, the raising of realization the best.
Generally, be 4 times of liquid crystal display horizontal scanning period the oscillation period that the present embodiment might be set the oscillating voltage that imposes on the memory capacitance counter electrode, liquid crystal display improves viewing angle characteristic by applying oscillating voltage to the memory capacitance counter electrode, therefore, realizes that many pixels show.Even on the large liquid crystal display of the high capacity electric capacity with CS bus and resistance, have on the high-resolution liquid crystal display of short horizontal scanning period or have high-speed driving and the liquid crystal display of short vertical, horizontal scanning period on, realize easily that also many pixels show.
Next, with reference to Figure 32, structure and operation according to the liquid crystal display of third aspect present invention embodiment are described.
This embodiment realizes that by the twice that is set as horizontal scanning period oscillation period with the oscillating voltage of CS bus the Area Ratio gray shade scale shows.Describe and concentrate on following points with reference to the accompanying drawings.First structure that relates to liquid crystal display centers around the memory capacitance counter electrode of the memory capacitance of connexon pixel and the connection pattern between the CS bus.Second point relates to CS bus oscillation period and the phase place according to the grid bus voltage waveform.Thirdly relate to driving and show state according to the sub-pixel of the present embodiment.
Figure 32 means the schematic diagram according to the equivalent electrical circuit of the liquid crystal display of third aspect present invention embodiment, corresponding Figure 29.The element identical with Figure 29 Reference numeral/symbolic representation identical with Figure 29 wherein described and omitted.Liquid crystal display in Figure 32 is different from the liquid crystal display in Figure 29, and wherein it has CS main line CSVtypeB1 and CSVtypeB2 and the connection status between CS main line and CS bus of two electrical isolations.
First that will note in Figure 32 is: the CS bus of the adjacent subpixels of pixel is electrically insulated from each other in the column direction adjacent lines.Especially for the capable sub-pixel CLCB_n of n, the CS bus CSBL_B_n of m and be used for the sub-pixel CLCA_n+1 of column direction adjacent lines pixel, the bus CSBL_A_n+1 of m is electrically insulated from each other.
The second point that will note in Figure 32 is: each CS bus (CSBL) is connected on two CS main lines (CSVtypeB1 and CSVtypeB2) of dull and stereotyped end.That is, in the liquid crystal display according to the present embodiment, the CS main line of two groups of electrical isolations is arranged.
What will note in Figure 32 is thirdly: the connection status between CS bus and two CS main lines (trunk), that is, and along the distribution of the CS bus of column direction electrical isolation.According to the concatenate rule of CS bus in Figure 32 and CS main line, be connected to CS bus on CS main line CSVtypeB1 and CSVtypeB2 as shown in following table 3.
[table 3]
The CS main line The CS bus that connects the CS main line The general symbol(s) of the CS bus that draw on the left side
CSVtypeB1 CSBL_A_n， CSBL_A_n+1， CSBL_A_n+2， CSBL_A_n+3， … CSBL_A_n+k， (k＝0，1，2，3，…)
CSVtypeB2 CSBL_B_n， CSBL_B_n+1， CSBL_B_n+2， CSBL_B_n+3， … CSBL_B_n+k， (k＝0，1，2，3，…)
The CS bus of two groups of electrical isolations is connected respectively on two CS main lines shown in top table 3.
Figure 33 A and 33B represent CS bus oscillation period and the phase place according to the grid bus voltage waveform, and the voltage of pixel electrode is shown.Figure 33 A and 33B are corresponding to Figure 30 A and the 30B of front embodiment.Element with Figure 30 A with the 30B identical Reference numeral/symbolic representation identical with 30B with Figure 30 A wherein described and omitted.Liquid crystal display generally is applied to direction of an electric field on the liquid crystal layer of each pixel with the counter-rotating of time interval of rule, therefore, needs to consider the driving voltage waveform of two types corresponding to direction of an electric field.Represent respectively this driving condition of two types in Figure 33 A and 33B.
First that will note in Figure 33 A and 33B is: the voltage VCSVtypeB1 of CSVtypeB1 and CSVtypeB2 and the oscillation period of VCSVtypeB2 are all 2 times (2H) of horizontal scanning period.
The second point that will note in Figure 33 A and 33B is: the phase place of VCSVtypeB1 and VCSVtypeB2 is as follows.At first, compare the phase place in the CS main line, VCSVtypeB2 is than the backward 1H of VCSVtypeB1.Next, observe the voltage of CS main line and the voltage of grid bus, the phase place of CS rail voltage and grid bus voltage is as follows.As shown in Figure 33 A and 33B, the flat that becomes time of VgL and CS main line from VgH corresponding to the voltage of the grid bus of each CS main line arrives the time consistency at their centers.In other words, the Td value in Figure 33 A and 33B is 0.5H.But the Td value is greater than any value of 0H less than 1H.
Here, the grid bus corresponding to each CS main line is that the CS bus is connected CS main line and the grid bus of identical pixel electrode through auxiliary capacitor CS with the TFT element.According to Figure 33 A and 33B, corresponding to expression in the grid bus of each the CS main line in this liquid crystal display and CS bus table 2 below.
[table 4]
The CS main line Corresponding grid bus Corresponding CS bus
CSVtypeB1 GBL_n，GBL_n+1，GBL_n+2， GBL_n+3，GBL_n+4，… ..................... [GBL_n+k (k＝0，1，2，3，…)] CSBL_A_n，CSBL_A_n+1，CSBL_A_n+2， CSBL_A_n+3，CSBL_A_n+4，… ..................... [CSBL_A_n+k (k＝0，1，2，3，…)]
CSVtypeB2 GBL_n，GBL_n+1，GBL_n+2， GBL_n+3，GBL_n+4，… .................... [GBL_n+k (k＝0，1，2，3，…)] CSBL_B_n，CSBL_B_n+1，CSBL_B_n+2， CSBL_B_n+3，CSBL_B_n+4，… ................................... [CSBL_B_n+k (k＝0，1，2，3，…)]
Although described voltage cycle and the phase place of CS main line with reference to Figure 33 A and 33B, the voltage waveform of CS main line is not limited to this.The CS main line can be other waveform that satisfies following two conditions.
First condition is: it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeB1 after VgL changes, and it is lower voltage that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeB2 after VgL changes.Figure 33 A satisfies this condition.
Second condition is: it is lower voltage that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeB1 after VgL changes, and it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeB2 after VgL changes.Figure 33 B satisfies this condition.
Figure 34 A and 34B general introduction are according to the driving condition of the liquid crystal display of the present embodiment.According to the polarity of sub-pixel driving voltage, the driving condition of liquid crystal display also is divided into two types, the situation as shown in Figure 34 A and 34B.Driving condition in Figure 34 A is corresponding to the driving voltage waveform of Figure 33 A, and the state in Figure 34 B is corresponding to the driving condition of Figure 33 B driving voltage waveform.Figure 34 A and 34B are corresponding to Figure 31 A and the 31B of previous embodiment.
The lime light of Figure 34 A and 34B is whether to satisfy the requirement of Area Ratio gray shade scale plate.Area Ratio gray shade scale plate has five requirements
First requirement is that each pixel is comprised of a plurality of different brightness sub-pixels when showing the middle gray grade.
Second no matter to require be the time, and the different sub-pixel intensity level of brightness is constant.
The 3rd requirement is that the sub-pixel of different brightness is arranged fine.
The 4th requirement is that the pixel of opposite polarity in all frames is arranged fine.
The 5th requirement is that the sub-pixel of identical polar, same luminance level (especially the brightest sub-pixel) in all frames is arranged fine.
Verify according to first requirement.In Figure 34 A and 34B, each pixel is comprised of two different sub-pixels of brightness.Particularly, for example in Figure 34 A, the pixel of the capable and m row of n is by the high brightness subpixel that is expressed as " b (bright) " and be expressed as the low-light level sub-pixel of " d (secretly) " and form.Therefore, satisfy first requirement.
Require to verify according to second.The liquid crystal display of the present embodiment replaces two kinds of show states of different driving state with the rule time interval.Figure 34 A and 34B represent to meet corresponding to the driving condition of two show states the position of high brightness subpixel and low-light level sub-pixel.Therefore, satisfy the second requirement.
Require to verify according to the 3rd.In Figure 34 A and 34B, the sub-pixel of different intensity levels (that is, being expressed as the sub-pixel and the sub-pixel that is expressed as " d (secretly) " of " b (bright) ") is arranged by lineament.The demonstration problem is not seen in the visualization of liquid crystal display, for example because different brightness sub-pixels reduce resolution.Therefore, satisfy the 3rd requirement.
Require to verify according to the 4th.In Figure 34 A and 34B, the Pixel arrangement of opposite polarity becomes lineament.Particularly, for example in Figure 34 A, the pixel at n+2 in capable and m+2 row has "+" polarity.From this pixel, follow direction and column direction and change polarity every a pixel between "-" and "+".For not satisfying the 4th liquid crystal display that requires, think to change to synchronize between "+" and "-" with the driving polarity of pixel to see flashing of display.But, can't see when the liquid crystal display of sight check the present embodiment and flash.Therefore, satisfy the 4th requirement.
Require to verify according to the 5th.In Figure 34 A and 34B, the sub-pixel of observing same luminance level drives polarity, and every two row sub-pixels (that is, every a pixel wide) counter-rotating drives polarity.Particularly, for example in n_B was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "-".In n+1_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "-".In n+1_B was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "+".In n+2_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "+".For not satisfying the 5th liquid crystal display that requires, think to change to synchronize between "+" and "-" with the driving polarity of pixel to see flashing of display.But, can't see during according to liquid crystal display of the present invention when sight check and flash.Therefore, satisfy the 5th requirement.
When the liquid crystal display according to the present embodiment is changed the amplitude VCSpp of CS voltage by people such as inventors, during oblique view, inhibition along with the display comparison degree, viewing angle characteristic improves, because the amplitude VCSpp of CS voltage increases (0V is used for the common liquid crystals display of support except the liquid crystal display according to the present invention) from 0V.But, further increase the VSCpp value and have the problem that reduces the display comparison degree.Therefore, the VSCpp value only is set to the scope that abundant raising viewing angle characteristic does not go wrong.Although as if according to the image that shows, the raising of viewing angle characteristic is slightly different, when setting VCSpp so that VLCaddpp value the 0.5-2 of the liquid crystal display threshold voltage of common drive pattern (VCSpp is 0V) doubly within the time, the raising of realization the best.
Generally, it is 2 times of liquid crystal display horizontal scanning period that the present embodiment might be set the oscillation period that imposes on the anti-counter electrode oscillating voltage of memory capacitance, liquid crystal display improves viewing angle characteristic by applying oscillating voltage to the memory capacitance counter electrode, therefore, realizes that many pixels show.Even on the large liquid crystal display of the high capacity electric capacity with CS bus and resistance, have on the high-resolution liquid crystal display of short horizontal scanning period or have high-speed driving and the liquid crystal display of short vertical, horizontal scanning period on, realize easily that also many pixels show.
Although in the above-described embodiments, CS main line electrical isolation (group) number is 4 or 2, is not limited to these according to CS main line electrical isolation (group) number of the liquid crystal display of invention third aspect embodiment, can be 3,5 or greater than 5.But it is even number that preferred electrical isolation CS main line is counted L.This is to exceed 180 oscillating voltages of spending phase places when (meaning that L is even number) because of form the CS main line when electrical isolation CS main line to also mutually supplying with, and may make the magnitude of current that flows through the memory capacitance counter electrode minimum.
Below the table 5 and 6 quantity L that is illustrated in electrical isolation CS main line be 6 or 8 situation, the CS main line relation of corresponding grid bus and CS bus.When L is even number, the relation of the CS main line of corresponding grid bus and CS bus be divided into roughly L/2 be odd number (L=2,6,10, situation 14...) and L/2 are even number (L=4,8,12, situations 16...).Describe in L/2 is universal relation table 5 below in the situation of odd number, and describe in L/2 is universal relation table 6 below in the situation of even number, wherein L=8.
[table 5]
The CS main line Corresponding grid bus Corresponding CS bus
CSVtypeC1 GBL_n，GBL_n+3，GBL_n+6， GBL_n+9，GBL_n+12，… ...................... [GBL_n+3·k (k＝0，1，2，3，…)] CSBL_A_n，CSBL_A_n+3，CSBL_A_n+6， CSBL_A_n+9，CSBL_A_n+12，… ............................ [CSBL_A_n+3·k， (k＝0，1，2，3，…)]
CSVtypeC2 GBL_n，GBL_n+3，GBL_n+6， GBL_n+9，GBL_n+12，… ...................... [GBL_n+3·k (k＝0，1，2，3，…)] CSBL_B_n，CSBL_B_n+3，CSBL_B_n+G， CSBL_B_n+9，CSBL_B_n+12，… ............................ [CSBL_B_n+3·k (k＝0，1，2，3，…)]
CSVtypeC3 GBL_n+ 1，GBL_n+4，GBL_n+7， GBL_n+10，GBL_n+13，… ....................... [GBL_n+1+3·k (k＝0，1，2，3，…)] CSBL_A_n+1，CSBL_A_n+4， CSBL_A_n+7， CSBL_A_n+10，CSBL_A_n+13，… ........................... [CSBL_A_n+1+3·k (k＝0，1，2，3，…)]
CSVtypeC4 GBL_n+ 1，GBL_n+4，GBL_n+7， GBL_n+10，GBL_n+13，… ...................... [GBL_n+1+3·k (k＝0，1，2，3，…)] CSBL_B_n+1，CSBL_B_n+4， CSBL_B_n+7， CSBL_B_n+10，CSBL_B_n+13，… ......................... [CSBL_B_n+1+3·k (k＝0，1，2，3，…)]
CSVtypeC5 GBL_n+ 2，GBL_n+5，GBL_n+8， GBL_n+11，GBL_n+14，… ....................... [GBL_n+2+3·k (k＝0，1，2，3，…)] CSBL_A_n+2，CSBL_A_n+5， CSBL_A_n+8， CSBL_A_n+11，CSBL_A_n+14，… .......................... [CSBL_A_n+2+3·k (k＝0，1，2，3，…)]
CSVtypeC6 GBL_n+ 2，GBL_n+5，GBL_n+8， GBL_n+11，GBL_n+14，… ......................... [GBL_n+2+3·k (k＝0，1，2，3，…)] CSBL_B_n+2，CSBL_B_n+5， CSBL_B_n+8， CSBL_B_n+11，CSBL_B_n+14，… .......................... [CSBL_B_n+2+3·k (k＝0，1，2，3，…)]
When electrical isolation CS main line is counted 1/2 of L and is odd number, be L=2,6,10 etc., if the storage capacitance line that is connected on the memory capacitance counter electrode of the first sub-pixel of pixel is expressed as CSBL_A_n, wherein pixel is arranged in any row and the place, point of crossing of the given row n of row that forms in a plurality of pixels of arranging by the ranks matrix, if the storage capacitance line that is connected on the memory capacitance counter electrode of the second sub-pixel is expressed as CSBL_B_n, and if k be natural number (comprising 0):
CSBL_A_n+ (L/2) * k is connected on the first memory capacitance main line,
CSBL_B_n+ (L/2) * k is connected on the second memory capacitance main line,
CSBL_A_n+1+ (L/2) * k is connected on the 3rd memory capacitance main line,
CSBL_B_n+1+ (L/2) * k is connected on the 4th memory capacitance main line,
CSBL_A_n+2+ (L/2) * k is connected on the 5th memory capacitance main line,
CSBL_B_n+2+ (L/2) * k is connected on the 6th memory capacitance main line,
... repeat similarly to connect,
CSBL_A_n+ (L/2)-2+ (L/2) * k is connected on (L-3) memory capacitance main line,
CSBL_B_n+ (L/2)-2+ (L/2) * k is connected on (L-2) memory capacitance main line,
CSBL_A_n+ (L/2)-1+ (L/2) * k is connected on (L-1) memory capacitance main line,
CSBL_B_n+ (L/2)-1+ (L/2) * k is connected on L memory capacitance main line.
[table 6]
The CS main line Corresponding grid bus Corresponding CS bus
CSVtypeD1 GBL_n，GBL_n+4，GBL_n+8， GBL_n+12，GBL_n+16，… ....................... [GBL_n+4·k (k＝0，1，2，3，…)] CSBL_A_n，CSBL_B_n+4，CSBL_A_n+8， CSBL_B_n+12，CSBL_A_n+16，… ............................. [CSBL_A_n+8·k，CSBL_B_n+4+8·k， (k＝0，1，2，3，…)]
CSVtypeD2 GBL_n，GBL_n+4，GBL_n+8， GBL_n+12，GBL_n+16，… ....................... [GBL_n+4·k (k＝0，1，2，3，…)] CSBL_B_n，CSBL_A_n+4，CSBL_B_n+8， CSBL_A_n+12，CSBL_B_n+16，… .............................. [CSBL_B_n+8·k，CSBL_A_n+4+8·k (k＝0，1，2，3，…)]
CSVtypeD3 GBL_n+ 1，GBL_n+5，GBL_n+9， GBL_n+13，GBL_n+17，… ........................ [GBL_n+1+4·k (k＝0，1，2，3，…)] CSBL_A_n+1，CSBL_B_n+5，CSBL_A_n+9， CSBL_B_n+13，CSBL_A_n+17，… .................................. [CSBL_A_n+1+8·k，CSBL_B_n+5+8·k， (k＝0，1，2，3，…)]
CSVtypeD4 GBL_n+ 1，GBL_n+5，GBL_n+9， GBL_n+13，GBL_n+17，… ....................... [GBL_n+1+4·k (k＝0，1，2，3，…)] CSBL_B_n+1，CSBL_A_n+5，CSBL_B_n+9， CSBL_A_n+13，CSBL_B_n+17，… ............................... [CSBL_B_n+1+8·k，CSBL_A_n+5+8·k (k＝0，1，2，3，…)]
CSVtypeD5 GBL_n+ 2，GBL_n+6， GBL_n+10， GBL_n+14，GBL_n+18，… ...................... [GBL_n+2+4·k (k＝0，1，2，3，…)] CSBL_A_n+2，CSBL_B_n+6，CSBL_A_n+10， CSBL_B_n+14，CSBL_A_n+18，… ................................ [CSBL_A_n+2+8·k，CSBL_B_n+6+8·k (k＝0，1，2，3，…)]
CSVtypeD6 GBL_n+ 2，GBL_n+6， GBL_n+10， GBL_n+14，GBL_n+18，… .................... [GBL_n+2+4·k (k＝0，1，2，3，…)] CSBL_B_n+2，CSBL_A_n+6，CSBL_B_n+10， CSBL_A_n+14，CSBL_B_n+18，… ................................. [CSBL_B_n+2+8·k，CSBL_A_n+6+8·k (k＝0，1，2，3，…)]
CSVtypeD7 GBL_n+ 3，GBL_n+7，GBL_n+11， GBL_n+15，GBL_n+19，… ......................... [GBL_n+3+4·k (k＝0，1，2，3，…)] CSBL_A_n+3，CSBL_B_n+7，CSBL_A_n+11， CSBL_B_n+15，CSBL_A_n+19，… ............................. [CSBL_A_n+3+8·k，CSBL_B_n+7+8·k (k＝0，1，2，3，…)]
CSVtypeC8 GBL_n+ 3，GBL_n+7，GBL_n+11， GBL_n+15，GBL_n+19，… ...................... [GBL_n+3+4·k (k＝0，1，2，3，…)] CSBL_B_n+3，CSBL_A_n+7，CSBL_B_n+11， CSBL_A_n+15，CSBL_B_n+19，… ................................... [CSBL_B_n+3+8·k，CSBL_A_n+7+8·k (k＝0，1，2，3，…)]
When electrical isolation memory capacitance main line is counted 1/2 of L and is even number, namely, L=4,8,12 etc., if the storage capacitance line that is connected on the memory capacitance counter electrode of the first sub-pixel of pixel is expressed as CSBL_A_n, wherein pixel is arranged in any row and the place, point of crossing of the given row n of row that forms in a plurality of pixels of arranging by the ranks matrix, if the storage capacitance line that is connected on the memory capacitance counter electrode of the second sub-pixel is expressed as CSBL_B_n, and if k be natural number (comprising 0):
CSBL_A_n+L*k and CSBL_B_n+ (L/2)+L*k is connected on the first memory capacitance main line,
CSBL_B_n+L*k and CSBL_A_n+ (L/2)+L*k is connected on the second memory capacitance main line,
CSBL_A_n+1+L*k and CSBL_B_n+ (L/2)+1+L*k is connected on the 3rd memory capacitance main line,
CSBL_B_n+1+L*k and CSBL_A_n+ (L/2)+1+L*k is connected on the 4th memory capacitance main line,
CSBL_A_n+2+L*k and CSBL_B_n+ (L/2)+2+L*k is connected on the 5th memory capacitance main line,
CSBL_B_n+2+L*k and CSBL_A_n+ (L/2)+2+L*k is connected on the 6th memory capacitance main line,
CSBL_A_n+3+L*k and CSBL_B_n+ (L/2)+3+L*k is connected on the 7th memory capacitance main line,
CSBL_B_n+3+L*k and CSBL_A_n+ (L/2)+3+L*k is connected on the 8th memory capacitance main line,
Repeat similarly to connect,
CSBL_A_n+ (L/2)-2+ (L/2) * k and CSBL_B_n+L-2+L*k are connected on (L-3) memory capacitance main line,
CSBL_B_n+ (L/2)-2+ (L/2) * k and CSBL_A_n+L-2+L*k are connected on (L-2) memory capacitance main line,
CSBL_A_n+ (L/2)-1+ (L/2) * k and CSBL_B_n+L-1+L*k are connected on (L-1) memory capacitance main line,
CSBL_B_n+ (L/2)-1+ (L/2) * k and CSBL_A_n+L-1+L*k are connected on L memory capacitance main line.
As mentioned above, a third aspect of the present invention makes the many pixel liquid crystal display of easy application, it can improve the display comparison degree during watching the liquid crystal display of large liquid crystal display, high-resolution liquid crystal display and high-speed driving and short vertical, horizontal scanning period in inclination widely.Because be applied to voltage oscillation cycle on the CS bus by increase, following point may easily be arranged: increase the waveform that oscillating voltage is applied to the size of many pixel liquid crystal display of CS bus, the load capacitance that increases the CS bus and resistance, passivation CS bus voltage; With the resolution and the actuating speed that increase liquid crystal display, reduce the CS bus oscillation period, increase the impact of waveform passivation and cause the effective value significant change of VLCadd in display screen, therefore cause show irregular.
In the liquid crystal display according to second aspect present invention embodiment, it makes the public CS bus of electricity consumption be used for the adjacent subpixels of adjacent lines pixel, and adopts the CS main line of two groups of electrical isolations, and be 1H the oscillation period of CS bus voltage.On the other hand, liquid crystal display according to third aspect present invention embodiment, it uses electrical isolation CS bus to be used for the adjacent subpixels of adjacent lines pixel, when using the CS main line of two groups of electrical isolations, can be set as 2H the oscillation period of CS bus voltage, when using the CS main line of four groups of electrical isolations, can be set as 4H the oscillation period of CS bus voltage.
Structure or drive waveforms according to the liquid crystal display of third aspect present invention embodiment, by using electrical isolation CS main line, the adjacent subpixels that is used for the adjacent lines pixel, and adopt L group insulation CS main line, can be set as the L of horizontal scanning period (LHs) oscillation period of CS bus doubly.
The below will describe according to the liquid crystal display of fourth aspect present invention embodiment and its driving method.
As mentioned above, liquid crystal display according to third aspect present invention embodiment, use the memory capacitance counter electrode (the CS main line of L electrical isolation) of L group electrical isolation, can will be applied to L that oscillating voltage on the memory capacitance counter electrode is set as horizontal scanning period oscillation period doubly.With the memory capacitance counter electrode line of heavy electric loading, may realize on large high-resolution liquid crystal display that many pixels show like this.
But, the embodiment of the third aspect need to use the memory capacitance counter electrode of electrical isolation, at the sub-pixel (that is, two of adjacent lines pixels) of two neighbors of column direction (for example is used for, referring to Figure 29), meaning each pixel needs two CS buses.There is like this problem that reduces the pixel aperture ratio.Particularly, for example, as shown in Figure 35 A, use the CS bus that is used for sub-pixel to be arranged in the structure at the center of each sub-pixel, make it need to provide black matrix B M1 to prevent by the light leak between the column direction neighbor.Therefore, the area of two CS buses and black matrix crossover can not be used for showing.This has just reduced the pixel aperture ratio.
On the contrary, according to the embodiment of fourth aspect, as shown in Figure 35 B, two adjacent subpixels of two different pixels of adjacent columns direction have the memory capacitance counter electrode that connects public CS bus, the CS bus allows to be arranged between the column direction neighbor, therefore makes the CS bus also play black matrix.Compare with the structure of Figure 35 A, have advantages of to reduce the CS number of buses, improved the aperture ratio of pixel by the black matrix B M1 that separately provides in addition is provided.
With regard to regard to the liquid crystal display of third aspect embodiment, be set as L times of horizontal scanning period oscillation period for the oscillating voltage that will be applied to the CS bus, require to use L electrical isolation CS main line, require L driving power to supply with the memory capacitance counter electrode.As a result, increase on demand the oscillating voltage oscillation period that imposes on the CS bus, thereby the driving power number that needs to increase the quantity of CS main line and supply with the memory capacitance counter electrode.Like this, use the liquid crystal display according to third aspect embodiment, being applied in increase has certain restriction aspect cycle of the oscillating voltage on the CS bus, because the driving power number that needs to increase CS main line number and supply with the memory capacitance counter electrode.
On the contrary, with regard to regard to the liquid crystal display of fourth aspect present invention embodiment, when electrical isolation CS main line number is L (L is even number), can be set as 2*K*L times (K is positive integer) of horizontal scanning period the oscillation period of oscillating voltage.
Therefore, be more suitable for large high-resolution liquid crystal display according to the liquid crystal display beguine of fourth aspect present invention embodiment according to the liquid crystal display of third aspect embodiment.
The below relates to description the embodiment of fourth aspect present invention, introduces the liquid crystal display example that realizes driving condition as shown in 36A and 36B.The direction of an electric field that is applied on the pixel liquid crystal layer is opposite between Figure 36 A that corresponds respectively to Figure 24 A and 24B and 36B.The below uses description to realize the structure of driving condition shown in Figure 36 A.Incidentally, in order to implement the driving condition shown in Figure 36 B, be applied to the polarity of voltage of power lead and memory capacitance polarity of voltage and can use the same way as of describing with reference to Figure 23 A and 23B from the reversal of poles shown in Figure 36 A.Like this might the first and second sub-pixels are in position (being " b (bright) " or " d (secretly) " in figure), simultaneously, the demonstration polarity (being "+" or "-" in figure) of counter-rotating pixel.But, the invention is not restricted to this, only allow to be applied to the voltage reversal of power bus.In this case, because the first and second sub-pixels change position (being " b (bright) " or " d (secretly) " in figure) in company with the counter-rotating of pixel polarity, therefore fixedly the time, may alleviate the problems such as bleeding that run into when location of pixels in middle gray grade procedure for displaying.
In the liquid crystal display according to following embodiment, as shown in Figure 35 B, the public CS bus CSBL that arranges between the adjacent pixel of column direction two (n capable and (n+1) OK) the pixel electrode 18b of the capable pixel of public n and the pixel electrode 18a of the capable pixel of n+1 is in order to supply with memory capacitance inverse voltage (oscillating voltage) auxiliary capacitor of sub-pixel.Public CS bus CSBL also plays the effect of black matrix, passes through to stop the light between capable and (n+1) row pixel of n.Public CS bus CSBL arranges like this: namely, and through dielectric film part crossover pixel electrode 18a and 18b.
Draw below basis in the liquid crystal display of the embodiment that makes example, be longer than horizontal scanning period and electrical isolation CS main line quantity oscillation period when being L (L is even number) when the oscillating voltage that is applied to the CS bus, the 2*K*L that the oscillating voltage that is applied to the CS bus can be set as a horizontal scanning period (K is positive integer) oscillation period doubly.Namely, although allow only to be set to L the oscillation period of oscillating voltage doubly according to the liquid crystal display of third aspect present invention embodiment, but have advantages of the oscillation period of allowing further by coefficient 2*K increase according to the liquid crystal display of fourth aspect present invention embodiment, wherein K does not depend on the quantity of electrical isolation CS main line.K depends between single electrical isolation CS main line and CS bus the parameter that connects pattern, and equal to connect the public CS main line in continuous CS bus CS number of buses (electrical equivalent CS bus) 1/2, the CS bus consists of the one-period that connects the CS main line.
According to many pixel drivers of the liquid crystal display of the embodiment of the present invention, each pixel is divided into two sub-pixels, different oscillating voltage (memory capacitance inverse voltage) is supplied with the auxiliary capacitor that connects each sub-pixel, therefore obtain transom pixel and dark sub-pixel.For example, be that voltage raises if TFT closes the first variation of rear oscillating voltage, the transom pixel appears, and on the contrary, be lower voltage if TFT closes the first variation of rear oscillating voltage, dark sub-pixel appears.Therefore, be connected to public CS main line if be used for the CS bus of the sub-pixel that oscillating voltage should raise after TFT closes, and the CS bus that is used for the sub-pixel that oscillating voltage should reduce after TFT closes just is connected to another public CS main line, may reduce CS main line quantity.K means by connecting the parameter that pattern increases the cycle effect between CS bus and CS main line.
By increasing the K value, may correspondingly increase oscillating voltage.But preferred K value is not too large.The below will describe reason.
The increase of K value has increased the number of sub-pixels that connects public CS main line.They connect different TFT, and it is closed with different intervals (multiple of 1H).Therefore, be connected on public CS main line and be connected on public CS main line to increase (or minimizing) the required time of another sub-pixel oscillating voltage of the very first time after sub-pixel TFT closes to increase (or minimizing) the required time of sub-pixel oscillating voltage of the very first time after sub-pixel TFT closes, to be different from.The increase of this mistiming with the K value increases, that is, increase with the increase that is connected to the CS bus number on public CS main line.This can cause the irregular vision of linear luminance.Irregular in order to prevent this brightness, be not more than 5% of number of scanning lines (number of lines of pixels) with the preferred mistiming of empirical method.For example, in the XGA situation, preferred K value set for the mistiming be not more than 768 row 5% or be not more than 38H.In the same manner, the low limit in oscillating voltage cycle should be set with reference to Figure 28 etc., can not produce like this brightness that causes due to the waveform passivation irregular.For example, in the situation of 45 inches XGA displays, if be 12H or larger oscillation period, there is no the problem of waveform passivation.Therefore, in the situation of 45 inches liquid crystal display, if K be set as 1 or 2, L be set as 6,8,10, or 12, the cycle of oscillating voltage may realize there is no the irregular high-quality display of brightness within being set in 12H-48H.In the same manner, consider oscillating voltage power supply (supplying with the driving power of memory capacitance counter electrode) number, electrical isolation CS main line is counted L should stipulate the first-class wiring of plate (TFT substrate).
The below will describe the Liquid Crystal Display And Method For Driving according to fourth aspect present invention embodiment, in quoting example, and K=1, L=4,6,8,10, or 12, in example, K=2, L=4 or 6.For fear of the content that repetition front embodiment has described, following description concentrates on the layout between CS bus and CS main line.
[K=1, L=4, oscillation period=8H]
The matrix structure of liquid crystal display according to the present invention (the connection pattern of CS bus) is used for the signal waveform of driving liquid crystal display as shown in figure 38 as shown in figure 37.And, be used for the connection pattern of Figure 37 shown in table 7.With matrix structure shown in Figure 37, because use the timing as shown in 38 that oscillating voltage is applied on the CS bus, therefore realized the driving condition shown in Figure 35 A.
In Figure 37, each CS bus is connected on all four CS main lines that are arranged on the left and right two ends of figure.Therefore, four groups of electrical isolation CS buses are arranged, so L=4.And in Figure 37, the pattern that connects between CS bus and CS main line has some rule, that is, every in the drawings 8 CS buses repeat identical pattern.Therefore, K=1 (=8/ (2L)).
[table 7]
L＝4，K＝1
The CS main line The CS bus that connects the CS main line
M1a CSBL_(n-1) B，(n )A CSBL_(n+4) B，(n+5)A
M2a CSBL_(n ) B，(n+1)A CSBL_(n+3) B，(n+4)A
M3a CSBL_(n+1) B，(n+2)A CSBL_(n+6) B，(n+7)A
M4a CSBL_(n+2) B，(n+3)A CSBL_(n+5) B，(n+6) A
N=1 wherein, 9,17 ...
As can be seen from Table 7, the CS bus in Figure 37 is divided into two types, that is:
Any p is satisfied the α type of following expression formula
CSBL_(p)B，(p+1)A
CSBL_(p+5)B，(p+6)A
With any p is satisfied the β type of following expression formula
CSBL_(p+1)B，(p+2)A
CSBL_(p+4)B，(p+5)A
Particularly, the CS bus that connects CS main line M1a and M3a is the α type, and the CS bus of connection CS main line M2a and M4a is the β type.
Be used for 8 continuous CS buses that connect the cycle by 4 α type buses (connect two buses of M1a and is connected two of M3a and connect buses) with are connected a β type bus (two buses of connection M2a and two connection buses that are connected M4a) and form.
Utilize parameter L and K, top expression formula can followingly provide any p:
CSBL_(p+2*(K-1))B，(p+2*(K-1)+1)A
CSBL_(p+2*(K-1)+K*L+1)B，(p+2*(K-1)+K*L+2)A
Or
CSBL_(p+2*(K-1)+1)B，(p+2*(K-1)+2)A
CSBL_(p+2*(K-1)+K*L)B，(p+2*(K-1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....Because do not have the CS bus to satisfy two α types and β type, therefore introduce this condition.
In the same manner, can find out that in Figure 38 be 8H the oscillating voltage oscillation period that is applied to the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
[K=1, L=6, oscillation period=12H]
Supposing has 6 groups of electrical isolation CS buses, connects pattern as shown in figure 39, and drive waveforms as shown in figure 40.And, be used for the connection pattern of Figure 39 shown in table 8.
In Figure 40, each CS bus is connected on all 6 CS main lines that are arranged on the left and right two ends of figure.Therefore, 6 groups of electrical isolation CS buses, L=6 are as a result arranged.
And, in Figure 39, some rule of connection pattern between CS bus and CS main line, that is, every in the drawings 12 CS buses repeat identical connection pattern.Therefore, K=1 (=12/ (2L)).
[table 8]
L＝4，K＝1
The CS main line The CS bus that connects the CS main line
M1a CSBL_(n-1) B，(n )A CSBL_(n+4) B，(n +5)A
M2a CSBL_(n ) B，(n +1)A CSBL_(n+3) B，(n+4)A
M3a CSBL_(n+1) B，(n+2)A CSBL_(n+6) B，(n+7)A
M4a CSBL_(n+2) B，(n+3)A CSBL_(n+5) B，(n+6)A
N=1 wherein, 9,17 ...
As can be seen from Table 8, the CS bus in Figure 39 is that electricity equates in each group that following expression formula groups by all represent:
CSBL_(p)B，(p+1)A
CSBL_(p+7)B，(p+8)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+6)B，(p+7)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL_(p+2*(K-1))B，(p+2*(K-1)+1)A
CSBL_(p+2*(K-1)+K*L+1)B，(p+2*(K-1)+K*L+2)A
Or
CSBL_(p+2*(K-1)+1)B，(p+2*(K-1)+2)A
CSBL_(p+2*(K-1)+K*L)B，(p+2*(K-1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 40, can find out that be 12H the oscillating voltage oscillation period that is applied on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
[K=1, L=8, oscillation period=16H]
Supposing has 8 groups of electrical isolation CS buses, connects pattern as shown in figure 41, and drive waveforms as shown in figure 42.And, be used for the connection pattern of Figure 41 shown in table 9.
In Figure 41, each CS bus is connected on all 8 CS main lines that are arranged on the left and right two ends of figure.Therefore, 8 groups of electrical isolation CS buses, L=8 are as a result arranged.
And in Figure 41, the connection pattern between CS bus and CS main line has some rule, that is, every in the drawings 16 CS buses repeat identical connection pattern.Therefore, K=1 (=16/ (2L)).
[table 9]
L＝8，K＝1
The CS main line The CS bus that connects the CS main line
M1c CSBL_(n-1) B，(n )A CSBL_(n+8) B，(n+9)A
M2c CSBL_(n ) B，(n+1)A CSBL_(n+7) B，(n+8)A
M3c CSBL_(n+1) B，(n+2)A CSBL_(n+10) B，(n+11)A
M4c CSBL_(n+2) B，(n+3)A CSBL_(n+9) B，(n+10)A
M5c CSBL_(n+3) B，(n+4)A CSBL_(n+12) B，(n+13)A
M6c CSBL_(n+4) B，(n+5)A CSBL_(n+11) B，(n+12)A
M7c CSBL_(n+5) B，(n+6)A CSBL_(n+14) B，(n+15)A
M8c CSBL_(n+6) B，(n+7)A CSBL_(n+13) B，(n+14)A
N=1 wherein, 17,33 ...
As can be seen from Table 9, the CS bus in Figure 41 is that electricity equates in each group that following expression formula groups by all represent:
CSBL_(p)B，(p+1)A
CSBL_(p+9)B，(p+10)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+8)B，(p+9)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL_(p+2*(K-1))B，(p+2*(K-1)+1)A
CSBL_(p+2*(K-1)+K*L+1)B，(p+2*(K-1)+K*L+2)A
Or
CSBL_(p+2*(K-1)+1)B，(p+2*(K-1)+2)A
CSBL_(p+2*(K-1)+K*L)B，(p+2*(K-1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 42, can find out that be 16H the oscillating voltage oscillation period that is applied on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
[K=1, L=10, oscillation period=20H]
Supposing has 10 groups of electrical isolation CS buses, connects pattern as shown in figure 43, and drive waveforms as shown in figure 44.And, be used for the connection pattern of Figure 43 shown in table 10.
In Figure 43, each CS bus is connected on all 10 CS main lines that are arranged on the left and right two ends of figure.Therefore, 10 groups of electrical isolation CS buses, L=10 are as a result arranged.And in Figure 43, the connection pattern between CS bus and CS main line has some rule, that is, every in the drawings 20 CS buses repeat identical connection pattern.Therefore, K=1 (=20/ (2L)).
[table 10]
L＝10，K＝1
The CS main line The CS bus that connects the CS main line
M1d CSBL_(n-1) B，(n )A CSBL_(n+10) B，(n+11)A
M2d CSBL_(n ) B，(n+1) A CSBL_(n+9) B，(n+10)A
M3d CSBL_(n+1) B，(n+2)A CSBL_(n+12) B，(n+13)A
M4d CSBL_(n+2) B，(n+3)A CSBL_(n+11) B，(n+12)A
M5d CSBL_(n+3) B，(n+4)A CSBL_(n+14) B，(n+15)A
M6d CSBL_(n+4) B，(n+5)A CSBL_(n+13) B，(n+14)A
M7d CSBL_(n+5) B，(n+6)A CSBL_(n+16) B，(n+17)A
M8d CSBL_(n+6) B，(n+7)A CSBL_(n+15) B，(n+16)A
M9d CSBL_(n+7) B，(n+6)A CSBL_(n+18) B，(n+19)A
M10d CSBL_(n+8) B，(n+7)A CSBL_(n+17) B，(n+18)A
N=1 wherein, 21,41 ...
As can be seen from Table 10, the CS bus in Figure 43 is that electricity equates in each group that following expression formula groups by all represent:
CSBL_(p)B，(p+1)A
CSBL_(p+11)B，(p+12)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+10)B，(p+11)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL_(p+2*(K-1))B，(p+2*(K-1)+1)A
CSBL_(p+2*(K-1)+K*L+1)B，(p+2*(K-1)+K*L+2)A
Or
CSBL_(p+2*(K-1)+1)B，(p+2*(K-1)+2)A
CSBL_(p+2*(K-1)+K*L)B，(p+2*(K-1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 44, can find out that be 20H the oscillating voltage oscillation period that is applied on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
[K=1, L=12, oscillation period=24H]
Supposing has 12 groups of electrical isolation CS buses, connects pattern as shown in figure 45, and drive waveforms as shown in figure 46.And, be used for the connection pattern of Figure 45 shown in table 11.
In Figure 45, each CS bus is connected on all 12 CS main lines that are arranged on the left and right two ends of figure.Therefore, 12 groups of electrical isolation CS buses, L=12 are as a result arranged.And in Figure 45, the connection pattern between CS bus and CS main line has some rule, that is, every in the drawings 24 CS buses repeat identical connection pattern.Therefore, K=1 (=24/ (2L)).
[table 11]
L＝12，K＝1
The CS main line The CS bus that connects the CS main line
M1e CSBL_(n-1) B，(n )A CSBL_(n+12) B，(n+13)A
M2e CSBL_(n ) B，(n+1)A CSBL_(n+11) B，(n+12)A
M3e CSBL_(n+1) B，(n+2)A CSBL_(n+14) B，(n+15)A
M4e CSBL_(n+2) B，(n+3)A CSBL_(n+13) B，(n+14)A
M5e CSBL_(n+3) B，(n+4)A CSBL_(n+16) B，(n+17)A
M6e CSBL_(n+4) B，(n+5)A CSBL_(n+15) B，(n+16)A
M7e CSBL_(n+5) B，(n+6) A CSBL_(n+18) B，(n+19)A
M8e CSBL_(n+6) B，(n+7)A CSBL_(n+17) B，(n+18)A
M9e CSBL_(n+7) B，(n+6)A CSBL_(n+20) B，(n+21)A
M10e CSBL_(n+8) B，(n+7)A CSBL_(n+19) B，(n+20)A
M11e CSBL_(n+9) B，(n+10)A CSBL_(n+22) B，(n+23)A
M12e CSBL_(n+10) B，(n+11)A CSBL_(n+21) B，(n+22)A
N=1 wherein, 25,49 ...
As can be seen from Table 11, the CS bus in Figure 45 is that electricity equates in each group that following expression formula groups by all represent:
CSBL_(p)B，(p+1)A
CSBL_(p+13)B，(p+14)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+12)B，(p+13)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL_(p+2*(K-1))B，(p+2*(K-1)+1)A
CSBL_(p+2*(K-1)+K*L+1)B，(p+2*(K-1)+K*L+2)A
Or
CSBL_(p+2*(K-1)+1)B，(p+2*(K-1)+2)A
CSBL_(p+2*(K-1)+K*L)B，(p+2*(K-1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 46, can find out that be 24H the oscillating voltage oscillation period that is applied on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
In all said circumstanceses, parameter K=1.Now, characterising parameter value K is 2 situation.
[K=2, L=4, oscillation period=16H]
Suppose that parameter value K is 2 and 4 groups of electrical isolation CS buses are arranged, connect pattern as shown in figure 47, drive waveforms as shown in figure 48.And, be used for the connection pattern of Figure 47 shown in table 12.
In Figure 47, each CS bus is connected on all 4 CS main lines that are arranged on the left and right two ends of figure.Therefore, 4 groups of electrical isolation CS buses, L=4 are as a result arranged.And in Figure 47, the connection pattern between CS bus and CS main line has some rule, that is, every in the drawings 16 CS buses repeat identical connection pattern.Therefore, K=1 (=16/ (2L)).
[table 12]
L＝4，K＝2
The CS main line The CS bus that connects the CS main line
M1f CSBL_(n-1) B，(n ) A CSBL_(n+1) B，(n+2) A CSBL_(n+8) B，(n+9) A CSBL_(n+10) B (n+11) A
M2f CSBL_(n ) B，(n+1) A CSBL_(n+2) B，(n+3) A CSBL_(n+7) B，(n+8) A CSBL_(n+9) B (n+10) A
M3f CSBL_(n+3) B，(n+4) A CSBL_(n+5) B，(n+6) A CSBL_(n+12) B，(n+13) A CSBL_(n+14) B (n+15) A
M4f CSBL_(n+4) B，(n+5) A CSBL_(n+6) B，(n+7) A CSBL_(n+11) B，(n+12) A CSBL_(n+13) B (n+14) A
N=1 wherein, 17,33 ...
As can be seen from Table 12, the CS bus in Figure 47 is that electricity equates in each group that following expression formula groups by all represent:
CSBL_(p)B，(p+1)A
CSBL_(p+2)B，(p+3)A
With
CSBL_(p+9)B，(p+10)A
CSBL_(p+11)B，(p+12)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+3)B，(p+4)A
With
CSBL_(p+8)B，(p+9)A
CSBL_(p+10)B，(p+11)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL_(p+2*(1-1))B，(p+2*(1-1)+1)A
CSBL_(p+2*(K-1))B，(p+2*(K-1)+1)A
With
CSBL_(p+2*(1-1)+K*L+1)B，(p+2*(1-1)+K*L+2)A
CSBL_(p+2*(K-1)+K*L+1)B，(p+2*(K-1)+K*L+2)A
Or
CSBL_(p+2*(1-1)+1)B，(p+2*(1-1)+2)A
CSBL_(p+2*(K-1)+1)B，(p+2*(K-1)+2)A
With
CSBL_(p+2*(1-1)+K*L)B，(p+2*(1-1)+K*L+1)A
CSBL_(p+2*(K-1)+K*L)B，(p+2*(K-1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 48, can find out that be 16H the oscillating voltage oscillation period that is applied on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
[K=2, L=6, oscillation period=24H]
Suppose that parameter value K is 2 and 6 groups of electrical isolation CS buses are arranged, connect pattern as shown in figure 49, drive waveforms as shown in figure 50.And, be used for the connection pattern of Figure 49 shown in table 13.
In Figure 49, each CS bus is connected on all 6 CS main lines that are arranged on the left and right two ends of figure.Therefore, 6 groups of electrical isolation CS buses, L=6 are as a result arranged.And in Figure 47, the connection pattern between CS bus and CS main line has some rule, that is, every in the drawings 24 CS buses repeat identical connection pattern.Therefore, K=1 (=24/ (2L)).
[table 13]
L＝6，K＝2
The CS main line The CS bus that connects the CS main line
M1g CSBL_(n-1) B，(n) A CSBL_(n+1) B，(n+2) A CSBL_(n+12)B，(n+13)A CSBL_(n+14)B (n+15)A
M2g CSBL_(n) B，(n+1) A CSBL_(n+2) B，(n+3) A CSBL_(n+11)B，(n+12)A CSBL_(n+13)B (n+14)A
M3g CSBL_(n+3) B，(n+4) A CSBL_(n+5) B，(n+6) A CSBL_(n+16)B，(n+17)A CSBL_(n+18)B (n+19)A
M4g CSBL_(n+4) B，(n+5) A CSBL_(n+6) B，(n+7) A CSBL_(n+15)B，(n+16)A CSBL_(n+17)B (n+18)A
N5g CSBL_(n+7) B，(n+8) A CSBL_(n+9) B，(n+10)A CSBL_(n+20)B，(n+21)A CSBL_(n+22)B (n+23)A
N6g CSBL_(n+8) B，(n+9) A CSBL_(n+10)B，(n+11)A CSBL_(n+19)B，(n+20)A CSBL_(n+21)B (n+22)A
N=1 wherein, 25,49,
As can be seen from Table 13, the CS bus in Figure 49 is that electricity equates in each group that following expression formula groups by all represent:
CSBL_(p)B，(p+1)A
CSBL_(p+2)B，(p+3)A
With
CSBL_(p+13)B，(p+14)A
CSBL_(p+15)B，(p+16)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+3)B，(p+4)A
With
CSBL_(p+12)B，(p+13)A
CSBL_(p+14)B，(p+15)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL_(p+2*(1-1))B，(p+2*(1-1)+1)A
CSBL_(p+2*(K-1))B，(p+2*(K-1)+1)A
With
CSBL_(p+2*(1-1)+K*L+1)B，(p+2*(1-1)+K*L+2)A
CSBL_(p+2*(K-1)+K*L+1)B，(p+2*(K-1)+K*L+2)A
Or
CSBL_(p+2*(1-1)+1)B，(p+2*(1-1)+2)A
CSBL_(p+2*(K-1)+1)B，(p+2*(K-1)+2)A
With
CSBL_(p+2*(1-1)+K*L)B，(p+2*(1-1)+K*L+1)A
CSBL_(p+2*(K-1)+K*L)B，(p+2*(K-1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 50, can find out that be 24H the oscillating voltage oscillation period that is applied on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
About parameter K and L, although described above at K=1 and L=4,6,8,10, or 12 situation and in the situation of K=2 and L=4 or 6, fourth aspect present invention embodiment is not limited to this.
The K value need be only positive integer, i.e. K=1, and 2,3,4,5,6,7,8,9 etc., L value need be only even number, i.e. L=2,4,6,8,10,12,14,16,18 etc.In addition, K value and L value can be set in scope separately independently.
About the connection between CS main line and CS bus, follow above-mentioned rule.
Particularly when the value difference (K=K, L=L) of parameter K and L is K and L, be connected to the CS bus on identical main line, that is, electrical equivalent CS bus should be as follows:
CSBL_(p+2*(1-1))B，(p+2*(1-1)+1)A
CSBL_(p+2*(2-1))B，(p+2*(2-1)+1)A
CSBL_(p+2*3-1)) B，(p+2*(3-1)+1)A
…
CSBL_(p+2*(K-1))B，(p+2*(K-1)+1)A
With
CSBL_(p+2*(1-1)+K*L+1)B，(p+2*(1-1)+K*L+2)A
CSBL_(p+2*(2-1)+K*L+1)B，(p+2*(2-1)+K*L+2)A
CSBL_(p+2*(3-1)+K*L+1)B，(p+2*(3-1)+K*L+2)A
…
CSBL_(p+2*(K-1)+K*L+1)B，(p+2*(K-1)+K*L+2)A
Or
CSBL_(p+2*(1-1)+1)B，(p+2*(1-1)+2)A
CSBL_(p+2*(2-1)+1)B，(p+2*(2-1)+2)A
CSBL_(p+2*(3-1)+1)B，(p+2*(3-1)+2)A
…
CSBL_(p+2*(K-1)+1)B，(p+2*(K-1)+2)A
With
CSBL_(p+2*(1-1)+K*L)B，(p+2*(1-1)+K*L+1)A
CSBL_(p+2*(2-1)+K*L)B，(p+2*(2-1)+K*L+1)A
CSBL_(p+2*(3-1)+K*L)B，(p+2*(3-1)+K*L+1)A
…
CSBL_(p+2*(K-1)+K*L)B，(p+2*(K-1)+K*L+1)A
P=1 wherein, 3,5 etc., or p=0,2,4 etc.
And, as parameter K and L when (K=K, L=L) is K and L respectively, be applied to oscillating voltage on bus CS and can be oscillation period the 2*K*L of horizontal scanning period doubly.
In the same manner, although in superincumbent description, the first sub-pixel of an adjacent image element and the public public CS bus of the second sub-pixel of another image component, certainly, they can use the different CS buses of electrical equivalent.
A first aspect of the present invention can realize reducing the high display quality of the view angle dependency of γ characteristic.A second aspect of the present invention can reduce the flicker of the liquid crystal display that causes in ac driving process.
A third aspect of the present invention can make according to the present invention first or the liquid crystal display of second aspect be fit to large or high-resolution liquid crystal display.
A fourth aspect of the present invention can make according to the present invention first or the liquid crystal display of second aspect be fit to large or high-resolution liquid crystal display, even more adapt to than the third aspect.

Claims (24)

1. liquid crystal display comprises: a large amount of pixels, each pixel have liquid crystal layer and a large amount of being used for executed alive electrode to liquid crystal layer, and electrode is the ranks matrix distribution, it is characterized in that,
Each of a large amount of pixels has can apply to liquid crystal layer the first subpixel and second subpixel of mutually different voltage, and the first subpixel has the brightness higher than the second subpixel under definite gray scale,
Each comprises the first subpixel and the second subpixel:
On-off element is connected to the sweep trace of being shared by described the first subpixel and the second subpixel;
By counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode; With
By the storage capacitor electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with storage capacitor electrode that are electrically connected on the subpixel electrode,
Counter electrode is the single electrode of being shared by the first subpixel and the second subpixel, and the memory capacitance counter electrode of the first subpixel and the second subpixel is electrically insulated from each other,
The memory capacitance counter electrode of the first subpixel in any of a large amount of pixels is electrically insulated from each other with memory capacitance counter electrode and the described sweep trace of the second subpixel of the adjacent image point of arbitrary pixel on column direction,
Comprise the first memory capacitance post and the second memory capacitance post that are electrically insulated from each other, be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of the first subpixel of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of the second subpixel, and if k is natural number or 0:
CSBL_A_n+k is connected on the first memory capacitance post,
CSBL_B_n+k is connected on the second memory capacitance post,
Supply with the first and second memory capacitance inverse voltages by the first and second memory capacitance posts,
Comprise two on-off elements that are respectively the first subpixel and the setting of the second subpixel,
Two on-off elements are opened and are closed by the scanning-line signal voltage of supplying with the common scanning line; When two on-off elements were opened, display voltage was applied on the storage capacitor electrode of each subpixel electrode and the first subpixel and the second subpixel from common signal line; When two on-off elements were closed, the voltage of each memory capacitance counter electrode of the first subpixel and the second subpixel changed,
After if Td represents that two on-off elements are closed, the first memory capacitance inverse voltage changes the required time in the very first time, and Td is greater than 0 horizontal scanning period and less than a horizontal scanning period.
2. liquid crystal display as claimed in claim 1, is characterized in that, the first subpixel of any pixel be scattered in column direction on second subpixel of adjacent image point of arbitrary pixel adjacent.
3. liquid crystal display as claimed in claim 1, is characterized in that, in each of a plurality of pixels, the first subpixel is scattered on column direction adjacent with the second subpixel.
4. liquid crystal display as claimed in claim 1, it is characterized in that, the quantity of the memory capacitance post that is electrically insulated from each other in a large amount of memory capacitance posts is L, and the memory capacitance inverse voltage of being supplied with by each memory capacitance post is oscillating voltage, and be L times of horizontal scanning period oscillation period.
5. liquid crystal display as claimed in claim 1, is characterized in that, a large amount of memory capacitance posts that are electrically insulated from each other are supplied with the memory capacitance inverse voltage of the vibration that 180 ° of phase differential are arranged each other for forming the even number memory capacitance post of paired memory capacitance post.
6. liquid crystal display as claimed in claim 1, it is characterized in that, the quantity of the memory capacitance post that is electrically insulated from each other is than large 8 times of the share of dividing a horizontal scanning period acquisition by the capacitance resistance time constant, and wherein the capacitance resistance time constant is near the maximum load impedance of storage capacitance line.
7. liquid crystal display as claimed in claim 1, it is characterized in that, the quantity of the memory capacitance post that is electrically insulated from each other is than large 8 times of the share of dividing a horizontal scanning period acquisition by the capacitance resistance time constant, and be even number, wherein the capacitance resistance time constant is near the maximum load impedance of storage capacitance line.
8. liquid crystal display as claimed in claim 1, is characterized in that, be respectively the twice of horizontal scanning period the oscillation period of the first and second memory capacitance inverse voltages of supplying with by the first and second memory capacitance posts.
9. liquid crystal display as claimed in claim 8, is characterized in that, the second memory capacitance inverse voltage is than the phase differential of a horizontal scanning period of the first memory capacitance inverse voltage hysteresis.
10. liquid crystal display as claimed in claim 1, is characterized in that, Td is approximately equal to 0.5 times of horizontal scanning period.
11. a liquid crystal display comprises: a large amount of pixels, each pixel have liquid crystal layer and a large amount of being used for executed alive electrode to liquid crystal layer, and electrode is the ranks matrix distribution, it is characterized in that,
Each of a large amount of pixels has can apply to liquid crystal layer the first subpixel and second subpixel of mutually different voltage, and the first subpixel has the brightness higher than the second subpixel under definite gray scale,
Each comprises the first subpixel and the second subpixel:
On-off element is connected to the sweep trace of being shared by described the first subpixel and the second subpixel;
By counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode; With
By the storage capacitor electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with storage capacitor electrode that are electrically connected on the subpixel electrode,
Counter electrode is the single electrode of being shared by the first subpixel and the second subpixel, and the memory capacitance counter electrode of the first subpixel and the second subpixel is electrically insulated from each other,
The memory capacitance counter electrode of the first subpixel in any of a large amount of pixels is electrically insulated from each other with memory capacitance counter electrode and the described sweep trace of the second subpixel of the adjacent image point of arbitrary pixel on column direction,
Comprise a large amount of memory capacitance posts that are electrically insulated from each other, wherein each memory capacitance post is electrically connected on any memory capacitance counter electrode of the first subpixel in a large amount of pixels and the second subpixel through storage capacitance line, and the quantity of described a large amount of memory capacitance posts is the even number more than or equal to 4.
12. liquid crystal display as claimed in claim 11 is characterized in that,
A large amount of memory capacitance posts comprise the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post and the 4th memory capacitance post that is electrically insulated from each other,
Be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of the first subpixel of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of the second subpixel, and if k is natural number or 0:
CSBL_A_n+4*k and CSBL_B_n+2+4*k are connected on the first memory capacitance post,
CSBL_B_n+4*k and CSBL_A_n+2+4*k are connected on the second memory capacitance post,
CSBL_A_n+1+4*k and CSBL_B_n+3+4*k are connected on the 3rd memory capacitance post,
CSBL_B_n+1+4*k and CSBL_A_n+3+4*k are connected on the 4th memory capacitance post.
13. liquid crystal display as claimed in claim 12 is characterized in that, is 4 times of horizontal scanning period the oscillation period of the first to fourth memory capacitance inverse voltage of supplying with by first to fourth memory capacitance post respectively.
14. liquid crystal display as claimed in claim 13, it is characterized in that, the second memory capacitance inverse voltage is than the phase differential of the first stagnant latter two horizontal scanning period of memory capacitance inverse voltage, the 3rd memory capacitance inverse voltage is than the phase differential of three horizontal scanning periods of the first memory capacitance inverse voltage hysteresis, and the 4th memory capacitance inverse voltage is than the phase differential of a horizontal scanning period of the first memory capacitance inverse voltage hysteresis.
15. liquid crystal display as claimed in claim 14 is characterized in that, comprises two on-off elements that are respectively the first subpixel and the setting of the second subpixel,
Two on-off elements are opened and are closed by the scanning-line signal voltage of supplying with the common scanning line; When two on-off elements were opened, display voltage was applied on the storage capacitor electrode of each subpixel electrode and the first subpixel and the second subpixel from common signal line; When two on-off elements were closed, the voltage of each memory capacitance counter electrode of the first subpixel and the second subpixel changed,
After if Td represents that two on-off elements are closed, the first memory capacitance inverse voltage changes the required time in the very first time, and Td is greater than 0 horizontal scanning period and less than two horizontal scanning periods.
16. liquid crystal display as claimed in claim 15 is characterized in that, Td is approximately equal to 1 times of horizontal scanning period.
17. liquid crystal display as claimed in claim 11 is characterized in that,
Described a large amount of memory capacitance post comprises the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post and the 6th memory capacitance post that is electrically insulated from each other,
Be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of the first subpixel of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of the second subpixel, and if k is natural number or 0:
CSBL_A_n+3*k is connected on the first memory capacitance post,
CSBL_B_n+3*k is connected on the second memory capacitance post,
CSBL_A_n+1+3*k is connected on the 3rd memory capacitance post,
CSBL_B_n+1+3*k is connected on the 4th memory capacitance post,
CSBL_A_n+2+3*k is connected on the 5th memory capacitance post,
CSBL_B_n+2+3*k is connected on the 6th memory capacitance post.
18. liquid crystal display as claimed in claim 17 is characterized in that, is 6 times of horizontal scanning period the oscillation period of the first to the 6th memory capacitance inverse voltage of supplying with by the first to the 6th memory capacitance post respectively.
19. liquid crystal display as claimed in claim 11 is characterized in that,
Described a large amount of memory capacitance post comprise the first memory capacitance post of being electrically insulated from each other, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post ... (L-3) memory capacitance post, (L-2) memory capacitance post, (L-1) memory capacitance post and L memory capacitance post etc. are L memory capacitance post altogether
When 1/2 of the quantity L of the memory capacitance post of electrical isolation is odd number, namely when L=6,10 ... Deng the time,
Be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of the first subpixel of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of the second subpixel, and if k is natural number or 0:
CSBL_A_n+ (L/2) * k is connected on the first memory capacitance post,
CSBL_B_n+ (L/2) * k is connected on the second memory capacitance post,
CSBL_A_n+1+ (L/2) * k is connected on the 3rd memory capacitance post,
CSBL_B_n+1+ (L/2) * k is connected on the 4th memory capacitance post,
CSBL_A_n+2+ (L/2) * k is connected on the 5th memory capacitance post,
CSBL_B_n+2+ (L/2) * k is connected on the 6th memory capacitance post,
CSBL_A_n+ (L/2)-2+ (L/2) * k is connected on (L-3) memory capacitance post,
CSBL_B_n+ (L/2)-2+ (L/2) * k is connected on (L-2) memory capacitance post,
CSBL_A_n+ (L/2)-1+ (L/2) * k is connected on (L-1) memory capacitance post,
CSBL_B_n+ (L/2)-1+ (L/2) * k is connected on L memory capacitance post.
20. liquid crystal display as claimed in claim 19 is characterized in that, respectively by first to L memory capacitance post supply with first to the L that is horizontal scanning period oscillation period of L memory capacitance inverse voltage doubly.
21. liquid crystal display as claimed in claim 11 is characterized in that,
Described a large amount of memory capacitance post comprises the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post, the 7th memory capacitance post and the 8th memory capacitance post that is electrically insulated from each other
Be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of the first subpixel of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of the second subpixel, and if k is natural number or 0:
CSBL_A_n+8*k and CSBL_B_n+4+8*k are connected on the first memory capacitance post,
CSBL_B_n+8*k and CSBL_A_n+4+8*k are connected on the second memory capacitance post,
CSBL_A_n+1+8*k and CSBL_B_n+5+8*k are connected on the 3rd memory capacitance post,
CSBL_B_n+1+8*k and CSBL_A_n+5+8*k are connected on the 4th memory capacitance post,
CSBL_A_n+2+8*k and CSBL_B_n+6+8*k are connected on the 5th memory capacitance post,
CSBL_B_n+2+8*k and CSBL_A_n+6+8*k are connected on the 6th memory capacitance post,
CSBL_A_n+3+8*k and CSBL_B_n+7+8*k are connected on the 7th memory capacitance post,
CSBL_B_n+3+8*k and CSBL_A_n+7+8*k are connected on the 8th memory capacitance post.
22. liquid crystal display as claimed in claim 21 is characterized in that, is 8 times of horizontal scanning period the oscillation period of the first to the 8th memory capacitance inverse voltage of supplying with by the first to the 8th memory capacitance post respectively.
23. liquid crystal display as claimed in claim 11 is characterized in that,
Described a large amount of memory capacitance post comprise the first memory capacitance post of being electrically insulated from each other, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post ... (L-3) memory capacitance post, (L-2) memory capacitance post, (L-1) memory capacitance post and L memory capacitance post etc. are L memory capacitance post altogether
When 1/2 of the quantity L of the memory capacitance post of electrical isolation is even number, namely when L=8,12 ... Deng the time, be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of the first subpixel of the pixel that is arranged in the row n of the nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of the second subpixel, and if k is natural number or 0:
CSBL_A_n+L*k and CSBL_B_n+ (L/2)+L*k is connected on the first memory capacitance post,
CSBL_B_n+L*k and CSBL_A_n+ (L/2)+L*k is connected on the second memory capacitance post,
CSBL_A_n+1+L*k and CSBL_B_n+ (L/2)+1+L*k is connected on the 3rd memory capacitance post,
CSBL_B_n+1+L*k and CSBL_A_n+ (L/2)+1+L*k is connected on the 4th memory capacitance post,
CSBL_A_n+2+L*k and CSBL_B_n+ (L/2)+2+L*k is connected on the 5th memory capacitance post,
CSBL_B_n+2+L*k and CSBL_A_n+ (L/2)+2+L*k is connected on the 6th memory capacitance post,
CSBL_A_n+3+L*k and CSBL_B_n+ (L/2)+3+L*k is connected on the 7th memory capacitance post,
CSBL_B_n+3+L*k and CSBL_A_n+ (L/2)+3+L*k is connected on the 8th memory capacitance post,
CSBL_A_n+ (L/2)-2+L*k and CSBL_B_n+L-2+L*k are connected on (L-3) memory capacitance post,
CSBL_B_n+ (L/2)-2+L*k and CSBL_A_n+L-2+L*k are connected on (L-2) memory capacitance post,
CSBL_A_n+ (L/2)-1+L*k and CSBL_B_n+L-1+L*k are connected on (L-1) memory capacitance post,
And CSBL_B_n+ (L/2)-1+L*k and CSBL_A_n+L-1+L*k are connected on L memory capacitance post.
24. liquid crystal display as claimed in claim 23 is characterized in that, respectively by first to L memory capacitance post supply with first to the L that is horizontal scanning period oscillation period of L memory capacitance inverse voltage doubly.
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