CN101510034A - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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CN101510034A
CN101510034A CN 200910126411 CN200910126411A CN101510034A CN 101510034 A CN101510034 A CN 101510034A CN 200910126411 CN200910126411 CN 200910126411 CN 200910126411 A CN200910126411 A CN 200910126411A CN 101510034 A CN101510034 A CN 101510034A
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memory capacitance
csbl
subpixel
post
voltage
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CN101510034B (en
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下敷领文一
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Sharp Corp
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Sharp Corp
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Abstract

A liquid crystal display of the invention includes a plurality of pixels each of which has a liquid crystal layer and a plurality of electrodes for applying a voltage to the liquid crystal layer and which are arranged in a matrix of rows and columns, wherein: each of the plurality of pixels has a first sub-pixel and a second sub-pixel which can apply mutually different voltages to the liquid crystal layer, where the first sub-pixel has a higher brightness than the second sub-pixel in certain gradations; the first sub-pixel and the second sub-pixel each has: a liquid crystal capacitor formed by a counter electrode and a sub-pixel electrode opposing the counter electrode via the liquid crystal layer, and a storage capacitor formed by a storage capacitor electrode connected electrically to the sub-pixel electrode, an insulating layer, and a storage capacitor counter electrode opposing the storage capacitor electrode via the insulating layer; the counter electrode is a single electrode shared by the first sub-pixel and the second sub-pixel, and the storage capacitor counter electrodes of the first sub-pixel and the second sub-pixel are electrically independent of each other; and the storage capacitor counter electrode of the first sub-pixel in any of the plurality of pixels and the storage capacitor counter electrode of the second sub-pixel of a pixel adjacent to any of the pixels in the column direction are electrically independent of each other.

Description

LCD
The application is to be on Dec 3rd, 2004 applying date, and application number is 200410099783X, and what " LCD " by name applied for divides an application.
Technical field
The present invention relates to a kind of structure and/or driving method that can reduce the view angle dependency of γ characteristic in the LCD.
Background technology
LCD is a kind of superperformance flat-panel monitor of (comprising high resolving power, less thickness, lighter weight and lower power consumption) that has.Along with the raising of display performance and output and the price advantage of comparing with other types of display, its market share is also in rapid expansion.
Usually the liquid crystal molecule that the conventional twisted nematic type of using has positive dielectric anisotropy to (TN) LCD, liquid crystal molecule with its major axis orientation approximate be parallel to substrate surface and reverse 90 ° mode along the thickness direction of liquid crystal layer be distributed in up and down between the substrate.When liquid crystal layer was applied voltage, liquid crystal molecule began to be parallel to electric field, discharged twisted arrangement.The TN LCD utilizes the change of the rotary polarization that the orientation change of the liquid crystal molecule that voltage causes causes to control light transmission capacity.
The TN LCD allows very wide manufacturing tolerance limit and high output.On the other hand, it also has the problem of display performance, especially viewing angle characteristic.Specifically, when looking side ways the display surface of TN LCD, show that contrast descends quite severely.Therefore, even clear image ground presents from black to white a plurality of gray scales when the dead ahead is seen, but the luminance difference between the gray scale also seems extremely unintelligible when stravismus.In addition, also exist the part that when the dead ahead is seen, shows dark when stravismus, to show bright phenomenon.
In order to improve the viewing angle characteristic of TN LCD, recently some LCD have been developed, comprise that the coplane described among the Japanese publication JP63-21907 switches (IPS) type LCD, Japan and treats that multidomain homeotropic alignment (MVA) type LCD, the Japan described in the publication treat that the little box of axial symmetry (ASM) escope described among the publication JP10-186330 and Japan treat the LCD of describing among the publication JP2002-55343.
Adopt the LCD of above-mentioned arbitrary novel pattern (wide field-of-view mode) to solve the particular problem of viewing angle characteristic.Especially they are less than contrast that shows when looking side ways the display surface of TN LCD or the remarkable problem that descends of display gray scale.
Under the improved situation of the display quality of LCD, face the new problem of viewing angle characteristic again, i.e. the view angle dependency of γ characteristic this means to have the γ property difference when watching display and stravismus display from the dead ahead.Just go wrong in displayed image (for example photo) or when showing television broadcasting etc. like this.
The view angle dependency of γ characteristic ratio in MVA pattern and ASM pattern is more outstanding in the IPS pattern.On the other hand, more be difficult to the making of high yield ground has higher contrast when the dead ahead is seen IPS plate than MVA or ASM plate.Thereby hope reduces the view angle dependency of the γ characteristic of MVA pattern or ASM pattern.
Produced the present invention in view of the above problems.Fundamental purpose of the present invention is to provide a kind of LCD with the γ characteristic view angle dependency that reduces.
Summary of the invention
To achieve these goals, a first aspect of the present invention provides a kind of LCD of normal black pattern, it comprises a large amount of pixels, each pixel has liquid crystal layer and is used for applying a large amount of electrodes of voltage to liquid crystal layer, it is characterized in that: each of a large amount of pixels comprises first subpixel and second subpixel that can apply mutually different voltage to liquid crystal layer separately; And (wherein gk and gn are not less than zero integer when the gray scale gk of 0≤gk≤gn is satisfied in each demonstration of a large amount of pixels, and the higher value of gk is corresponding to higher brightness), if suppose Δ V12 (gk)=V1 (gk)-V2 (gk), then in the scope of 0＜gk≤n-1, satisfy relationship delta V12 (gk) at least〉0V and Δ V12 (gk)〉Δ V12 (gk+1), wherein, V1 (gk) and V2 (gk) are the r.m.s. voltage that is applied to the liquid crystal layer of first subpixel and second subpixel respectively.By the way, " pixel " herein represented the minimum display unit on the LCD, and under the situation of color monitor, it is corresponding to showing single color (typically being R, G or B) " picture dot (or point) " of planting.
LCD can be constructed like this: each in a large amount of pixels comprises the 3rd subpixel that can apply the voltage that is different from first subpixel and second subpixel to its liquid crystal layer; With as each display gray scale gk of a large amount of pixels, during and Δ V13 (gk)=V1 (gk)-V3 (gk),, then satisfy and concern 0V＜Δ V13 (gk)＜Δ V12 (gk) if the r.m.s. voltage that applies to the liquid crystal layer of the 3rd subpixel is V3 (gk).
The r.m.s. voltage that preferably is applied to liquid crystal layer satisfies relationship delta V12 (gk) 〉=Δ V12 (gk+1) at least in the scope of 0＜gk≤n-1.
Preferably when each pixel has the 3rd subpixel, in the scope of 0＜gk≤n-1, satisfy relationship delta V12 (gk) 〉=Δ V12 (gk+1) and Δ V13 (gk) 〉=Δ V13 (gk+1) at least.
In a preferred embodiment, first subpixel and second subpixel each comprise: by counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode; And by the memory capacitance that is electrically connected to the subpixel electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with storage capacitor electrode; And counter electrode is the single electrode of sharing with first subpixel and second subpixel, and the memory capacitance counter electrode of first subpixel and second subpixel is electrically insulated from each other.Typically, counter electrode is arranged in the relative substrate (being called " public electrode " sometimes), but in the IPS pattern, counter electrode is arranged in the substrate identical with the subpixel electrode.By the way, " through the liquid crystal layer counter electrode relative with the subpixel electrode " needn't be relative every the thickness of liquid crystal layer with the subpixel electrode.In the IPS LCD, it is placed in the liquid crystal layer relative every liquid crystal layer with the subpixel electrode.
In a preferred embodiment, LCD comprises that two are respectively the on-off elements that first subpixel and second subpixel are provided with, and it is characterized in that two on-off elements open and close by the scanning-line signal voltage of supplying with the common scanning line; When two on-off elements were opened, shows signal voltage was applied on each subpixel electrode and storage capacitor electrode of first subpixel and second subpixel from common signal line; After two on-off elements were closed, the voltage of each memory capacitance counter electrode of first subpixel and second subpixel changed; And the variable quantity difference between first subpixel and second subpixel that limits by the size and Orientation that changes.Herein not only about size (absolute value), and about the variable quantity of direction definition memory capacitance counter electrode.For example, the absolute value of the voltage variety of the memory capacitance counter electrode of first subpixel and second subpixel equates, opposite in sign.In brief, if the voltage of one of them memory capacitance counter electrode raises and the voltage decline of another memory capacitance counter electrode after on-off element disconnects, then the absolute value of Bian Huaing can equate.
Preferred liquid crystal layer is the liquid crystal layer of homeotropic alignment, and comprise have negative dielectric anisotropic row mutually to liquid crystal material.
Each liquid crystal layer of preferred first subpixel and second subpixel is included in four the about 90 ° farmlands that are separated by on the azimuth direction, and liquid crystal molecule just tilts when applying voltage in four farmlands.
Preferred first subpixel and second subpixel are placed on the opposition side of common signal line; Each all has a large amount of protruding ribs to liquid crystal layer in counter electrode one side for first subpixel and second subpixel, and a large amount of ribs is included in the upwardly extending first rib of first party and approximately perpendicular to the upwardly extending second rib of the second party of first direction; And first subpixel and second subpixel in each first rib and second rib be symmetrical arranged with respect to the center line that is parallel to the common scanning line, and first and second subpixel one of in the distribution of first rib and second rib with respect to other subpixel in being distributed symmetrically of first rib and second rib.
Preferably the center line that is parallel to the common scanning line in each in first subpixel and second subpixel is provided with to be approximately equal to half interval of array of scan lines spacing in first subpixel and second subpixel.
The area of preferred first subpixel is equal to or less than the area of second subpixel.When each of a large amount of pixels all had three or more subpixel, the subpixel area that preferably is applied in maximum r.m.s. voltage was not more than the area of other subpixel.
In LCD according to a further aspect of the invention: be applied to that the direction of an electric field on the liquid crystal layer reverses in a large amount of pixels between each vertical-scan period; And when showing intermediate gray-scale, in the situation of any row pixel, direction of an electric field is at line direction phase last week sex reversal, and in the situation of arbitrary row pixel, the direction of an electric field of each pixel reverses on the column direction.
According to an embodiment, in the situation of any row pixel, the direction of an electric field of each pixel counter-rotating on the line direction.
According to an embodiment, in the situation of any row pixel, the direction of an electric field of per two pixels counter-rotating on the line direction.
According to the LCD of an embodiment with normal black pattern work; It is characterized in that at least two subpixel comprise two subpixel SPa (p, q) and SPb (p, q); And (wherein gk and gn are not less than zero integer when the gray scale gk of 0≤gk≤gn is satisfied in each demonstration of a large amount of pixels, and bigger gk value is corresponding to higher brightness), if suppose Δ V12 (gk)=V1 (gk)-V2 (gk), then in the scope of 0＜gk≤n-1, satisfy relationship delta V12 (gk) at least〉0V and Δ V12 (gk) 〉=Δ V12 (gk+1), wherein, V1 (gk) and V2 (gk) are the r.m.s. voltage that is applied to respectively on the liquid crystal layer of first subpixel and second subpixel.
According to an embodiment, in the scope of 0＜gk≤n-1, satisfy relationship delta V12 (gk) 〉=Δ V12 (gk+1) at least.
According to an embodiment, SPa (p, q) and SPb (p, q) each comprises: by counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode, with by the storage capacitor electrode that is electrically connected to the subpixel electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with memory capacitance; And counter electrode be SPa (p, q) and SPb (p, q) shared single electrode, SPa (p, q) and SPb (p, memory capacitance counter electrode q) is electrically insulated from each other.
According to an embodiment, LCD comprise be respectively SPa (p, q) and SPb (p, q) two on-off elements of She Zhiing is characterized in that these two on-off elements open and close by the scanning-line signal voltage of supplying with the common scanning line; When these two on-off elements are opened, shows signal voltage from common signal line be applied to SPa (p, q) and SPb (p is on q) each subpixel electrode and storage capacitor electrode; After these two on-off elements are closed, SPa (P, q) and SPb (p, the voltage of each memory capacitance counter electrode q) just change; And the variable quantity that limits by the size and Orientation that changes SPa (p, q) and SPb (p, q) between difference.Specifically, when these two on-off elements are opened, voltage just is applied on each memory capacitance counter electrode of VSpa (on) and VSpb (on), thereby make when these two on-off elements disconnect, the electromotive force of each memory capacitance counter electrode will change, for example become VSpa (off) and VSpb (off) from VSpa (on) and VSpb (on) respectively, and each variable quantity " VSpa (off)-VSpa (on) " and " VSpb (off)-VSpb (on) " are with different.
According to an embodiment, SPa (p, q) and SPb (p, q) change in voltage of memory capacitance counter electrode equates on amount, and is opposite on the direction.
According to an embodiment, SPa (p, q) and SPb (p, the voltage of memory capacitance counter electrode q) is the oscillating voltage that 180 ° of phase differential are arranged each other.Oscillating voltage can be square wave, sine wave or triangular wave.
According to an embodiment, SPa (p, q) and SPb (p, each has the cycle that is approximately equal to a horizontal scanning period oscillating voltage of memory capacitance counter electrode q).
According to an embodiment, SPa (p, q) and SPb (p, each has the cycle that is shorter than a horizontal scanning period oscillating voltage of memory capacitance counter electrode q).
According to an embodiment, if average in the cycle, and SPa (p, q) and SPb (p, the oscillating voltage of memory capacitance counter electrode q) approximately equal in any horizontal scanning period.
According to an embodiment, be half of a horizontal scanning period oscillation period.
According to an embodiment, oscillating voltage is that dutycycle is 1: 1 a square wave.
According to an embodiment, SPa (p, q) and SPb (p q) has different areas, little area belong to and have the SPa that is applied to the big r.m.s. voltage on its liquid crystal layer (p, q) or SPb (p, q).
According to an embodiment, SPa (p, q) and SPb (p, area q) is in fact equal.
A third aspect of the present invention provides a kind of LCD, it comprises: a large amount of pixels, each pixel has liquid crystal layer and is used for applying the electrode of voltage to liquid crystal layer in a large number, electrode is the ranks matrix distribution, it is characterized in that: each of a large amount of pixels has first subpixel and second subpixel that can apply mutually different voltage to liquid crystal layer, is determining that first subpixel has the brightness that is higher than second subpixel under the gray scale; Each comprises first subpixel and second subpixel: by counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode, with by the storage capacitor electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with storage capacitor electrode that are electrically connected on the subpixel electrode; Counter electrode is the single electrode of being shared by first subpixel and second subpixel, and the memory capacitance counter electrode of first subpixel and second subpixel is electrically insulated from each other; The memory capacitance counter electrode of second subpixel of the pixel that any pixel is adjacent on the memory capacitance counter electrode of first subpixel of a large amount of pixels in any and the column direction is electrically insulated from each other.
According to an embodiment, first subpixel of any pixel be scattered in column direction on second subpixel of adjacent image point of any pixel adjacent.
According to an embodiment, in each of a plurality of pixels, first subpixel is scattered on column direction adjacent with second subpixel.
According to an embodiment, LCD comprises a large amount of memory capacitance posts that are electrically insulated from each other, and it is characterized in that each memory capacitance post is electrically connected on any memory capacitance counter electrode of first subpixel in a large amount of pixels and second subpixel through storage capacitance line.
According to an embodiment, the quantity of the memory capacitance post that is electrically insulated from each other in a large amount of memory capacitance posts (trunk) is L, and the memory capacitance inverse voltage of being supplied with by each memory capacitance post is an oscillating voltage, and be L times of horizontal scanning period oscillation period.
According to an embodiment, a large amount of memory capacitance posts that are electrically insulated from each other are, form the even number memory capacitance post of paired memory capacitance post, supply with the memory capacitance inverse voltage of the vibration that 180 ° of phase differential are arranged each other.
According to an embodiment, the quantity of the memory capacitance post that is electrically insulated from each other is bigger 8 times than the share of dividing a horizontal scanning period acquisition by the CR time constant, and wherein the CR time constant is near the maximum load impedance of storage capacitance line.
According to an embodiment, the quantity of the memory capacitance post that is electrically insulated from each other is bigger 8 times than the share of dividing a horizontal scanning period acquisition by the CR time constant, and is even number, and wherein the CR time constant is near the maximum load impedance of storage capacitance line.
According to an embodiment, a large amount of memory capacitance posts comprises the first memory capacitance post and the second memory capacitance post that is electrically insulated from each other; And if the storage capacitance line of memory capacitance counter electrode that is connected to first subpixel of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form is made as CSBL_A_n, if the storage capacitance line that is connected on the memory capacitance counter electrode of second subpixel is made as CSBL_B_n, if and k is natural number (comprising 0), then CSBL_A_n+k just is connected on the first memory capacitance post, and CSBL_B_n just is connected on the second memory capacitance post.
According to an embodiment, are twices of horizontal scanning period the oscillation period of the first and second memory capacitance inverse voltages of supplying with by the first and second memory capacitance posts respectively.
According to an embodiment, the second memory capacitance inverse voltage is than the phase differential of a horizontal scanning period of first memory capacitance inverse voltage hysteresis.
According to an embodiment, LCD comprises that two are respectively the on-off elements that first subpixel and second subpixel are provided with, and it is characterized in that these two on-off elements open and close by the scanning-line signal voltage of supplying with the common scanning line; When these two on-off elements were opened, shows signal voltage was applied on the electrode of subpixel separately and storage capacitor electrode of first subpixel and second subpixel from common signal line; After these two on-off elements were closed, the voltage of the counter electrode of memory capacitance separately of first subpixel and second subpixel just changed; And if Td represents that these two on-off elements close the back first memory capacitance inverse voltage and change the required time in the very first time, then Td greater than 0 horizontal scanning period less than a horizontal scanning period.
According to an embodiment, Td is approximately equal to 0.5 times of horizontal scanning period.
According to an embodiment, a large amount of memory capacitance posts comprise the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post and the 4th memory capacitance post that is electrically insulated from each other; And if the storage capacitance line that is connected to the first subpixel memory capacitance counter electrode of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form is made as CSBL_A_n, be made as CSBL_B_n if be connected to the storage capacitance line of the second subpixel memory capacitance counter electrode, if and k is natural number (comprising 0), then CSBL_A_n+4*k and CSBL_B_n+2+4*k just are connected on the first memory capacitance post, CSBL_B_n+4*k and CSBL_A_n+2+4*k just are connected on the second memory capacitance post, CSBL_A_n+1+4*k and CSBL_B_n+3+4*k just are connected on the 3rd memory capacitance post, and CSBL_B_n+1+4*k and CSBL_A_n+3+4*k just are connected on the 4th memory capacitance post.
According to an embodiment, be 4 times of horizontal scanning period respectively the oscillation period of the first to fourth memory capacitance inverse voltage of supplying with by first to fourth memory capacitance post.
According to an embodiment, the second memory capacitance inverse voltage is than the phase differential of stagnant latter two horizontal scanning period of the first memory capacitance inverse voltage, the 3rd memory capacitance inverse voltage is than the phase differential of three horizontal scanning periods of first memory capacitance inverse voltage hysteresis, and the 4th memory capacitance inverse voltage is than the phase differential of a horizontal scanning period of first memory capacitance inverse voltage hysteresis.
According to an embodiment, LCD comprises that two are respectively the on-off elements that first subpixel and second subpixel are provided with, and it is characterized in that these two on-off elements open and close by the scanning-line signal voltage of supplying with the common scanning line; When these two on-off elements were opened, shows signal voltage was applied on each subpixel electrode and storage capacitor electrode of first subpixel and second subpixel from common signal line; When two on-off elements were closed, the voltage of each memory capacitance counter electrode of first subpixel and second subpixel changed; And if Td represents that two on-off elements close the back first memory capacitance inverse voltage and change the required time in the very first time, then Td greater than 0 horizontal scanning period less than two horizontal scanning periods.
According to an embodiment, Td is approximately equal to a horizontal scanning period.
According to an embodiment, a large amount of memory capacitance posts comprise the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post and the 6th memory capacitance post that is electrically insulated from each other; And if the storage capacitance line that is connected to the first subpixel memory capacitance counter electrode of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form is made as CSBL_A_n, be made as CSBL_B_n if be connected to the storage capacitance line of the second subpixel memory capacitance counter electrode, if and k is natural number (comprising 0), then CSBL_A_n+3*k just is connected on the first memory capacitance post, CSBL_B_n+3*k just is connected on the second memory capacitance post, CSBL_A_n+1+3*k just is connected on the 3rd memory capacitance post, CSBL_B_n+1+3*k just is connected on the 4th memory capacitance post, CSBL_A_n+2+3*k just is connected on the 5th memory capacitance post, and CSBL_B_n+2+3*k just is connected on the 6th memory capacitance post.
According to an embodiment, be 6 times of horizontal scanning period respectively the oscillation period of first to the 6th memory capacitance inverse voltage of supplying with by first to the 6th memory capacitance post.
According to an embodiment, a large amount of memory capacitance posts comprise the first memory capacitance post that is electrically insulated from each other, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post ... (L-3) memory capacitance post, (L-2) memory capacitance post, (L-1) memory capacitance post and L memory capacitance post etc. are L memory capacitance post altogether; And when 1/2 of the quantity L of the memory capacitance post of electrical isolation is odd number, promptly work as L=2,6,10, Deng the time, be made as CSBL_A_n if be connected to the storage capacitance line of the first subpixel memory capacitance counter electrode of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the second subpixel memory capacitance counter electrode, if and k is natural number (comprising 0), then CSBL_A_n+ (L/2) * k just is connected on the first memory capacitance post, CSBL_B_n+ (L/2) * k just is connected on the second memory capacitance post, CSBL_A_n+1+ (L/2) * k just is connected on the 3rd memory capacitance post, CSBL_B_n+1+ (L/2) * k just is connected on the 4th memory capacitance post, CSBL_A_n+2+ (L/2) * k just is connected on the 5th memory capacitance post, CSBL_B_n+2+ (L/2) * k just is connected on the 6th memory capacitance post, CSBL_A_n+ (L/2)-2+ (L/2) * k just is connected on (L-3) memory capacitance post, CSBL_B_n+ (L/2)-2+ (L/2) * k just is connected on (L-2) memory capacitance post, CSBL_A_n+ (L/2)-1+ (L/2) * k just is connected on (L-1) memory capacitance post, and CSBL_B_n+ (L/2)-1+ (L/2) * k just is connected on the L memory capacitance post.
According to an embodiment, respectively by first to L memory capacitance post supply with first to the L that is horizontal scanning period oscillation period of L memory capacitance inverse voltage doubly.
According to an embodiment, a large amount of memory capacitance posts comprise the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post, the 7th memory capacitance post and the 8th memory capacitance post that is electrically insulated from each other; And if the storage capacitance line that is connected to the first subpixel memory capacitance counter electrode of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form is made as CSBL_A_n, be made as CSBL_B_n if be connected to the storage capacitance line of the second subpixel memory capacitance counter electrode, if and k is natural number (comprising 0), then CSBL_A_n+8*k and CSBL_B_n+4+8*k just are connected on the first memory capacitance post, CSBL_B_n+8*k and CSBL_A_n+4+8*k just are connected on the second memory capacitance post, CSBL_A_n+1+8*k and CSBL_B_n+5+8*k just are connected on the 3rd memory capacitance post, CSBL_B_n+1+8*k and CSBL_A_n+5+8*k just are connected on the 4th memory capacitance post, CSBL_A_n+2+8*k and CSBL_B_n+6+8*k just are connected on the 5th memory capacitance post, CSBL_B_n+2+8*k and CSBL_A_n+6+8*k just are connected on the 6th memory capacitance post, CSBL_A_n+3+8*k and CSBL_B_n+7+8*k just are connected on the 7th memory capacitance post, and CSBL_B_n+3+8*k and CSBL_A_n+7+8*k just are connected on the 8th memory capacitance post.
According to an embodiment, be 8 times of horizontal scanning period respectively the oscillation period of first to the 8th memory capacitance inverse voltage of supplying with by first to the 8th memory capacitance post.
According to an embodiment, a large amount of memory capacitance posts comprise the first memory capacitance post that is electrically insulated from each other, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post, the 7th memory capacitance post, the 8th memory capacitance post ... (L-3) memory capacitance post, (L-2) memory capacitance post, (L-1) memory capacitance post and L memory capacitance post etc. are L memory capacitance post altogether; And when 1/2 of the quantity L of the memory capacitance post of electrical isolation is even number, promptly work as L=4,8,12, Deng the time, if be connected to be arranged in the ranks matrix arbitrarily the storage capacitance line of the first subpixel memory capacitance counter electrode of the pixel of the n of the row nominated bank infall that forms of row and a large amount of pixels be made as CSBL_A_n, be made as CSBL_B_n if be connected to the storage capacitance line of the second subpixel memory capacitance counter electrode, if and k is natural number (comprising 0), then CSBL_A_n+L*k and CSBL_B_n+ (L/2)+L*k just is connected on the first memory capacitance post, CSBL_B_n+L*k and CSBL_A_n+ (L/2)+L*k just is connected on the second memory capacitance post, CSBL_A_n+1+L*k and CSBL_B-n+ (L/2)+1+L*k just is connected on the 3rd memory capacitance post, CSBL_B_n+1+L*k and CSBL_A_n+ (L/2)+1+L*k just is connected on the 4th memory capacitance post, CSBL_A_n+2+L*k and CSBL_B_n+ (L/2)+2+L*k just is connected on the 5th memory capacitance post, CSBL_B_n+2+L*k and CSBL_A_n+ (L/2)+2+L*k just is connected to the 6th memory capacitance post, CSBL_A_n+3+L*k and CSBL_B_n+ (L/2)+3+L*k just is connected on the 7th memory capacitance post, CSBL_B_n+3+L*k and CSBL_A_n+ (L/2)+3+L*k just is connected on the 8th memory capacitance post, CSBL_A_n+ (L/2)-2+L*k and CSBL_B_n+L-2+L*k just are connected on (L-3) memory capacitance post, CSBL_B_n+ (L/2)-2+L*k and CSBL_A_n+L-2+L*k just are connected on (L-2) memory capacitance post, CSBL_A_n+ (L/2)-1+L*k and CSBL_B_n+L-1+L*k just are connected on (L-1) memory capacitance post, and CSBL_B_n+ (L/2)-1+L*k and CSBL_A_n+L-1+L*k just are connected on the L memory capacitance post.
According to an embodiment, respectively by first to L memory capacitance post supply with first to the L that is horizontal scanning period oscillation period of L memory capacitance inverse voltage doubly.
A fourth aspect of the present invention provides a kind of LCD, it comprises a large amount of pixels, each pixel has liquid crystal layer and is used for liquid crystal layer is applied a large amount of electrodes with the ranks matrix distribution of voltage, and each that it is characterized in that a large amount of pixels has first subpixel and second subpixel that can apply mutually different voltage to liquid crystal layer; This is in determines that first subpixel has the brightness that is higher than second subpixel under the gray scale; Each comprises first subpixel and second subpixel: by counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode, with by the storage capacitor electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative with storage capacitor electrode that are electrically connected on the subpixel electrode; Counter electrode is the single electrode of being shared by first subpixel and second subpixel, and the memory capacitance counter electrode of first subpixel and second subpixel is electrically insulated from each other; LCD also comprises the memory capacitance post that is electrically insulated from each other in a large number, each memory capacitance post is electrically connected on any memory capacitance counter electrode of first subpixel and second subpixel in a large amount of pixels through storage capacitance line, and the memory capacitance counter electrode of first subpixel of one of two adjacent image points is connected on the equipotential storage capacitance line of memory capacitance counter electrode of second subpixel with another on the column direction; And the quantity of the memory capacitance post that is electrically insulated from each other in a large amount of memory capacitance posts is L or bigger (L is an even number), the memory capacitance inverse voltage of being supplied with by each memory capacitance post is an oscillating voltage, and be 2*K*L (K is a positive integer) times of horizontal scanning period oscillation period.
According to an embodiment, be made as CSBL_ (n) A if be connected to the storage capacitance line of memory capacitance counter electrode of first subpixel of the pixel of the row nominated bank year infall that the pixel that is arranged in any row and a large amount of ranks matrix distribution forms, the storage capacitance line that is connected to the memory capacitance counter electrode of second subpixel is made as CSBL_ (n) B, and the CS bus that is connected to the memory capacitance post of L electrical isolation satisfies following relationship:
CSBL_(p+2*(1-1))B，(p+2*(1-1))+1)A，
CSBL_(p+2*(2-1))B，(p+2*(2-1))+1)A，
CSBL_(p+2*(3-1))B，(p+2*(3-1))+1)A，
…
CSBL_ (p+2* (K-1)) B, (p+2* (K-1))+1) A and
CSBL_(p+2*(1-1)+K*L+1)B，(p+2*(1-1))+K*L+2)A，
CSBL_(p+2*(2-1)+K*L+1)B，(p+2*(2-1))+K*L+2)A，
CSBL_(p+2*(3-1)+K*L+1)B，(p+2*(3-1))+K*L+2)A，
…
CSBL_(p+2*(K-1)+K*L+1)B，(p+2*(3-1))+K*L+2)A，
Or
CSBL_(p+2*(1-1)+1)B，(p+2*(1-1)+2)A，
CSBL_(p+2*(2-1)+1)B，(p+2*(2-1)+2)A，
CSBL_(p+2*(3-1)+1)B，(p+2*(3-1)+2)A，
…
CSBL_(p+2*(K-1)+1)B，(p+2*(K-1)+2)A，
With
CSBL_(p+2*(1-1)+K*L)B，(p+2*(1-1)+K*L+1)A，
CSBL_(p+2*(2-1)+K*L)B，(p+2*(2-1)+K*L+1)A，
CSBL_(p+2*(3-1)+K*L)B，(p+2*(3-1)+K*L+1)A，
…
CSBL_(p+2*(K-1)+K*L)B，(p+2*(K-1)+K*L+1)A，
Herein, p=1,3,5 etc., or p=0,2,4 etc.
According to an embodiment, K is 1 or 2, and L is any one in 6,8,10 and 12.
According to an embodiment, preferred storage capacitance line places on the column direction between two neighboring pixels.
According to an embodiment, LCD comprises: two on-off elements that are respectively first subpixel and the configuration of second subpixel; Be connected to two sweep traces on the on-off element jointly, it is characterized in that the common scanning line places between first subpixel and second subpixel.
According to an embodiment, a large amount of memory capacitance posts are supplied with the memory capacitance inverse voltage for forming the even number memory capacitance post of paired memory capacitance post, and the vibration of inverse voltage has 180 ° phase differential each other.
According to an embodiment, in any two adjacent image points of column direction, the memory capacitance counter electrode of the memory capacitance counter electrode of first subpixel of a pixel and second subpixel of another pixel is connected on the common storage electric capacity line
According to an embodiment, the dutycycle of memory capacitance inverse voltage is 1:1.
According to an embodiment, first subpixel in the arbitrary pixel be arranged to column direction on second subpixel of arbitrary pixel neighboring pixels adjacent, and in each of a large amount of pixels, first subpixel be arranged to column direction on second subpixel adjacent.
According to an embodiment, first subpixel and the second subpixel area approximation equate.
According to an embodiment, the area of second subpixel is greater than the area of first subpixel.
A first aspect of the present invention can reduce the view angle dependency of γ characteristic in the LCD.Particularly, can there be the LCD at wide visual angle such as the γ characteristic of MAV or ASV LCD to realize high display quality by improvement.
A second aspect of the present invention can reduce by the flicker that exchanges on electrically driven (operated) LCD.Reduce flicker by merging a first aspect of the present invention and second aspect, can providing a kind of, improved the viewing angle characteristic of γ characteristic and the LCD of high display quality.
A third aspect of the present invention can increase the oscillation period of the voltage (oscillating voltage) that is applied to memory capacitance counter electrode in the LCD according to second aspect.Thereby, a kind of such LCD can be provided, and this display is suitable for by a pixel being divided into two or more subpixel and with different luminance levels subpixel illumination being improved greatly or the viewing angle characteristic of the LCD of high-resolution.
A fourth aspect of the present invention can also utilize common storage electric capacity line (CS bus) that the subpixel of adjacent image point on the column direction is supplied with oscillating voltage except the same oscillation period that can increase the voltage (oscillating voltage) that is applied to the memory capacitance counter electrode with the third aspect.Therefore, if storage capacitance line places between the adjacent image point on the column direction, also can be used as black matrix" (BM).Thereby fourth aspect has the advantage that can increase the pixel aperture ratio, and it can save, and the black matrix" that provides separately is provided in the LCD situation of the third aspect, and has reduced the quantity of CS bus than the third aspect.
Description of drawings
Fig. 1 is the pixel structure synoptic diagram according to the LCD 100 of first aspect present invention embodiment;
Fig. 2 A～2C is the structural representation according to the LCD of the embodiment of the invention;
Fig. 3 A～3C is the structural representation of the conventional LCD 100 ' of expression;
Fig. 4 A～4C is the display characteristic sketch of MVA LCD, and wherein Fig. 4 A is transmissivity and the relation curve that applies voltage, and Fig. 4 B is the perspective rate figure about Fig. 4 A after the transmissivity normalization under the white mode, and Fig. 4 C is the sketch of expression γ characteristic;
Fig. 5 A～5D is the sketch of the state A～D of the expression voltage that is applied to the liquid crystal layer by dividing the subpixel that pixel obtains;
Fig. 6 A～6B is illustrated in the γ family curve that voltage status A shown in Figure 5～D obtains down, and wherein Fig. 6 A represents the visual angle γ characteristic on 60 ° on right side, and Fig. 6 B is the visual angle γ characteristic of 60 ° of expression upper right sides;
Fig. 7 is illustrated in white mode transmissivity (facing) curve that voltage status A～D obtains down;
Fig. 8 A～8B be expression according to the embodiment of the invention the area between the subpixel under the voltage status C than with the curve of γ characteristic, wherein Fig. 8 A represents the visual angle γ characteristic on 60 ° on right side, Fig. 8 B is the visual angle γ characteristic of 60 ° of expression upper right sides;
Fig. 9 is at the relation curve between white mode transmissivity (facing) and the subpixel area ratio under the voltage status C according to the embodiment of the invention;
Figure 10 A～10B is the curve of expression according to embodiment of the invention γ characteristic of subpixel under voltage status B, and wherein Figure 10 A represents the visual angle γ characteristic on 60 ° on right side, and Figure 10 B is the visual angle γ characteristic of 60 ° of expression upper right sides;
Figure 11 is that expression is according to the relation curve of the embodiment of the invention between white mode transmissivity under the voltage status B and subpixel number;
Figure 12 is the pixel structure synoptic diagram of LCD 200 according to another embodiment of the present invention;
Figure 13 is the equivalent circuit schematic of the pixel of expression LCD 200;
Figure 14 is the sketch that is used to drive the various voltage waveforms (a)-(f) of LCD 200;
Figure 15 is the sketch that concerns that is applied in the LCD 200 between the voltage of liquid crystal layer of subpixel;
Figure 16 A～16B is the γ characteristic sketch of expression LCD 200, and wherein Figure 16 A represents the visual angle γ characteristic on 60 ° on right side, and Figure 16 B is the visual angle γ characteristic of 60 ° of expression upper right sides;
Figure 17 is the pixel distribution schematic diagram of expression according to the LCD of second aspect present invention;
Figure 18 is the sketch that is used to drive various voltages (signal) waveforms (a)-(j) of the LCD with structure shown in Figure 17;
Figure 19 represents the pixel distribution schematic diagram of LCD according to another embodiment of the present invention;
Figure 20 is the sketch that is used to drive various voltages (signal) waveforms (a)-(j) of the LCD with structure shown in Figure 19;
Figure 21 A is the pixel distribution schematic diagram of LCD according to another embodiment of the present invention, and Figure 21 B is the synoptic diagram of the layout of expression storage capacitance line and storage capacitor electrode;
Figure 22 is the equivalent circuit schematic according to the specific region of the LCD of second aspect present invention;
Figure 23 A is expression is applied to the oscillating voltage of CS bus with regard to the voltage waveform of grid bus oscillation period and a phase place sketch, also represents the voltage of the subpixel electrode of LCD shown in Figure 22;
Figure 23 B is the oscillating voltage of CS bus is supplied with in expression with regard to the voltage waveform of grid bus oscillation period and a phase place, and the voltage (voltage that is applied to liquid crystal layer has the polarity opposite with Figure 23 A) of the subpixel in the LCD shown in expression Figure 22
Figure 24 A is the driving condition synoptic diagram (adopting the voltage shown in Figure 23 A herein) of LCD shown in expression Figure 22;
Figure 24 B is the driving condition synoptic diagram (adopting the voltage shown in Figure 23 B herein) of LCD shown in expression Figure 22;
To be expression be used for supplying with the structural representation of the oscillating voltage of LCD CS bus according to the embodiment of second aspect present invention to Figure 25 A, and Figure 25 B is the equivalent electrical circuit of expression near the LCD electrical load resistance;
Figure 26 represents that the subpixel electrode does not have the blunt nosed oscillating voltage waveform (a)～(e) of CS voltage waveform;
Figure 27 represents that the subpixel electrode is not corresponding to the blunt nosed oscillating voltage waveform (a)～(e) of the CS voltage waveform of " 0.2H " CR time constant;
Figure 28 is the relation curve of the oscillation period of the expression oscillating voltage mean value of calculating based on waveform in Figure 26 and 27 and effective value and CS bus voltage;
Figure 29 is the equivalent voltage synoptic diagram according to the LCD of third aspect present invention embodiment;
Figure 30 A is that the oscillation period and the phase place of the oscillating voltage of CS bus are supplied with in expression with regard to the voltage waveform of grid bus, and represents the voltage of the subpixel in the LCD shown in Figure 29;
Figure 30 B is the oscillating voltage of CS bus is supplied with in expression with regard to the voltage waveform of grid bus oscillation period and a phase place, and the voltage (voltage that is applied to liquid crystal layer has the polarity opposite with Figure 30 A) of the subpixel in the LCD shown in expression Figure 22
Figure 31 A is the driving condition sketch (adopting the voltage shown in Figure 30 A herein) of LCD shown in expression Figure 29;
Figure 31 B is the driving condition sketch (adopting the voltage shown in Figure 30 B herein) of LCD shown in expression Figure 29;
Figure 32 is the equivalent voltage synoptic diagram according to the LCD of third aspect present invention embodiment;
Figure 33 A is that the oscillation period and the phase place of the oscillating voltage of CS bus are supplied with in expression with regard to the voltage waveform of grid bus, and represents the voltage of the subpixel in the LCD shown in Figure 32;
Figure 33 B is the oscillating voltage of CS bus is supplied with in expression with regard to the voltage waveform of grid bus oscillation period and a phase place, and the voltage (voltage that is applied to liquid crystal layer has the polarity opposite with Figure 33 A) of the subpixel in the LCD shown in expression Figure 32;
Figure 34 A is the driving condition sketch (adopting the voltage shown in Figure 33 A herein) of LCD shown in expression Figure 32;
Figure 34 B is the driving condition sketch (adopting the voltage shown in Figure 33 B herein) of LCD shown in expression Figure 32;
Figure 35 A represents according to the profile synoptic diagram of black matrix" between CS bus and pixel in the LCD of third aspect present invention embodiment, and Figure 35 B is the total line profile of representing also as black matrix" between pixel in the LCD of fourth aspect present invention embodiment of CS;
Figure 36 A is the driving condition sketch of expression according to the LCD of fourth aspect present invention embodiment;
Figure 36 B is the driving condition sketch of expression according to the LCD of fourth aspect present invention embodiment, and the electric field that wherein is applied to liquid crystal layer is opposite with the direction of driving condition shown in Figure 33 A;
Figure 37 is matrix structure (the connection pattern of the CS bus) synoptic diagram of expression according to the LCD of fourth aspect present invention embodiment;
Figure 38 is the drive signal waveform synoptic diagram of expression LCD shown in Figure 37;
Figure 39 is matrix structure (the connection pattern of the CS bus) synoptic diagram of expression according to the LCD of another embodiment of fourth aspect present invention;
Figure 40 is the synoptic diagram of the drive signal waveform of expression LCD shown in Figure 39;
Figure 41 is matrix structure (the connection pattern of the CS bus) synoptic diagram of expression according to the LCD of another embodiment of fourth aspect present invention;
Figure 42 is the synoptic diagram of the drive signal waveform of expression LCD shown in Figure 41;
Figure 43 is matrix structure (the connection pattern of the CS bus) synoptic diagram of expression according to the LCD of another embodiment of fourth aspect present invention;
Figure 44 is the synoptic diagram of the drive signal waveform of expression LCD shown in Figure 43;
Figure 45 is matrix structure (the connection pattern of the CS bus) synoptic diagram of expression according to the LCD of another embodiment of fourth aspect present invention;
Figure 46 is the synoptic diagram of the drive signal waveform of expression LCD shown in Figure 45;
Figure 47 is matrix structure (the connection pattern of the CS bus) synoptic diagram of expression according to the LCD of another embodiment of fourth aspect present invention;
Figure 48 is the synoptic diagram of the drive signal waveform of expression LCD shown in Figure 47;
Figure 49 is matrix structure (the connection pattern of the CS bus) synoptic diagram of expression according to the LCD of another embodiment of fourth aspect present invention;
Figure 50 is the synoptic diagram of the drive signal waveform of expression LCD shown in Figure 49
Embodiment
The structure and the operation of the LCD among the first aspect present invention embodiment are described below with reference to accompanying drawing.
At first referring to Fig. 1,2A, 2B and 2C.Fig. 1 is the synoptic diagram of expression according to distribution of electrodes in the pixel of the LCD 100 of the embodiment of the invention.Fig. 2 A is the general structure synoptic diagram of LCD 100, and Fig. 2 B is the synoptic diagram of electrode structure in the pixel, and Fig. 2 C is along the sectional view of 2C-2C ' among Fig. 2 B.For the purpose of reference, Fig. 3 A, 3B and 3C represent distribution of electrodes in the pixel of conventional LCD 100 ', electrode structure respectively and along the sectional view of 3C-3C '.
LCD 100 according to present embodiment is deceived pattern work with normal, and comprises that a large amount of pixels, each pixel have liquid crystal layer and a large amount of electrodes that are used for liquid crystal layer is applied voltage.Though this sentences the TFT LCD is example, also can replace with other on-off element (as the MIM element).
LCD 100 has a large amount of pixels 10 with matrix distribution.Each of a large amount of pixels 10 has liquid crystal layer 13.In addition, pixel has pixel capacitors 18 and the counter electrode 17 of oneself, to apply voltage to liquid crystal layer 13.Typically, counter electrode 17 is single electrodes public to all pixels 10.
In the LCD 100 according to present embodiment, each of a large amount of pixels 10 has the first subpixel 10a and the second subpixel 10b that can apply mutually different voltage, as shown in Figure 1.
0 ≦ gk ≦ gn (herein when demonstration is satisfied, gk and gn are not less than zero integer, and bigger gk value is corresponding to higher brightness) gray scale the time, each of a large amount of pixels is to satisfy Δ V12 (gk) at least in the scope of 0＜gk≤n-1〉0V and Δ V12 (gk) " mode of Δ V12 (gk+1) drives, wherein, Δ V12 (gk)=V1 (gk)-V2 (gk) is r.m.s. voltage V2 (gk) poor that is applied to the r.m.s. voltage V1 (gk) of the first subpixel 10a liquid crystal layer and is applied to the liquid crystal layer of 10 ones of second subpixel.
The subpixel quantity that each pixel 10 has (being called the quantity that pixel is divided sometimes) is not limited to two.Each pixel 10 can also have the 3rd subpixel (not shown), and it is applied the voltage that is different from the first subpixel 10a and the second subpixel 10b.In this case, if pixel design becomes hypothesis Δ V13=V1 (gk)-V3 (gk), the r.m.s. voltage of V3 (gk) for the liquid crystal layer of the 3rd subpixel is applied herein, and Δ V13 (gk) then satisfies 0V＜Δ V13 (gk)＜Δ V12 (gk) for the r.m.s. voltage and r.m.s. voltage poor that imposes on the 3rd subpixel liquid crystal layer of the liquid crystal layer that imposes on first subpixel
The r.m.s. voltage that preferably is applied to the subpixel liquid crystal layer satisfies relationship delta V12 (gk) at least in the scope of 0＜gk≤n-1〉Δ V12 (gk+1).Thereby preferred grey level becomes high more, and the difference that is applied to the r.m.s. voltage of the first subpixel 10a and the second subpixel 10b liquid crystal layer becomes more little.In other words, preferably along with grey level's step-down (near black), the difference that is applied to the r.m.s. voltage of the first subpixel 10a and the second subpixel 10b liquid crystal layer becomes big more.In addition, if each pixel has the 3rd subpixel, then preferably in the scope of 0＜gk≤n-1, satisfy relationship delta V12 (gk) at least〉Δ V12 (gk+1) and Δ V13 (gk)〉Δ V13 (gk+1).
The area of the first subpixel 10a is equal to or less than the area of the second subpixel 10b.If each of a large amount of pixels has three or more subpixel, the area (being first subpixel in the case) that then preferably is applied in the subpixel of the highest r.m.s. voltage is not more than subpixel (the being second subpixel in the case) area that is applied in minimum r.m.s. voltage.Specifically, if each pixel 10 have a large amount of subpixel SP1, SP2 ... and SPn, and the r.m.s. voltage that is applied to liquid crystal layer be V1 (gk), V2 (gk) ... and Vn (gk), then preferably satisfy V1 (gk)〉V2 (gk) ... Vn (gk).In addition, if the area of subpixel be SSP1, SSP2 ... and SSPn, then preferably satisfy SSP1≤SSP2≤...≤SSPn.
If satisfy V1 (gk) for all gray scales (that is, in the scope of 0＜gk≤n-1) at least except the highest gray scale and minimum gray scale〉V2 (gk)〉... Vn (gk), then can realize the present invention.But, also can implement a kind of structure that all gray scales (that is, in the scope of 0≤gk≤n) is satisfied this relational expression.
In this way,, and the liquid crystal layer of subpixel applied different voltage, then obtain the mixing of different γ characteristics if each pixel is divided into a large amount of subpixel, thereby, the view angle dependency of γ characteristic can be reduced.In addition, because the r.m.s. voltage difference of low gray scale is provided with greatlyyer, so reduce greatly at normal view angle dependency of deceiving black side (low brightness levels) the γ characteristic of pattern.This is very effective aspect the raising display quality.
Can apply r.m.s. voltage in the mode that satisfies the above-mentioned relation formula to the liquid crystal layer of subpixel 10a and 10b with different structures.
For example, LCD 100 can constitute as shown in Figure 1.Specifically, in conventional LCD 100 ', pixel 10 only has a pixel capacitors 18 to be connected on the signal wire 14 through TFT16, and LCD 100 has two sub-pixel capacitors 18a to be connected on different the signal wire 14a and 14b through TFT16a and 16b respectively with 18b.
Because subpixel 10a and 10b form a pixel 10,, and open and close by the common scanning signal so the grid of TFT16a and 16b is connected on the common scanning line (gate line) 12.Signal wire (source bus line) 14a and 14b are supplied with the signal voltage (grayscale voltage) that satisfies above-mentioned relation.The gate configuration of preferred TFT16a and 16b becomes public grid.
Perhaps, each comprises by the storage capacitor electrode that is electrically connected to the subpixel electrode in first subpixel and second subpixel, in the structure of insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative (back description) with storage capacitor electrode, first subpixel that is electrically insulated from each other and the memory capacitance counter electrode of second subpixel preferably are provided, and by changing the r.m.s. voltage that the voltage (being called the memory capacitance counter electrode voltage) of supplying with the memory capacitance counter electrode changes the r.m.s. voltage that is applied to the first subpixel liquid crystal layer and is applied to the second subpixel liquid crystal layer.By value of regulating memory capacitance and the voltage swing of supplying with the memory capacitance counter electrode, can control the size of the r.m.s. voltage that is applied to the subpixel liquid crystal layer.
In this structure,,, and can supply with identical signal voltage to them so TFT three 16a and 16b can be connected on the common signal line because do not need antithetical phrase pixel capacitors 18a to apply different signal voltages with 18b.Therefore, the quantity of signal wire is identical under the situation of conventional LCD 100 ' shown in Figure 3, and can utilize the signal-line driving circuit that same structure is arranged with conventional LCD 100 '.Certainly, because TFT three 16a and 16b are connected on the same sweep trace, thus preferred the same with the situation of above-mentioned example, share public grid.
Preferred the present invention is applied to the LCD of the liquid crystal layer that adopts homeotropic alignment, and wherein liquid crystal layer comprises the nematic liquid crystal material with negative dielectric anisotropic.Particularly, preferably the liquid crystal layer of each subpixel comprises four and separates about 90 ° farmland at azimuth direction, liquid crystal molecule just tilt (MVA) when applying voltage.Perhaps, the liquid crystal layer of each subpixel is kept when applying voltage and is axially arranged (ASM) symmetrically.
Under regard to MVA LCD 100 embodiments of the present invention will be described in more detail, wherein the liquid crystal layer of each subpixel comprises four and separates about 90 ° farmland at azimuth direction, liquid crystal molecule just tilts when applying voltage.
Shown in Fig. 2 A, MVA LCD 100 comprises liquid crystal board 10A, (the typically being the phase difference compensation plate) 20a that is installed in the phase difference compensating element of liquid crystal board 10A both sides and 20b, polaroid 30a and 30b and backlight assembly 40 that compensating plate is clipped in the middle.The axis of homology of polaroid 30a and 30b (being also referred to as polarization axle) orthogonal (Niccol distribution) is to such an extent as to show black when the liquid crystal layer (not shown) of liquid crystal board 10A do not applied voltage (homeotropic alignment state).Provide phase difference compensating element 20a and 20b improving the viewing angle characteristic of LCD, and utilize the known technology optimal design.Specifically, optimizing (gk=0) brightness (black level) when look side ways with top view with the arbitrary orientation angle differs from and is kept to minimum.When optimizing phase difference compensating element 20a and 20b by this way, the present invention can produce bigger visual field effect.
In fact, on substrate 11a, form common scanning line 12, signal wire 14a and 14b and TFT16a and 16b (see figure 1), so that antithetical phrase pixel capacitors 18a and 18b apply prearranged signal voltage at the fixed time respectively.In addition, form circuit etc. as required to drive these elements.In addition, on another substrate 11b, colored filter etc. is set as required.
Below with reference to Fig. 2 A～2C pixel structure in the MVA LCD 100 is described.For example treat to have described among the publication application JP11-242225 structure and the work of MVA LCD in Japan.
As described in reference to figure 1, the pixel 10 in the MVA LCD 100 has two subpixel 10a and 10b, and the subpixel 10a in the subpixel has subpixel electrode 18a, and subpixel 10b has subpixel electrode 18b.Shown in Fig. 2 C, the subpixel electrode 18a (with subpixel electrode 18b (not shown)) that is formed on the substrate of glass 11a has slit 18s, and forms tilting electric field every the relative counter electrode 17 of liquid crystal layer 13 with being placed to subpixel electrode 18a.In addition, in the arrangement of substrate of glass 11b protruding rib 19 to liquid crystal layer 13 is set on the surface of counter electrode 17.Liquid crystal layer 13 is made by the nematic liquid crystal material with negative dielectric anisotropic.When not applying voltage, it is arranged by the homeotropic alignment film (not shown) near vertical ground that covers counter electrode 17, rib 19 and subpixel electrode 18a and 18b.The liquid crystal molecule of homeotropic alignment is laid on predetermined direction restfully by rib 19 surfaces (dip plane) and tilting electric field.
Shown in Fig. 2 C, rib 19 is centroclinal to it in the mode that forms an angle.The liquid crystal molecule near vertical is arranged in ground, dip plane.Thereby, the inclination angle of rib 19 decision liquid crystal molecules (angle that forms by the major axis of substrate surface and liquid crystal molecule) distribution.Slit 18s changes the direction of the electric field that is applied to liquid crystal layer regularly.Therefore, when applying electric field, liquid crystal molecule is by rib 19 and slit 18 four direction shown in the arrow in the drawings--upper right, upper left, lower-left and bottom right---arrange, vertical and viewing angle characteristic horizontal symmetrical, good are provided.The rectangle display surface of liquid crystal board 10A is parallel to longer yardstick with axis of homology of its long yardstick horizontal positioned and polaroid 30a and places typically and be orientated.On the other hand, pixel 10 typically is orientated with the longer yardstick that its longer yardstick is orthogonal to liquid crystal board 10A, shown in Fig. 2 B.
Preferably, shown in Fig. 2 B, the area of the first subpixel 10a and the second subpixel 10b is in fact equal, each subpixel is included in first rib that first direction extends and at the upwardly extending second rib of second party, first rib in each subpixel and second rib are placed with respect to the center line symmetry that is parallel to sweep trace 12, and the rib in the distribution of the rib in one of them subpixel and another subpixel distributes with respect to the center line symmetry that is orthogonal to sweep trace 12.This kind distribution causes liquid crystal molecule in each subpixel at four direction--upper right, upper left, lower-left and bottom right---and go up and distribute, and make that the area on liquid crystal farmland is in fact equal in the whole pixel that comprises first subpixel and second subpixel, vertical and horizontal symmetrical and good viewing angle characteristic are provided.In addition, the center line that preferably is parallel to the common scanning line in each subpixel is placed to be approximately equal to half interval of array of scan lines spacing.
Next, work and display characteristic according to the LCD 100 of the embodiment of the invention are described.
At first, referring to Fig. 4, to having the display characteristic of the MVA LCD of identical electrodes structure to describe with conventional LCD 100 ' shown in Figure 3.By the way, the liquid crystal layer according to subpixel 10a in the LCD 100 of the embodiment of the invention and 10b (being subpixel electrode 18a and 18b) is applied the display characteristic that display characteristic that identical r.m.s. voltage obtained is approximately equal to conventional LCD.
Fig. 4 A is (N1), right side 60 ° (L1) from the front side and watches transmissivity and the dependence that applies voltage when showing from upper right 60 ° (LU1).Fig. 4 B is to be three transmittance graphs shown in Fig. 4 A after 100% normalization to use transmissivity that the highest grayscale voltage (voltage that display white is required) obtains.Under three kinds of conditions of its expression: face state (N2), right side 60 ° (L2) and from the transmissivity and the relation that applies voltage of upper right 60 ° of (LU2) normalization: face state (N2), right side 60 ° (L2) and from upper right 60 ° (LU2).By the way, " 60 ° " are meant the angle with 60 ° on display surface normal folder.
As can be seen from Figure 4B, the display characteristic of facing is different from the display characteristic of 60 ° of 60 ° on right side and upper right sides.This shows that the γ characteristic depends on direction of observation.
Fig. 4 C more clearly represents the difference of γ characteristic.In order clearly to represent the difference of γ characteristic, transverse axis representative (facing transmissivity/100 of normalization) ^ (1/2.2), and vertical axes is represented the gamma characteristic under N3, L3 and the LU3 state: face gamma characteristic=(facing transmissivity/100 of normalization) ^ (1/2.2), 60 ° of visual angle gamma characteristics in right side=(transmissivity/100 of the 60 ° of normalization in right side) ^ (1/2.2), 60 ° of visual angle gamma characteristics in upper right side=(transmissivity/100 of the 60 ° of normalization in upper right side) ^ (1/2.2), "-" represents index herein, and the inverse of index is corresponding to the γ value.In typical liquid crystal, the γ value of facing gamma characteristic is made as 2.2.
Referring to Fig. 4 C, abscissa value overlaps with ordinate value under the state (N3) facing, thereby the gamma characteristic under this state (N3) is linear.On the other hand, the 60 ° of visual angle gamma characteristics in 60 ° of visual angle gamma characteristics in right side (L3) and upper right side (LU3) are curve.The deviation of facing state (N3) lower curve (L3 and LU3) and straight line is represented each deviation of γ characteristic quantitatively, i.e. the deviation (difference) of gray scale demonstration.
The present invention is intended to reduce this deviation in the normal black liquor crystal display.Desirable situation is to represent the curve (L3 and LU3) of the 60 ° of visual angle gamma characteristics in 60 ° of visual angle gamma characteristics in right side (L3) and upper right side (LU3) to overlap with the straight line that gamma characteristic (N3) is faced in representative.Assessment improves the effect of γ characteristic below with reference to the accompanying drawings, and wherein accompanying drawing is represented the difference of γ characteristic, as the situation shown in Fig. 4 C.
Referring to Fig. 4 B, will how can describe the present invention below by first subpixel and second subpixel being set in each pixel and the liquid crystal layer of subpixel being applied the cardinal principle that different r.m.s. voltage reduces the deviation of γ characteristic.Suppose that first subpixel and second subpixel have area identical herein.
For the LCD 100 ' of routine, at the voltage place that is faced transmissivity by a NA representative, the 60 ° of visual angle transmissivities in right side are represented that by a LA its mid point LA represents the 60 ° of visual angle transmissivities in right side with the identical voltage of NA.About the present invention, obtain with put NA identical face transmissivity, the transmissivity of facing of first subpixel and second subpixel can be separately positioned on a NB1 and NB2.Because the transmissivity of facing at some NB2 place is approximately zero, and first subpixel and second subpixel have area identical, so the transmissivity of facing at NB1 place is the twice that a NA place faces transmissivity.The difference of the r.m.s. voltage between some NB1 and the NB2 is Δ V12.In addition, for the present invention, the 60 ° of visual angle transmissivities in right side are represented by a P, 60 ° of visual angles, right side transmissivity LB1 at identical with NB2 with a NB1 respectively voltage of its conduct place and the mean value of LB2.
For LCD according to the present invention, the some P that represents the 60 ° of visual angle transmissivities in right side is than the more approaching some NA that faces transmissivity that represents correspondence of the some LA of the 60 ° of visual angle transmissivities in right side of the conventional LCD 100 ' of representative.The deviation that this means the γ characteristic reduces.
From as can be seen above-mentioned, 60 ° of visual angle transmissivities in the right side of second subpixel (seeing a LB2) have strengthened effect of the present invention near zero the fact.Thereby, strengthen effect of the present invention, the increase of transmissivity when blank screen is looked side ways in preferred control.From then on viewpoint is set out, and phase difference compensating element 20a and 20b shown in Fig. 2 A preferably are installed as required, thereby controls the increase of transmissivity when looking side ways blank screen.
LCD 100 according to the present invention applies different r.m.s. voltage by two liquid crystal layers to each subpixel 10a and 10b in each pixel 10 and improves the γ characteristic.When doing like this, difference Δ V12 (gk)=V1 (the gk)-V2 (gk) of r.m.s. voltage that is applied to each liquid crystal layer of subpixel 10a and 10b is arranged to satisfy Δ V12 (gk)〉0V and Δ V12 (gk) 〉=Δ V12 (gk+1).To be described in the situation that satisfies above-mentioned relation in the gamut of 0＜gk≤n below.
Fig. 5 A～5D represent to be applied to pixel 10 shown in Figure 1 the first subpixel 10a liquid crystal layer r.m.s. voltage V1 (gk) and be applied to multiple relation between the r.m.s. voltage V2 (gk) of liquid crystal layer of the second subpixel 10b.
Apply under the state A at the voltage shown in Fig. 5 A, apply identical voltage (V1=V2) to the liquid crystal layer of two sub-pixel 10a and 10b.Thereby, Δ V12 (gk)=0V.
Under the voltage status B shown in Fig. 5 B, keep concerning V1〉V2, and Δ V12 is and the irrelevant constant of V1 value.Thereby, under voltage status B, any gray scale gk is satisfied relationship delta V12 (gk)=Δ V12 (gk+1).This embodiment adopts Δ V12 (gk)=1.5V as representative value, certainly, also can adopt other value.Bigger Δ V12 (gk) value has strengthened effect of the present invention, but causes the problem of the brightness (transmissivity) that reduces in the white mode.In addition, when the value of Δ V12 (gk) surpassed the threshold voltage (being the Vth shown in Fig. 4 B) of transmissivity of LCD, the brightness (transmissivity) of black pattern increased, and shows that contrast reduces, and this is a problem.Therefore, Δ V12 (gk)≤Vth preferably.
Under the voltage status C shown in Fig. 5 C, keep concerning V1〉V2, and Δ V12 reduces along with the increase of V1.Thereby, under voltage status C, any gray scale gk is satisfied relationship delta V12 (gk)〉Δ V12 (gk+1).
This embodiment adopts Δ V12 (0)=1.5V and Δ V12 (n)=0V as representative value, certainly, also can adopt other value.Yet, as mentioned above, preferably during looking side ways, light Δ V12 (gk)≤Vth from the setting that shows contrast, preferably Δ V12 (n)=0V is lighted in the setting of brightness from white mode.
Under the voltage status D shown in Fig. 5 D, keep concerning V1〉V2, and Δ V12 increases with the increase of V1.Thereby, under voltage status D, any gray scale gk is kept Δ V12 (gk)＜Δ V12 (gk+1).
Present embodiment adopts Δ V12 (0)=0V and Δ V12 (n)=1.5V as representative value.
In LCD 100 according to the embodiment of the invention, the liquid crystal layer of subpixel 10a and 10b is applied voltage, make and will satisfy voltage status B or voltage status C.By the way, though in Fig. 5 B and Fig. 5 C, satisfy Δ V12 (gk) for all gray scales〉0, optimum gradation or under the situation of high gray scale Δ V12=0 all set up.
The gamma characteristic of MVA LCD under voltage status A～D is described below with reference to Fig. 6.Transverse axis representative (facing transmissivity/100 of normalization) ^ (1/2.2) among Fig. 6 A and the 6B, vertical axes representative (transmissivity/100 of the 60 ° of normalization in right side) ^ (1/2.2) among Fig. 6 A, vertical axes representative (transmissivity/100 of the 60 ° of normalization in the upper right side) ^ (1/2.2) among Fig. 6 B.Also show among the figure and represent the straight line of facing gamma characteristic to be used for reference in the lump.
Under voltage status A, the liquid crystal layer of subpixel 10a and 10b is applied identical voltage (Δ V12 (gk)=0).Shown in Fig. 6 A and 6B, the same with conventional LCD shown in Fig. 4, the γ characteristic greatly departs from.
Voltage status D is to the influence of the view angle dependency that reduces the γ characteristic situation less than voltage status B and C.For example, the voltage status of the pixel divided corresponding to the conventional capacity that utilizes Japan to treat to describe among the publication application JP6-332009 of voltage status D.Though influential to improving viewing angle characteristic under normal white mode, the view angle dependency that reduces the γ characteristic under the normal black pattern there is not very big influence.
As mentioned above, preferred voltage state B or C are used to reduce the view angle dependency of γ characteristic under the often black pattern.
Next, referring to Fig. 7, the variation to white mode transmissivity in the voltage status, when promptly applying the highest grayscale voltage is described.
Transmissivity in the white mode is in the situation that is lower than naturally under voltage status B and the D under voltage status A.The transmissivity of white mode equals the transmissivity under the voltage status A under the voltage status C.In this regard, preferably voltage status B and D of voltage status C.Thereby, consider the view angle dependency of γ characteristic and the transmissivity in the white mode, we can say that voltage status C is more superior.
Next the preferred area ratio between the descriptor pixel.
According to the present invention, if be applied to subpixel SP1, SP2 ... with the r.m.s. voltage of the liquid crystal layer of SPn be V1, V2 ... Vn, if the area of subpixel be SSP1, SSP2 ... and SSPn, and if keep concerning V1〉V2〉... Vn then preferably satisfies SSP1≤SSPn.Will there be description the back.
Suppose that SSP1 and SSP2 are the areas of subpixel 10a and 10b in the pixel 10 shown in Figure 1.Fig. 8 has compared under the voltage status C area than the γ characteristic between (SSP1:SSP2)=(1:3), (1:2), (1:1), (2:1), (3:1).Fig. 8 A represents the γ characteristic at visual angle, right side, and Fig. 8 B represents the γ characteristic at visual angle, upper right side.Fig. 9 represents the transmissivity of facing of different Xia Sew ratios.
As can be seen from Figure 8, be applied in high voltage subpixel (10a) the area ratio reduce the view angle dependency that reduces the γ characteristic more effective.
When area during than (SSP1:SSP2)=(1:1) transmissivity in the white mode get maximal value, and along with the area ratio becomes inhomogeneous and reduces.This is because if the area ratio becomes inhomogeneous, then no longer can obtain good multidomain homeotropic alignment, thereby has reduced the area of first subpixel and second subpixel.This trend is concluded in having the high-resolution liquid crystal display of little elemental area.Thereby, though preferred area is considered the influence of view angle dependency, the transmissivity in the white mode and the utilization of LCD etc. that reduce the γ characteristic than for 1:1, can regulate as required.
Next the number of partitions of pixel will be described.
Though for LCD shown in Figure 1 100, pixel 10 is made up of two subpixel (10a and 10b), the invention is not restricted to this, the quantity of subpixel can be for three or more.
The γ characteristic that Figure 10 comparison obtains under three kinds of voltage statuss: pixel is divided into two subpixel; Pixel is divided into four subpixel; Be not divided with pixel.Figure 10 A represents the γ characteristic at visual angle, right side, and Figure 10 B represents the visual angle γ characteristic of upper right side.Figure 11 represents the corresponding transmissivity of LCD in the white mode.The constant area of pixel, and adopted voltage status B.
As can be seen from Figure 10, the increase of subpixel quantity has increased the effect of proofreading and correct the deviation in the γ characteristic.Compare with not dividing pixel, the effect a when pixel is divided into two subpixel is especially affirmed.When the quantity of dividing when two rise to four, though there is not very big difference on the deviation of γ characteristic, characteristic is improved with regard to the smooth change of the deviation relevant with grey scale change.But as can be seen from Figure 11, the transmissivity in the white mode (facing) descends with the increase of division numbers.Especially when two are increased to four, descend very big in the quantity of dividing.This very big main reasons for decrease is that the area of each subpixel reduces as described above greatly.The main cause that transmissivity reduces when more not dividing and being divided into two state is to have adopted voltage status B.Thereby, consider influence, the quantity that can regulate division as required to the view angle dependency that reduces the γ characteristic, transmissivity in the white mode and employing of LCD etc.
From as can be seen last, the view angle dependency of the deviation of γ characteristic, the shape distortion of deviation and γ characteristic increases with the increase of pixel division numbers.These effects are particularly remarkable when more not dividing pixel and pixel and be divided into the state of two (two subpixel).Thereby, consider the decline of the white mode transmissivity that the decline by the increase of subpixel quantity and manufacturability causes, preferably a pixel is divided into two subpixel.
In LCD shown in Figure 1 100, subpixel 10a and 10b are connected on TFT16a and the TFT 16b independently of one another.The source electrode of TFT 16a and TFT16b is connected respectively on signal wire 14a and the 14b.Thereby, LCD 100 allows any r.m.s. voltage to be applied on each liquid crystal layer of subpixel, but requiring is the twice ( signal wire 14a and 14b) of signal wire 14 of conventional LCD 100 ' shown in Figure 3, also needs the signal-line driving circuit more than the twice.
On the contrary, LCD 200 has the signal wire with conventional LCD 100 ' equal number according to another embodiment of the present invention, but can the liquid crystal layer to subpixel 10a and 10b applies mutually different r.m.s. voltage under the voltage status of above-mentioned voltage status C being similar to.
Figure 12 represents the circuit structure of LCD 200 according to another embodiment of the present invention.Have with the element of LCD 100 identical functions shown in Figure 1 and adopt the label identical and save description with counter element.
Pixel 10 is divided into subpixel 10a and 10b, and these subpixel are connected respectively on TFT 16a and TFT16b and memory capacitance (CS) 22a and the 22b.The gate electrode of TFT16a and TFT16b is connected on the sweep trace 12, and the source electrode is connected on the common signal line 14. Memory capacitance 22a and 22b are connected respectively on storage capacitance line (CS bus) 24a and the 24b.Memory capacitance 22a and 22b are formed by the insulation course (not shown) that is electrically connected to the memory capacitance on subpixel electrode 18a and the 18b, the memory capacitance counter electrode that is electrically connected with storage capacitance line 24a and 24b and be formed at therebetween respectively.The memory capacitance counter electrode of memory capacitance 22a and 22b is independently of one another, and is provided with mutually different memory capacitance inverse voltage through storage capacitance line 24a and 24b.
Next, with reference to the accompanying drawings, how LCD 200 is described the principle that the liquid crystal layer of subpixel 10a and 10b applies different r.m.s. voltage.
Figure 13 represents the equivalent electrical circuit of a pixel of LCD 200.In equivalent electrical circuit, the liquid crystal layer of subpixel 10a and 10b is represented with label 13a and 13b.Represent with Clca and Clcb by the liquid crystal capacitance that subpixel electrode 18a and 18b, liquid crystal layer 13a and 13b and counter electrode 17 ( subpixel 10a and 10b are shared) form.
Suppose that liquid crystal capacitance Clca and Clcb have identical capacitance CLC (V).The value of CLC (V) depends on the r.m.s. voltage of the liquid crystal layer that imposes on subpixel 10a and 10b.The memory capacitance 22a and the 22b that are connected to independently of one another on the liquid crystal capacitance of subpixel 10a and 10b are represented by Ccsa and Ccsb, and suppose that their capacitance is CCS.
The electrode of one of the liquid crystal capacitance Clca of subpixel 10a and memory capacitance Ccsa is connected on the drain electrode of TFT16a with driven element pixel 10a.Other electrode of liquid crystal capacitance Clca is connected on the counter electrode, and another electrode of memory capacitance Ccsa is connected on the storage capacitance line 24a.The electrode of one of the liquid crystal capacitance Clcb of subpixel 10b and memory capacitance Ccsb is connected on the drain electrode of TFT 16b with driven element pixel 10b.Another electrode of liquid crystal capacitance Clcb is connected on the counter electrode, and another electrode of memory capacitance Ccsb is connected on the storage capacitance line 24b.The gate electrode of TFT16a and TFT16b is connected on the sweep trace 12, and the source electrode is connected on the signal wire 14.
Figure 14 represents to be used to drive the voltage application chronogram of LCD 200.
In Figure 14, waveform (a) is the voltage waveform Vs of signal wire 14, waveform (b) is the voltage waveform Vcsa of storage capacitance line 24a, waveform (c) is the voltage waveform Vcsb of storage capacitance line 24b, waveform (d) is the voltage waveform Vg of sweep trace 12, waveform (e) is the voltage waveform V1ca of the subpixel electrode 18a of subpixel 10a, and waveform (f) is the voltage waveform Vlcb of the subpixel electrode 18b of subpixel 10b.Dotted line among the figure is represented the voltage waveform COMMON (Vcom) of counter electrode 17.
The work of the equivalent electrical circuit among Fig. 3 is described with reference to Fig. 4.
At T1 constantly, when voltage Vg when VgL changes to VgH, TFT16a and TFT16b conducting simultaneously, and voltage Vs is transferred to subpixel electrode 18a and the 18b of subpixel 10a and 10b from signal wire 14, causes subpixel 10a and 10b to change.Similarly, the memory capacitance Csa of each subpixel and Csb charge from signal wire.
At moment T2, when the voltage Vg of sweep trace 12 when VgH becomes VgL, TFT 16a and TFT16b end simultaneously.Therefore, subpixel 10a and 10b and memory capacitance Csa and Csb end with signal wire 14.Because the pulling effect that the stray capacitance of TFT 16a and TFT 16b causes, afterwards, the voltage V1ca of each subpixel and the V1ca approximately uniform voltage Vd that promptly descends becomes:
Vlca＝Vs-Vd
V1cb＝Vs-Vd
At this moment, the voltage Vcsa of each bar storage capacitance line and Vcsb are:
Vcsa＝Vcom-Vad
Vcsb＝Vcom+Vad
At moment T3, the voltage Vcsa that is connected to the storage capacitance line 24a on the memory capacitance Csa becomes " Vcom+Vad " from " Vcom-Vad ", and the voltage Vcsb that is connected to the storage capacitance line 24b on the memory capacitance Csb changes the Vad of twice to " Vcom-Vad " from " Vcom+Vad ".The result that storage capacitance line 24a and 24b voltage change is that the voltage Vlca and the V1cb of each subpixel become:
Vlca＝Vs-Vd+2*Kc*Vad
V1cb＝Vs-Vd-2*Kc*Vad
Herein, Kc=CCS/ (CLC (V)+CCS))
At moment T4, Vcsa becomes " Vcom-Vad " from " Vcom+Vad ", and Vcsb becomes " Vcom+Vad " from the Vad that " Vcom-Vad " changes twice.Therefore, V1ca and V1cb from:
V1ca＝Vs-Vd+2*Kc*Vad
V1cb＝Vs-Vd-2*Kc*Vad
Become:
V1ca＝Vs-Vd
V1cb＝Vs-Vd
At moment T5, Vcsa becomes " Vcom+Vad " from the Vad of " Vcom-Vad " change twice, and Vcsb becomes " Vcom-Vad " from the Vad that " Vcom+Vad " changes twice.Therefore, V1ca and V1cb from:
V1ca＝Vs-Vd
V1cb＝Vs-Vd
Become:
V1ca＝Vs-Vd+2*Kc*Vad
V1cb＝Vs-Vd-2*Kc*Vad
Vcsa, Vcsb, V1ca and Vlcb change above-mentioned variation at the T4 and the T5 moment with the interval of the integral multiple of level write time 1H.Be used to change integer 1,2 or 3 at interval ... driving method (method of reversal of poles etc.) and the display condition (flicker, granularity etc.) that can consider LCD are provided with afterwards as required.These replacement cycles repeat to pixel 10 always and are re-written to next constantly, that is, and and up to the moment that equals T1.Therefore, the effective value of the voltage Vlca of subpixel and V1cb is
V1ca＝Vs-Vd+Kc*Vad
V1cb＝Vs-Vd-Kc*Vad
Thereby, be applied to the liquid crystal layer 13a of subpixel 10a and 10b and r.m.s. voltage V1 and the V2 of 13b and be:
V1＝V1ca-Vcom
V2＝V1cb-Vcom
As a result,
V1＝Vs-Vd+Kc*Vad-Vcom
V2＝Vs-Vd-Kc*Vad-Vcom
Therefore, be applied to the r.m.s. voltage of the liquid crystal layer 13a of subpixel 10a and 10b and 13b difference Δ V12 (=V1-V2) be Δ V12=2*Kc*Vad (Kc=CCS/ (CLC (V)+CCS)), herein.This means and to apply mutually different voltage.
Be shown in Figure 15 according to the V1 of Figure 12 to 14 illustrated embodiment and the relation between the V2.
As can be seen from Figure 15, in the LCD 200 according to present embodiment, the V1 value is more little, and Δ V12 value is just big more.The result that this and above-mentioned voltage status C obtain down is similar.The fact that Δ V12 value changes according to V1 or V2 is owing to the capacitance CLC (V) of liquid crystal capacitance.
γ characteristic according to the LCD 200 of present embodiment is shown in Figure 16.For the ease of comparing, the γ characteristic that obtains when subpixel 10a is applied identical voltage with 10b also is shown in Figure 16.As can be seen from the figure, also improve according to γ characteristic in the LCD of present embodiment.
As mentioned above, embodiments of the invention can improve the γ characteristic of normal black liquor crystal display, especially MVA LCD.But, the invention is not restricted to this, also can be applied in the IPS LCD.
Next, the LCD according to second aspect present invention embodiment is described.
Below the distribute preferred form of (sub-pixel array) of the driving method that can reduce " flicker " on the LCD or pixel is described, in pixel distributes, the subpixel that brightness differed from one another when each pixel had at least two to show middle gray.Though this structure and operation of sentencing the LCD of present embodiment are described as the LCD example that has according to the division pixel structure of first aspect present invention embodiment, the effect that produces is not subjected to the restriction of pixel division but pixel distributes, and can adopt the LCD with another kind of pixel partition structure yet.
" flicker " problem on the LCD is at first described.
From reliability, typical liquid crystal is designed so that with alternating voltage as the voltage (being also referred to as " ac drives method " sometimes) that is applied to the pixel liquid crystal layer.The magnitude relationship of the electromotive force between pixel capacitors and the counter electrode is reversed at a certain time interval, and the direction of an electric field (line of electric force) that therefore is applied to each liquid crystal layer is also with this time interval counter-rotating.Be placed in exemplary lcd on the different base for counter electrode and pixel capacitors, the direction of an electric field that is applied to each liquid crystal layer is reversed to the direction of observer-light source from light source-observer's direction.
Typical situation is, the direction of an electric field returing cycle that is applied to each liquid crystal layer be the twice of Frame cycle (as 16.667ms) (as, 33.333ms).In other words, in LCD, be applied to direction of an electric field counter-rotating when each displayed image (frame image) changes of each liquid crystal layer.Thereby, when showing still image, if in electric field intensity (voltage that applies) the out of true ground of alternating direction coupling, if promptly electric field intensity changes when each direction of an electric field changes, then the brightness of pixel changes with the change of electric field intensity, thereby causes showing flicker.
In order to prevent flicker, electric field intensity (voltage that applies) is equated.But,, be difficult to make electric field intensity on alternating direction, to equate for industrial LCD.Therefore, reduce flicker, the opposite pixel of direction of an electric field is close to place the brightness of average pixel spatially thus.Usually, the method is known as " some counter-rotating " or " row counter-rotating ".The capable counter-rotating of 1-) and per two go and the reversal of poles of every row various " inversion driving " method can be arranged, comprise one by one (line by line, by row reversal of poles: the counter-rotating of the 1-point) counter-rotating of lineament pattern on pixel, counter-rotating line by line (counter-rotating line by line:.Select wherein a kind of as required.
As mentioned above, realize high-quality demonstration, preferably satisfy following three conditions: (1) adopts ac to drive, the feasible direction of an electric field that imposes on each liquid crystal layer with particular time interval such as each Frame periodic reversal, (2) quantity of electric charge in making the voltage that imposes on each liquid crystal layer on the alternating electric field direction (or be stored in the liquid crystal capacitance the quantity of electric charge) and being stored in memory capacitance equate and (3) in each vertical-scan period (as the Frame cycle) that pixel is opposite each other by the direction of an electric field (being called " polarity of voltage " sometimes) of being arranged to and being applied to liquid crystal layer.By the way, " vertical-scan period " can be defined as and choose behind the scan line up to the cycle of choosing this scan line again.Scan period equal under the noninterlace driving situation a Frame cycle and corresponding to a field duration under the staggered driving situation.In addition, in each vertical-scan period, choose the moment of a scan line and choose poor (cycle) in the moment of this scan line again and be known as horizontal scanning period (1H).
The above embodiment of the present invention is by being divided into each pixel at least two subpixel and making each other different demonstrations that realize good viewing angle characteristic of brightness (transmissivity).The inventor finds, when each pixel is divided into the different subpixel of a large amount of brightness, preferably also satisfies the 4th condition about the subpixel distribution except above-mentioned three conditions.Specifically, the preferred different subpixel of brightness is placed randomly with the order of any brightness.With regard to display quality, most preferably not the identical subpixel of brightness be placed to be expert at or column direction on adjacent.In other words, most preferably the identical subpixel of brightness with tessellated pattern distribution.
The driving method, the pixel that below description are suitable for the above embodiment of the present invention distribute and the subpixel distribution.Below with reference to Figure 17 and 18 the driving method example that is used for according to the LCD of the embodiment of the invention is described.
Quote such example as proof in the following description, pixel is with multirow (1～rp) and multiple row (1～cq) matrix form (rp, cq) distribute, each pixel is expressed as P (p, q) (herein 1≤p≤≤ rp and 1≤q≤cq), and have at least two subpixel SPa (p, q) and SPb (p, q), as shown in figure 17.Figure 17 be the synoptic diagram of a kind of relative distribution of expression (8 row * 6 row): signal wire S-C1, the S-C2 in the LCD of present embodiment,, S-C3,, S-C4, ... S-Ccq; Sweep trace G-L1, G-L2, G-L3 ..., G-Lrp; Storage capacitance line CS-A and CS-B; Pixel P (p, q); With the subpixel SPa that forms pixel (p, q) and SPb (p, q).
As shown in figure 17, pixel P (p, q) have the subpixel SPa that approximate on sweep trace G-Lp either side is the central horizontal spread with the pixel (p, q) and SPb (p, q).Subpixel SPa (p, q) and SPb (p q) is distributed on the column direction of each pixel.Subpixel SPa (p, q) and SPb (p, storage capacitor electrode (not shown) q) is connected respectively on adjacent the storage capacitance line CS-A and CS-B.(p, q) signal wire S-Ccq vertical distribution between pixel of supply signal voltage is supplied with signal voltage with the TFT element (not shown) of the subpixel on the signal wire right side to pixel P according to the image that shows.According to structure shown in Figure 17, a storage capacitance line or a sweep trace are shared by two subpixel.This is the benefit that increases the pixel aperture opening ratio.
Figure 18 represents to be used to drive the oscillogram of the various voltages (signal) of the LCD with structure shown in Figure 17.By have the LCD of structure shown in Figure 17 with driven, can satisfy above-mentioned four conditions with voltage waveform shown in Figure 180 (a)-(j).
Next, how the LCD of describing according to present embodiment is satisfied above-mentioned four conditions.Simple in order to explain, suppose that all pixels all show with intermediate gray-scale.
In Figure 18, waveform (a) be supply with signal wire S-C1, S-C3,, S-C5 ... the shows signal voltage waveform (source signal voltage waveform) of (the odd number signal line group also is known as S-O sometimes); Waveform (b) be supply with signal wire S-C2,, S-C4,, S-C6 ... the shows signal voltage waveform of (the odd number signal line group also is known as S-E sometimes); Waveform (c) is a memory capacitance inverse voltage waveform of supplying with storage capacitance line CS-A; Waveform (d) is a memory capacitance inverse voltage waveform of supplying with CS-B; Waveform (e) is a scanning voltage waveform of supplying with sweep trace G-L1; Waveform (f) is a scanning voltage waveform of supplying with sweep trace G-L2; Waveform (g) is a scanning voltage waveform of supplying with sweep trace G-L3; Waveform (h) is a scanning voltage waveform of supplying with sweep trace G-L4; Waveform (i) is a scanning voltage waveform of supplying with sweep trace G-L5; Waveform (j) is a scanning voltage waveform of supplying with sweep trace G-L6.Sweep trace voltage constitutes a horizontal scanning period (1H) from the cycle that low-level (VgL) became between the time of high level (VgH) and next sweep trace voltage becomes VgH from VgL time.The cycle that the voltage of sweep trace remains on high level (VgH) is called sometimes chooses cycle PS.
Because all pixels show with intermediate gray-scale, so all shows signal voltage (waveform among Figure 18 (a) and (b)) has the waveform of fixed amplitude.In addition, be two horizontal scanning periods (2H) oscillation period of shows signal voltage.Shows signal voltage be waveform and signal wire S-O (S-C1, S-C3 ...) and signal wire S-E (S-C2, S-C4 ...) voltage waveform the reason of 180 ° of aberrations is arranged is to satisfy above-mentioned the 3rd condition.Usually in TFT drives, be subjected to the variable effect (being called pull-in phenomena sometimes) of scanning voltage waveform to the line voltage signal of pixel capacitors through the TFT element transmission.Consider pull-in phenomena, the line voltage signal waveform is delivered to after the pixel capacitors, and inverse voltage is close to the center that is positioned at the line voltage signal waveform.In Figure 18, the pixel capacitors voltage waveform is higher than the inverse voltage part, signal voltage "+" number expression, and the pixel capacitors voltage waveform is lower than the inverse voltage part, signal voltage "-" number expression."+" and "-" is number corresponding to the direction of an electric field that is applied to liquid crystal layer.Direction of an electric field is opposite when "+" number and "-" number.
As described in referring to Figure 12～15, when the scanning voltage of sweep trace is VgH, be connected to the TFT conducting on the sweep trace, cause shows signal voltage supply company to be connected to the subpixel of TFT.Then, when the scanning voltage of sweep trace became VgL, the memory capacitance inverse voltage changed.Because the variation of memory capacitance inverse voltage (comprising the change of direction and symbol) is different between two subpixel, so r.m.s. voltage is applied to subpixel.
In example shown in Figure 180, the amplitude of oscillation of memory capacitance inverse voltage and cycle (waveform (c) and (d)) are got identical value between storage capacitance line CS-A and CS-B; For example, be two times Vad (seeing Figure 14) and 1H respectively.In addition, if one of them phase shift is 180 °, then the waveform of CS-A and CS-B is with overlapping.That is, their phase differential is 0.5H.If the voltage of corresponding sweep trace becomes VgL first change in voltage increase of corresponding stored electric capacity line afterwards from VgH, the average voltage of each subpixel then is higher than the shows signal voltage of the respective signal line in cycle when being present in corresponding sweep trace and being in the VgH attitude, if but first change in voltage of corresponding stored electric capacity line reduces, then be lower than the shows signal voltage that is present in the respective signal line in the cycle that corresponding sweep trace is in the VgH attitude.
Therefore, if the shows signal voltage shown in Figure 18 (waveform (a) or (b)) with "+" number mark, then to be in the r.m.s. voltage that is applied to liquid crystal layer when higher than decline state just higher when the change in voltage of storage capacitance line.On the other hand, if the shows signal voltage shown in Figure 18 (waveform (a) or (b)) with "-" number mark, then to be in the r.m.s. voltage that is applied to liquid crystal layer when higher than decline state just lower when the change in voltage of storage capacitance line.
Figure 17 represent pixel P in the vertical-scan period (in this example for Frame cycle) (p, q) and subpixel SPa (p, q) and SPb (p, state q).Below with respect to the state of three symbolic representation subpixel of the sweep trace symmetry of each subpixel.
The first symbol H or L represent to be applied to the magnitude relationship of the r.m.s. voltage of subpixel, and symbol H represents that the r.m.s. voltage that applies is very high, and symbol L represents that the r.m.s. voltage that applies is very low.Voltage swing relation between second symbol "+" and "-" expression counter electrode and the subpixel electrode, in other words, its expression is applied to the direction of an electric field of liquid crystal layer.The voltage of symbol "+" expression subpixel electrode is higher than the voltage of counter electrode, and the voltage of symbol "-" expression subpixel electrode is lower than the voltage of counter electrode.The 3rd symbol A or B represent that suitable storage capacitance line is CS-A or CS-B.
For example, the state of the subpixel SPa (1,1) of pixel P (1,1) and SPb (1,1).From waveform shown in Figure 180 (a)～(e) see, in the cycle (scanning voltage is the cycle PS of VgH) of selecting GL-1, shows signal voltage is "+".When the scanning voltage of GL-1 when VgH becomes VgL, the voltage of the storage capacitance line of each subpixel (waveform (c) and (d)) is in the state of arrow shown in Figure 180 (from first arrow on a left side) expression.Thereby after VgH became VgL, first change in voltage of the memory capacitance inverse voltage of SPa (1,1) was increase (with " U " in the waveform (c) expression) shown in Figure 180 at the scanning voltage of GL-1.On the other hand, the scanning voltage of GL-1 is after VgH becomes VgL, and first change in voltage of the memory capacitance inverse voltage of SPa (1,1) is shown in Figure 180 reducing (with " D " in the waveform (d) expression).Therefore, the r.m.s. voltage of SPa (1,1) increases, and the r.m.s. voltage of SPb (1,1) reduces.So the r.m.s. voltage of the SPa that applies (1,1) is higher than the r.m.s. voltage of SPb (1,1), and symbol H is attached to SPa (1,1), and symbol L is attached to SPb (1,1).
According to waveform shown in Figure 180 (b), in the cycle of selecting GL-1, being used for the SPa (1,1) of P (1,1) and the shows signal voltage of SPb (1,1) is "-".When the scanning voltage of GL-1 when VgH becomes VgL, the voltage of the storage capacitance line of each subpixel (waveform (c) and (d)) is in the state shown in the arrow among Figure 18 (first arrow on the left side).Thereby after VgH became VgL, first change in voltage of the memory capacitance inverse voltage of SPa (1,2) increased (" U "), as shown in figure 18 at the scanning voltage of GL-1.On the other hand, the scanning voltage of GL-1 is after VgH becomes VgL, and first change in voltage of the memory capacitance inverse voltage of SPb (1,2) reduces (" D "), as shown in figure 18.Therefore, the r.m.s. voltage of SPa (1,2) reduces and the r.m.s. voltage increase of SPb (1,2).So the r.m.s. voltage of the SPa that applies (1,2) is higher than the r.m.s. voltage of SPb (1,2), and symbol L is attached to SPa (1,2), and symbol H is attached to SPb (1,2).
According to waveform shown in Figure 180 (a), selecting in the cycle of GL-2, it is "-" that the S that is used for P (2,1) criticizes the shows signal voltage that a (2,1) and S criticize b (2,1).When the scanning voltage of GL-2 when VgH becomes VgL, the voltage of the storage capacitance line of each subpixel (waveform (c) and (d)) is in the state shown in the arrow among Figure 18 (second arrow on the left side).Thereby after VgH became VgL, first change in voltage of the memory capacitance inverse voltage of SPa (2,1) reduced (" D "), shown in Figure 18 D at the scanning voltage of GL-2.On the other hand, the scanning voltage of GL-2 is after VgH becomes VgL, and first change in voltage of the memory capacitance inverse voltage of SPb (2,1) increases (" D "), shown in Figure 18 C.Therefore, the r.m.s. voltage of SPa (2,1) increases and the r.m.s. voltage of SPb (2,1) reduces.So the r.m.s. voltage of the SPa that applies (2,1) is higher than the r.m.s. voltage of SPb (2,1), and symbol H is attached to SPa (2,1), and symbol L is attached to SPb (2,1).State shown in Figure 17 occurs by this way.
LCD according to present embodiment can drive in this mode that satisfies first condition.
Because whether Figure 17 and the state of 18 expression Frame in the cycle satisfy so can not assess first condition from figure.But, by move 180 ° in the phase place that every signal line (S-O (Figure 18 A) or S-E (Figure 18 B)) goes up voltage waveform by Frame, can carry out ac and drive, wherein be applied to each Frame periodic reversal of direction of an electric field of each liquid crystal layer.
In addition, in LCD according to present embodiment, for the magnitude relation of the subpixel that prevents pixel is that the brightness order (relative position among Figure 17 " H " and " L ") of subpixel in the display screen changes change 180 when the voltage waveform of the phase place of storage capacitance line CS-A and the last voltage waveform of CS-B on signal wire changes by Frame 0Therefore, be suitable for symbol "+" and "-" among Figure 17 in next Frame, reverse (for example (+, H) (, H) and (+, L) (, L)).Above-mentioned first condition can satisfy in this way.
Below we will check whether satisfy second condition, promptly the liquid crystal layer of each subpixel (memory capacitance of subpixel) is charged to par at different field directions.In the LCD according to present embodiment, different r.m.s. voltage is applied to the liquid crystal layer of the subpixel in each pixel, display quality for example glimmer be subjected to the very high subpixel of brightness, be the decisive influence of the subpixel of symbol among Figure 17 " H " expression.Thereby second condition especially influences the subpixel of symbol " H " expression.
Below with reference to voltage waveform shown in Figure 180 second condition is described.
At the voltage of corresponding sweep trace is to the liquid crystal capacitance and the memory capacitance charging of subpixel in cycle (selection cycle PS) of VgH.The quantity of electric charge that is stored in the liquid crystal capacitance depends on the shows signal voltage of signal wire in the selection cycle and the voltage difference between the inverse voltage (not shown among Figure 18), depends on voltage difference between the shows signal voltage of signal wire in the selection cycle and the voltage of storage capacitance line (memory capacitance inverse voltage) and be stored in the quantity of electric charge on the memory capacitance.
As shown in figure 18, the shows signal voltage in each selection cycle can be a kind of in two classes of "+" or "-" number expression among the figure.Under any situation, voltage does not change in each selection cycle.No matter the inverse voltage (not shown) how, all subpixel all applied the identical dc voltage that does not change in time.
Two class storage capacitance line CS-A and CS-B are arranged.The voltage waveform of CS-A is all identical in the selection cycle of any sweep trace.Similarly, the voltage waveform of CS-B is all identical in the selection cycle of any sweep trace.In other words, the DC composition of the voltage of storage capacitance line (DC level) is got identical value in the selection cycle of any sweep trace.
Thereby, can satisfy second condition by the DC composition (DC level) of regulating following voltage: the shows signal voltage of each sweep trace, the voltage of counter electrode and the voltage of each storage capacitance line.
Next, we will confirm whether the 3rd condition is satisfied, and promptly whether the pixel that field direction is opposite is placed with in per frame period and gets together.In the LCD according to present embodiment, different r.m.s. voltage is applied to the liquid crystal layer of subpixel in each pixel, and the 3rd condition is applied to the subpixel that is provided identical r.m.s. voltage and the relation between the pixel.The particularly important is, the subpixel of the 3rd condition by high brightness, be that the subpixel of symbol among Figure 17 " H " expression is met, as the situation of second condition.
As shown in figure 17, "+" and "-" that represent each pixel polarity (direction of an electric field) changes once at per two pixels of line direction (horizontal direction) (two row), as (+,-), (+,-), (+,-), change once at per two pixels of column direction (vertical direction) (two row), as (+,-), (+,-), (+,-), (+,-).See according to pixel one by one, show a counter-rotating, satisfy the 3rd condition.
Next, the subpixel of our high brightness, the i.e. subpixel of symbol " H " expression among Figure 17.
Referring to Figure 17, there is not reversal of poles in line direction shown in the figure, for example first the row on about subpixel SPa+H ,+H ,+H, but polarity transformation once for per two pixels of column direction shown in the figure (two row), as in first row (+H ,-H), (+H ,-H), (+H,-H), (+H ,-H).The state that is known as the row counter-rotating can be observed at the level place of the high brightness subpixel that is even more important, and this means their satisfied the 3rd conditions.The subpixel of being represented by symbol L also with the pattern distribution of rule, satisfies the 3rd condition.
Next, we will discuss the 4th condition.The 4th condition needs the identical subpixel of brightness in the subpixel should be by placing, and this makes brightness change to some extent.
According to present embodiment, the subpixel that brightness changes, promptly be applied to the different subpixel of the r.m.s. voltage of its liquid crystal layer with the symbol " H " among Figure 17 or " L " expression.
In Figure 17, if subpixel is divided into be made up of two sub-pixels of two subpixel of line direction and column direction four groups (as SPa (1,1), SPb (1,1), SPa (1,2) and SPb (1,2)), then whole matrix is formed by the subpixel group, wherein H and L from left to right distribute in the row of top, and L and H are distributed in the row of bottom.Thereby in Figure 17, symbol " H " and " L " distribute with the gridiron pattern pattern in the subpixel level, satisfy the 4th condition.
Matrix, in the pixel level, correspondence between the position of the subpixel that distributes on the brightness order of subpixel and the column direction in each pixel under the pixel situation of any row changes in line direction phase last week property (each pixel), but constant under the situation when the pixel of row arbitrarily.Thereby, any pixel P of row (p, q) in, the brightest subpixel (using the subpixel of " H " expression in this example) q during for odd number be SPa (p, q), q during for even number be SPb (p, q).Otherwise, when q is odd number the brightest subpixel be SPb (p, q), q during for even number be SPa (p, q).On the other hand, any pixel P of row (p, q) in, the brightest subpixel in same row always SPa (p, q) or SPb (p, q), no matter p is odd number or even number.Herein SPa (p, q) or SPb (p, q) mean alternately no matter p is odd number or even number, in the odd column the brightest subpixel be SPa (p, q), and no matter p is odd number or even number, in the even number line the brightest subpixel be SPb (p, q).
, satisfy above-mentioned four conditions according to the LCD of present embodiment, and thereby can realize high-quality demonstration with reference to shown in figure 17 and 18 as above-mentioned.
Next, with reference to Figure 19 and 20 LCD of utilization to another embodiment of the different driving method of pixel and subpixel described.Figure 19 and 20 is corresponding to Figure 17 and 18.
As shown in figure 20, in the LCD according to present embodiment, the every 2H vibration of shows signal voltage and memory capacitance inverse voltage once.Thereby be 4H (four level write times) oscillation period.((the oscillating phase potential difference of the signal voltage of S-C2, S-C4, S-C6...) is 180 degree (being 2H with the time) to odd number signal wire S-O for S-C1, S-C3, S-C5...) and even signal line S-E.The voltage oscillation phase differential of storage capacitance line CS-A and CS-B also is 180 degree (being 2H with the time).In addition, the voltage oscillation of signal wire is than voltage oscillation phase lag 45 degree (1/8 cycle, i.e. H/2) of storage capacitance line CS-A.By the way, the phase differential of 45 degree are used to prevent that the change in voltage of the VgH-VgL change in voltage of sweep trace and storage capacitance line is overlapping, and the value that herein adopts is not to be strict with, and also can adopt other value as required.
For the LCD according to present embodiment, each pixel is changed by two brightness and is made up of the subpixel of " H " or " L " expression.In addition, as shown in figure 19, the subpixel of being represented by symbol " H " or " L " distributes with the gridiron pattern pattern, this means and satisfies the 4th condition, and is the same with top embodiment.About first condition, can utilize the reversal process the same to satisfy with employing in above-mentioned Figure 17 and 18 illustrated embodiments.
But the embodiment shown in Figure 19 and 20 can not satisfy above-mentioned second condition.
Refer now among Figure 19 pixel P (1,1), P (2,1), P (3,1) and P (4,1) shown in first to fourth row of first row than transom pixel Pa (1,1), Pa (2,1), Pa (3,1) and Pa (4,1).As Pa (1,1) when being recharged, promptly when selecting G-L1, the polarity sign of respective signal line is "+".As Pa (3,1) when being recharged, promptly when selecting G-L3, the polarity sign of respective signal line is "-".In addition, as Pa (1,1) when being recharged, promptly when selecting G-L1, the voltage waveform of corresponding stored electric capacity line CS-A begins staged and descends in the center near selection cycle.As Pa (3,1) when being recharged, promptly when selecting G-L3, the voltage waveform of corresponding stored electric capacity line CS-A begins staged and rises in the center near selection cycle.Thereby the phase place of the voltage waveform signal by accurate control store electric capacity line CS-B and sweep trace can make the memory capacitance counter electrode be recharged and Pa (3,1) has identical DC level when being recharged at Pa (1,1).By DV being horizontally disposed with Pa (1, voltage of memory capacitance counter electrode when 1) being recharged (equaling the voltage of subpixel electrode) and Pa (3, the mean value of the voltage of memory capacitance counter electrode when 1) being recharged (equaling the voltage of subpixel electrode), can make and be stored in Pa (1,1) equal with the quantity of electric charge among the Pa (3,1).Next locate at Pa (2,1), in the cycle of correspondence, promptly when selecting G-L2, the polarity sign of respective signal line is "-" (identical with the situation of above-mentioned Pa (3,1)), and the voltage of corresponding stored electric capacity line is got fixed value (not being as above-mentioned waveform).Thereby, identical by making about Pa (1,1) and Pa (3,1) corresponding to the magnitude of voltage of the storage capacitance line of Pa (2,1) and above-mentioned DC level, can make the quantity of electric charge that is stored among Pa (1,1), Pa (2,1) and the Pa (3,1) identical.But, because underlying cause can not make the quantity of electric charge that is stored among the Pa (4,1) identical with the quantity of electric charge that is stored among Pa (1,1), Pa (2,1) and the Pa (3,1).The polarity sign of the signal wire of Pa (4,1) and Pa's (1,1) is identical, and whatsoever constantly, the voltage of corresponding stored electric capacity line is got fixed value (not being aforesaid waveform).Therefore, the magnitude of voltage (said fixing value) that need make the storage capacitance line of Pa (4,1) and DC level are about Pa (1,1) and Pa (3,1) identical, identical with the situation of Pa (2,1), promptly equal Pa (4,1) and for the magnitude of voltage (said fixing value) of the storage capacitance line of Pa (2,1).But, this is impossible because from Figure 19 and 20 as can be seen, for Pa (2,1) and Pa (4,1) storage capacitance line is CS-B, and they are waveform clocklike, at Pa (2,1) selects the maximal value of waveform in the selection cycle, and in the selection cycle of Pa (4,1), select the minimum value of waveform, make two voltages inevitable different.
In addition, with regard to the subpixel of distribution identical polar so that with regard to its 3rd condition not adjacent one another are as much as possible, present embodiment is inferior to the foregoing description shown in Figure 17 and 18.
Referring to Figure 19, we by big voltage be applied to its liquid crystal layer the subpixel of forming pixel, be the reversal of poles of the subpixel represented of symbol H.In Figure 19, there is not reversal of poles in line direction shown in the figure, as in first row for subpixel SPa+H ,+H ,+H (as Figure 17), but per four pixel reversal of poles of column direction shown in the figure, as in first row (+H ,-H ,-H ,+H), (+H,-H ,-H ,+H).In referring to Figure 17 and 18 described embodiment, a reversal of poles takes place in per two pixels, and the reversal of poles cycle of present embodiment is 1/2.In other words, in referring to Figure 17 and 18 described embodiment, the reversal of poles frequency is above twice referring to Figure 19 and 20 described embodiment.At this on the one hand, present embodiment (referring to Figure 19 and 20 described) is inferior to referring to Figure 17 and 18 described embodiment.
In fact display quality compares between the driving method of the driving method of implementing the last embodiment that pixel shown in Figure 17 distributes and present embodiment, and finds out difference in display quality.Specifically, for example when observing the demonstration of 64/255 gray scale with fixing sight line, two kinds of driving methods do not see that evident difference is arranged, and wherein this gray scale is at the bigger luminance difference of subpixel generation that is used for changing brightness.But, when observing demonstration, in the driving method of present embodiment, see horizontal clause (Figure 19), and the driving method of last embodiment (Figure 17) does not have these problems by mobile sight line.Can believe that described difference is by due to the difference in above-mentioned reversal of poles cycle.Because the brightness of two subpixel that comprise in each pixel is more remarkable, so preferably make reversal of poles cycle minimum than the transom pixel.Each pixel is divided into two subpixel in above-mentioned example, but also can be divided into three or more subpixel, and the subpixel that preferably distributes in this manner promptly, makes the reversal of poles cycle minimum of transom pixel.Much less, preferably other all subpixel all has the identical reversal of poles cycle with transom pixel.
Next, referring to Figure 21 A and 21B the following examples are described, among this embodiment, even observe demonstration by mobile sight line, the above-mentioned horizontal clause that utilizes the shorter reversal of poles cycle is also than more not obvious among the embodiment shown in Figure 17.
According to embodiment shown in Figure 17, though form on the column direction shown in (+,-), (+,-), (+,-) and (+,-), reversing of pixel than transom pixel (with symbol " H " expression), but+,+,+,+,+,+or-,-,-,-,-,-shown in direction nonreversible.On the contrary,, not only on the column direction shown in (+,-), (+,-), (+,-), (+,-), reverse, and on the line direction shown in (+,-), (+,-), reverse than "+" and "-" of transom pixel according to embodiment shown in Figure 21.Thereby embodiment shown in Figure 20 has adopted the reversal of poles cycle than weak point embodiment illustrated in fig. 17.In this regard, embodiment shown in Figure 20 more is better than embodiment shown in Figure 17.
Even in the embodiment shown in Figure 21, in the subpixel of forming pixel, the 4th condition is satisfied in distributing with the gridiron pattern pattern than the transom pixel of symbol " H " expression.
Pixel shown in can following enforcement Figure 21 A distributes.
Shown in Figure 21 B, per two row of memory capacitance counter electrode that are used for subpixel in every row alternately are connected to storage capacitance line CS-A or CS-B.This structural change can be clear that by the previous embodiment shown in present embodiment more shown in Figure 21 and Figure 17 or 18.Specifically, this can find out by checking the storage capacitance line that line direction subpixel place chooses.For example, at subpixel SPa (1,1)～SPa (1,6) in the row, from the memory capacitance counter electrode of symbol " A " or " B " expression, be SPa (1,1) choosing " A ", for SPa (1,2) choosing " B ", be SPa (1,4) and SPa (1,5) choosing " A ", be SPa (1,6) choosing " B ", as shown in figure 21, and to all subpixel SPa shown in Figure 17 or 18 (1,1)～SPa (1,6) selects " A ".
According to embodiment shown in Figure 21, the voltage waveform shown in Figure 18 (a)～(j) can be as the voltage waveform of supplying with the lead that comprises storage capacitance line CSA and CS-B.But, because the per two row conversions of shows signal voltage once, therefore the shows signal voltage that has a waveform shown in Figure 180 (a) offer S-C1, S-C2, S-C5, S-C6 ... shown in Figure 21 A, and the shows signal voltage with waveform shown in Figure 20 (b) offer the S-C3 shown in Figure 21 A, S-C4, S-C7 (not shown), S-C8 (not shown) ...
Although in the above-described embodiments, the memory capacitance inverse voltage of supplying with storage capacitance line is that dutycycle is 1: 1 a square wave oscillation voltage, and the present invention can not be 1: 1 square wave with duty-cycle yet.In addition, can also use other waveform, for example sine wave or triangular wave.In this case, when the TFT that is connected to a plurality of sub-pixels closed, the variation that produces in the voltage of supplying with sub-pixel memory capacitance counter electrode can change according to sub-pixel.But amount of charge that is stored in different subpixel (liquid crystal capacitance and memory capacitance) and the voltage root mean square that is applied on the different subpixel equate easily to use square wave to make.
And, although above-mentioned with reference to Figure 17 and 21 described embodiment in, be 1H oscillating voltage oscillation period of supplying with storage capacitance line (waveform (c) and (d)), as shown in figure 18, removed the mark of resulting 1H, for example 1/1H but also can be 1H by natural number, 1/2H, 1/3H, 1/4H etc.But,, therefore be difficult to constitute the power consumption increase of driving circuit or driving circuit because oscillating voltage shortens oscillation period.
Next, the embodiment of third aspect present invention is described.
The embodiment of third aspect present invention relates to big or high-resolution liquid crystal display and its driving method that improves viewing angle characteristic, especially raising demonstration contrast by the sub-pixel that each pixel is divided into a plurality of different brightness.
As mentioned above, the embodiment of first aspect present invention improves viewing angle characteristic, especially shows the LCD or the driving method of contrast by the sub-pixel that each pixel is divided into a plurality of different brightness.Such demonstration and driving are meant many pixel demonstrations, many pixel drive here, area shows than gray shade scale or area drives than gray shade scale.Also have, the embodiment of second aspect present invention has the LCD of the array of sub-pixels that can reduce demonstration " flicker " or its driving method, and suitably makes up with first aspect embodiment.
In the LCD according to second aspect present invention embodiment, the oscillating voltage (memory capacitance inverse voltage) that is applied to CS bus (storage capacitance line) equals or be shorter than a horizontal scanning period oscillation period.If will lack the oscillating voltage of oscillation period by this way is applied on the CS bus, increase the resolution and the size of display board, make the short oscillation period of resulting oscillating voltage clapp oscillator circuit difficulty (costliness) to make up, increase power consumption, or increase the influence of the waveform passivation that causes by CS bus electrical load resistance.
Compare with LCD, describe LCD, describe concrete structure and operation here once more according to the LCD of second aspect present invention embodiment according to third aspect present invention embodiment according to second aspect embodiment.Be to realize the example of above-mentioned area below than gray shade scale by being set at a horizontal scanning period oscillation period with CS bus oscillating voltage.With reference to accompanying drawing, concentrate and describe following 3 points.First structure that relates to LCD centers around the memory capacitance counter electrode of the memory capacitance of connexon pixel and the connection pattern between the CS bus.Second CS bus oscillation period and phase place that relates to according to the grid bus voltage waveform.The driving and the show state that thirdly relate to sub-pixel.
Figure 22 is the equivalent circuit diagram in certain zone with LCD of pel array shown in Figure 17.LCD has the pixel that row and column is arranged in matrix.Each pixel has two sub-pixels (representing with symbol A and B).Each sub-pixel comprises liquid crystal capacitance CLCA_n, m or CLCB_n, m and memory capacitance CCSA_n, m or CCSB_n, m.Each liquid crystal capacitance is made up of pixel electrode, counter electrode ComLC and the liquid crystal layer that is clipped between them.Each memory capacitance is made up of storage capacitor electrode, dielectric film and memory capacitance counter electrode (ComCSA_n or ComCSB_n).Two sub-pixels are through each TFTA_n, and m and TFTB_n, m are connected on common signal line (power bus) SBL_m.Come opening and closing TFTA_n, m and TFTB_n, m by the scanning voltage signal that is applied on common scanning line (grid bus) GBL_n.When two TFT opened, monitor signal voltage was supplied with the storage capacitor electrode of each pixel electrode and two sub-pixels through common signal line.Through CS bus (CSBL), the memory capacitance counter electrode of one of two pixel electrodes is connected on memory capacitance main line (CS main line) CSVtypeR1, and the memory capacitance counter electrode of other sub-pixel is connected on memory capacitance main line (CS main line) CSVtypeR2.
Should note sharing electric public CS bus at the sub-pixel of Figure 22 column direction neighbor.Have CLCB_n especially for n in capable, the CS bus CSBL of the sub-pixel of m and be used for the column direction adjacent lines and have CLCA_n+1, the CS bus CSBL electricity of the sub-pixel of m pixel is shared.
Figure 23 A and 23B illustrate with regard to the voltage waveform of grid bus and shown in supply with the oscillation period and the phase place of the oscillating voltage of CS bus with regard to the pixel electrode voltage.LCD reverse usually (with specific time interval) be applied to the direction of an electric field of each pixel liquid crystal layer, therefore, need to consider two type driving voltage waveform of corresponding direction of an electric field.In Figure 23 A and Figure 23 B, two types driving condition is shown respectively.
In Figure 23 A and 23B, VSBL_m represents to supply with the waveform of the shows signal voltage (power supply signal voltage) of m row power bus SBL_m, and simultaneously VGBL_n represents to supply with the waveform of scanning voltage signal (signal voltage) of the grid bus GBL_n of n row.VCSVtypeR1 and VCSVtypeR2 represent to supply with the waveform of the oscillating voltage of CS main line CSVtypeR1 and CSVtypeR2 respectively, as the memory capacitance inverse voltage.VPEA_m, n and VPEB_m, n represent the voltage waveform of each sub-pixel liquid crystal capacitance.
Note in Figure 23 A and 23B first is all to equal oscillation period of the voltage VCSVtypeR1 of CSVtypeR1 and CSVtypeR2 and VCSVtypeR2 a horizontal scanning period (1H).
Note in Figure 23 A and 23B second is that the phase place of VCSVtypeR1 and VCSVtypeR2 is as follows.At first, observe the phase differential between the CS main line, it is 0.5H that VCSVtypeR2 falls behind VCSVtypeR1.Next, observe the voltage of CS main line and grid bus, the voltage-phase of CS main line and grid bus is as follows.As can be seen, the grid bus voltage of corresponding each CS main line becomes time of VgL from VgH consistent with the time at their center of flat arrival of CS rail voltage from Figure 23 A and 23B.In other words, the Td value in Figure 23 A and 23B is 0.25H.But Td can be greater than 0H but less than any value of 0.5H.
Although with reference to voltage-phase and cycle that Figure 23 A and 23B have described the CS main line, the voltage waveform of CS main line is not limited thereto, the CS main line can be any waveform, as long as satisfy one of following two conditions.First condition is after the voltage of corresponding grid bus becomes HgL from VgH, and it is that voltage increases that first of voltage VCSVtypeR1 changes, and after the voltage of corresponding grid bus became HgL from VgH, it was that voltage reduces that first of voltage VCSVtypeR2 changes.Second condition is after the voltage of corresponding grid bus becomes HgL from VgH, and it is that voltage reduces that first of voltage VCSVtypeR1 changes, and after the voltage of corresponding grid bus became HgL from VgH, it was that voltage increases that first of voltage VCSVtypeR2 changes.
The driving condition of Figure 24 A and 24B general introduction LCD.According to a plurality of driving voltages of the sub-pixel of Figure 23 A and 23B example shown, the driving condition of LCD also is divided into two types.The driving voltage waveform of the driving condition corresponding diagram 23A of Figure 24 A, and the driving voltage waveform of the driving condition corresponding diagram 23B of Figure 24 B.
Figure 24 A and 24B are shown schematically in the pixel drive state of " capable of 8 capable row of n+7 from n " * " being listed as 6 row of m+5 row from m " in a plurality of pixels by arranged.Each pixel has the sub-pixel of different brightness.Promptly be expressed as the sub-pixel and the sub-pixel that is expressed as " d (secretly) " of " b (bright) ".Figure 24 A is identical with Figure 17 basically with 24B.
The lime light of Figure 24 A and Figure 24 B is whether to satisfy the requirement of area than gray shade scale plate.Area has five requirements than gray shade scale plate.
First requirement is that each pixel is made up of a plurality of pixels of different brightness when showing the middle gray grade.
Second requirement is not consider the time, and the sub-pixel intensity level of different brightness is constant.
The 3rd requirement is that the sub-pixel of different brightness is arranged fine.
The 4th requirement is that the pixel of opposite polarity in all frames is arranged fine.
The 5th requirement is that the sub-pixel of identical polar, same luminance level (particularly the brightest sub-pixel) in all frames is arranged fine.
Require to verify according to first.Here, each pixel is made up of the sub-pixel of two different brightness.Particularly, for example in Figure 24 A, the pixel of the capable and m row of n is by the high brightness subpixel that is expressed as " b (bright) " and be expressed as the low-light level sub-pixel of " d (secretly) " and form.Therefore, satisfy first requirement.
Require to verify according to second.LCD replaces two kinds of show states of different driving state with time interval of rule.Figure 24 A and 24B represent to meet corresponding to the driving condition of two kinds of show states the position of high brightness subpixel and low-light level sub-pixel.Therefore, satisfy second requirement.
Require to verify according to the 3rd.In Figure 24 A and 24B, the sub-pixel of different intensity levels (that is, being expressed as the sub-pixel and the sub-pixel that is expressed as " d (secretly) " of " b (bright) ") is arranged by lineament.The visible observation of LCD does not have to occur such as using different brightness sub-pixels to reduce the demonstration problem of resolution.Therefore, satisfy the 3rd requirement.
Require to check according to the 4th.The pixel of opposite polarity is arranged in lineament in Figure 24 A and 24B.Particularly, for example in Figure 24 A, the pixel at n+2 in the capable and m+2 row has "+" polarity.From this pixel, follow direction and column direction and between "-" and "+", change polarity every a pixel.For not satisfying the 4th LCD that requires, think and the driving polarity of pixel changes between "+" and "-" and sees flashing of display synchronously.But, when the LCD of sight check embodiment, just can't see and flash.Therefore, satisfy the 4th requirement.
Require to check according to the 5th.In Figure 24 A and 24B, the sub-pixel of observing same luminance level drives polarity, per two row sub-pixel (that is, every a pixel wide) inversion driving polarity.Particularly, for example in the n_B of Figure 24 A was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "-".In n+1_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "-".In n+1_B was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "+".In n+2_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "+".For not satisfying the 5th LCD that requires, think and the driving polarity of pixel changes between "+" and "-" and sees flashing of display synchronously.But, just can't see during when sight check and to flash according to LCD of the present invention.Therefore, satisfy the 5th requirement.
When observing LCD by the amplitude VCSpp that changes CS voltage, during oblique view, along with the raising that shows contrast, viewing angle characteristic just improves, because the amplitude VCSpp of CS voltage begins to increase (0V is used to support the general LCD except the LCD according to the present invention) from 0V.Although as if the raising according to the image aspects characteristic that shows slightly different, when VCSpp be set at make VLCaddpp value the 0.5-2 of the LCD threshold voltage of common drive pattern (VCSpp is 0V) doubly within the time, the raising of then realization the best.
Therefore, LCD according to second aspect present invention embodiment improves viewing angle characteristic by applying oscillating voltage on the memory capacitance counter electrode, realize that thus many pixels show, wherein be applied to oscillating voltage on the memory capacitance counter electrode and equal oscillation period or be shorter than a horizontal scanning period.But, when the oscillation period that is applied to the oscillating voltage on the CS bus in short-term, just quite be difficult on the display of the high-resolution liquid crystal display of the high capacity electric capacity of CS bus and the big LCD of resistance, short horizontal scanning period or high-speed driving and short vertical, horizontal scanning period, realize many pixels demonstrations.
This problem is described with reference to Figure 25-28.
Figure 25 A is in the LCD that is illustrated in according to second aspect present invention embodiment, be used for oscillating voltage supply with the CS bus structural representation.A plurality of CS buses that oscillating voltage is provided with LCD panel from the CS mains supply.Oscillating voltage is supplied with the CS main line through tie point ContP1 and ContP2 and process ContP3 and ContP4 from CS bus voltage generator circuit.Owing to increase the size of LCD panel, therefore the distance from the pixel at display board center to tie point ContP1 and ContP2 increases, and makes it can not ignore loaded impedance between center pixel and the tie point.The main element of loaded impedance comprises liquid crystal capacitance (CLC) and memory capacitance (CCS), the resistance R CS of CS bus and the resistance R trunk of CS main line of pixel.The low-pass filter that the first approximation of loaded impedance can be made up of above-mentioned electric capacity shown in Figure 25 B and resistance.The value of loaded impedance is the function of liquid crystal display Board position.For example, it is the function apart from tie point ContP1, ContP2, ContP3 and ContP4 distance.Particularly, loaded impedance increases with the increase of distance tie point distance, reducing and reduce with distance tie point distance.
That is to say that the CS bus voltage that is produced by the oscillating voltage generator circuit is subjected to the influence of the approximate CS bus load of CR low-pass filter, the CS bus changes position on flat board through the waveform passivation.
As described in the embodiment of first aspect present invention, oscillating voltage imposes on the CS bus, so that constitute each pixel of two or more sub-pixels and change the brightness of sub-pixel.That is, use such structure and driving method: form the voltage waveform of pixel electrode according to the oscillating voltage of CS bus, and change effective voltage according to the waveform of CS bus according to the LCD of the embodiment of the invention.Therefore, if CS bus voltage waveform changes to another position from a position, the effective voltage of pixel electrode also is like this.In other words, if the waveform passivation of CS bus voltage changes the position, display brightness is also with change in location, thereby obtains irregular display brightness.
By proofreading and correct the irregular ability of display brightness the oscillation period that increases the CS bus is advantage according to the third aspect present invention LCD.To lay down a definition below.
Figure 26 and 27 is shown schematically in the oscillating voltage waveform of the situation pixel electrode that the CS load remains unchanged.Figure 26 and 27 be the voltage of supposition pixel electrode when the CS bus voltage is not oscillating voltage for " 0V ", and the amplitude of the pixel electrode voltage that is produced by the vibration of CS bus is " 1V " ' synoptic diagram.Waveform among Figure 26 (a)-(e) expression CS voltage does not have the waveform of waveform passivation, promptly, the CR time constant of CR low-pass filter is " 0H ", and the waveform passivation of waveform (a)-(e) expression when the CR of CR low-pass filter time constant is " 0.2H " among Figure 27.Figure 26 and 27 schematically shows the voltage waveform of pixel electrode voltage when the CR of CR low-pass filter time constant is " 0H " and " 0.2H " respectively, and be changed the oscillation period of CS bus oscillating voltage.Ripple among Figure 26 and 27 (a)-(e) the expression oscillating waveform cycle is respectively the situation of 1H, 2H, 4H, 8H.
When Figure 26 and 27 compared, waveform difference reduced with the increase of oscillation period among Figure 26 and 27 as can be seen.This trend quantificational expression in Figure 28.
Figure 28 represents based on the waveform of Figure 27 (corresponding horizontal scanning period of one-period: the mean value of the oscillating voltage that 1H) calculates and the relation of effective value oscillation period than CS bus voltage.As can be seen from Figure 28, when the CR time constant is 0H and the CR time constant when being 0.2H between the deviation of average voltage and effective voltage reduce with the increase of CS bus oscillation period.As can be seen, can reduce the influence of waveform passivation largely, particularly when oscillation period of CS bus oscillating voltage during greater than 8 times of the CR time constant (approximate value of loaded impedance) of CS bus.
Like this, by increasing the oscillation period of CS bus oscillating voltage, it is irregular to reduce the display brightness that the passivation of CS bus waveform causes.Can reduce the influence of waveform passivation largely, particularly when oscillation period of CS bus oscillating voltage during greater than 8 times of the CR time constant (approximate value of loaded impedance) of CS bus.
Because the LCD according to second aspect present invention has the problems referred to above, therefore a third aspect of the present invention is proposed.This aspect provides the preferred structure and the method for LCD, and it can increase the oscillation period that is applied to the oscillating voltage on the CS bus.
In LCD according to third aspect present invention embodiment, the CS bus of electrical isolation is used at the same column of matrix driving LCD and sub-pixel (for example, first sub-pixel and second sub-pixel) along the column direction different intensity levels of sub-pixel adjacent one another are.Be electrically insulated from each other especially for the CS bus of capable first sub-pixel of n and the CS bus of capable second sub-pixel of n+1.Here, the pixel in matrix driving LCD same column is by the pixel of same signal line (being generally power bus) driving.And, the pixel of the scanning line driving of being selected by adjacent time point in sweep trace (being generally grid bus) in the column direction of matrix driving LCD pixel adjacent one another are by the time shaft select progressively.In addition, supposing has L group CS main line electrical isolation, and the vibration period of CS bus can be L a times of horizontal scanning period.As mentioned above, 8 times of the merchant that obtains divided by the CR time constant that is approximately equal to the impedance of CS bus maximum load greater than a horizontal scanning period of the quantity of preferred CS main line.And as hereinafter described, preferably this numerical value is except greater than 8 multiples or even number.At this, the quantity of CS main line electrical isolation group (L group) can be represented with the quantity of the CS main line (L main line) of electrical isolation.If the CS main line of electrical equivalent is installed in the plate both sides, the quantity of the CS main line of electrical equivalent is then constant.
With reference to the accompanying drawings, describe according to the LCD of third aspect present invention embodiment and its driving method.
At first, with reference to Figure 29-31B, describe LCD and realize that by being set at 4 times of horizontal scanning period the oscillation period with the oscillating voltage of CS bus area shows than gray shade scale.Description concentrates on following points, and provides with reference to accompanying drawing.First relates to liquid crystal display device structure, centers around the connection pattern between the memory capacitance counter electrode that is connected to the memory capacitance on sub-pixel and the CS bus.Second oscillation period and oscillation phase that relates to according to the CS bus of grid bus voltage waveform.Thirdly relate to driving and show state according to the sub-pixel of present embodiment.
Figure 29 is the schematic equivalent circuit according to the LCD of third aspect present invention embodiment, corresponding Figure 22.With the Reference numeral/symbolic representation identical with Figure 22 of Figure 22 components identical, it describes omission.LCD among Figure 29 is different from the LCD among Figure 22, and wherein it has the CS main line CSVtypeA1-CSVtypeA4 and the connection status between CS main line and CS bus of four electrical isolations.
First that will note in Figure 29 is: the CS bus of the adjacent subpixels of pixel in the column direction adjacent lines (for example, corresponding CLCB_n, m and CLCA_n+1, the sub-pixel of m) is electrically insulated from each other.Particularly, for example be used for the capable sub-pixel CLCB_n of n, the CS bus CSBL_B_n of m and the sub-pixel CLCA_n+1 that is used for column direction adjacent lines pixel, the bus CSBL_A_n+1 of m is electrically insulated from each other.
Second that will note in Figure 29 is: each CS bus (CSBL) is connected on one of four CS main lines (CSVtypeA1, CSVtypeA2, CSVtypeA3 and CSVtypeA4) of dull and stereotyped end.That is, in LCD, the CS main line of four groups of electrical isolations is arranged according to present embodiment.
What will note among Figure 29 thirdly is: the connection status between CS bus and four CS main lines, that is, and along the distribution of the CS bus of column direction electrical isolation.According to the concatenate rule of CS bus among Figure 29 and CS main line, be connected to bus on CS main line CSVtypeA1, CSVtypeA2, CSVtypeA3 and the CSVtypeA4 shown in the table 1.
[table 1]
The CS main line Be connected to the CS bus on the CS main line The general symbol(s) of the CS bus that draw on the left side
CSVtypeA1 CSBL_A_n， CSBL_B_n+2， CSBL_A_n+4， CSBL_B_n+6， CSBL_A_n+8， CSBL_B_n+10， CSBL_A_n+12， CSBL_B_a+14， … CSBL_A_n+4·k， CSBL_B_n+2+4·k (k＝0，1，2，3，…)
CSVtypeA2 CSBL_B_n， CSBL_A_n+2， CSBL_B_n+4， CSBL_A_n+6， CSBL_B_n+8， CSBL_A_n+10， CSBL_B_n+12， CSBL_A_n+14， … CSBL_B_n+4·k， CSBL_A_n+2+4·k (k＝0，1，2，3，…)
CSVtypeA3 CSBL_A_n+ 1， CSBL_B_n+3， CSBL_A_n+5， CSBL_B_n+7， CSBL_A_n+9， CSBL_B_n+11， CSBL_An+13， CSBL_B_n+15， … CSBL_A_n+1+4·k， CSBL_B_n+3+4·k (k＝0，1，2，3，…)
CSVtypeA4 CSBL_B_n+ 1， CSBL_A_n+3， CSBL_B_n+5， CSBL_A_n+7， CSBL_B_n+9， CSBL_A_n+11， CSBL_B_n+13， CSBL_A_n+15， … CSBL_B_n+1+4·k， CSBL_A_n+3+4·k (k＝0，1，2，3，…)
The CS bus of four groups of electrical isolations is connected respectively on four CS main lines shown in the above-mentioned table 1.
Figure 30 A and 30B represent CS bus oscillation period and the phase place according to the voltage waveform of grid bus, and the voltage of expression pixel electrode.Corresponding above-mentioned Figure 23 A of Figure 30 A and 30B and 23B.With the Reference numeral/symbolic representation identical with 23B of Figure 23 A and 23B components identical, omit description at this with Figure 23 A.LCD generally is applied to direction of an electric field on the liquid crystal layer of each pixel with the counter-rotating of time interval of rule, therefore, needs to consider two types driving voltage waveform corresponding to direction of an electric field.Represent this driving condition of two types among Figure 30 A and the 30B respectively.
First that will note among Figure 30 A and the 30B is: all be 4 times (4H) of horizontal scanning period the oscillation period of voltage VCSVtypeA1, VCSVtypeA2, VCSVtypeA3 and the VCSVtypeA4 of CSVtypeA1, CSVtypeA2, CSVtypeA3 and CSVtypeA4.
Second that will note among Figure 30 A and the 30B is: the phase place of VCSVtypeA1, VCSVtypeA2, VCSVtypeA3 and VCSVtypeA4 is as follows.At first, compare the phase place in the CS main line, VCSVtypeA2 is than the backward 2H of VCSVtypeA1, and VCSVtypeA3 is than the backward 3H of VCSVtypeA1, and VCSVtypeA4 is than the backward 1H of VCSVtypeA1.Next, observe the voltage of CS main line and the voltage of grid bus, the phase place of CS bus voltage and grid bus voltage is as follows.Shown in Figure 30 A and 30B, the time that becomes VgL corresponding to the voltage of the grid bus of each CS main line from VgH is consistent with the time that the flat of CS main line arrives their centers.In other words, the Td value among Figure 30 A and the 30B is 1H.But the Td value is any greater than the value of 0H less than 2H.
Here, the grid bus corresponding to each Cs main line is the CS bus is connected identical pixel electrode with the TFT element through auxiliary capacitor CS CS main line and a grid bus.According to Figure 29, corresponding to expression in the grid bus of each the CS main line in this LCD and the CS bus table 2 below.
[table 2]
The CS main line Corresponding grid bus Corresponding C S bus
CSVtypeAl GBL_n，GBL_n+2，GBL_n+4， GBLn+6，GBL_n+8，… ......................... [GBL_n+2·k (k＝0，1，2，3，…)] CSBL_A_n，CSBL_B_n+2，CSBL_A_n+4、 CSBL_B_n+6，CSBL_A_n+8，… ............................... (CSBL_A_n+4·k，CSBL_B_n+2+4·k (k＝0，1，2，3，…)]
CSVtypeA2 CBL_n，GBL_n+2，GBL_n+4， GBL_n+6，GBL_n+8，… ......................... (GBL_n+2·k (k＝0，1，2，3，…)] CSBL_B_n，CSBL_A_n+2，CSBL_B_n+4， CSBL_A_n+6，CSBL_B_n+8，… ............................... [CSBL_B_n+4·k，CSBL_A_n+2+4·k (k＝0，1，2，3，…)]
CSVtypeA3 GBL_n+ 1，GBL_n+3，GBL_n+5， GBL_n+7，GBL_n+9、… ......................... [GBL_n+1+2·k (k＝0，1，2，3，…)] CSBL_A_n+1，CSBL_B_n+3， CSBL_A_n+5， CSBL_B_n+7，CSBL_A_n+9、… ......................... [CSBL_A_n+1+4·k，CSBL_B_n+3+4·k (k＝0，1，2，3，…)]
CSVtypeA4 GBL_n+ 1，GBL_n+3，GBL_n+5， GBL_n+7，GBL_n+9，… ......................... [GBL_n+1+2·k (k＝0，1，2，3，…)] CSBL_B_n+1，CSBL_A_n+3， CSBL_B_n+5， CSBL_A_n+7，CSBL_B_n+9，… ......................... [CSBL_B_n+1+4·k，CSBL_A_n+3+4·k (k＝0，1，2，3，…)]
Although described the cycle and the phase place of CS rail voltage with reference to Figure 30 A and 30B, the voltage waveform of CS main line is not limited thereto.The CS main line can be other waveform that satisfies following two conditions.
First condition is: it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA1 behind the VgL changes, it is that voltage reduces that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA2 behind the VgL changes, it is that voltage reduces that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA3 behind the VgL changes, and it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA4 behind the VgL changes.Driving voltage waveform shown in Figure 30 A satisfies this condition.
Second condition is: it is that voltage reduces that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA1 behind the VgL changes, it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA2 behind the VgL changes, it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA3 behind the VgL changes, and it is that voltage reduces that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeA4 behind the VgL changes.Driving voltage waveform shown in Figure 30 B satisfies this condition.
But,, preferably use the waveform shown in Figure 30 A and the 30B for the reason that describes below.
In Figure 30 A and 30B, be constant oscillation period.This can simplify signal generator circuit.
And in Figure 30 A and 30B, the vibration dutycycle is constant.May keep amplitude of oscillation constant like this, and when oscillating voltage was used as the CS bus voltage, the voltage variety that is applied to liquid crystal display layer depends on the amplitude and the dutycycle of vibration, therefore simplify signal generator circuit.Therefore, the vibration dutycycle remains unchanged, and just may make the amplitude of vibration constant.For example, dutycycle is set at 1:1.
And, in Figure 30 A and 30B,, there is the oscillating voltage (oscillating voltage of opposite phase) that exceeds 180 degree phase places for any CS oscillating voltage.That is, four electrical isolation CS main lines are formed the CS main line to (two pairs), and it supplies with the oscillating voltage that exceeds 180 degree phase places mutually.This just may make the magnitude of current minimum that flows through the memory capacitance counter electrode, therefore simplifies the driving circuit that connects counter electrode.
The driving condition of Figure 31 A and 31B general introduction present embodiment LCD.According to the polarity of sub-pixel driving voltage, the driving condition of LCD also is divided into two types, the situation shown in Figure 30 A and 30B.Driving condition among Figure 31 A is corresponding to the driving voltage waveform of Figure 30 A, and simultaneously, the state among Figure 31 B is corresponding to the driving condition of Figure 30 B driving voltage waveform.Figure 31 A and 31B are corresponding to above-mentioned Figure 24 A and 24B.
Lime light among Figure 31 A and the 31B is whether to satisfy the requirement of area than gray shade scale plate.Verify than five requirements of gray shade scale plate according to following area.
First requirement is that each pixel is made up of a plurality of different brightness sub-pixels when showing the middle gray grade.
Second no matter to require be the time, and the different sub-pixel intensity level of brightness is constant.
The 3rd requirement is that the sub-pixel of different brightness is arranged fine.
The 4th requirement is that the pixel of opposite polarity in all frames is arranged fine.
The 5th requirement is that the sub-pixel of identical polar, same luminance level (especially the brightest sub-pixel) in all frames is arranged fine.
Require to verify according to first.In Figure 31 A and 31B, each pixel is made up of two different sub-pixels of brightness.Particularly, for example in Figure 31 A, the pixel of the capable and m row of n is by the high brightness subpixel that is expressed as " b (bright) " and be expressed as the low-light level sub-pixel of " d (secretly) " and form.Therefore, satisfy first requirement.
Require to verify according to second.LCD replaces two kinds of show states of different driving state with the rule time interval.Figure 31 A and 31B represent to meet corresponding to the driving condition of two show states the position of high brightness subpixel and low-light level sub-pixel.Therefore, satisfy second requirement.
Require to verify according to the 3rd.In Figure 31 A and 31B, the sub-pixel of different intensity levels (that is, being expressed as the sub-pixel and the sub-pixel that is expressed as " d (secretly) " of " b (bright) ") is arranged by lineament.The demonstration problem is not seen in the visualization of LCD, for example because different brightness sub-pixel reduces resolution.Therefore, satisfy the 3rd requirement.
Require to verify according to the 4th.In Figure 31 A and 31B, the pixel of opposite polarity is arranged in lineament.Particularly, for example in Figure 31 A, the pixel at n+2 in the capable and m+2 row has "+" polarity.From this pixel, follow direction and column direction and between "-" and "+", change polarity every a pixel.For not satisfying the 4th LCD that requires, think and the driving polarity of pixel changes between "+" and "-" and sees flashing of display synchronously.But, when the LCD of sight check embodiment, can't see and flash.Therefore, satisfy the 4th requirement.
Require to verify according to the 5th.In Figure 31 A and 31B, the sub-pixel of observing same luminance level drives polarity, per two row sub-pixel (that is, every a pixel wide) inversion driving polarity.Particularly, for example in nB was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "-".In n+1_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "-".In n+1_B was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "+".In n+2_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "+".For not satisfying the 5th LCD that requires, think and the driving polarity of pixel changes between "+" and "-" and sees flashing of display synchronously.But, can't see during when sight check and to flash according to LCD of the present invention.Therefore, satisfy the 5th requirement.
When the LCD of observing by the amplitude VCSpp that changes CS voltage according to present embodiment, during oblique view, along with the inhibition (surpressed) that shows contrast, viewing angle characteristic improves, because the amplitude VCSpp of CS voltage increases (0V is used to support the common liquid crystals display except the LCD according to the present invention) from 0V.Although as if according to the image that shows, the raising of viewing angle characteristic is slightly different, when setting VCSpp so that VLCaddpp value the 0.5-2 of the LCD threshold voltage of common drive pattern (VCSpp is 0V) doubly within the time, the raising of then realization the best.
Generally, be 4 times of LCD horizontal scanning period the oscillation period that present embodiment might be set the oscillating voltage that imposes on the memory capacitance counter electrode, LCD improves viewing angle characteristic for the memory capacitance counter electrode by applying oscillating voltage, therefore, realizes that many pixels show.Even on the big LCD of high capacity electric capacity with CS bus and resistance, have on the high-resolution liquid crystal display of short horizontal scanning period or have high-speed driving and the LCD of short vertical, horizontal scanning period on, also realize many pixels demonstrations easily.
Next, with reference to Figure 32 structure and operation according to the LCD of third aspect present invention embodiment are described.
This embodiment realizes that by the twice that is set at horizontal scanning period oscillation period with the oscillating voltage of CS bus area shows than gray shade scale.Describe and concentrate on the following points with reference to the accompanying drawings.First structure that relates to LCD centers around the memory capacitance counter electrode of the memory capacitance of connexon pixel and the connection pattern between the CS bus.Second CS bus oscillation period and phase place that relates to according to the grid bus voltage waveform.Thirdly relate to driving and show state according to the sub-pixel of present embodiment.
Figure 32 is the synoptic diagram of expression according to the equivalent electrical circuit of the LCD of third aspect present invention embodiment, corresponding Figure 29.With the Reference numeral/symbolic representation identical of Figure 29 components identical, wherein describe and omit with Figure 29.LCD among Figure 32 is different from the LCD among Figure 29, and wherein it has CS main line CSVtypeB1 and the CSVtypeB2 and the connection status between CS main line and CS bus of two electrical isolations.
First that will note among Figure 32 is: the CS bus of the adjacent subpixels of pixel is electrically insulated from each other in the column direction adjacent lines.Especially for the capable sub-pixel CLCB_n of n, the CS bus CSBL_B_n of m and the sub-pixel CLCA_n+1 that is used for column direction adjacent lines pixel, the bus CSBL_A_n+1 of m is electrically insulated from each other.
Second that will note among Figure 32 is: each CS bus (CSBL) is connected on two CS main lines (CSVtypeB1 and CSVtypeB2) of dull and stereotyped end.That is, in LCD, the CS main line of two groups of electrical isolations is arranged according to present embodiment.
What will note among Figure 32 thirdly is: the connection status between CS bus and two CS main lines (trunk), that is, and along the distribution of the CS bus of column direction electrical isolation.According to the concatenate rule of CS bus among Figure 32 and CS main line, be connected to CS bus on CS main line CSVtypeB1 and the CSVtypeB2 shown in following table 3.
[table 3]
The CS main line The CS bus that connects the CS main line The general symbol(s) of the CS bus that draw on the left side
CSVtypeB1 CSBL_A_n， CSBL_A_n+1， CSBL_A_n+2， CSBL_A_n+3， … CSBL_A_n+k， (k＝0，1，2，3，…)
CSVtypeB2 CSBL_B_n， CSBL_B_n+1， CSBL_B_n+2， CSBL_B_n+3， … CSBL_B_n+k， (k＝0，1，2，3，…)
The CS bus of two groups of electrical isolations is connected respectively on two CS main lines shown in the top table 3.
Figure 33 A and 33B represent CS bus oscillation period and the phase place according to the grid bus voltage waveform, and the voltage of pixel electrode is shown.Figure 33 A and 33B are corresponding to Figure 30 A and the 30B of front embodiment.With the Reference numeral/symbolic representation identical with 30B of Figure 30 A and 30B components identical, wherein describe and omit with Figure 30 A.LCD generally is applied to direction of an electric field on the liquid crystal layer of each pixel with the counter-rotating of time interval of rule, therefore, needs to consider two types driving voltage waveform corresponding to direction of an electric field.Represent this driving condition of two types among Figure 33 A and the 33B respectively.
First that will note in Figure 33 A and 33B is: the voltage VCSVtypeB1 of CSVtypeB1 and CSVtypeB2 and the oscillation period of VCSVtypeB2 all are 2 times (2H) of horizontal scanning period.
Second that will note in Figure 33 A and 33B is: the phase place of VCSVtypeB1 and VCSVtypeB2 is as follows.At first, compare the phase place in the CS main line, VCSVtypeB2 is than the backward 1H of VCSVtypeB1.Next, observe the voltage of CS main line and the voltage of grid bus, the phase place of CS rail voltage and grid bus voltage is as follows.Shown in Figure 33 A and 33B, the time that becomes VgL corresponding to the voltage of the grid bus of each CS main line from VgH is consistent with the time that the flat of CS main line arrives their centers.In other words, the Td value among Figure 33 A and the 33B is 0.5H.But the Td value is greater than any value of OH less than 1H.
Here, the grid bus corresponding to each CS main line is the CS bus is connected identical pixel electrode with the TFT element through auxiliary capacitor CS CS main line and a grid bus.According to Figure 33 A and 33B, corresponding to expression in the grid bus of each the CS main line in this LCD and the CS bus table 2 below.
[table 4]
The CS main line Corresponding grid bus Corresponding C S bus
CSVtypeB1 GBL_n，GBL_n+1，GBL_n+2， GBL_n+3，GBL_n+4，… ................................ [GBL_n+k (k＝0，1，2，3，…)] CSBL_A_n，CSBL_A_n+1、CSBL_A_n+2， CSBL_A_n+3、CSBL_A_n+4，… ................................ [CSBL_A_n+k (k＝0，1，2，3，…)]
CSVtypeB2 GBL_n，GBL_n+1，GBL_n+2， GBL_n+3，GBL_n+4，… ................................ [GBL_n+k (k＝0，1，2，3，…)] CSBL_B_n，CSBL_B_n+1，CSBL_B_n+2， CSBL_B_n+3，CSBL_B_n+4，… ................................ [CSBL_B_n+k (k＝0，1，2，3，…)]
Although described the voltage cycle and the phase place of CS main line with reference to Figure 33 A and 33B, the voltage waveform of CS main line is not limited thereto.The CS main line can be other waveform that satisfies following two conditions.
First condition is: it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeB1 behind the VgL changes, and it is that voltage reduces that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeB2 behind the VgL changes.Figure 33 A satisfies this condition.
Second condition is: it is that voltage reduces that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeB1 behind the VgL changes, and it is that voltage raises that the voltage of corresponding grid bus becomes from VgH that first of voltage VCSVtypeB2 behind the VgL changes.Figure 33 B satisfies this condition.
Figure 34 A and 34B general introduction are according to the driving condition of the LCD of present embodiment.According to the polarity of sub-pixel driving voltage, the driving condition of LCD also is divided into two types, the situation shown in Figure 34 A and 34B.Driving condition among Figure 34 A is corresponding to the driving voltage waveform of Figure 33 A, and the state among Figure 34 B is corresponding to the driving condition of Figure 33 B driving voltage waveform.Figure 34 A and 34B are corresponding to Figure 31 A and the 31B of previous embodiment.
The lime light of Figure 34 A and 34B is whether to satisfy the requirement of area than gray shade scale plate.Area has five requirements than gray shade scale plate
First requirement is that each pixel is made up of a plurality of different brightness sub-pixels when showing the middle gray grade.
Second no matter to require be the time, and the different sub-pixel intensity level of brightness is constant.
The 3rd requirement is that the sub-pixel of different brightness is arranged fine.
The 4th requirement is that the pixel of opposite polarity in all frames is arranged fine.
The 5th requirement is that the sub-pixel of identical polar, same luminance level (especially the brightest sub-pixel) in all frames is arranged fine.
Require to verify according to first.In Figure 34 A and 34B, each pixel is made up of two different sub-pixels of brightness.Particularly, for example in Figure 34 A, the pixel of the capable and m row of n is by the high brightness subpixel that is expressed as " b (bright) " and be expressed as the low-light level sub-pixel of " d (secretly) " and form.Therefore, satisfy first requirement.
Require to verify according to second.The LCD of present embodiment replaces two kinds of show states of different driving state with the rule time interval.Figure 34 A and 34B represent to meet corresponding to the driving condition of two show states the position of high brightness subpixel and low-light level sub-pixel.Therefore, satisfy second requirement.
Require to verify according to the 3rd.In Figure 34 A and 34B, the sub-pixel of different intensity levels (that is, being expressed as the sub-pixel and the sub-pixel that is expressed as " d (secretly) " of " b (bright) ") is arranged by lineament.The demonstration problem is not seen in the visualization of LCD, for example because different brightness sub-pixel reduces resolution.Therefore, satisfy the 3rd requirement.
Require to verify according to the 4th.In Figure 34 A and 34B, the pixel of opposite polarity is arranged in lineament.Particularly, for example in Figure 34 A, the pixel at n+2 in the capable and m+2 row has "+" polarity.From this pixel, follow direction and column direction and between "-" and "+", change polarity every a pixel.For not satisfying the 4th LCD that requires, think and the driving polarity of pixel changes between "+" and "-" and sees flashing of display synchronously.But, when the LCD of sight check present embodiment, can't see and flash.Therefore, satisfy the 4th requirement.
Require to verify according to the 5th.In Figure 34 A and 34B, the sub-pixel of observing same luminance level drives polarity, per two row sub-pixel (that is, every a pixel wide) inversion driving polarity.Particularly, for example in n_B was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "-".In n+1_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "-".In n+1_B was capable, the sub-pixel in m+1, m+3 and m+5 row was " b (bright) ", and the polarity of all these sub-pixels is "+".In n+2_A is capable, be " b (bright) " in the pixel of m, m+2 and m+4 row, and the polarity of all these sub-pixels is "+".For not satisfying the 5th LCD that requires, think and the driving polarity of pixel changes between "+" and "-" and sees flashing of display synchronously.But, can't see during when sight check and to flash according to LCD of the present invention.Therefore, satisfy the 5th requirement.
When the LCD according to present embodiment is changed the amplitude VCSpp of CS voltage by people such as inventors, during oblique view, along with the inhibition that shows contrast, viewing angle characteristic improves, because the amplitude VCSpp of CS voltage increases (0V is used to support the common liquid crystals display except the LCD according to the present invention) from 0V.But, further increase the VSCpp value and have the problem that reduces the demonstration contrast.Therefore, the VSCpp value only is set to the scope that abundant raising viewing angle characteristic does not go wrong.Although as if according to the image that shows, the raising of viewing angle characteristic is slightly different, when setting VCSpp so that VLCaddpp value the 0.5-2 of the LCD threshold voltage of common drive pattern (VCSpp is 0V) doubly within the time, the raising of then realization the best.
Generally, it is 2 times of LCD horizontal scanning period that present embodiment might be set the oscillation period that imposes on the anti-counter electrode oscillating voltage of memory capacitance, LCD improves viewing angle characteristic for the memory capacitance counter electrode by applying oscillating voltage, therefore, realizes that many pixels show.Even on the big LCD of high capacity electric capacity with CS bus and resistance, have on the high-resolution liquid crystal display of short horizontal scanning period or have high-speed driving and the LCD of short vertical, horizontal scanning period on, also realize many pixels demonstrations easily.
Although in the above-described embodiments, CS main line electrical isolation (group) number is 4 or 2, is not limited to these according to CS main line electrical isolation (group) number of the LCD of invention third aspect embodiment, can be 3,5 or greater than 5.But it is even number that preferred electrical isolation CS main line is counted L.This is to exceed 180 oscillating voltages of spending phase places when (meaning that L is an even number) because of form the CS main line when electrical isolation CS main line to also supplying with mutually, may make the magnitude of current minimum that flows through the memory capacitance counter electrode.
Below the table 5 and 6 quantity L that is illustrated in electrical isolation CS main line be 6 or 8 situation, the CS main line relation of corresponding grid bus and CS bus.When L is even number, the relation of the CS main line of corresponding grid bus and CS bus be divided into roughly L/2 be odd number (L=2,6,10, situation 14...) and L/2 are even number (L=4,8,12, situations 16...).In L/2 is universal relation table 5 below in the situation of odd number, describe, and in L/2 is universal relation table 6 below in the situation of even number, describe, wherein L=8.
[table 5]
The CS main line Corresponding grid bus Corresponding CS bus
CSVtypeC1 GBL_n，GBL_n+3，GBL_n+6， GBL_n+9，GBL_n+12，… .................................. [GBL_n+3·k (k＝0，1，2，3，…)] CSBL_A_n，CSBL_A_n+3，CSBL_A_n+6， CSBL_A_n+9，CSBL_A_n+12，… .................................. [CSBL_A_n+3·k， (k＝0，1，2，3，…)]
CSVtypeC2 GBL_n，GBL_n+3，GBL_n+6， GBL_n+9，GBL_n+12，… .................................. [GBL_n+3·k (k＝0，1，2，3，…)] CSBL_B_n，CSBL_B_n+3，CSBL_B_n+G， CSBL_B_n+9，CSBL_B_n+12，… .................................. [CSBL_B_n+3·k (k＝0，1，2，3，…)]
CSVtypeC3 GBL_n+ 1，GBL_n+4，GBL_n+7， GBL_n+10，GBL_n+13、… .................................. [GBL_n+1+3·k (k＝0，1，2，3，…)] CSBL_A_n+1，CSBL_A_n+4， CSBL_A_n+7， CSBL_A_n+10，CSBL_A_n+13、… .................................. [CSBL_A_n+1+3·k (k＝0，1，2，3，…)]
CSVtypeC4 GBL_n+ 1，GBL_n+4，GBLn+7， GBL_n+10、GBL_n+13，… .................................. [GBL_n+1+3·k (k＝0，1，2，3，…)] CSBLB_n+1，CSBL_B_n+4， CSBL_Bn+7， CSBL_B_n+10，CSBL_B_n+13，… .................................. [CSBL_B_n+1+3·k (k＝0，1，2，3，…)]
CSVtypeC5 GBL_n+ 2，GBL_n+5，GBL_n+8， GBL_n+11，GBL_n+14，… .................................. [GBL_n+2+3·k (k＝0，1，2，3，…)] CSBL_A_n+2，CSBL_A_n+5， CSBL_A_n+8， CSBL_A_n+11，CSBL_A_n+14，… .................................. [CSBL_A_n+2+3·k (k＝0，1，2，3，…)]
CSVtypeC6 GBL_n+ 2，GBL_n+5，GBL_n+8， GBL_n+11，GBL_n+14，… .................................. [GBL_n+2+3·k (k＝0，1，2，3，…)] CSBL_B_n+2，CSBL_B_n+5， CSBL_B_n+8， CSBL_B_n+11，CSBL_B_n+14，… .................................. [CSBL_B_n+2+3·k (k＝0，1，2，3，…)]
When electrical isolation CS main line is counted 1/2 of L and is odd number, be L=2,6,10 etc., if the storage capacitance line that is connected on the memory capacitance counter electrode of first sub-pixel of pixel is expressed as CSBL_A_n, wherein pixel is arranged in any row and the place, point of crossing of the given capable n of row that forms in a plurality of pixels by the ranks arranged, if storage capacitance line on the memory capacitance counter electrode of second sub-pixel is expressed as CSBL_B_n and k is natural number (comprising 0) if be connected to:
CSBL_A_n+ (L/2) * k is connected on the first memory capacitance main line,
CSBL_B_n+ (L/2) * k is connected on the second memory capacitance main line,
CSBL_A_n+1+ (L/2) * k is connected on the 3rd memory capacitance main line,
CSBL_B_n+1+ (L/2) * k is connected on the 4th memory capacitance main line,
CSBL_A_n+2+ (L/2) * k is connected on the 5th memory capacitance main line,
CSBL_B_n+2+ (L/2) * k is connected on the 6th memory capacitance main line,
... repeat similarly to connect,
CSBL_A_n+ (L/2)-2+ (L/2) * k is connected on (L-3) memory capacitance main line,
CSBL_B_n+ (L/2)-2+ (L/2) * k is connected on (L-2) memory capacitance main line,
CSBL_A_n+ (L/2)-1+ (L/2) * k is connected on (L-1) memory capacitance main line,
CSBL_B_n+ (L/2)-1+ (L/2) * k is connected on the L memory capacitance main line.
[table 6]
The CS main line Corresponding grid bus Corresponding C S bus
CSVtypeD1 GBL_n，GBL_n+4，GBL_n+8， GBL_n+12，GBL_n+16，… ................................... [GBL_n+4·k (k＝0，1，2，3，…)] CSBL_A_n，CSBL_B_n+4，CSBL_A_n+8， CSBL_B_n+12，CSBL_A_n+16，… ................................... [CSBL_A_n+8·k，CSBL_B_n+4+8·k， (k＝0，1，2，3，…)]
CSVtypeD2 GBL_n，GBL_n+4，GBL_n+8， GBL_n+12，GBL_n+16，… ................................... [GBL_n+4·k (k＝0，1，2，3，…)] CSBL_B_n，GSBL_A_n+4，CSBL_B_n+8， CSBL_A_n+12，CSBL_B_n+16，… ................................... [CSBL_B_n+8·k，CSBL_A_n+4+8·k (k＝0，1，2，3，…)]
CSVtypeD3 GBL_n+ 1，GBL_n+5，GBL_n+9， GBL_n+13，GBL_n+17，… ................................... [GBL_n+1+4·k (k＝0，1，2，3，…)] CSBL_A_n+1，CSBL_B_n+5，CSBL_A_n+9， CSBL_B_n+13，CSBL_A_n+17、… ................................... [CSBL_A_n+1+8·k，CSBL_B_n+5+B·k， (k＝0，1，2，3，…)]
CSVtypeD4 GBL_n+ 1，GBL_n+5，GBL_n+9， GBL_n+13，GBL_n+17，… ................................... [GBL_n+1+4·k (k＝0，1，2，3，…)] CSBL_B_n+1，CSBL_A_n+5，CSBL_B_n+9， CSBL_A_n+13，CSBL_B_n+17，… ................................... [CSBL_B_n+1+8·k，CSBL_A_n+5+8·k (k＝0，1，2，3，…)]
CSVtypeD5 GBL_n+ 2，GBL_n+6， GBL_n+10， GBL_n+14，GBL_n+18，… ................................... [GBL_n+2+4·k (k＝0，1，2，3，…)] CSBL_A_n+2，CSBL_B_n+6，CSBL_A_n+10， CSBL_B_n+14，CSBL_A_n+18，… ................................... [CSBL_A_n+2+8·k，CSBL_B_n+6+8·k (k＝0，1，2，3，…)]
CSVtypeD6 GBL_n+ 2，GBL_n+G， GBL_n+10， GBL_n+14，GBL_n+18，… ................................... [GBL_n+2+4·k (k＝0，1，2，3，…)] CSBL_B_n+2，CSBL_A_n+6，CSBL_B_n+10， CSBL_A_n+14，CSBL_B_n+1B，… ................................... [CSBL_B_n+2+8·k，CSBL_A_n+6+8·k (k＝0，1，2，3，…)]
CSVtypeD7 GBL_n+ 3，GBL_n+7、GBL_n+11， GBL_n+15，GBL_n+19，… ................................... [GBL_n+3+4·k (k＝0，1，2，3，…)] CSBL_A_n+3，CSBL_B_n+7，CSBL_A_n+11， CSBL_B_n+15，CSBL_A_n+19，… ................................... [CSBL_A_n+3+8·k，CSBL_B_n+7+B·k (k＝0，1，2，3，…)]
CSVtypeC8 GBL_n+ 3，GBL_n+7，GBL_n+11， GBL_n+15，GBL_n+19，… ................................... [GBL_n+3+4·k (k＝0，1，2，3，…)] CSBL_B_n+3，CSBL_A_n+7，CSBL_B_n+11、 CSBL_A_B+15，CSBL_B_n+19，… ................................... [CSBL_B_n+3+8·k，CSBL_A_n+7+8·k (k＝0，1，2，3，…)]
When electrical isolation memory capacitance main line is counted 1/2 of L and is even number, promptly, L=4,8,12 etc., if the storage capacitance line that is connected on the memory capacitance counter electrode of first sub-pixel of pixel is expressed as CSBL_A_n, wherein pixel is arranged in any row and the place, point of crossing of the given capable n of row that forms in a plurality of pixels by the ranks arranged, storage capacitance line on the memory capacitance counter electrode of second sub-pixel is expressed as CSBL_B_n and if k is natural number (comprising 0) if be connected to:
CSBL_A_n+L*k and CSBL_B_n+ (L/2)+L*k is connected on the first memory capacitance main line,
CSBL_B_n+L*k and CSBL_A_n+ (L/2)+L*k is connected on the second memory capacitance main line,
CSBL_A_n+1+L*k and CSBL_B_n+ (L/2)+1+L*k is connected on the 3rd memory capacitance main line,
CSBL_B_n+1+L*k and CSBL_A_n+ (L/2)+1+L*k is connected on the 4th memory capacitance main line,
CSBL_A_n+2+L*k and CSBL_B_n+ (L/2)+2+L*k is connected on the 5th memory capacitance main line,
CSBL_B_n+2+L*k and CSBL_A_n+ (L/2)+2+L*k is connected on the 6th memory capacitance main line,
CSBL_A_n+3+L*k and CSBL_B_n+ (L/2)+3+L*k is connected on the 7th memory capacitance main line,
CSBL_B_n+3+L*k and CSBL_A_n+ (L/2)+3+L*k is connected on the 8th memory capacitance main line,
... repeat similarly to connect,
CSBL_A_n+ (L/2)-2+ (L/2) * k and CSBL_B_n+L-2+L*k are connected on (L-3) memory capacitance main line,
CSBL_B_n+ (L/2)-2+ (L/2) * k and CSBL_A_n+L-2+L*k are connected on (L-2) memory capacitance main line,
CSBL_A_n+ (L/2)-1+ (L/2) * k and CSBL_B_n+L-1+L*k are connected on (L-1) memory capacitance main line,
CSBL_B_n+ (L/2)-1+ (L/2) * k and CSBL_A_n+L-1+L*k are connected on the L memory capacitance main line.
As mentioned above, a third aspect of the present invention makes uses many pixel liquid crystal display easily, it is watched during the LCD of big LCD, high-resolution liquid crystal display and high-speed driving and short vertical, horizontal scanning period in inclination, can improve the demonstration contrast widely.Because be applied to voltage oscillation cycle on the CS bus by increase, following point may be arranged easily: increase the waveform that oscillating voltage is applied to the size of many pixel liquid crystal display of CS bus, the load capacitance that increases the CS bus and resistance, passivation CS bus voltage; With the resolution and the actuating speed that increase LCD, reduce the CS bus oscillation period, increase the influence of waveform passivation and cause the effective value significant change of VLCadd in the display screen, therefore cause show irregular.
In the LCD according to second aspect present invention embodiment, it makes the public CS bus of electricity consumption be used for the adjacent subpixels of adjacent lines pixel, and adopts the CS main line of two groups of electrical isolations, and be 1H the oscillation period of CS bus voltage.On the other hand, LCD according to third aspect present invention embodiment, it uses electrical isolation CS bus to be used for the adjacent subpixels of adjacent lines pixel, when using the CS main line of two groups of electrical isolations, can be set at 2H the oscillation period of CS bus voltage, when using the CS main line of four groups of electrical isolations, can be set at 4H the oscillation period of CS bus voltage.
Structure or drive waveforms according to the LCD of third aspect present invention embodiment, by using electrical isolation CS main line, the adjacent subpixels that is used for the adjacent lines pixel, and adopt L group insulation CS main line, can be set at L times of horizontal scanning period (LHs) oscillation period of CS bus.
To describe below according to the LCD of fourth aspect present invention embodiment and its driving method.
As mentioned above, LCD according to third aspect present invention embodiment, use the memory capacitance counter electrode (the CS main line of L electrical isolation) of L group electrical isolation, can will be applied to L that oscillating voltage on the memory capacitance counter electrode is set at horizontal scanning period oscillation period doubly.With the memory capacitance counter electrode line of heavy electric loading, may realize on big high-resolution liquid crystal display that many pixels show like this.
But the embodiment of the third aspect need use the memory capacitance counter electrode of electrical isolation, is used for the sub-pixel (that is, two pixels of adjacent lines) (for example, referring to Figure 29) at two neighbors of column direction, and meaning each pixel needs two CS buses.There is the problem that reduces the pixel aperture ratio like this.Particularly, for example, shown in Figure 35 A, the CS bus that is used for sub-pixel is arranged in the structure at the center of each sub-pixel, makes it need provide black matrix B M1 to prevent by the light leak between the column direction neighbor.Therefore, the area of two CS buses and black matrix crossover can not be used for showing.This has just reduced the pixel aperture ratio.
On the contrary, according to the embodiment of fourth aspect, shown in Figure 35 B, two adjacent subpixels of two different pixels of adjacent column direction have the memory capacitance counter electrode that connects public CS bus, the CS bus allows to be arranged between the column direction neighbor, therefore makes the CS bus also play black matrix.Compare with the structure of Figure 35 A, have the advantage that can reduce the CS number of buses, by the aperture ratio that the black matrix B M1 that separately provides has in addition improved pixel is provided.
With regard to regard to the LCD of third aspect embodiment, the L that is set at horizontal scanning period oscillation period for the oscillating voltage that will be applied to the CS bus doubly requires to use L electrical isolation CS main line, requires L driving power supply memory capacitance counter electrode.As a result, increase the oscillating voltage oscillation period that imposes on the CS bus on demand, thereby the driving power number that needs to increase the quantity of CS main line and supply with the memory capacitance counter electrode.Like this, use the LCD according to third aspect embodiment, being applied in increase has certain restriction aspect cycle of the oscillating voltage on the CS bus, because the driving power number that needs to increase CS main line number and supply with the memory capacitance counter electrode.
On the contrary, with regard to regard to the LCD of fourth aspect present invention embodiment, when electrical isolation CS main line number is L (L is an even number), can be set at 2*K*L times (K is a positive integer) of horizontal scanning period the oscillation period of oscillating voltage.
Therefore, be more suitable for big high-resolution liquid crystal display according to the LCD beguine of fourth aspect present invention embodiment according to the LCD of third aspect embodiment.
The embodiment that below description is related to fourth aspect present invention introduces the LCD example that realizes driving condition shown in 36A and 36B.The direction of an electric field that is applied on the pixel liquid crystal layer is opposite between Figure 36 A that corresponds respectively to Figure 24 A and 24B and 36B.Use description to realize the structure of driving condition shown in Figure 36 A below.Incidentally, in order to implement the driving condition shown in Figure 36 B, be applied to the polarity of voltage of power lead and memory capacitance polarity of voltage and can use the same way as of describing with reference to Figure 23 A and 23B from the reversal of poles shown in Figure 36 A.Like this might be with the first and second sub-pixel fix in position (being " b (bright) " or " d (secretly) " among the figure), simultaneously, the demonstration polarity (being "+" or "-" among the figure) of counter-rotating pixel.But, the invention is not restricted to this, only allow to be applied to the voltage reversal of power bus.In this case, because first and second sub-pixels change position (being " b (bright) " or " d (secretly) " among the figure) in company with the counter-rotating of pixel polarity, therefore when location of pixels fixedly the time, may alleviate the problems such as bleeding that in middle gray grade procedure for displaying, run into.
In LCD according to following embodiment, shown in Figure 35 B, the public CS bus CSBL that is provided with between column direction two adjacent pixels (n capable and (n+1) OK) the pixel electrode 18b of the capable pixel of public n and the pixel electrode 18a of the capable pixel of n+1 is so that supply with memory capacitance inverse voltage (oscillating voltage) auxiliary capacitor of sub-pixel.Public CS bus CSBL also plays the effect of black matrix, passes through to stop the light between capable and (n+1) row pixel of n.Public CS bus CSBL is provided with like this: promptly, and through dielectric film part crossover pixel electrode 18a and 18b.
Below basis, draw in the LCD of the embodiment that makes example, be longer than horizontal scanning period and electrical isolation CS main line quantity oscillation period when being L (L is an even number) when the oscillating voltage that is applied to the CS bus, the 2*K*L that the oscillating voltage that is applied to the CS bus can be set at a horizontal scanning period (K is a positive integer) oscillation period doubly.Promptly, although the LCD according to third aspect present invention embodiment allows only to be set to L the oscillation period of oscillating voltage doubly, but the LCD according to fourth aspect present invention embodiment has the advantage that allows further to increase by coefficient 2*K oscillation period, and wherein K does not depend on the quantity of electrical isolation CS main line.K depends between single electrical isolation CS main line and the CS bus parameter that connects pattern, and equal to connect the public CS main line in the continuous CS bus CS number of buses (electrical equivalent CS bus) 1/2, the CS bus constitutes the one-period that connects the CS main line.
Many pixel drive according to the LCD of the embodiment of the invention are divided into two sub-pixels with each pixel, and different oscillating voltage (memory capacitance inverse voltage) is supplied with the auxiliary capacitor that connects each sub-pixel, therefore obtain transom pixel and dark sub-pixel.For example, be that voltage raises if TFT closes first variation of back oscillating voltage, the transom pixel then appears, and on the contrary, be that voltage reduces if TFT closes first variation of back oscillating voltage, dark sub-pixel then appears.Therefore, be connected to public CS main line if be used for the CS bus of the sub-pixel that oscillating voltage should raise after TFT closes, and the CS bus that is used for the sub-pixel that oscillating voltage should reduce after TFT closes just is connected to another public CS main line, then may reduce CS main line quantity.K is that expression is by connecting the parameter that pattern increases the cycle effect between CS bus and the CS main line.
By increasing the K value, may correspondingly increase oscillating voltage.But preferred K value is not too big.Below reason will be described.
The increase of K value has increased the number of sub-pixels that connects public CS main line.They connect different TFT, and it is closed with different intervals (multiple of 1H).Therefore, be connected on the public CS main line and be connected on the public CS main line to increase (or minimizing) the required time of another sub-pixel oscillating voltage of the very first time after sub-pixel TFT closes to increase (or minimizing) the required time of sub-pixel oscillating voltage of the very first time after sub-pixel TFT closes, to be different from.The increase of this mistiming with the K value increases, that is, increase with the increase that is connected to the CS bus number on the public CS main line.This can cause the irregular vision of linear luminance.Irregular in order to prevent this brightness, be not more than 5% of number of scanning lines (number of lines of pixels) with the preferred mistiming of empirical method.For example, in the XGA situation, preferred K value is set the mistiming for and is not more than 768 capable 5% or be not more than 38H.In the same manner, the low limit in oscillating voltage cycle should wait with reference to Figure 28 to be set, and it is irregular can not produce the brightness that causes owing to the waveform passivation like this.For example, in the situation of 45 inches XGA displays,, then there is not the problem of waveform passivation if be 12H or bigger oscillation period.Therefore, in the situation of 45 inches LCD, if K is set at 1 or 2, L is set at 6,8,10, or 12, the cycle of oscillating voltage is set within 12H-48H, then may realize not having the irregular high-quality display of brightness.In the same manner, consider oscillating voltage power supply (supplying with the driving power of memory capacitance counter electrode) number, electrical isolation CS main line is counted L should stipulate the first-class wiring of plate (TFT substrate).
Liquid Crystal Display And Method For Driving according to fourth aspect present invention embodiment will be described below, in quoting example, K=1, L=4,6,8,10, or 12, in example, K=2, L=4 or 6.For fear of repeating the content that front embodiment has described, following description concentrates on the layout between CS bus and the CS main line.
[K=1, L=4, oscillation period=8H]
The matrix structure of LCD according to the present invention (the connection pattern of CS bus) as shown in figure 37, the signal waveform that is used to drive LCD is as shown in figure 38.And the connection pattern that is used for Figure 37 is shown in the table 7.With matrix structure shown in Figure 37,, therefore realized the driving condition shown in Figure 35 A because use the timing shown in 38 that oscillating voltage is applied on the CS bus.
In Figure 37, each CS bus is connected on all four CS main lines that are arranged on the left and right two ends of figure.Therefore, four groups of electrical isolation CS buses are arranged, so L=4.And in Figure 37, the pattern that connects between CS bus and the CS main line has some rule, that is, per in the drawings 8 CS buses repeat identical pattern.Therefore, K=1 (=8/ (2L)).
[table 7]
L＝4，K＝1
CS thousand lines The CS bus that connects the CS main line
M1a CSBL_(n—1)B，(n)A CSBL_(n+4)B，(n+5)A
M2a CSBL_(n)B，(n+1)A CSBL_(n+3)B，(n+4)A
M3a CSBL_(n+1)B，(n+2)A CSBL_(n+6)B，(n+7)A
M4a CSBL_(n+2)B，(n+3)A CSBL_(n+5)B，(n+6)A
N=1 wherein, 9,17 ...
As can be seen from Table 7, the CS bus among Figure 37 is divided into two types, that is:
Any p is satisfied the α type of following expression formula
CSBL_(p)B，(p+1)A
CSBL_(p+5)B，(p+6)A
With the β type that any p is satisfied following expression formula
CSBL_(p+1)B，(p+2)A
CSBL_(p+4)B，(p+5)A
Particularly, the CS bus that connects CS main line M1a and M3a is the α type, and the CS bus of connection CS main line M2a and M4a is the β type.
Being used for 8 continuous CS buses that connect the cycle is made up of 4 α type buses (two buses and two connecting bus that are connected M3a that connect M1a) and 4 β type buses (two buses and two connecting bus that are connected M4a that are connected M2a).
Utilize parameter L and K, top expression formula can followingly provide any p:
CSBL_(p+2*(K—1))B，(p+2*(K—1)+1)A
CSBL_(p+2*(K—1)+K*L+1)B，(p+2*(K—1)+K*L+2)A
Or
CSBL_(p+2*(K—1)+1)B，(p+2*(K—1)+2)A
CSBL_(p+2*(K—1)+K*L)B，(p+2*(K—1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....Because there is not the CS bus to satisfy two α types and β type, therefore introduce this condition.
In the same manner, be 8H the oscillating voltage oscillation period that is applied to the CS bus in Figure 38 as can be seen, that is, the 2*K*L of horizontal scanning period doubly.
[K=1, L=6, oscillation period=12H]
Supposing has 6 groups of electrical isolation CS buses, connects pattern as shown in figure 39, and drive waveforms as shown in figure 40.And the connection pattern that is used for Figure 39 is shown in the table 8.
In Figure 40, each CS bus is connected on all 6 CS main lines that are arranged on the left and right two ends of figure.Therefore, 6 groups of electrical isolation CS buses, L=6 are as a result arranged.
And, in Figure 39, some rule of connection pattern between CS bus and CS main line, that is, per in the drawings 12 CS buses repeat identical connection pattern.Therefore, K=1 (=12/ (2L)).
[table 8]
L＝4，K＝1
The CS main line The CS bus that connects CS thousand lines
M1a CSBL_(n1)B，(n)A CSBL_(n+4)B，(n+5)A
M2a CSBL_(n)B，(n+1)A CSBL_(n+3)B，(n+4)A
M3a CSBL_(n+1)B，(n+2)A CSBL_(n+6)B，(n+7)A
M4a CSBL_(n+2)B，(n+3)A CSBL_(n+5)B，(n+6)A
N=1 wherein, 9,17 ..
As can be seen from Table 8, the CS bus among Figure 39 is that electricity equates in each group that following expression formula groups by all are represented:
CSBL_(p)B，(p+1)A
CSBL_(p+7)B，(p+8)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+6)B，(p+7)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL_(p+2*(K—1))B，(p+2*(K—1)+1)A
CSBL_(p+2*(K—1)+K*L+1)B，(p+2*(K—1)+K*L+2)A
Or
CSBL_(p+2*(K—1)+1)B，(p+2*(K—1)+2)A
CSBL_(p+2*(K—1)+K*L)B，(p+2*(K—1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 40, be 12H the oscillating voltage oscillation period that is applied to as can be seen on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
[K=1, L=8, oscillation period=16H]
Supposing has 8 groups of electrical isolation CS buses, connects pattern as shown in figure 41, and drive waveforms as shown in figure 42.And the connection pattern that is used for Figure 41 is shown in the table 9.
In Figure 41, each CS bus is connected on all 8 CS main lines that are arranged on the left and right two ends of figure.Therefore, 8 groups of electrical isolation CS buses, L=8 are as a result arranged.
And in Figure 41, the connection pattern between CS bus and CS main line has some rule, that is, per in the drawings 16 CS buses repeat identical connection pattern.Therefore, K=1 (=16/ (2L)).
[table 9]
L＝8，K＝1
The CS main line The CS bus that connects the CS main line
M1c CSBL_(n—1)B，(n)A CSBL_(n+8)B，(n+9)A
M2c CSBL_(n)B，(n+1)A CSBL_(n+7)B，(n+8)A
M3c CSBL_(n+1)B，(n+2)A CSBL_(n+10)B，(n+11)A
M4c CSBL_(n+2)B，(n+3)A CSBL_(n+9)B，(n+10)A
M5c CSBL_(n+3)B，(n+4)A CSBL_(n+12)B，(n+13)A
M6c CSBL_(n+4)B，(n+5)A CSBL_(n+11)B，(n+12)A
M7c CSBL_(n+5)B，(n+6)A CSBL_(n+14)B，(n+15)A
M8c CSBL_(n+6)B，(n+7)A CSBL_(n+13)B，(n+14)A
N=1 wherein, 17,33 ...
As can be seen from Table 9, the CS bus among Figure 41 is that electricity equates in each group that following expression formula groups by all are represented:
CSBL_(p)B，(p+1)A
CSBL_(p+9)B，(p+10)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+8)B，(p+9)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL_(p+2*(K—1))B，(p+2*(K—1)+1)A
CSBL_(p+2*(K—1)+K*L+1)B，(p+2*(K—1)+K*L+2)A
Or
CSBL_(p+2*(K—1)+1)B，(p+2*(K—1)+2)A
CSBL_(p+2*(K—1)+K*L)B，(p+2*(K—1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 42, be 16H the oscillating voltage oscillation period that is applied to as can be seen on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
[K=1, L=10, oscillation period=20H]
Supposing has 10 groups of electrical isolation CS buses, connects pattern as shown in figure 43, and drive waveforms as shown in figure 44.And the connection pattern that is used for Figure 43 is shown in the table 10.
In Figure 43, each CS bus is connected on all 10 CS main lines that are arranged on the left and right two ends of figure.Therefore, 10 groups of electrical isolation CS buses, L=10 are as a result arranged.And in Figure 43, the connection pattern between CS bus and CS main line has some rule, that is, per in the drawings 20 CS buses repeat identical connection pattern.Therefore, K=1 (=20/ (2L)).
[table 10]
L＝10，K＝1
The CS main line The CS bus that connects the CS main line
M1d CSBL_(n—1)B，(n)A CSBL_(n+10)B，(n+11)A
M2d CSBL_(n)B，(n+1)A CSBL_(n+9)B，(n+10)A
M3d CSBL_(n+1)B，(n+2)A CSBL_(n+12)B，(n+13)A
M4d CSBL_(n+2)B，(n+3)A CSBL_(n+11)B，(n+12)A
M5d CSBL_(n+3)B，(n+4)A CSBL_(n+14)B，(n+15)A
M6d CSBL_(n+4)B，(n+5)A CSBL_(n+13)B，(n+14)A
M7d CSBL_(n+5)B，(n+6)A CSBL_(n+16)B，(n+17)A
M8d CSBL_(n+6)B，(n+7)A CSBL_(n+15)B，(n+16)A
M9d CSBL_(n+7)B，(n+6)A CSBL_(n+18)B，(n+19)A
M10d CSBL_(n+8)B，(n+7)A CSBL_(n+17)B，(n+18)A
N=1 wherein, 21,41 ...
As can be seen from Table 10, the CS bus among Figure 43 is that electricity equates in each group that following expression formula groups by all are represented:
CSBL_(p)B，(p+1)A
CSBL_(p+11)B，(p+12)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+10)B，(p+11)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL_(p+2*(K—1))B，(p+2*(K—1)+1)A
CSBL_(p+2*(K—1)+K*L+1)B，(p+2*(K—1)+K*L+2)A
Or
CSBL_(p+2*(K—1)+1)B，(p+2*(K—1)+2)A
CSBL_(p+2*(K—1)+K*L)B，(p+2*(K—1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 44, be 20H the oscillating voltage oscillation period that is applied to as can be seen on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
[K=1, L=12, oscillation period=24H]
Supposing has 12 groups of electrical isolation CS buses, connects pattern as shown in figure 45, and drive waveforms as shown in figure 46.And the connection pattern that is used for Figure 45 is shown in the table 11.
In Figure 45, each CS bus is connected on all 12 CS main lines that are arranged on the left and right two ends of figure.Therefore, 12 groups of electrical isolation CS buses, L=12 are as a result arranged.And in Figure 45, the connection pattern between CS bus and CS main line has some rule, that is, per in the drawings 24 CS buses repeat identical connection pattern.Therefore, K=1 (=24/ (2L)).
[table 11]
L＝12，K＝1
The CS main line The CS bus that connects CS thousand lines
M1e CSBL_(n—1)B，(n)A CSBL_(n+12)B，(n+13)A
M2e CSBL_(n)B，(n+1)A CSBL_(n+11)B，(n+12)A
M3e CSBL_(n+1)B，(n+2)A CSBL_(n+14)B，(n+15)A
M4e CSBL_(n+2)B，(n+3)A CSBL_(n+13)B，(n+14)A
M5e CSBL_(n+3)B，(n+4)A CSBL_(n+16)B，(n+17)A
M6e CSBL_(n+4)B，(n+5)A CSBL_(n+15)B，(n+16)A
M7e CSBL_(n+5)B，(n+6)A CSBL_(n+18)B，(n+19)A
M8e CSBL_(n+6)B，(n+7)A CSBL_(n+17)B，(n+18)A
M9e CSBL_(n+7)B，(n+6)A CSBL_(n+20)B，(n+21)A
M10e CSBL_(n+8)B，(n+7)A CSBL_(n+19)B，(n+20)A
M11e CSBL_(n+9)B，(n+10)A CSBL_(n+22)B，(n+23)A
M12e CSBL_(n+10)B，(n+11)A CSBL_(n+21)B，(n+22)A
N=1 wherein, 25,49 ...
As can be seen from Table 11, the CS bus among Figure 45 is that electricity equates in each group that following expression formula groups by all are represented:
CSBL_(p)B，(p+1)A
CSBL_(p+13)B，(p+14)A
Or
CSBL(p+1)B，(p+2)A
CSBL_(p+12)B，(p+13)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL(p+2*(K—1))B，(p+2*(K—1)+1)A
CSBL_(p+2*(K—1)+K*L+1)B，(p+2*(K—1)+K*L+2)A
Or
CSBL(p+2*(K—1)+1)B，(p+2*(K—1)+2)A
CSBL_(p+2*(K—1)+K*L)B，(p+2*(K—1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 46, be 24H the oscillating voltage oscillation period that is applied to as can be seen on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
In all said circumstanceses, parameter K=1.Now, characterising parameter value K is 2 situation.
[K=2, L=4, oscillation period=16H]
Suppose that parameter value K is 2 and 4 groups of electrical isolation CS buses are arranged, connect pattern as shown in figure 47, drive waveforms as shown in figure 48.And the connection pattern that is used for Figure 47 is shown in the table 12.
In Figure 47, each CS bus is connected on all 4 CS main lines that are arranged on the left and right two ends of figure.Therefore, 4 groups of electrical isolation CS buses, L=4 are as a result arranged.And in Figure 47, the connection pattern between CS bus and CS main line has some rule, that is, per in the drawings 16 CS buses repeat identical connection pattern.Therefore, K=1 (=16/ (2L)).
[table 12]
L＝4，K＝2
The CS main line The CS bus that connects the CS main line
M1f CSBL_(n—1)B，(n)A CSBL_(n+1)B，(n+2)A CSBL_(n+8)B，(n+9)A CSBL_(n+10)B(n+11)A
M2f CSBL_(n)B，(n+1)A CSBL_(n+2)B，(n+3)A CSBL_(n+7)B，(n+8)A CSBL_(n+9)B(n+10)A
M3f CSBL_(n+3)B，(n+4)A CSBL_(n+5)B，(n+6)A CSBL_(n+12)B，(n+13)A CSBL_(n+14)B(n+15)A
M4f CSBL_(n+4)B，(n+5)A CSBL_(n+6)B，(n+7)A CSBL_(n+11)B，(n+12)A CSBL_(n+13)B(n+14)A
N=1 wherein, 17,33 ...
As can be seen from Table 12, the CS bus among Figure 47 is that electricity equates in each group that following expression formula groups by all are represented:
CSBL_(p)B，(p+1)A
CSBL_(p+2)B，(p+3)A
With
CSBL_(p+9)B，(p+10)A
CSBL_(p+11)B，(p+12)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+3)B，(p+4)A
With
CSBL_(p+8)B，(p+9)A
CSBL_(p+10)B，(p+11)A
P=1 wherein, 3,5 ... or P=0), 2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows: CSBL_ (p+2* (1-1)) B, (p+2* (1-1)+1) A
CSBL_(p+2*(K—1))B，(p+2*(K—1)+1)A
With
CSBL_(p+2*(1—1)+K*L+1)B，(p+2*(1—1)+K*L+2)A
CSBL_(p+2*(K—1)+K*L+1)B，(p+2*(K—1)+K*L+2)A
Or
CSBL_(p+2*(1—1)+1)B，(p+2*(1—1)+2)A
CSBL_(p+2*(K—1)+1)B，(p+2*(K—1)+2)A
With
CSBL_(p+2*(1—1)+K*L)B，(p+2*(1—1)+K*L+1)A
CSBL_(p+2*(K—1)+K*L)B，(p+2*(K—1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 48, be 16H the oscillating voltage oscillation period that is applied to as can be seen on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
[K=2, L=6, oscillation period=24H]
Suppose that parameter value K is 2 and 6 groups of electrical isolation CS buses are arranged, connect pattern as shown in figure 49, drive waveforms as shown in figure 50.And the connection pattern that is used for Figure 49 is shown in the table 13.
In Figure 49, each CS bus is connected on all 6 CS main lines that are arranged on the left and right two ends of figure.Therefore, 6 groups of electrical isolation CS buses, L=6 are as a result arranged.And in Figure 47, the connection pattern between CS bus and CS main line has some rule, that is, per in the drawings 24 CS buses repeat identical connection pattern.Therefore, K=1 (=24/ (2L)).
[table 13]
L＝6，K＝2
The CS main line The CS bus that connects the CS main line
M1g CSBL_(n—1)B，(n)A CSBL_(n+1)B，(n+2)A CSBL_(n+12)B，(n+13)A CSBL_(n+14)B(n+15)A
M2g CSBL_(n)B，(n+1)A CSBL_(n+2)B，(n+3)A CSBL_(n+11)B，(n+12)A CSBL_(n+13)B(n+14)A
M3g CSBL_(n+3)B，(n+4)A CSBL_(n+5)B，(n+6)A CSBL_(n+16)B，(n+17)A CSBL_(n+18)B(n+19)A
M4g CSBL_(n+4)B，(n+5)A CSBL_(n+6)B，(n+7)A CSBL_(n+15)B，(n+16)A CSBL_(n+17)B(n+18)A
N5g CSBL_(n+7)B，(n+8)A CSBL_(n+9)B，(n+10)A CSBL_(n+20)B，(n+21)A CSBL_(n+22)B(n+23)A
N6g CSBL_(n+8)B，(n+9)A CSBL_(n+10)B，(n+11)A CSBL_(n+19)B，(n+20)A CSBL_(n+21)B(n+22)A
N=1 wherein, 25,49 ..
As can be seen from Table 13, the CS bus among Figure 49 is that electricity equates in each group that following expression formula groups by all are represented:
CSBL_(p)B，(p+1)A
CSBL_(p+2)B，(p+3)A
With
CSBL_(p+13)B，(p+14)A
CSBL_(p+15)B，(p+16)A
Or
CSBL_(p+1)B，(p+2)A
CSBL_(p+3)B，(p+4)A
With
CSBL_(p+12)B，(p+13)A
CSBL_(p+14)B，(p+15)A
P=1 wherein, 3,5 ... or P=0,2,4 ...
Utilize parameter L and K, for any p, above-mentioned expression formula can be given as follows:
CSBL_(p+2*(1—1))B，(p+2*(1—1)+1)A
CSBL_(p+2*(K—1))B，(p+2*(K—1)+1)A
With
CSBL_(p+2*(1—1)+K*L+1)B，(p+2*(1—1)+K*L+2)A
CSBL_(p+2*(K—1)+K*L+1)B，(p+2*(K—1)+K*L+2)A
Or
CSBL_(p+2*(1—1)+1)B，(p+2*(1—1)+2)A
CSBL_(p+2*(K—1)+1)B，(p+2*(K—1)+2)A
With
CSBL_(p+2*(1—1)+K*L)B，(p+2*(1—1)+K*L+1)A
CSBL_(p+2*(K—1)+K*L)B，(p+2*(K—1)+K*L+1)A
Therefore, make by the CS bus electricity in each CS bus group of each expression of above-mentioned expression formula group to equate it is enough, P=1 wherein, 3,5 ... or p=0,2,4 ....
In the same manner, in Figure 50, be 24H the oscillating voltage oscillation period that is applied to as can be seen on the CS bus, that is, the 2*K*L of horizontal scanning period doubly.
About parameter K and L, although described above at K=1 and L=4,6,8,10, or 12 situation and in the situation of K=2 and L=4 or 6, fourth aspect present invention embodiment is not limited thereto.
The K value only need be a positive integer, i.e. K=1, and 2,3,4,5,6,7,8,9 etc., the L value only need be an even number, i.e. L=2,4,6,8,10,12,14,16,18 etc.In addition, K value and L value can be set in scope separately independently.
About the connection between CS main line and the CS bus, follow above-mentioned rule.
Particularly when the value of parameter K and L respectively (K=K when L=L) being K and L, is connected to the CS bus on the identical main line, that is, electrical equivalent CS bus should be as follows:
CSBL_(p+2*(1—1))B，(p+2*(1—1)+1)A
CSBL_(p+2*(2—1))B，(p+2*(2—1)+1)A
CSBL_(p+2*3—1))B，(p+2*(3—1)+1)A
…
CSBL_(p+2*(K—1))B，(p+2*(K—1)+1)A
With
CSBL_(p+2*(1—1)+K*L+1)B，(p+2*(1—1)+K*L+2)A
CSBL_(p+2*(2—1)+K*L+1)B，(p+2*(2—1)+K*L+2)A
CSBL_(p+2*(3—1)+K*L+1)B，(p+2*(3—1)+K*L+2)A
…
CSBL_(p+2*(K—1)+K*L+1)B，(p+2*(K—1)+K*L+2)A
Or
CSBL_(p+2*(1—1)+1)B，(p+2*(1—1)+2)A
CSBL_(p+2*(2—1)+1)B，(p+2*(2—1)+2)A
CSBL_(p+2*(3—1)+1)B，(p+2*(3—1)+2)A
…
CSBL_(p+2*(K—1)+1)B，(p+2*(K—1)+2)A
With
CSBL_(p+2*(1—1)+K*L)B，(p+2*(1—1)+K*L+1)A
CSBL_(p+2*(2—1)+K*L)B，(p+2*(2—1)+K*L+1)A
CSBL_(p+2*(3—1)+K*L)B，(p+2*(3—1)+K*L+1)A
…
CSBL_(p+2*(K—1)+K*L)B，(p+2*(K—1)+K*L+1)A
P=1 wherein, 3,5 etc., or p=0,2,4 etc.
And (K=K, when L=L) being K and L, the 2*K*L that is applied to oscillating voltage on the bus CS and can is oscillation period horizontal scanning period doubly respectively as parameter K and L.
In the same manner, although in the superincumbent description, first sub-pixel of an adjacent image element and the public public CS bus of second sub-pixel of another image component, certainly, they can use the different CS buses of electrical equivalent.
A first aspect of the present invention can realize reducing the high display quality of the view angle dependency of γ characteristic.A second aspect of the present invention can reduce the flicker of the LCD that causes in ac driving process.
A third aspect of the present invention can make according to the present invention first or the LCD of second aspect be fit to big or high-resolution liquid crystal display.
A fourth aspect of the present invention can make according to the present invention first or the LCD of second aspect be fit to big or high-resolution liquid crystal display, even more adapt to than the third aspect.

Claims (26)

1. LCD comprises: a large amount of pixels, and each pixel has liquid crystal layer and is used for liquid crystal layer is applied the electrode of voltage in a large number, and electrode is the ranks matrix distribution, it is characterized in that:
Each of a large amount of pixels has first subpixel and second subpixel that can apply mutually different voltage to liquid crystal layer, is determining that first subpixel has the brightness that is higher than second subpixel under the gray scale;
Each comprises first subpixel and second subpixel:
On-off element is connected to the sweep trace of being shared by described first subpixel and second subpixel;
By counter electrode and the liquid crystal capacitance that forms through the liquid crystal layer subpixel electrode relative with counter electrode and
By the storage capacitor electrode, insulation course and the memory capacitance that forms through the insulation course memory capacitance counter electrode relative that are electrically connected on the subpixel electrode with storage capacitor electrode;
Counter electrode is the single electrode of being shared by first subpixel and second subpixel, and the memory capacitance counter electrode of first subpixel and second subpixel is electrically insulated from each other; With
The memory capacitance counter electrode of first subpixel in any of a large amount of pixels is electrically insulated from each other with the memory capacitance counter electrode and the described sweep trace of second subpixel of the adjacent image point of arbitrary pixel on the column direction.
2. LCD as claimed in claim 1, first subpixel that it is characterized in that any pixel be scattered in column direction on second subpixel of adjacent image point of arbitrary pixel adjacent.
3. LCD as claimed in claim 1 is characterized in that first subpixel is scattered on column direction adjacent with second subpixel in each of a plurality of pixels.
4. LCD as claimed in claim 1, it is characterized in that comprising a large amount of memory capacitance posts that are electrically insulated from each other, wherein each memory capacitance post is electrically connected on any memory capacitance counter electrode of first subpixel in a large amount of pixels and second subpixel through storage capacitance line.
5. LCD as claimed in claim 4, the quantity that it is characterized in that the memory capacitance post that is electrically insulated from each other in a large amount of memory capacitance posts is L, the memory capacitance inverse voltage of being supplied with by each memory capacitance post is an oscillating voltage, and be L times of horizontal scanning period oscillation period.
6. LCD as claimed in claim 4, a large amount of memory capacitance posts that it is characterized in that being electrically insulated from each other are supplied with the memory capacitance inverse voltage of the vibration that 180 ° of phase differential are arranged each other for forming the even number memory capacitance post of paired memory capacitance post.
7. LCD as claimed in claim 4, the quantity that it is characterized in that the memory capacitance post that is electrically insulated from each other is bigger 8 times than divide the share that a horizontal scanning period obtains by the capacitance resistance time constant, and wherein the capacitance resistance time constant is near the maximum load impedance of storage capacitance line.
8. LCD as claimed in claim 4, the quantity that it is characterized in that the memory capacitance post that is electrically insulated from each other is bigger 8 times than divide the share that a horizontal scanning period obtains by the capacitance resistance time constant, and be even number, wherein the capacitance resistance time constant is near the maximum load impedance of storage capacitance line.
9. LCD as claimed in claim 4 is characterized in that a large amount of memory capacitance posts comprises the first memory capacitance post and the second memory capacitance post that is electrically insulated from each other; With
Be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of first subpixel of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of second subpixel, if and k is natural number or 0, then:
CSBL_A_n+k be connected on the first memory capacitance post and
CSBL_B_n is connected on the second memory capacitance post.
10. LCD as claimed in claim 9 is characterized in that be respectively the twice of horizontal scanning period the oscillation period of the first and second memory capacitance inverse voltages supplied with by the first and second memory capacitance posts.
11. LCD as claimed in claim 10 is characterized in that the phase differential of the second memory capacitance inverse voltage than a horizontal scanning period of first memory capacitance inverse voltage hysteresis.
12. LCD as claimed in claim 11 comprises
Two on-off elements that are respectively first subpixel and the setting of second subpixel,
It is characterized in that two on-off elements open and close by the scanning-line signal voltage of supplying with the common scanning line; When two on-off elements were opened, shows signal voltage was applied on the storage capacitor electrode of each subpixel electrode and first subpixel and second subpixel from common signal line; When two on-off elements were closed, the voltage of each memory capacitance counter electrode of first subpixel and second subpixel changed; With
When if Td represents that two on-off elements are closed, the first memory capacitance inverse voltage changes the required time in the very first time, and then Td is greater than 0 horizontal scanning period and less than a horizontal scanning period.
13. LCD as claimed in claim 12 is characterized in that Td is approximately equal to 0.5 times of horizontal scanning period.
14. LCD as claimed in claim 4 is characterized in that:
A large amount of memory capacitance posts comprise the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post and the 4th memory capacitance post that is electrically insulated from each other; With
Be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of first subpixel of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of second subpixel, if and k is natural number or 0, then:
CSBL_A_n+4*k and CSBL_B_n+2+4*k are connected on the first memory capacitance post,
CSBL_B_n+4*k and CSBL_A_n+2+4*k are connected on the second memory capacitance post,
CSBL_A_n+1+4*k and CSBL_B_n+3+4*k are connected on the 3rd memory capacitance post,
CSBL_B_n+1+4*k and CSBL_A_n+3+4*k are connected on the 4th memory capacitance post.
15. LCD as claimed in claim 14 is 4 times of horizontal scanning period the oscillation period that it is characterized in that respectively the first to fourth memory capacitance inverse voltage supplied with by first to fourth memory capacitance post.
16. LCD as claimed in claim 15, it is characterized in that the phase differential of the second memory capacitance inverse voltage than stagnant latter two horizontal scanning period of the first memory capacitance inverse voltage, the 3rd memory capacitance inverse voltage is than the phase differential of three horizontal scanning periods of first memory capacitance inverse voltage hysteresis, and the 4th memory capacitance inverse voltage is than the phase differential of a horizontal scanning period of first memory capacitance inverse voltage hysteresis.
17. LCD as claimed in claim 16 comprises two on-off elements that are respectively first subpixel and the setting of second subpixel,
It is characterized in that two on-off elements open and close by the scanning-line signal voltage of supplying with the common scanning line; When two on-off elements were opened, shows signal voltage was applied on the storage capacitor electrode of each subpixel electrode and first subpixel and second subpixel from common signal line; When two on-off elements were closed, the voltage of each memory capacitance counter electrode of first subpixel and second subpixel changed; With
When if Td represents that two on-off elements are closed, the first memory capacitance inverse voltage changes the required time in the very first time, and then Td is greater than 0 horizontal scanning period and less than two horizontal scanning periods.
18. LCD as claimed in claim 17 is characterized in that Td is approximately equal to a horizontal scanning period.
19. LCD as claimed in claim 4 is characterized in that a large amount of memory capacitance posts comprise the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post and the 6th memory capacitance post that is electrically insulated from each other; With
Be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of first subpixel of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of second subpixel, if and k is natural number or 0, then:
CSBL_A_n+3*k is connected on the first memory capacitance post,
CSBL_B_n+3*k is connected on the second memory capacitance post,
CSBL_A_n+1+3*k is connected on the 3rd memory capacitance post,
CSBL_B_n+1+3*k is connected on the 4th memory capacitance post,
CSBL_A_n+2+3*k is connected on the 5th memory capacitance post,
CSBL_B_n+2+3*k is connected on the 6th memory capacitance post.
20. LCD as claimed in claim 19 is 6 times of horizontal scanning period the oscillation period that it is characterized in that respectively first to the 6th memory capacitance inverse voltage supplied with by first to the 6th memory capacitance post.
21. LCD as claimed in claim 4, it is characterized in that a large amount of memory capacitance posts comprise the first memory capacitance post that is electrically insulated from each other, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post ... (L-3) memory capacitance post, (L-2) memory capacitance post, (L-1) memory capacitance post and L memory capacitance post etc. are L memory capacitance post altogether; With
When 1/2 of the quantity L of the memory capacitance post of electrical isolation is odd number, promptly when L=2,6,10 ... Deng the time,
Be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of first subpixel of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of second subpixel, if and k is natural number or 0, then:
CSBL_A_n+ (L/2) * k is connected on the first memory capacitance post,
CSBL_B_n+ (L/2) * k is connected on the second memory capacitance post,
CSBL_A_n+1+ (L/2) * k is connected on the 3rd memory capacitance post,
CSBL_B_n+1+ (L/2) * k is connected on the 4th memory capacitance post,
CSBL_A_n+2+ (L/2) * k is connected on the 5th memory capacitance post,
CSBL_B_n+2+ (L/2) * k is connected on the 6th memory capacitance post,
CSBL_A_n+ (L/2)-2+ (L/2) * k is connected on (L-3) memory capacitance post,
CSBL_B_n+ (L/2)-2+ (L/2) * k is connected on (L-2) memory capacitance post,
CSBL_A_n+ (L/2)-1+ (L/2) * k is connected on (L-1) memory capacitance post,
CSBL_B_n+ (L/2)-1+ (L/2) * k is connected on the L memory capacitance post.
22. LCD as claimed in claim 21, it is characterized in that respectively by first to L memory capacitance post supply with first to the L that is horizontal scanning period oscillation period of L memory capacitance inverse voltage doubly.
23. LCD as claimed in claim 4 is characterized in that: a large amount of memory capacitance posts comprise the first memory capacitance post, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post, the 7th memory capacitance post and the 8th memory capacitance post that is electrically insulated from each other; With
Be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of first subpixel of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of second subpixel, if and k is natural number or 0, then:
CSBL_A_n+8*k and CSBL_B_n+4+8*k are connected on the first memory capacitance post,
CSBL_B_n+8*k and CSBL_A_n+4+8*k are connected on the second memory capacitance post,
CSBL_A_n+1+8*k and CSBL_B_n+5+8*k are connected on the 3rd memory capacitance post,
CSBL_B_n+1+8*k and CSBL_A_n+5+8*k are connected on the 4th memory capacitance post,
CSBL_A_n+2+8*k and CSBL_B_n+6+8*k are connected on the 5th memory capacitance post,
CSBL_B_n+2+8*k and CSBL_A_n+6+8*k are connected on the 6th memory capacitance post,
CSBL_A_n+3+8*k and CSBL_B_n+7+8*k are connected on the 7th memory capacitance post,
CSBL_B_n+3+8*k and CSBL_A_n+7+8*k are connected on the 8th memory capacitance post.
24. LCD as claimed in claim 23 is 8 times of horizontal scanning period the oscillation period that it is characterized in that respectively first to the 8th memory capacitance inverse voltage supplied with by first to the 8th memory capacitance post.
25. LCD as claimed in claim 4 is characterized in that:
A large amount of memory capacitance posts comprise the first memory capacitance post that is electrically insulated from each other, the second memory capacitance post, the 3rd memory capacitance post, the 4th memory capacitance post, the 5th memory capacitance post, the 6th memory capacitance post ... (L-3) memory capacitance post, (L-2) memory capacitance post, (L-1) memory capacitance post and L memory capacitance post etc. are L memory capacitance post altogether; With
When 1/2 of the quantity L of the memory capacitance post of electrical isolation is even number, promptly when L=4,8,12 ... Deng the time, be made as CSBL_A_n if be connected to the storage capacitance line of memory capacitance counter electrode of first subpixel of the pixel that is arranged in the n of the row nominated bank infall that any row and a large amount of pixels form, be made as CSBL_B_n if be connected to the storage capacitance line of the memory capacitance counter electrode of second subpixel, if and k is natural number or 0, then:
CSBL_A_n+L*k and CSBL_B_n+ (L/2)+L*k is connected on the first memory capacitance post,
CSBL_B_n+L*k and CSBL_A_n+ (L/2)+L*k is connected on the second memory capacitance post,
CSBL_A_n+1+L*k and CSBL_A_n+ (L/2)+1+L*k is connected on the 3rd memory capacitance post,
CSBL_B_n+1+L*k and CSBL_A_n+ (L/2)+1+L*k is connected on the 4th memory capacitance post,
CSBL_A_n+2+L*k and CSBL_B_n+ (L/2)+2+L*k is connected on the 5th memory capacitance post,
CSBL_B_n+2+L*k and CSBL_A_n+ (L/2)+2+L*k is connected on the 6th memory capacitance post,
CSBL_A_n+3+L*k and CSBL_B_n+ (L/2)+3+L*k is connected on the 7th memory capacitance post,
CSBL_B_n+3+L*k and CSBL_A_n+ (L/2)+3+L*k is connected on the 8th memory capacitance post,
CSBL_A_n+ (L/2)-2+L*k and CSBL_B_n+L-2+L*k are connected on (L-3) memory capacitance post,
CSBL_B_n+ (L/2)-2+L*k and CSBL_A_n+L-2+L*k are connected on (L-2) memory capacitance post,
CSBL_A_n+ (L/2)-1+L*k and CSBL_B_n+L-1+L*k are connected on (L-1) memory capacitance post,
And CSBL_B_n+ (L/2)-1+L*k and CSBL_A_n+L-1+L*k are connected on the L memory capacitance post.
26. LCD as claimed in claim 25, it is characterized in that respectively by first to L memory capacitance post supply with first to the L that is horizontal scanning period oscillation period of L memory capacitance inverse voltage doubly.
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