CN101471609A - Tri-terminal integration synchronous rectifier and inverse-excitation type synchronous rectifying circuit - Google Patents
Tri-terminal integration synchronous rectifier and inverse-excitation type synchronous rectifying circuit Download PDFInfo
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- CN101471609A CN101471609A CNA2007103059172A CN200710305917A CN101471609A CN 101471609 A CN101471609 A CN 101471609A CN A2007103059172 A CNA2007103059172 A CN A2007103059172A CN 200710305917 A CN200710305917 A CN 200710305917A CN 101471609 A CN101471609 A CN 101471609A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention relates to a three-terminal integrated synchronous rectifier and a flyback synchronous rectifier circuit. A synchronous rectifier chip is designed for comprising minimum number of contacts; a control terminal is used for providing a control signal which is simultaneously used as the power supply bias voltage and the synchronous pulse, so as to enable the synchronous rectifier chip to operate normally; the control signal is extracted from an output terminal of an auxiliary winding and obtained after passing through a diode; and the other two terminals are a drain contact and a source contact of an internal power transistor respectively and connected between an output winding and a voltage output terminal, and transfer the energy of a transformer for supplying the current needed by an output load. The invention can provide minimum number of pins for packaging and minimum number of external parts, thereby being capable of saving the area of a printed circuit board and reducing the overall cost.
Description
Technical field
The present invention relates to a kind of tri-terminal integration synchronous rectifier and inverse-excitation type synchronous rectifying circuit, utilize control terminal to provide control signal simultaneously as power supply bias voltage and synchronizing signal, and the built-in power transistor reaches minimum pin count design in single encapsulation, can simplify known synchronous rectification mode control circuit and power transistor isolating construction, reduce the printed circuit board (PCB) area occupied, reduce whole power supply unit cost.
Background technology
Switched power supplier is to take the diode rectification mode traditionally, the application of synchronous rectification mode is along with environmental protection and energy saving subject under discussion, heat radiation and efficient requirement, then be accepted gradually in recent years and adopt replace the conventional diode rectifier system, but known synchronous rectification application circuit is all the structure that control circuit and power transistor separate.Few more application pin count will make circuit cost lower in practical application, and the minimum desirable synchronous rectifier encapsulation of cost should belong to three terminal packaged types, promptly a terminal provides control signal as power supply bias voltage and lock-out pulse, and two other terminal is respectively internal power transistor drain contact and source contact.Present known synchronous rectification application circuit is subject to packages limits and must selects more expensive synchronous rectification control mode to comprise synchronous rectifying controller and some the peripheral discrete elements and the external power transistor of one eight pin.
As shown in Figure 1, be known synchronous rectification application circuit, include DC power supply VIN, input filter capacitor C1, starting resistance R1, grid bias power supply filter capacitor C2, elementary pulse-width modulation (PWM) controller 11, transformer T1 has elementary main winding 12, elementary auxiliary winding 13, with secondary output winding 20, rectifier diode D1 provides dc bias power VCC, the energy delivery of primary side power transistor Q1 control transformer, primary current detects resistance R 2 restriction peak power outputs, the primary side power transistor Q2 provide the primary side rectification, and synchronous commutating control circuit 23 is controlled primary side power transistor Q2 conductings correctly and closed feedback compensation error amplifier 24 and optical coupler 25.Power initiation moment DC power supply VIN charges to grid bias power supply filter capacitor C2 via starting resistance R1.When charging voltage reaches the starting resistor of elementary PDM keyer 11, elementary PDM keyer 11 begins to export Continuity signal control primary side power transistor Q1 normal switch action and makes electric current flow into elementary main winding 12, and therefore transformer T1 begins action and grid bias power supply and develop gradually by elementary auxiliary winding 13 and supply via rectifier diode D1, grid bias power supply filter capacitor C2.The primary side voltage feedback signal inputs to elementary PDM keyer 11 corresponding to the change in voltage of the secondary side output terminal VO primary side that is communicated to by feedback compensation error amplifier 24 and optical coupler 25.Synchronous commutating control circuit 23 provides grid bias power supply VDD by output, drain electrode (DRAIN) and source electrode (SOURCE) that synchronous commutating control circuit 23 respectively has a D and S test side to be connected in primary side power transistor Q2, and output G grid (GATE) the control primary side power transistor Q2 conducting correctly that is connected in primary side power transistor Q2 with close.
In known synchronous rectification application circuit technical field, need the above encapsulation of 4 pins at least, get rid of the possibility that can use the 3 terminal industry-standard package that have economic benefit most such as TO-220, DPAK, TO-3P fully.On the other hand, known synchronous rectification application circuit power supply bias voltage VDD is necessary for direct current (D.C.) voltage, must increase the power supply bias voltage VDD that could supply the synchronous rectifying controller chip after the step-down of linear voltage decreasing device if the output voltage of power supply unit is too high, if ability power supply bias voltage VDD will increase cost of parts and lower efficiency after the too low also necessary secondary auxiliary winding of increase of the output voltage of power supply unit and rectifying and wave-filtering element and the step-down of linear voltage decreasing device.
Summary of the invention
In view of this, the object of the invention is for providing a kind of integrated synchronous rectifier of three terminals encapsulation, briefly, concrete enforcement of the present invention is that tri-terminal integration synchronous rectifier has control terminal, provide control signal as power supply bias voltage and lock-out pulse, and two other terminal is respectively internal power transistor drain contact and source contact, is connected between output winding and the output, transmits the required electric current of transformer energy supply output loading.
Advantage on the circuit of the present invention is that the integrated circuit design provides minimum pin count encapsulation and exterior part number, can save printed circuit board area, and advantage economically is the reduction of whole cost.
For reaching above-mentioned purpose, the invention provides a kind of tri-terminal integration synchronous rectifier, have first, second and third electric terminal, this tri-terminal integration synchronous rectifier comprises power transistor and synchronous commutating control circuit.Above-mentioned power transistor has and first exports/go into end, second and export/go into end and control end, and this first is exported/go into end and be coupled to this first electric terminal, and this second is exported/go into end and be coupled to this second electric terminal.Above-mentioned synchronous commutating control circuit is in order to control the electrical property state of this power transistor, comprise input control end, two test sides and an output, this input control end is coupled to the 3rd electric terminal, this two test side be coupled to this power transistor respectively this first export/go into end and this second and export/go into end, this output is coupled to this control end of this power transistor.Wherein, when this synchronous commutating control circuit received synchronizing signal at this input control end, controlling this power transistor was conducting state; When detecting electric current that this power transistor flows through less than predetermined current value in this two test side, controlling this power transistor is cut-off state.
Aforesaid tri-terminal integration synchronous rectifier, wherein this synchronous commutating control circuit comprises: testing circuit, coupling this first exports/goes into end and this second and export/go into end to form described two test sides, in order to the flow through electric current of this power transistor of detection, and at this electric current during less than this predetermined current value, the output pick-off signal; Delay circuit couples this testing circuit, after this pick-off signal continues first scheduled time length, and the output confirmation signal; And driver, couple this delay circuit and this input control end, when this input control end received this synchronizing signal, controlling this power transistor was conducting state, when receiving this confirmation signal, controlling this power transistor is cut-off state.
Aforesaid tri-terminal integration synchronous rectifier, wherein said testing circuit comprises first bipolar junction transistor and second bipolar junction transistor, the base stage of described two bipolar junction transistors is connected to each other, the emitter of the collector electrode of this first bipolar junction transistor and this second bipolar junction transistor then is described two test sides, the base stage of this first bipolar junction transistor and emitter are connected to each other and couple this input control end, and the collector electrode of this second bipolar junction transistor is coupled to this delay circuit.
Aforesaid tri-terminal integration synchronous rectifier, wherein this delay circuit comprises: the first transistor couples this testing circuit; At least one electric capacity couples this first transistor; And transistor seconds, couple described at least one electric capacity and this driver, and be positioned at conducting or cut-off state according to the current potential of described at least one electric capacity; Wherein, when this pick-off signal did not send, discharging and recharging of described at least one electric capacity of this first transistor control made transistor seconds be positioned at cut-off state; When this pick-off signal sent, discharging and recharging of described at least one electric capacity of this first transistor control made transistor seconds be positioned at conducting state, to produce this confirmation signal.
Aforesaid tri-terminal integration synchronous rectifier, wherein this delay circuit also comprises at least one resistance, couple described at least one electric capacity to reference potential, when transistor seconds is positioned at conducting state, slowly, make described transistor seconds transfer cut-off state to after described at least one second scheduled time of capacitor charge and discharge length.
The present invention also provides a kind of inverse-excitation type synchronous rectifying circuit, comprises inverse-excitation type transducer, output capacitance, tri-terminal integration synchronous rectifier, output detecting unit, electrical isolation unit and elementary PDM keyer.Above-mentioned inverse-excitation type transducer comprises the transformer of first power transistor and tool primary side and primary side, and this first power transistor couples this primary side.Above-mentioned output capacitance is coupled to this primary side of this transformer.Above-mentioned tri-terminal integration synchronous rectifier has first, second and third electric terminal, and this first electric terminal and this second electric terminal couple this primary side and this output capacitance of this transformer respectively, and the 3rd electric terminal is in order to receive synchronizing signal.Above-mentioned output detecting unit is coupled to this primary side of this transformer, and the electrical property state that detects this primary side is to produce output detection signal.Above-mentioned electrical isolation unit couples this output detecting unit, exports this output detection signal in the electrical isolation mode.Above-mentioned elementary PDM keyer couples this inverse-excitation type transducer and this electrical isolation unit, to control the conduction and cut-off state of this first power transistor according to this output detection signal.Wherein, when this tri-terminal integration synchronous rectifier receives this synchronizing signal, transfer conducting state to, during less than predetermined value, transfer cut-off state at this output current with the conducting output current.
Aforesaid inverse-excitation type synchronous rectifying circuit, wherein this three ends synchronous rectification comprises: second power transistor, have and first export/go into end, second and export/go into end and control end, this first is exported/goes into end and is coupled to this first electric terminal, and this second is exported/go into end and be coupled to this second electric terminal; And synchronous commutating control circuit, in order to control the electrical property state of this second power transistor, comprise input control end, two test sides and an output, this input control end is coupled to the 3rd electric terminal, described two test sides be coupled to this second power transistor respectively this first export/go into end and this second and export/go into end, this output is coupled to this control end of this second power transistor; Wherein, when this synchronous commutating control circuit received this synchronizing signal at this input control end, controlling this second power transistor was conducting state; When detecting electric current that this second power transistor flows through less than predetermined current value in described two test sides, controlling this second power transistor is cut-off state.
Aforesaid inverse-excitation type synchronous rectifying circuit, wherein this synchronous commutating control circuit comprises: testing circuit, coupling this first exports/goes into end and this second and export/go into end to form described two test sides, in order to the flow through electric current of this second power transistor of detection, and at this electric current during less than this predetermined current value, the output pick-off signal; Delay circuit couples this testing circuit, after this pick-off signal continues first scheduled time length, and the output confirmation signal; And driver, couple this delay circuit and this input control end, when this input control end received this synchronizing signal, controlling this second power transistor was conducting state, when receiving this confirmation signal, controlling this second power transistor is cut-off state.
Aforesaid inverse-excitation type synchronous rectifying circuit, wherein testing circuit comprises first bipolar junction transistor and second bipolar junction transistor, the base stage of described two bipolar junction transistors is connected to each other, the emitter of the collector electrode of this first bipolar junction transistor and this second bipolar junction transistor then is described two test sides, the base stage of this first bipolar junction transistor and emitter are connected to each other and couple this input control end, and the collector electrode of this second bipolar junction transistor is coupled to this delay circuit.
Aforesaid inverse-excitation type synchronous rectifying circuit, wherein this delay circuit comprises: the first transistor couples this testing circuit; At least one electric capacity couples this first transistor; And transistor seconds, couple described at least one electric capacity and this driver, and be positioned at conducting or cut-off state according to the current potential of described at least one electric capacity; Wherein, when this pick-off signal did not send, discharging and recharging of described at least one electric capacity of this first transistor control made transistor seconds be positioned at cut-off state; When this pick-off signal sent, discharging and recharging of described at least one electric capacity of this first transistor control made transistor seconds be positioned at conducting state, to produce this confirmation signal.
Aforesaid inverse-excitation type synchronous rectifying circuit, wherein this delay circuit also comprises at least one resistance, couple described at least one electric capacity to reference potential, when transistor seconds is positioned at conducting state, slowly to described at least one capacitor charge and discharge after second scheduled time length, make transistor seconds transfer cut-off state to.
Aforesaid inverse-excitation type synchronous rectifying circuit, wherein the primary side of this transformer has primary side main winding and elementary auxiliary winding, this primary side main winding connects input power supply and this first power transistor, this elementary auxiliary winding couples this elementary PDM keyer, to provide driven by power this elementary PDM keyer.
Aforesaid inverse-excitation type synchronous rectifying circuit, wherein the primary side of this transformer has primary side winding and secondary auxiliary winding, this secondary auxiliary winding couples the 3rd electric terminal of this tri-terminal integration synchronous rectifier by diode, produces this synchronizing signal with the conduction and cut-off state according to this first power transistor.
The present invention can provide minimum pin count encapsulation and exterior part number for integrated circuit design, can save printed circuit board area, and reduce whole cost.
Description of drawings
Fig. 1 is known synchronous rectification application circuit;
Fig. 2 specifically is applied to the schematic diagram of inverse-excitation type synchronous rectifying circuit for tri-terminal integration synchronous rectifier of the present invention;
Fig. 3 is another specific embodiment schematic diagram of tri-terminal integration synchronous rectifier of the present invention;
Fig. 4 is the functional block diagram of synchronous commutating control circuit of the present invention;
Fig. 5 is a tri-terminal integration synchronous rectifier internal circuit schematic diagram of the present invention; And
Fig. 6 and Fig. 7 are tri-terminal integration synchronous rectifier movement oscillogram of the present invention.
Wherein, description of reference numerals is as follows:
11 elementary PDM keyer
12 elementary main windings
13 elementary auxiliary windings
20 level output windings
21 auxiliary windings of level
22 tri-terminal integration synchronous rectifiers
23 synchronous commutating control circuits
231 gate drivers
232 delay circuits
233 current detection circuits
24 feedback compensation error amplifiers
25 optical couplers
C imports control end
The C1 input filter capacitor
C2 grid bias power supply filter capacitor
The C3 output filter capacitor
C4, C5 electric capacity
D1, D2 rectifier diode
D3, D4, D5, D6 diode
Q1 primary side power switch
Q2 primary side power transistor
Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10 transistor
The R1 starting resistance
The R2 primary current detects resistance
R3, R4, R5, R6, R7, R8, R9 resistance
The T1 transformer
The VIN DC power supply
The VCC dc bias power
The VDD grid bias power supply
The VO secondary side output terminal
The G output
D, S test side
Embodiment
Figure 2 shows that tri-terminal integration synchronous rectifier of the present invention specifically is applied to the schematic diagram of inverse-excitation type synchronous rectifying circuit, include DC power supply VIN, input filter capacitor C1, starting resistance R1, grid bias power supply filter capacitor C2, output filter capacitor C3, elementary PDM keyer 11, transformer T1, it has elementary main winding 12, elementary auxiliary winding 13, secondary output winding 20 and secondary auxiliary winding 21, rectifier diode D1 provides dc bias power VCC, primary side power transistor Q1 control transformer T1 transmits energy, primary current detects resistance R 2 restriction peak power outputs, tri-terminal integration synchronous rectifier 22, output detecting unit (is the feedback compensation error amplifier at present embodiment) 24 and electrical isolation unit (is optical coupler at present embodiment) 25.Power initiation moment DC power supply VIN charges to grid bias power supply filter capacitor C2 via starting resistance R1, when charging voltage reaches the starting resistor of elementary PDM keyer 11, elementary PDM keyer 11 begins to export Continuity signal control primary side power transistor Q1 normal switch action and makes electric current flow into elementary main winding 12, and therefore transformer T1 begins action and grid bias power supply and develop gradually by elementary auxiliary winding 13 and supply via rectifier diode D1, grid bias power supply filter capacitor C2.The primary side voltage feedback signal is to be communicated to primary side by feedback compensation error amplifier 24 and optical coupler 25 corresponding to the change in voltage of secondary side output terminal VO, inputs to elementary PDM keyer 11.Tri-terminal integration synchronous rectifier 22 includes power transistor Q2 and synchronous commutating control circuit 23, and synchronous commutating control circuit 23 comprises input control end C (CONTROL), D and S test side and output G.Input control end C is connected in secondary auxiliary winding 21 via rectifier diode D2, obtains the positive potential pulse power supply bias voltage and synchronizing signal are provided.D and S test side are connected in the drain electrode (DRAIN) and source electrode (SOURCE) of power transistor Q2, and output G is connected in the grid (GATE) of power transistor Q2.The first terminal of tri-terminal integration synchronous rectifier 22 is coupled to the source electrode of power transistor Q2, and second terminal is coupled to the drain electrode of power transistor Q2, and the 3rd terminal is coupled to the input control end C of synchronous rectification control unit 23.
Figure 3 shows that another specific embodiment of tri-terminal integration synchronous rectifier of the present invention figure, it changes secondary auxiliary winding 21 shown in Figure 2 and tri-terminal integration synchronous rectifier 22 and is placed on secondary output winding 20 outputs, tri-terminal integration synchronous rectifier 22 still can operate as normal, this moment synchronous commutating control circuit 23 the reference data current potential be source electrode (SOURCE) the floating voltage level with shown in Figure 2 be reference data current potential difference to some extent with ground, but no any difference is moved in synchronous rectification.
Figure 4 shows that the functional block diagram of synchronous commutating control circuit of the present invention, comprise driver 231, delay circuit 232, testing circuit 233 and power transistor Q2.When driver 231 receives synchronizing signal at input control end C, make power transistor Q2 conducting, and prevent to import the polarization state conversion moment ring of the auxiliary winding 21 of control end C dimension level and energy by delay circuit 232 control and discharge the harmonic wave that finishes and cause that driver 231 produces unusual switching signal.Testing circuit 233 is responsible for the electric current of detection power transistor Q2 conducting, when power transistor Q2 electric current by successively decreasing greatly near zero the time, testing circuit 233 outputs to delay circuit 232 immediately, output by delay circuit 232 Control Driver 231 transfers electronegative potential to again, closes power transistor Q2 and prevents that primary side output filter capacitor C3 storage power from pouring in down a chimney back transformer T1.The polarization state that transfers the secondary auxiliary winding 21 of conducting as primary side power transistor Q1 to is converted to negative polarity, input control end C stop supplies power supply bias voltage, then tri-terminal integration synchronous rectifier 22 will be returned to initial condition gradually, when secondary auxiliary winding 21 transfers positive polarity once again to, input control end C obtains positive polarity voltage and begins to supply with driver 231 outputs and make power transistor Q2 transfer conducting once again to, so go round and begin again, normally reach the synchronous rectification action.
Fig. 5 is the internal circuit diagram of the embodiment of tri-terminal integration synchronous rectifier of the present invention.As shown in Figure 5, driver 231 includes four transistor Q7, Q8, Q9, Q10 and diode D5 and resistance R 7, R8 forms.Delay circuit 232 can be formed for shellproof jumping circuit includes two transistor Q5, Q6 and two diode D3, D4 and resistance R 4, R5, R6, R9 and capacitor C 4, C5.Testing circuit 233 includes two transistor Q3, Q4 and resistance R 3 is formed.The base stage of transistor Q3, Q4 is connected to each other, and the emitter of the collector electrode of transistor Q3 and transistor Q4 is coupled to D and S test side respectively.The base stage of transistor Q3 and emitter are connected to each other and couple this input control end C by resistance R 3, and the collector electrode of transistor Q4 is coupled to this delay circuit 232.Because bipolar junction transistor has the characteristic of base stage-high counter withstand voltage of inter-collector diode much larger than counter withstand voltage between base-emitter, so transistor Q3 can improve the withstand voltage of transistor Q3 by base stage and emitter mode connected to one another.
Cooperate Fig. 6 and Fig. 2 (or Fig. 3) that the running of tri-terminal integration synchronous rectifier of the present invention is described.As shown in Figure 6, secondary auxiliary winding 21 two ends waveforms when waveform A is heavy duty, the waveform of the control terminal of tri-terminal integration synchronous rectifier 22 of the present invention when waveform B is heavy duty, the gate terminal waveform of the power transistor Q2 of tri-terminal integration synchronous rectifier 22 of the present invention when waveform C is heavy duty.When at time point t1, primary side power transistor Q1 transfer to by the time, the energy that is stored in the transformer T1 begins to secondary release, shown in Fig. 6 waveform A.At this moment, the voltage of secondary auxiliary winding 21 transfers positive voltage to, and because of state exchange moment produces ring (Ring) phenomenon, shown in Fig. 6 waveform B.In addition, because the voltage of input control end C is drawn high, transistor Q7, the Q8 of the Darlington circuit (Darlington) in the driver 231 transfer conducting state to, and transistor Q9, Q10 transfer cut-off state to, the grid potential of power transistor Q2 is drawn high and conducting, shown in Fig. 6 waveform C.Do not move enough height to and before making power transistor Q2 conducting in grid potential, the electric current of secondary output winding 20 can flow through the body diode D6 of power transistor Q2, after power transistor Q2 conducting, then flow through power transistor Q2, therefore, the electric current of secondary output winding 20 can cause the source electrode (S) of power transistor Q2 and forward bias voltage drop (before the power transistor Q2 conducting) that the voltage difference of drain electrode between (D) is body diode D6 or I*RDSon (after the power transistor Q2 conducting, I is the electric current of secondary output winding 20, and RDSon is a power transistor Q2 conduction impedance).When testing circuit 233 is drawn high at the voltage of input control end C, transistor Q3 also transfers conducting to thereupon, and because the voltage difference of the source electrode (S) of power transistor Q2 and drain electrode (D), the emitter current potential of transistor Q4 is higher than the collector potential of transistor Q3 and makes the transistor Q4 of testing circuit 233 is cut-off state.When transistor Q4 is cut-off state, make transistor Q5, the Q6 of delay circuit 232 be respectively conducting, cut-off state.And secondary auxiliary winding 21 produces ringing and may make testing circuit 233 or driver 231 misoperations for positive voltage moment because of transition, the normal operation that the capacitor C 4 by delay circuit 232, the energy that C5 absorbs ringing and buffering can avoid influencing driver 231.
The energy that is stored in transformer T1 is about to discharge and finishes, the electric current of power transistor Q2 of flowing through begins to reduce, when making the voltage difference (being size of current) of the source electrode (S) of power transistor Q2 and drain electrode (D) drop to a certain predetermined value, transistor Q4 will transfer conducting state to.At this moment, the transistor Q5 of delay circuit 232 transfers cut-off state to, and input control end C begins capacitor C 4, C5 charging by resistance R 5 and diode D3, and wherein diode D3 is in order to the charging process of speed-up capacitor C5.Through scheduled time transistor Q5 still is cut-off state, capacitor C 5 charges to the current potential that is enough to transistor Q6 conducting, at time point t2, and transistor Q6 conducting, make transistor Q9, the Q10 of driver 231 follow conducting, the grid potential of power transistor Q2 is descended the general fast and is transferred cut-off state to.Transistor Q7, the Q8 of driver 231 are in transferring procedures of turn-off to, and the electric charge that stores in its parasitic capacitance can quicken transistor Q7, Q8 and transfer the speed of ending to by diode D5 rapid release.Then, the both end voltage of secondary auxiliary winding 21 begins to descend, and during to time point t3, primary side power transistor Q1 transfers conducting to, and transformer T1 state is changed once again, and DC power supply VIN is again to transformer T1 energy storage.Capacitor C 5 stored electric charges discharge gradually by resistance R 9; Capacitor C 4 stored electric charges then discharge by resistance R 6, diode D3 and resistance R 9, and tri-terminal integration synchronous rectifier 22 will be returned to initial condition gradually.
In addition, with reference to figure 7 waveform D～F, the gate terminal waveform of the power transistor Q2 of the waveform of the control terminal of secondary auxiliary winding 21 two ends waveforms, tri-terminal integration synchronous rectifier 22 and tri-terminal integration synchronous rectifier 22 when being respectively underloading.When time point t4, primary side power transistor Q1 transfer to by the time, the energy that is stored in the transformer T1 begins to secondary release, shown in Fig. 7 waveform D.The energy that is stored in transformer T1 is about to discharge and finishes, and the electric current that testing circuit 233 detects the power transistor Q2 that flows through drops to below a certain predetermined value, and sends pick-off signal.After delayed circuit 232 delay scheduled times are confirmed, at time point t5, reach driver 231 and the grid potential of drop-down power transistor Q2 makes it transfer cut-off state to, shown in Fig. 7 waveform F.Because the relation of underloading, energy stored is less in the transformer T1, finish compared to very fast release of heavy duty meeting, so the time interval of t4-t5 is shorter than the time interval of t1-t2.
At during this period of time (that is, time point t5 to the time point t6) of power transistor Q2 by the end of primary side power transistor Q1 conducting, primary side can produce resonance phenomena, as Fig. 7 waveform D, E.For avoiding resonance phenomena to cause the misoperation of synchronous commutating control circuit 23, capacitor C 4, C5 to keep being enough to allowing the current potential of transistor Q6 conducting, the grid potential that makes driver 231 holding power transistor Q2 is in low level.In addition,, therefore utilize diode D4 if strangulation transistor Q5 can cause capacitor C 4, the unexpected discharge of C5 because of resonance phenomena misleads, can be when transistor Q6 conducting, the base potential of strangulation transistor Q5 makes strangulation transistor Q5 be unlikely to mislead.At time point t6, primary side power transistor Q1 transfers secondary auxiliary winding 21 polarization state of conducting to and is converted to negative polarity, and input control end C stop supplies power supply bias voltage then tri-terminal integration synchronous rectifier 22 will be returned to initial condition gradually.Because the situation (that is, time point t3 is to time point t1) under the relation of underloading, the time span of power transistor Q1 conducting (that is, time point t6 is to time point t4) are also heavily loaded is for short.
As mentioned above, the present invention has novelty, creativeness and industrial applicibility.The present invention is open with preferred embodiment hereinbefore, but it will be understood by those skilled in the art that this embodiment only is used to describe the present invention, does not limit the scope of the invention and should not be read as.It should be noted that the variation and the displacement of every and this embodiment equivalence all are interpreted as being encompassed in the scope of the present invention.Therefore, protection scope of the present invention is when being as the criterion with the scope that appending claims was defined.
Claims (13)
1. a tri-terminal integration synchronous rectifier has first electric terminal, second electric terminal and the 3rd electric terminal, it is characterized in that, comprising:
Power transistor has and first exports/go into end, second and export/go into end and control end, and this first is exported/go into end and be coupled to this first electric terminal, and this second is exported/go into end and be coupled to this second electric terminal; And
Synchronous commutating control circuit, in order to control the electrical property state of this power transistor, comprise input control end, two test sides and an output, this input control end is coupled to the 3rd electric terminal, described two test sides be coupled to this power transistor respectively this first export/go into end and this second and export/go into end, this output is coupled to this control end of this power transistor;
Wherein, when this synchronous commutating control circuit received synchronizing signal at this input control end, controlling this power transistor was conducting state; When detecting electric current that this power transistor flows through less than predetermined current value in described two test sides, controlling this power transistor is cut-off state.
2. tri-terminal integration synchronous rectifier as claimed in claim 1 is characterized in that, wherein this synchronous commutating control circuit comprises:
Testing circuit couples this and first exports/go into end and this second and export/go into end forming described two test sides, in order to the flow through electric current of this power transistor of detection, and at this electric current during less than this predetermined current value, the output pick-off signal;
Delay circuit couples this testing circuit, after this pick-off signal continues first scheduled time length, and the output confirmation signal; And
Driver couples this delay circuit and this input control end, and when this input control end received this synchronizing signal, controlling this power transistor was conducting state, and when receiving this confirmation signal, controlling this power transistor is cut-off state.
3. tri-terminal integration synchronous rectifier as claimed in claim 2, it is characterized in that, wherein said testing circuit comprises first bipolar junction transistor and second bipolar junction transistor, the base stage of described two bipolar junction transistors is connected to each other, the emitter of the collector electrode of this first bipolar junction transistor and this second bipolar junction transistor then is described two test sides, the base stage of this first bipolar junction transistor and emitter are connected to each other and couple this input control end, and the collector electrode of this second bipolar junction transistor is coupled to this delay circuit.
4. tri-terminal integration synchronous rectifier as claimed in claim 2 is characterized in that, wherein this delay circuit comprises:
The first transistor couples this testing circuit;
At least one electric capacity couples this first transistor; And
Transistor seconds couples described at least one electric capacity and this driver, and is positioned at conducting or cut-off state according to the current potential of described at least one electric capacity;
Wherein, when this pick-off signal did not send, discharging and recharging of described at least one electric capacity of this first transistor control made transistor seconds be positioned at cut-off state; When this pick-off signal sent, discharging and recharging of described at least one electric capacity of this first transistor control made transistor seconds be positioned at conducting state, to produce this confirmation signal.
5. tri-terminal integration synchronous rectifier as claimed in claim 2, it is characterized in that, wherein this delay circuit also comprises at least one resistance, couple described at least one electric capacity to reference potential, when transistor seconds is positioned at conducting state, slowly, make described transistor seconds transfer cut-off state to after described at least one second scheduled time of capacitor charge and discharge length.
6. an inverse-excitation type synchronous rectifying circuit is characterized in that, comprises:
The inverse-excitation type transducer comprises first power transistor and has primary side and one of them transformer of primary side, and this first power transistor couples this primary side;
Output capacitance is coupled to this primary side of this transformer;
Tri-terminal integration synchronous rectifier, have first electric terminal, second electric terminal and the 3rd electric terminal, this first electric terminal and this second electric terminal couple this primary side and this output capacitance of this transformer respectively, and the 3rd electric terminal is in order to receive synchronizing signal;
Export detecting unit, be coupled to this primary side of this transformer, the electrical property state that detects this primary side is to produce output detection signal;
The electrical isolation unit couples this output detecting unit, exports this output detection signal in the electrical isolation mode;
Elementary PDM keyer couples this inverse-excitation type transducer and this electrical isolation unit, to control the conduction and cut-off state of this first power transistor according to this output detection signal;
Wherein, when this tri-terminal integration synchronous rectifier receives this synchronizing signal, transfer conducting state to, during less than predetermined value, transfer cut-off state at this output current with the conducting output current.
7. inverse-excitation type synchronous rectifying circuit as claimed in claim 6 is characterized in that, wherein this three ends synchronous rectification comprises:
Second power transistor has and first exports/go into end, second and export/go into end and control end, and this first is exported/go into end and be coupled to this first electric terminal, and this second is exported/go into end and be coupled to this second electric terminal; And
Synchronous commutating control circuit, in order to control the electrical property state of this second power transistor, comprise input control end, two test sides and an output, this input control end is coupled to the 3rd electric terminal, described two test sides be coupled to this second power transistor respectively this first export/go into end and this second and export/go into end, this output is coupled to this control end of this second power transistor;
Wherein, when this synchronous commutating control circuit received this synchronizing signal at this input control end, controlling this second power transistor was conducting state; When detecting electric current that this second power transistor flows through less than predetermined current value in described two test sides, controlling this second power transistor is cut-off state.
8. inverse-excitation type synchronous rectifying circuit as claimed in claim 7 is characterized in that, wherein this synchronous commutating control circuit comprises:
Testing circuit couples this and first exports/go into end and this second and export/go into end forming described two test sides, in order to the flow through electric current of this second power transistor of detection, and at this electric current during less than this predetermined current value, the output pick-off signal;
Delay circuit couples this testing circuit, after this pick-off signal continues first scheduled time length, and the output confirmation signal; And
Driver couples this delay circuit and this input control end, and when this input control end received this synchronizing signal, controlling this second power transistor was conducting state, and when receiving this confirmation signal, controlling this second power transistor is cut-off state.
9. inverse-excitation type synchronous rectifying circuit as claimed in claim 8, it is characterized in that, wherein testing circuit comprises first bipolar junction transistor and second bipolar junction transistor, the base stage of described two bipolar junction transistors is connected to each other, the emitter of the collector electrode of this first bipolar junction transistor and this second bipolar junction transistor then is described two test sides, the base stage of this first bipolar junction transistor and emitter are connected to each other and couple this input control end, and the collector electrode of this second bipolar junction transistor is coupled to this delay circuit.
10. inverse-excitation type synchronous rectifying circuit as claimed in claim 8 is characterized in that, wherein this delay circuit comprises:
The first transistor couples this testing circuit;
At least one electric capacity couples this first transistor; And
Transistor seconds couples described at least one electric capacity and this driver, and is positioned at conducting or cut-off state according to the current potential of described at least one electric capacity;
Wherein, when this pick-off signal did not send, discharging and recharging of described at least one electric capacity of this first transistor control made transistor seconds be positioned at cut-off state; When this pick-off signal sent, discharging and recharging of described at least one electric capacity of this first transistor control made transistor seconds be positioned at conducting state, to produce this confirmation signal.
11. inverse-excitation type synchronous rectifying circuit as claimed in claim 8, it is characterized in that, wherein this delay circuit also comprises at least one resistance, couple described at least one electric capacity to reference potential, when transistor seconds is positioned at conducting state, slowly to described at least one capacitor charge and discharge after second scheduled time length, make transistor seconds transfer cut-off state to.
12. inverse-excitation type synchronous rectifying circuit as claimed in claim 6, it is characterized in that, wherein the primary side of this transformer has primary side main winding and elementary auxiliary winding, this primary side main winding connects input power supply and this first power transistor, this elementary auxiliary winding couples this elementary PDM keyer, to provide driven by power this elementary PDM keyer.
13. inverse-excitation type synchronous rectifying circuit as claimed in claim 6, it is characterized in that, wherein the primary side of this transformer has primary side winding and secondary auxiliary winding, this secondary auxiliary winding couples the 3rd electric terminal of this tri-terminal integration synchronous rectifier by diode, produces this synchronizing signal with the conduction and cut-off state according to this first power transistor.
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