CN101452863B - Manufacturing method for using compliant layer in grain reconfigured encapsulation construction - Google Patents

Manufacturing method for using compliant layer in grain reconfigured encapsulation construction Download PDF

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CN101452863B
CN101452863B CN2007101961025A CN200710196102A CN101452863B CN 101452863 B CN101452863 B CN 101452863B CN 2007101961025 A CN2007101961025 A CN 2007101961025A CN 200710196102 A CN200710196102 A CN 200710196102A CN 101452863 B CN101452863 B CN 101452863B
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crystal grain
sacrifice layer
layer
metal wire
active face
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CN101452863A (en
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吴佩宪
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

The invention relates to an encapsulation structure for reconfiguring crystal grains. The encapsulation structure comprises a crystal grain, an encapsulating body, a plurality of protrudent block structures, a plurality of patternized metal wire sections and a protective layer, wherein one active surface of the crystal grain is provided with a plurality of welding pads; the encapsulating body covers five sides of the crystal grain; the plurality of the protrudent block structures are formed from a macromelocular material and are arranged on the active surface of the crystal grain in an array mode; one end of each patternized metal wire section is in electric connection with the plurality of the welding pads on the active surface of the crystal grain; the other end of each patternized metal wire section extends and covers each protrudent block structure; and the protective layer is used for covering each patternized metal wire section and part of a patternized macromolecular material layer and exposing the protrudent block and the patternized metal wire section covered on the protrudent block structure.

Description

Use the manufacture method of compliant layer in the encapsulating structure that crystal grain reconfigures
Technical field
The invention relates to a kind of method for packing semiconductor, particularly relevant on crystal grain, forming macromolecular convex and metal level to replace the tin ball with as conducting element.
Background technology
Semi-conductive technology has developed suitable rapidly, therefore microminiaturized semiconductor grain (Dice) must have the demand of diversified function, make semiconductor grain must in very little zone, dispose more I/o pad (I/Opads), thereby make the density of metal pin (pins) also improve fast.Therefore, early stage leaded package technology has been not suitable for the high-density metal pin; So develop the encapsulation technology that a kind of ball array (Ball Grid Array:BGA), the ball array encapsulation is except having than the more highdensity advantage of leaded package, and its tin ball also relatively is not easy infringement and distortion.
Popular along with 3C Product, for example: mobile phone (CellPhone), PDA(Personal Digital Assistant) or iPod etc., all the System on Chip/SoC of many complexity must be put into a very little space, therefore be this problem of solution, a kind of being called " wafer-class encapsulation (waferlevel package; WLP) " encapsulation technology develops out, its can cut crystal become many crystal grain before, just earlier wafer is encapsulated.United States Patent (USP) announces the 5th, 323, has promptly disclosed this " wafer-class encapsulation " technology No. 051.Yet, this " wafer-class encapsulation " technology is along with the increase of the weld pad on the crystal grain active surface (pads) number, make that the spacing of weld pad (pads) is too small, except meeting causes the problem of signal coupling or signal interference, also can cause the problems such as reliability reduction of encapsulation because the weld pad spacing is too small.Therefore, after crystal grain further dwindles again, make aforesaid encapsulation technology all can't satisfy.
For solving this problem, United States Patent (USP) announces the 7th, 196, disclosed a kind of wafer that will finish semiconductor technology for No. 408, after test and cutting, with test result is that good crystal grain (good die) reapposes on another substrate, and then carry out packaging technology, so, make these intercrystallines that reapposed have the spacing of broad, so horizontal expansion (fan out) technology is for example used in distribution that can the weld pad on the crystal grain is suitable, therefore can effectively solve because of spacing too small, the problem that causes signal coupling or signal to disturb except meeting.
Yet, for making semiconductor chip that less and thin encapsulating structure can be arranged, before carrying out the wafer cutting, can carry out thinning to wafer earlier and handle, for example wafer is thinned to 2-20mil, and then cuts into many crystal grain in back of the body mill (backside lapping) mode.This crystal grain through the thinning processing through reconfiguring on another substrate, forms a packaging body packaging body with injection molded with a majority crystal grain again; Because crystal grain is very thin, make that packaging body also is very thin, so after packaging body disengaging substrate, the stress of packaging body itself can make packaging body generation warpage increases follow-up difficulty of carrying out cutting technique.
In addition, after the wafer cutting, reconfigure when another substrate, be of a size of greatly because the size of new substrate is more original, therefore plant in the ball technology follow-up, can can't aim at, its encapsulating structure reliability reduces.
Summary of the invention
Because the problem of planting ball aligning and packaging body warpage described in the background of invention, the invention provides a kind of registration mark that utilizes the crystal grain back side, and on crystal grain, form encapsulating structure and method thereof that metal level (UBM) reconfigures as the crystal grain of the electric connection of conducting element and weld pad, the method that most crystal grain are configured again and encapsulate.So main purpose of the present invention is to dispose adhesion coating on substrate, and crystal grain is utilized most the registration marks that substrate back disposes and can be seated on the adhesion coating of substrate accurately, and utilizing metal level (UBM) to form as conducting element and with weld pad respectively electrically connects, to carry out the method for packing that crystal grain reconfigures, make in subsequent technique, outside the technology of planting ball can be aimed at, packaging body itself can overcome stress and can make packaging body after breaking away from substrate, keep smooth, the yield of manufacturing and reliability can be effectively improved and low voltage component can be applied to, memory component for example is as RAM.
Another main purpose of the present invention is at the method for packing that provides a kind of crystal grain to reconfigure, it can be reconfigured in 12 inches crystal grain that wafer cut out on the substrate of 8 inches wafers, so can effectively use the sealed in unit that promptly has of 8 inches wafers, and need not to re-establish the sealed in unit of 12 inches wafers, can reduce the packaging cost of 12 inches wafers.
Of the present invention also have a main purpose at the method for packing that provides a kind of crystal grain to reconfigure, make that the chip that encapsulates all is " known is normally functioning chip " (Known good die), can save encapsulating material, so also can reduce the cost of technology.
A main purpose more of the present invention makes that at the method for packing that provides a kind of crystal grain to reconfigure the chip that encapsulates all is " known is normally functioning chip " (Known good die), can save encapsulating material, so also can reduce the cost of technology.
According to the above, the invention provides the method for packing that a kind of crystal grain reconfigures, comprising: most crystal grain are provided, and each crystal grain has and disposes most weld pads on active surface and the active surface; Pick and place on most crystal grain to one substrates, each crystal grain is to cover crystal type the adhesion coating that active surface and is disposed on the substrate to be connected; Form a polymer material layer on substrate and part crystal grain; Cover die device on polymer material layer,, and make polymer material layer riddle most intergranules and coat each crystal grain with the planarization polymer material layer; Break away from die device, to expose the surface of polymer material layer; Break away from substrate, with active surface and each weld pad that exposes each crystal grain, to form a packaging body; Form active surface and each weld pad of one first sacrifice layer to cover each crystal grain; Form one second sacrifice layer on first sacrifice layer; Remove partly second sacrifice layer and first sacrifice layer forming a ladder structure, and form most holes, to expose each weld pad at most weld pad places with respect to the active surface of each crystal grain; The metal wire sections that forms most patternings and forms and electrically connects with most weld pads on the active surface of each crystal grain on second sacrifice layer and first sacrifice layer; Form a patterned protective layer, covering the metal wire sections of most patternings, and expose the metal wire sections of the part patterning that is positioned on second sacrifice layer; And the cutting packaging body, to form most the crystal grain of independently finishing encapsulation separately, wherein five of each crystal grain faces coat by polymer material layer.
The method for packing that reconfigures according to above-mentioned crystal grain, the present invention also discloses a kind of wafer level chip encapsulating structure, comprise: dispose most weld pads on its active surface of a crystal grain, five faces of one packaging body coats crystal grain, the metal wire sections of the macromolecule borrow layer of one patterning and most patternings covers the partly polymer material layer of patterning, be electrically connected to most weld pads on the active surface of each crystal grain by the metal wire sections of most patternings, it is characterized in that: the polymer material layer of patterning, be on the active surface of crystal grain and a part of zone, the outside forms a step structure that stretches out (fan out), have higher structure in its hierarchic structure of wherein outward extending end points place and form a hole, to expose each weld pad at most weld pad places with respect to the active surface of crystal grain; The metal wire sections of a most patterning is to be formed on the polymer material layer of patterning, so that the metal wire sections of most patternings on the polymer material layer of most individual weld pad on the active surface of each crystal grain and step structure electrically connects; And a protective layer, with the metal wire sections that covers most patternings and the polymer material layer of patterning partly, and expose a surface of the metal wire sections of most patternings on the polymer material layer of the patterning that is positioned at higher position in the hierarchic structure.
Description of drawings
For making purpose of the present invention, structure, feature and function thereof there are further understanding, below cooperate embodiment and accompanying drawing to be described in detail as follows, wherein:
Fig. 1 is the schematic diagram of expression prior art;
Fig. 2 is disclosed technology according to the present invention, at the vertical view of the encapsulating structure at the back side of the substrate with registration mark; And
Fig. 3 A to Fig. 3 G is disclosed technology according to the present invention, each step schematic diagram of the encapsulating structure that the method for packing that utilizes the crystal grain of wafer aligned sign to reconfigure forms.
Embodiment
The present invention is the method for packing that a kind of crystal grain reconfigures in this direction of inquiring into, a majority crystal grain is reconfigured on another substrate the method that encapsulates then.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that the operator had the knack of of the mode of chip stack.On the other hand, the detailed step of last part technologies such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet, for preferred embodiment of the present invention, can be described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, its with after claim be as the criterion.
In the semiconductor packaging process in modern times, all be that a wafer (wafer) of having finished FEOL (Front End Process) is carried out thinning processing (Thinning Process) earlier, for example the thickness with chip is ground between the 2-20mil; Then, the cutting (sawing process) of carrying out wafer is to form many crystal grain; Then, use fetching device (pick and place) that many crystal grain are positioned on another substrate 100, as shown in Figure 1 one by one.Clearly, the crystal grain interval region on the substrate 100 is bigger than crystal grain 110, therefore, and can be so that these be by 110 spacings with broad of crystal grain of being reapposed, so distribution that can the weld pad on the crystal grain 110 is suitable.In addition, the employed method for packing of present embodiment, 12 inches crystal grain that wafer cut out 110 can be reconfigured on the substrate 100 of 8 inches wafers, so can effectively use the sealed in unit that promptly has of 8 inches wafers, and need not to re-establish the sealed in unit of 12 inches wafers, can reduce the packaging cost of 12 inches wafers.Be stressed that then, embodiments of the invention do not limit the substrate 100 that uses 8 inches wafer size, as long as it can provide the function of carrying, for example: glass, quartz, pottery, circuit board or sheet metal (metal foil) etc., all can be used as the substrate 100 of present embodiment, so the shape of substrate 100 is not limited yet.
Please refer to Fig. 2, is the vertical view that its back side of expression one substrate has registration mark.As shown in Figure 2, be to be illustrated on the x-y direction at the back side on the upper surface of wafer substrates, be provided with most registration marks (alignment mark) 202.Known to prior statement, after a wafer (not expression in the drawings) is through cutting, form most crystal grain, when again these crystal grain being configured in new substrate 20 one by one again, because the crystal grain interval region between the new substrate 20 is bigger than the crystal grain of configuration again, the ball step (ball mount) of planting in follow-up packaging technology is understood and can't be aimed at, and conducting element (expression) in the drawings is formed on accurately desired position on the back side of crystal grain, and cause the reliability of encapsulating structure to reduce.Therefore, in specific embodiments of the invention, the mode that forms registration mark 202 can be utilized photoetch (photo-etching) technology, and it is to form most registration marks 202 at the back side of substrate 20 and on the x-y direction, and it is shaped as the sign of cross.In addition, the mode that forms registration mark 202 also comprises utilizes laser label (laser mark) technology, to form most registration marks 202 on the back side of substrate 20.
Then, Fig. 3 A to Fig. 3 G is each step schematic diagram of the embodiment that reconfigures of expression the present invention disclosed crystal grain.At first, as shown in Figure 3A, be that a wafer (not expression in the drawings) that will dispose most crystal grain cuts, forming most crystal grain 210, each crystal grain 210 has an active surface and in disposing most weld pads 212 on the active surface and then most crystal grain 210 being reconfigured on new substrate 20; Wherein, on substrate 20, dispose an adhesion coating 30, this adhesion coating 30 is a rubber-like sticky material, for example silicon rubber (silicon rubber), silicones (silicon resin), elasticity PU, porous PU, acrylic rubber (acrylic rubber) or crystal grain cutting glue etc.Then, use fetching device (not representing in the drawings) crystal grain 210 to be placed and is pasted to the adhesion coating 30 on the substrate 20 one by one, wherein crystal grain 210 is covering crystalline substance (flip chip) mode and according to most the registration marks at substrate 20 back sides, and the weld pad on its active surface 212 is connected with adhesion coating 30 on the substrate 20.Then, same with reference to figure 3A, in substrate 20 and coating polymer material layer 40 on 210 on the crystal grain partly, polyimide for example, and use a die device 500 that polymer material layer 40 is flattened, make polymer material layer 40 form the surface of a planarization, and make polymer material layer 40 be filled between the crystal grain 210 and five faces of each crystal grain 210 coat by polymer material layer 40.
Then, can be optionally the polymer material layer 40 of planarization be carried out a baking program, so that polymer material layer 40 solidifies.Follow again, carry out demoulding program, with die device 500 with solidify after polymer material layer 40 separate, with the surface of the polymer material layer 40 that exposes planarization; Then, use cutter (not being shown among the figure) on the surface of polymer material layer 40, to form most bar Cutting Roads 410, shown in Fig. 3 B; The degree of depth of each bar Cutting Road 410 is 0.5-1 Mill (mil), and the width of Cutting Road 410 then is 5 to 25 microns.In preferable a embodiment, this Cutting Road 410 can be mutual vertical interlaced, and the reference line when can be used as actual cutting crystal grain.
At last, polymer material layer 40 is separated with substrate 20, for example polymer material layer 40 is put into the groove (expression) in the drawings of deionized water with substrate 20, polymer material layer 40 and adhesion coating 30 and substrate 20 are separated from each other, to form a packaging body; Five faces of each crystal grain 210 of this packaging body coats, and only expose weld pad 212 on the active surface of each crystal grain 210.Owing on the back side with respect to the active surface of crystal grain 210 of packaging body most bar Cutting Roads 410 are arranged, therefore after first polymer material layer 40 is peeled off with substrate 20, stress on the packaging body can be offset by these Cutting Road 410 formed zones, so can solve the problem of packaging body warpage effectively.
Then, shown in Fig. 3 C, form first sacrifice layer (dummylayer) 50 and second sacrifice layer 52 on most weld pads 212 on the active surface of each crystal grain 210, wherein the material of first sacrifice layer 50 and second sacrifice layer 52 can be polyimide or macromolecular material.Then, remove partly second sacrifice layer 52 and partly first sacrifice layer 50 and form most holes 60 forming a step structure at most weld pad 212 places with respect to the active surface of each crystal grain 210, to expose each weld pad 212; At this, remove partly second sacrifice layer 52 and partly first sacrifice layer 50 comprise with the step that forms a step structure: the photoresist layer (expression in the drawings) that on second sacrifice layer 52, forms a patterning; Then, carry out an etching step, for example Wet-type etching, is etched with and removes second sacrifice layer 52 partly as etch stop layer (etch stop layer) with first sacrifice layer 50; Then, again with the second residual sacrifice layer 52 as etch shield, be etched with and remove partly first sacrifice layer 50, forming most holes 60 with respect to most weld pad 212 places, and exposing most weld pads 212.At this, second sacrifice layer 52 of patterning and first sacrifice layer 50 are positioned at a part of zone of the active surface of each crystal grain 210 and the outside thereof and form a step structure that stretches out (fan out), partly having higher structure wherein is for second sacrifice layer 52, shown in Fig. 3 D.
Then, as Fig. 3 E, be form most patternings metal wire sections 70 on second sacrifice layer 52 and first sacrifice layer 50, and the metal wire sections 70 of each patterning is that most weld pads 212 on the active surface with each crystal grain 210 form and electrically connect; The step that wherein forms the metal wire sections 70 of patterning comprises: form a metal level (not expression in the drawings) to cover on second sacrifice layer 52 and first sacrifice layer 50; Utilize semiconductor process techniques, sharp as development and etching at first, form a patterning photoresist layer (expression in the drawings) on metal level; Be etched with and remove partly metal level, be retained in the metal level on second sacrifice layer 52 and the most individual weld pad 212, to form the metal wire sections 70 of most patternings; And the photoresist layer of strip patternization.In addition, metal wire sections can be the UBM metal level, and its material can be Ti/Cu or TiW/Cu; And the thickness that is formed on the UBM metal level 70 on second sacrifice layer 52 of patterning is about 5 microns.
Then, shown in Fig. 3 F, form the structure that a protective layer 80 is illustrated with coverage diagram 3E; Next, utilize semiconductor process techniques, for example develop and etching, the photoresist layer (not expression in the drawings) that forms a patterning earlier is on protective layer 80; Be etched with and remove protective layer 80 partly to expose the metal wire sections 70 of most patternings on second sacrifice layer 52; And the photoresist layer of strip patternization.At this, the pattern metal line segment 70 and second sacrifice layer 52 that are positioned on second sacrifice layer 52 can be considered as a tin ball, yet the metal wire sections 70 by patterning can electrically connect with weld pad 212, it has omitted in the technology that generally reroutes (RDL), after metal wire sections forms, also must on metal wire sections, plant a step of ball, therefore, in the encapsulating structure that this crystal grain reconfigures, the metal wire sections 70 that is positioned at the patterning on second sacrifice layer 52 can replace the tin ball as conducting element.At last, cut packaging body, to form most the crystal grain of independently finishing encapsulation separately, shown in Fig. 3 G.
In addition, the method that forms the metal wire sections 70 of most patternings can also be behind the formation step structure, on the surface of second sacrifice layer 52, first sacrifice layer 50 and most holes 60, form a crystal seed layer (seed layer) (not expression in the drawings) earlier, and then on crystal seed layer, form metal level in the mode of electroplating, and then utilize semiconductor process techniques, for example develop and etching, form the photoresist layer (not expression in the drawings) of a patterning earlier, be etched with and remove partly metal level and crystal seed layer; The photoresist layer of strip patternization, with the metal wire sections 70 that forms most patternings on the surface of second sacrifice layer 52, with as conducting element.
Though the present invention discloses as above with aforesaid preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of alike operator; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, therefore scope of patent protection of the present invention must be looked being as the criterion that the appended claim scope of this specification defined.

Claims (6)

1. the method for packing that crystal grain reconfigures is characterized in that, comprising:
A plurality of crystal grain are provided, and each this crystal grain has on an active face and this active face and disposes a plurality of weld pads, and each this crystal grain is the normal crystal grain of known function;
Pick and place on described a plurality of crystal grain to one substrate, each this crystal grain is to cover crystal type the adhesion coating that this active face and is disposed on this substrate to be connected, and wherein a back side of a back side of this substrate and each this crystal grain all disposes a plurality of registration marks;
Form a polymer material layer on this substrate and the described a plurality of crystal grain of part;
Cover a die device to this polymer material layer,, make this polymer material layer riddle described a plurality of intergranule and coat each this crystal grain with this polymer material layer of planarization;
Break away from this die device, to expose a surface of this polymer material layer;
Break away from this substrate, with this active face and each this weld pad that exposes each this crystal grain, to form a packaging body;
Form one first sacrifice layer this active face and each this weld pad to cover each this crystal grain;
Form one second sacrifice layer on this first sacrifice layer;
Remove part this second sacrifice layer and this first sacrifice layer forming a step structure, and form a plurality of holes, to expose each this weld pad at described a plurality of weld pads place with respect to this active face of each this crystal grain;
The metal wire sections that forms a plurality of patternings and forms described a plurality of weld pads on this active face of the end of metal wire sections of described a plurality of patternings and each this crystal grain to electrically connect on this second sacrifice layer and this first sacrifice layer;
Form a patterned protective layer, with the part that covers described a plurality of pattern metal line segments and expose the metal wire sections that is positioned at the described a plurality of patternings of part on this second sacrifice layer; And
Cut this packaging body, to form a plurality of crystal grain of independently finishing encapsulation separately.
2. the method for packing that crystal grain as claimed in claim 1 reconfigures is characterized in that, wherein removes this second sacrifice layer and this first sacrifice layer and comprises with the step that formation has this step structure of height:
Form a patterning photoresist layer on this second sacrifice layer;
With this first sacrifice layer is etch stop layer, is etched with to remove this second sacrifice layer of part; And
With this second sacrifice layer of part is shielding, removes this first sacrifice layer of part and forms described a plurality of hole in the described a plurality of weld pads place with respect to this active face of each this crystal grain, to expose each this weld pad.
3. the method for packing that crystal grain as claimed in claim 1 reconfigures is characterized in that, wherein removes this first sacrifice layer and this second sacrifice layer is to be formed by a wet etch process.
4. the method for packing that crystal grain as claimed in claim 1 reconfigures is characterized in that, the metal wire sections that wherein forms described a plurality of patternings comprises:
Form a metal level to cover on this second sacrifice layer and this first sacrifice layer;
The photoresist layer that forms a patterning is on this metal level;
Remove this metal level of part, to be retained in the metal level on this second sacrifice layer and the described weld pad, to form the metal wire sections of described patterning.
5. the method for packing that crystal grain as claimed in claim 4 reconfigures is characterized in that, wherein removing this metal level of part is to utilize Wet-type etching.
6. the encapsulating structure that crystal grain reconfigures is characterized in that, comprising:
One crystal grain disposes a plurality of weld pads on the one active face, wherein this each this crystal grain is that the known normally functioning crystal grain and a back side of each this crystal grain all dispose a plurality of registration marks;
One packaging body coats five faces of this crystal grain and exposes this active face of this crystal grain;
The formed projection cube structure of a plurality of macromolecular materials is disposed at array way on the active face of this crystal grain;
The metal wire sections of a plurality of patternings, a plurality of weld pads on the active face of one end and this crystal grain electrically connect, and its other end then extends in the fan-out mode and is covered on each this projection cube structure; And
One protective layer in order to metal wire sections and the part packaging body that covers described patterning, and exposes this projection and is covered in the metal wire sections of the described a plurality of patternings on this projection cube structure.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751060A (en) * 1995-01-25 1998-05-12 International Business Machines Corporation Electronic package
US6214640B1 (en) * 1999-02-10 2001-04-10 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages
US6486005B1 (en) * 2000-04-03 2002-11-26 Hynix Semiconductor Inc. Semiconductor package and method for fabricating the same
CN1431708A (en) * 2002-01-10 2003-07-23 裕沛科技股份有限公司 Wafer formed diffusion type capsulation structure and its mfg. methods

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751060A (en) * 1995-01-25 1998-05-12 International Business Machines Corporation Electronic package
US6214640B1 (en) * 1999-02-10 2001-04-10 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages
US6486005B1 (en) * 2000-04-03 2002-11-26 Hynix Semiconductor Inc. Semiconductor package and method for fabricating the same
CN1431708A (en) * 2002-01-10 2003-07-23 裕沛科技股份有限公司 Wafer formed diffusion type capsulation structure and its mfg. methods

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