CN101425799B - Protection circuit for avoiding overvoltage bearing by NMOS component - Google Patents

Protection circuit for avoiding overvoltage bearing by NMOS component Download PDF

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Publication number
CN101425799B
CN101425799B CN200710166739XA CN200710166739A CN101425799B CN 101425799 B CN101425799 B CN 101425799B CN 200710166739X A CN200710166739X A CN 200710166739XA CN 200710166739 A CN200710166739 A CN 200710166739A CN 101425799 B CN101425799 B CN 101425799B
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China
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voltage
source
grid
coupled
transistor
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CN200710166739XA
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Chinese (zh)
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CN101425799A (en
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叶俊文
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晨星半导体股份有限公司
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Publication of CN101425799A publication Critical patent/CN101425799A/en
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Abstract

The invention provides a protection circuit referring to an NMOS assembly, which comprises a series connection NMOS transistor and an adjusting circuit, wherein the series connection transistor is connected in series between the NMOS assembly and an external voltage source, and the adjusting circuit is coupled to the external voltage source, a first internal voltage source and a gate pole of the series connection NMOS transistor and is used for adjusting the voltage of the gate pole of the series connection NMOS transistor according to the external voltage source and the voltage of the first internal voltage source so as to prevent the NMOS assembly from bearing the over-high voltage caused by the external voltage source.

Description

In order to avoid the NMOS assembly to bear the protective circuit of too high voltages

Technical field

The present invention relates to protective circuit, particularly a kind of in order to avoid the NMOS assembly to bear the protective circuit of too high voltages.

Background technology

Owing to the progress of integrated circuit technique, the size of CMOS transistor component is constantly dwindled in recent years.In order to cooperate the characteristic of small size components, and reduce the power that the CMOS transistor component consumes, be supplied to the supply voltage of CMOS transistor component also can to descend usually along with the size of assembly.

Yet early the integrated circuit (IC) chip of producing still adopts higher supply voltage (for example 5V).In order to cooperate these to adopt the circuit of higher supply voltage, adopt the circuit of lower supply voltage (for example 3.3V or 1.8V) must utilize special circuit framework as the interface circuit between high low-voltage.See also Fig. 1, Fig. 1 is the embodiment of an interface circuit in the prior art.

As shown in Figure 1, a series connection nmos pass transistor NC is serially connected with between a NMOS component N D and the external voltage source VEXT.The grid of transistor NC is coupled to the internal source voltage VINT of the integrated circuit under it usually.The effect of transistor NC is to provide the cross-pressure between its drain electrode and the source electrode, directly bears the too high voltages that external voltage source VEXT may cause to avoid NMOS component N D.

With the voltage of outside voltage source V EXT is that the voltage of 5V and internal source voltage VINT is that 3.3V is an example.The source voltage of transistor NC is usually less than the voltage of grid, and its voltage difference is the limit voltage (threshold voltage) of transistor NC itself.Therefore, when the grid voltage of transistor NC is 3.3V, transistor.The source voltage of NC can approximate 2.3V.Under this situation, the drain electrode of transistor NC and the cross-pressure between source electrode are 2.7V.Because still in the scope that transistor NC can bear, transistor NC can't meet with the problem of too high voltages to this cross-pressure, therefore can bring into play the function of protection component N D.

Yet if the voltage of external voltage source VEXT is 5V, the voltage of internal source voltage VINT is reduced to 1.8V, and the source voltage of transistor NC will approximate 1V, and the drain electrode of transistor NC and the cross-pressure between source electrode are 4V.Under this situation, transistor NC is just probably because of too high voltage is damaged, and thereby the effect of forfeiture protection component N D.

Summary of the invention

For addressing the above problem, the invention provides a kind of protective circuit.In protective circuit of the present invention, the voltage of grid that is supplied to transistor NC is relevant with the voltage of outer/inner voltage source.Say that more clearly this voltage can suitably be adjusted along with the change in voltage of outer/inner voltage source.Whereby, protective circuit of the present invention can make transistor NC maintain normal operating state, and then protection component N D avoids bearing the too high voltages that causes because of external voltage source.

A preferred embodiment of the present invention is a protective circuit at the NMOS assembly, wherein comprises a series connection nmos pass transistor and and adjusts circuit.This series connection nmos pass transistor is serially connected with between this a NMOS assembly and the external voltage source.This adjustment circuit is coupled to this external voltage source, one first internal source voltage; an and grid of the nmos pass transistor of should connecting; and in order to voltage according to this external voltage source and this first internal source voltage; adjust the voltage of this grid of this series connection nmos pass transistor, protect this NMOS assembly to avoid bearing a too high voltages that causes because of this external voltage source whereby.

Description of drawings

For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment of the present invention is described in detail below in conjunction with accompanying drawing:

Fig. 1 is the embodiment of an interface circuit in the prior art;

Fig. 2 is the schematic diagram of protective circuit of the present invention; And

Fig. 3 A, Fig. 3 B, Fig. 4 and Fig. 5 are the preferred embodiments of adjustment circuit of the present invention.

Embodiment

A preferred embodiment of the present invention is a protective circuit at the NMOS assembly.See also Fig. 2, Fig. 2 is the schematic diagram of this protective circuit.In this embodiment, protective circuit 20 is born too high voltage in order to avoid NMOS component N D, and it comprises a series connection nmos pass transistor NC and and adjusts circuit 22.

Transistor NC is serially connected with between a component N D and the external voltage source VEXT.Adjust 22 in circuit and be coupled to this external voltage source VEXT, one first internal source voltage VINT, and the grid of transistor NC, and, adjust the voltage of the grid of transistor NC in order to voltage according to the external voltage source VEXT and the first internal source voltage VINT.

According to the present invention,, adjust circuit 22 and can make the voltage of the grid of transistor NC approximate the voltage of the first internal source voltage VINT when the voltage of external voltage source VEXT is less than or equal to the voltage of the first internal source voltage VINT.When the voltage of external voltage source VEXT is higher than the voltage of the first internal source voltage VINT, adjust the voltages that 22 in circuit can appropriateness be heightened the grid of transistor NC, with the drain electrode of dwindling transistor NC and the cross-pressure between source electrode.Whereby, adjusting circuit 22 can avoid transistor NC to be damaged because of too high voltages.Protective circuit 20 and then can protect component N D to avoid bearing the too high voltages that causes because of external voltage source VEXT.

Voltage with the first internal source voltage VINT is that 1.8V is an example.If the voltage of external voltage source VEXT is 0~1.8V, adjusts circuit 22 and can make that the voltage of the grid of transistor NC is 1.8V.Relatively, if the voltage of external voltage source VEXT is 1.8~5V, then adjust circuit 22 and can be supplied to the voltage lifting of the grid of transistor NC to be 1.8V~3.3V, the voltage of the grid of transistor NC and the voltage of external voltage source VEXT have a proportionate relationship at this moment.

See also Fig. 3 A, Fig. 3 A is a preferred embodiment of adjusting circuit 22.In this embodiment, the voltage of the first internal source voltage VINT is assumed to be 1.8V; Adjust circuit 22 and comprise a voltage divider 22A, a switch 22B and one the 2nd PMOS transistor P2.Voltage divider 22A is coupled between external voltage source VEXT and one second internal source voltage (earth terminal).Voltage divider 22A among this embodiment is made up of MOS transistor; In actual applications, the constituent components of voltage divider 22A is not as limit.In addition, switch 22B is coupled between the grid of external voltage source VEXT and transistor P2.The source electrode of transistor P2 and drain electrode then are coupled to the grid of the first internal source voltage VINT and transistor NC respectively.

Switch 22B among this embodiment comprises one the 3rd of transmission gate (transmission gate) form that is coupled to: PMOS transistor P3 and one first nmos pass transistor N1.The grid of transistor P3 and transistor N1 all is coupled to the first internal source voltage VINT.When the voltage of external voltage source VEXT between 0~1.8V, the voltage of the grid of transistor P2 can be a little less than 1.8V.Because the small voltage difference that exists between the grid of transistor P2 and the source electrode, transistor P2 can be in linear condition or inferior limit (sub-threshold) state that faces; Therefore the voltage of the grid of transistor NC can be charged to 1.8V by transistor P2.Because the voltage of external voltage source VEXT is not higher than 1.8V, under this situation, transistor NC can't meet with the problem of too high voltages, therefore can bring into play the function of protection component N D.

Voltage divider 22A offers the dividing potential drop of the grid of transistor NC can be along with the change in voltage of external voltage source VEXT.By suitably designing the resistance of each assembly among the voltage divider 22A, when the voltage of external voltage source VEXT is 5V, the dividing potential drop that voltage divider 22A offers the grid of transistor NC can be set to 3.3V.Under this situation, the voltage of the source electrode of transistor NC can approximate 2.3V, and drain electrode and the cross-pressure between source electrode of transistor NC then approximate 2.7V.Because this cross-pressure value is still in the scope that transistor NC can bear, but also operate as normal of transistor NC, the function of performance protection component N D.In addition, when the voltage of external voltage source VEXT is 5V, the voltage of the grid of transistor P2 also can approximate 5V; Therefore transistor P2 can be closed.

See also Fig. 3 B, Fig. 3 B is another preferred embodiment of adjusting circuit 22.In this embodiment, adjust circuit 22 and further comprise one the one a PMOS transistor P1 and an electrostatic defending resistance R ESD.Electrostatic defending resistance R ESD is subjected to the destruction of electrostatic charge in order to the circuit that prevents to be connected to external voltage source VEXT.

The grid of transistor P1, source electrode and drain electrode are coupled to the first internal source voltage VINT, external voltage source VEXT respectively, and voltage divider 22A.When the voltage of external voltage source VEXT between 0~1.8V, transistor P1 can be closed, therefore working as voltage divider 22A is resistance embodiment, and external voltage source VEXT is 0 o'clock, can prevent to produce drain current path between the grid of transistor NC and external voltage source VEXT, cause the grid voltage of transistor NC to be affected.

See also Fig. 4, Fig. 4 is for adjusting another preferred embodiment of circuit 22.In this embodiment, between the two ends of the voltage divider 22A difference external voltage source VEXT and the first internal source voltage VINT.Whereby, when the voltage of external voltage source VEXT is lower than 1.8V (that is when transistor P2 be conducting), voltage divider 22A can not provide the first internal source voltage VINT and the leakage path between the earth terminal originally.

In actual applications, when the voltage of the first internal source voltage VINT is 1.8V, because the relation of time threshold current, the voltage of the grid of transistor P2 might be charged to 1.8V; Therefore transistor P2 may be closed and cause the voltage of the grid of transistor NC to enter uncertain state.For preventing this from occurring, adjust circuit 22 and can further comprise one second nmos pass transistor N2 and one the 3rd nmos pass transistor N3.See also Fig. 5, Fig. 5 adjusts the corresponding schematic diagram of circuit 22 for this reason.Transistor N2 and transistor N3 can provide a little leakage path between the grid of transistor P2 and earth terminal, make the grid of transistor P2 remain state a little less than 1.8V, may pent problem to solve above-mentioned transistor P2.

As previously discussed, in protective circuit of the present invention, the voltage that is supplied to the grid of transistor NC is fitted the property adjustment according to the voltage of outer/inner voltage source.Whereby, protective circuit of the present invention can guarantee that transistor NC maintains normal state, and D avoids bearing the too high voltages that causes because of external voltage source with the protection component N.

Below preferred embodiment of the present invention is specified, but the present invention is not limited to described embodiment, those of ordinary skill in the art also can make all modification that is equal to or replacement under the prerequisite of spirit of the present invention, modification that these are equal to or replacement all are included in the application's claim institute restricted portion.

Claims (8)

1. one kind in order to avoid a NMOS assembly to bear the protective circuit of too high voltages, it is characterized in that, comprises:
One series connection nmos pass transistor is serially connected with between a described NMOS assembly and the external voltage source; And
One adjusts circuit; be coupled to described external voltage source; one first internal source voltage; an and grid of described series connection nmos pass transistor; in order to voltage according to described external voltage source and described first internal source voltage; adjust the voltage of the described grid of described series connection nmos pass transistor; protect described NMOS assembly to avoid bearing a too high voltages that causes because of described external voltage source whereby; wherein said adjustment circuit comprises a voltage divider; described voltage divider is coupled between described external voltage source and one second internal source voltage; when the voltage of described external voltage source is higher than the voltage of described first internal source voltage, described voltage divider offers a dividing potential drop the described grid of described series connection nmos pass transistor.
2. protective circuit as claimed in claim 1; it is characterized in that: described adjustment circuit further comprises one the one PMOS transistor; the transistorized grid of a described PMOS is coupled to described first internal source voltage; the transistorized one source pole of a described PMOS is coupled to described external voltage source, and the transistorized drain electrode of a described PMOS is coupled to described voltage divider.
3. one kind in order to avoid a NMOS assembly to bear the protective circuit of too high voltages, it is characterized in that, comprises:
One series connection nmos pass transistor is serially connected with between a described NMOS assembly and the external voltage source; And
One adjusts circuit; be coupled to described external voltage source; one first internal source voltage; an and grid of described series connection nmos pass transistor; in order to voltage according to described external voltage source and described first internal source voltage; adjust the voltage of the described grid of described series connection nmos pass transistor; protect described NMOS assembly to avoid bearing a too high voltages that causes because of described external voltage source whereby; wherein said adjustment circuit comprises a voltage divider; described voltage divider is coupled between described external voltage source and described first internal source voltage; when the voltage of described external voltage source is higher than the voltage of described first internal source voltage, described voltage divider offers a dividing potential drop the described grid of described series connection nmos pass transistor.
4. protective circuit as claimed in claim 3; it is characterized in that: described adjustment circuit further comprises one the one PMOS transistor; the transistorized grid of a described PMOS is coupled to described first internal source voltage; the transistorized one source pole of a described PMOS is coupled to described external voltage source, and the transistorized drain electrode of a described PMOS is coupled to described voltage divider.
5. one kind in order to avoid a NMOS assembly to bear the protective circuit of too high voltages, it is characterized in that, comprises:
One series connection nmos pass transistor is serially connected with between a described NMOS assembly and the external voltage source; And
One adjusts circuit; be coupled to described external voltage source; one first internal source voltage; an and grid of described series connection nmos pass transistor; in order to voltage according to described external voltage source and described first internal source voltage; adjust the voltage of the described grid of described series connection nmos pass transistor; protect described NMOS assembly to avoid bearing a too high voltages that causes because of described external voltage source whereby; wherein said adjustment circuit comprises a switch and one the 2nd PMOS transistor; described switch is coupled between described external voltage source and the transistorized grid of described the 2nd PMOS; the transistorized one source pole of the 2nd PMOS is coupled to described first internal source voltage; the transistorized drain electrode of the 2nd PMOS is coupled to the described grid of described series connection nmos pass transistor; when the voltage of described external voltage source is lower than the voltage of described first internal source voltage, described switch makes described the 2nd PMOS transistor turns.
6. protective circuit as claimed in claim 5; it is characterized in that: described switch comprises one the 3rd PMOS transistor and one first nmos pass transistor of the transmission gate form that is coupled to, and a grid of transistorized grid of described the 3rd PMOS and described first nmos pass transistor all is coupled to described first internal source voltage.
7. protective circuit as claimed in claim 5; it is characterized in that: described adjustment circuit further comprises one second nmos pass transistor and one the 3rd nmos pass transistor; one grid of described second nmos pass transistor is coupled to the described grid of described series connection nmos pass transistor; one drain electrode of described second nmos pass transistor is coupled to the transistorized grid of described the 2nd PMOS; the one source pole of described second nmos pass transistor is coupled to a drain electrode of described the 3rd nmos pass transistor, and the one source pole of described the 3rd nmos pass transistor and a grid all are coupled to one second internal source voltage.
8. as each described protective circuit in the claim 1,3,5, it is characterized in that: be coupled with an electrostatic defending resistance between described external voltage source and the described adjustment circuit.
CN200710166739XA 2007-11-02 2007-11-02 Protection circuit for avoiding overvoltage bearing by NMOS component CN101425799B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200710166739XA CN101425799B (en) 2007-11-02 2007-11-02 Protection circuit for avoiding overvoltage bearing by NMOS component

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Application Number Priority Date Filing Date Title
CN200710166739XA CN101425799B (en) 2007-11-02 2007-11-02 Protection circuit for avoiding overvoltage bearing by NMOS component

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CN101425799B true CN101425799B (en) 2011-04-20

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1655086A (en) * 2005-02-25 2005-08-17 清华大学 Bias compensation circuit for adjusting transconductance variation range of transistor in load
CN1868104A (en) * 2003-10-10 2006-11-22 飞思卡尔半导体公司 Electrostatic discharge protection circuit and method of operation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1868104A (en) * 2003-10-10 2006-11-22 飞思卡尔半导体公司 Electrostatic discharge protection circuit and method of operation
CN1655086A (en) * 2005-02-25 2005-08-17 清华大学 Bias compensation circuit for adjusting transconductance variation range of transistor in load

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Effective date of registration: 20191213

Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China

Patentee after: MediaTek.Inc

Address before: Taiwan Hsinchu County Tai Yuan Street China jhubei City, No. 26 4 floor 1

Patentee before: MStar Semiconductor Co., Ltd.