CN101425329B - Semiconductor storage device - Google Patents
Semiconductor storage device Download PDFInfo
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- CN101425329B CN101425329B CN2008101311642A CN200810131164A CN101425329B CN 101425329 B CN101425329 B CN 101425329B CN 2008101311642 A CN2008101311642 A CN 2008101311642A CN 200810131164 A CN200810131164 A CN 200810131164A CN 101425329 B CN101425329 B CN 101425329B
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Abstract
This invention discloses a semiconductor storage device, comprising: a data line sense amplifier/write buffer (6) connected to data lines DL and XDL of a memory array (1), a data line sense amplifier control signal generating logic circuit connected to a dummy data lines DDL and XDDL of a dummy memory array (2). The sense amplifier (6) is activated in accordance with an output signal of the logic circuit (7). Therefore, in a semiconductor storage device, such as a dynamic random access memory (DRAM) which amplifies and read the dynamic data is capable of accessing in a high speed and easily realizing size of each memory.
Description
Technical field
The present invention relates to a kind of semiconductor storage that comprises dynamic RAM (DRAM) etc.
Background technology
The high speed of semiconductor storage has in recent years changed into important problem, and the high speed of carrying storer of mixing that particularly is used in the system LSI has changed into important problem.Utilize the technology in the moment that the data on the bit line that duplicate circuit determines in sensor amplifier to read from storage unit theoretically amplify, a kind of means that solve this technical problem exactly.Can moment tolerance limit optimization can also be dealt with the influence of external condition, process deviation etc. simultaneously by this technology.
Figure 15 shows the circuit structure that contains duplicate circuit of existing DRAM.In this circuit structure, comprise: respectively by a transistor and the storage unit MC that capacitor constitutes; Word line WL0; WL1; Bit line is to BL0～BLn/XBL0～XBLn; Sensor amplifier SA0～SAn that this bit line is amplified the data of BL0～BLn/XBL0～XBLn; Illusory storage unit DMC; Dummy word line DWL; Dummy is to DBL/XDBL; Detect this dummy to the data of DBL/XDBL and produce the data detection circuit 201 of signal; In order to start the SA control signal generation circuit 202 (reference example such as patent documentation 1) of sensor amplifier SA0～SAn.
Utilize the sequential chart of Figure 16 that the core action by the existing semiconductor storage of above-mentioned formation is described.At first,, select word line WLO just to be activated, transferred to bit line BL0～BLn from charge storing unit if DRAM is had visiting demand.Because this moment, dummy word line DWL also was activated simultaneously, so electric charge is transferred to dummy DBL equally.This electric charge passes on action and can cause the potential level of dummy DBL to change, if this changing value surpasses the threshold value of data detection circuit 201, SA control signal generation circuit 202 just is activated, and produces SA control signal SEN.Sensor amplifier SA also just can be amplified to desirable current potential to BL/XBL with bit line by this signal enabling.
Because, can eliminate the misoperation of circuit, and realize optimization constantly, move high speed constantly so can make through utilizing illusory storage unit to determine the moment that is exaggerated up to bit line data theoretically like this.
Patent documentation 1: Japanese publication communique spy opens flat 6-176568 communique
Summary of the invention
But the problem under the existing structure is when utilizing the charge detection level, if the potential change amount is no more than threshold value, just can not carry out correct circuit operation.Particularly, resembling under the situation that capacity is very small the storage unit, the problems referred to above that influence that receive process deviation, leakage current etc. are exactly very important.
When preset threshold has for example surpassed transistorized threshold value, compare with the potential change that embodies bit line from storage unit, will become very large current potential generally speaking.For example, reduce, make the stray capacitance minimizing of bit line etc., just need make plane arrangement structure and common memory cell array that very big difference is arranged in order to make illusory charge storing unit amount.If so, then be difficult to generate the correct moment that starts sensor amplifier as duplicate circuit.This also is a problem.
Utilizing reference potential etc. to read under the situation of small potential difference (PD), carrying out circuit design and must guarantee that this design can tackle the reference potential of process deviation, external condition.Reserve the area of additional quantity for arranging reference circuit.This also is a problem.
Carry out 1 at needs resemble DRAM) electric charge read operation, 2) sensing, preserve operation, 3 again) under the circuit structure of these three kinds of memory cell operations of precharge operation; Be exactly only to make electric charge read operation high speed; Can what big effect not arranged to the high speed of the whole operation of storage unit, the high speed to access does not have any big effect yet equally yet.
For example, under the circuit structure of static RAM (SRAM), be to come sense data through electric current is transferred to bit line.But DRAM is different with SRAM, and DRAM stores data at capacitor with electric charge; The quantity that is connected the storage unit on the bit lines is limited by the capacity ratio, the sensitivity of sensor amplifier of stray capacitance of electric capacity and the bit line of storage unit; So, in the quantity that is connected the storage unit on the bit line through change freely, that is; The bar number of word line; When being launched (line up), memory span entire team (for example, under several 512 situation of 16～512 of word number of lines, bit line bar, can memory span be carried out diversified expansion between 8KB～256KB); Even compromise consider to utilize duplicate circuit to generate best sensor amplifier corresponding to memory span to start the area additional quantity of this way and duplicate circuit constantly, also hopelessly receive too big effect.
And; Resemble and mix to carry a storer, particularly carry a DRAM as mixing, memory span is big and need under the situation of various specifications expansion; No matter from still dwindling of the stability of circuit operation from circuit area; Do not change the number of memory cells that is connected on the bit line, and the quantity that changes the memory array contain bit line realizes that the number of memory cells that is connected on the bit line than change is more effective.Therefore; Compare constantly with the startup of the sensor amplifier that determines theoretically bit line is amplified; The startup of the sensor amplifier that determines theoretically length of arrangement wire, electric charge are amplified along with the memory span data line that great changes will take place constantly; Just being not only the important topic that realizes high speed, also is the important topic that can easily realize various storer specifications.
The present invention researchs and develops out for addressing the above problem just; Its purpose is: provide a kind of through determining theoretically to the startup of the sensor amplifier that changes according to memory span and amplify from the heaviest data line of access time load constantly; Realize access at a high speed; Shorten the access time, and can realize the semiconductor storage of various storer specifications at an easy rate.
For addressing the above problem; Semiconductor storage of the present invention comprises: the logical circuit that storage unit, the word line that is connected with said storage unit and bit line, first sensor amplifier that is connected with said bit line, illusory storage unit, the dummy that is connected with said illusory storage unit, second sensor amplifier that is connected with said dummy, the data line that is connected with said first sensor amplifier, the third reading that is connected with said data line go out amplifier, the dummy data line that is connected with said second sensor amplifier and be connected with said dummy data line.The output signal of said logical circuit is to start the input signal that said third reading goes out amplifier.
Said logical circuit; With utilizing the current potential on the said dummy data line to detect the signal that the static data that in said second sensor amplifier that the dynamic data that reads into said dummy is amplified, generates has surpassed transistorized conduction and cut-off current potential and output, as starting the input signal that said third reading goes out amplifier.
So; Be utilized in that second sensor amplifier amplifies and gone out by the third reading that the potential level on the dummy data line that passes on amplifies data line under the duplicate circuit structure in the moment of amplifier in generation, the best that can be created on the data line that load all can alter a great deal under each memory span is passed on the moment.
Utilizing second sensor amplifier to make electric current flow into the dummy data line; And under the structure of this electric current of logical circuit detection; The such circuit operation bad phenomenon of threshold value of testing circuit can not take place to surpass; The plane arrangement structure of dummy circuit part does not have very big variation yet, therefore, and can be by about institutes such as technologic deviation, external condition.
Because be connected the word line on the illusory storage unit, the word line that is connected on the storage unit is same wiring; So need not set the area additional quantity of a duplicate circuit; Simultaneously; Because by from physically generating constantly with being started by the very near place of the storage unit of access, error is very little constantly so can make.
Illusory storage unit is with to contain the line decoder of word line driver adjacent and establish; Delay circuit with output time of regulating logical circuit, so, through generating the startup moment that third reading goes out amplifier the earliest; Just can realize the access high speed; Simultaneously, because can utilize this delay circuit that inching is carried out in the startup that third reading goes out amplifier constantly, so can prevent because the misoperation that constantly causes too early.
Utilizing switch that plural second sensor amplifier is connected under the structure on the dummy data line; The threshold size that goes out amplifier when the threshold size and the third reading of logical circuit is for example 4: 1 the time; 4 second sensor amplifiers are coupled together, can realize that just third reading goes out the optimum actuation moment of amplifier.
Comprise logic with dummy data line of getting more than two and the logical circuit of function, the data of the dummy data line more than two are identical logical values.So, through the startup moment that logic and the generation third reading of utilizing the dummy data line goes out amplifier, even then rub-out signal is transferred to the dummy data line, the such bad phenomenon of startup moment signal that third reading goes out amplifier can not take place not generate yet.
Through adopting redundancy structure, when word line, be connected storage unit or illusory storage unit on the word line and exist bad the time, also can save storer through being replaced into this way of redundant word line.
The data that have illusory storage unit read into outside device, so just can the used duplicate circuit of judgment data line very deny.
As stated; According to the present invention; Can provide a kind of through determining theoretically constantly to the startup of the sensor amplifier that changes along with memory span and amplify from the heaviest data line of access time load; Realize access at a high speed, shorten the access time, and can realize the semiconductor storage of various storer specifications at an easy rate.
The simple declaration of accompanying drawing
Fig. 1 is the block scheme of primary structure that shows the semiconductor storage of first embodiment of the invention.
Fig. 2 is the block scheme of the particular circuit configurations of the memory array in the displayed map 1, illusory memory array and line decoder.
Fig. 3 is that data line in the displayed map 1 is with the circuit diagram of the particular circuit configurations of sensor amplifier/write buffer.
Fig. 4 is that data line in the displayed map 1 is with the circuit diagram of the particular circuit configurations of sensor amplifier control signal formation logic circuit.
Fig. 5 is the sequential chart of the data read operation of the semiconductor storage in the displayed map 1.
Fig. 6 is the circuit diagram of the data line of displayed map 4 with the variation of sensor amplifier control signal formation logic circuit.
Fig. 7 is the block scheme of the variation of the illusory memory array in the displayed map 2.
Fig. 8 is the block scheme of other variation of the illusory memory array in the displayed map 2.
Fig. 9 is the block scheme that shows the primary structure of the semiconductor storage in the variation of first embodiment of the present invention.
Figure 10 is the data line in the displayed map 9 is controlled the particular circuit configurations of formation logic circuit with sensor amplifier a circuit diagram.
Figure 11 is the block scheme of particular circuit configurations that shows memory array, illusory memory array and the line decoder of the semiconductor storage in second embodiment of the present invention.
Figure 12 is the sequential chart that shows the data write operation of the semiconductor storage in the 3rd embodiment of the present invention.
Figure 13 is the block scheme of the primary structure of the semiconductor storage in the variation of the 3rd embodiment of the present invention.
Figure 14 is the block scheme that shows the primary structure of the semiconductor storage in the 4th embodiment of the present invention.
Figure 15 is the block scheme that shows the primary structure of conventional semiconductor memory storage.
Figure 16 is the sequential chart of circuit operation that shows the semiconductor storage of Figure 15.
Embodiment
With reference to accompanying drawing, preferred forms of the present invention is described.
(first embodiment)
Fig. 1 is the block scheme of primary structure that shows the semiconductor storage of first embodiment of the invention.In Fig. 1, the 1st, memory array comprises: the storage unit that is made up of a transistor and capacitor, be connected word line and the bit line on this storage unit and be connected the sensor amplifier on this bit line.The 2nd, illusory memory array; Comprise: the illusory storage unit that constitutes by a transistor and a capacitor (can be with by a transistor and the same circuit structure of said memory cells that capacitor constitutes, also can be and the different circuit structure of said memory cells), be connected word line and the dummy on this illusory storage unit and be connected the sensor amplifier on this dummy.The 3rd, the line decoder of selecting to be connected the word line on storage unit and the illusory storage unit and it being activated.The 4th, pre-charge circuit carries out precharge to the data line that is used for carrying out to storage unit 1 data access to DL < m:0 >/XDL < m:0 >.The 5th, pre-charge circuit carries out precharge to the dummy data line that illusory storage unit 2 is carried out data access to DDL/XDDL to being used for.The 6th, comprise the write buffer when data are write data line to DL < m:0 >/XDL < m:0>and the data line that amplifies when data are read with the circuit block (data line is with sensor amplifier/write buffer) of sensor amplifier.The 7th, data line when the current potential of dummy data line DDL surpasses a certain threshold value, just generates the signal that activates with sensor amplifier 61 in order to data line with sensor amplifier control signal formation logic circuit.The 8th, in order to the control circuit of control store action.
Fig. 2 shows the particular circuit configurations of memory array 1, illusory memory array 2 and line decoder 3 among Fig. 1.Here; Being connected storage unit on the bit line of memory array 1, being connected the number of the illusory storage unit on the dummy of illusory memory array 2, is by the capacity ratio of the stray capacitance of cell capacitance and bit line or dummy, the sensitivity of sensor amplifier and the number that the desired speed of storer determines.
Fig. 3 shows the particular circuit configurations of data line with sensor amplifier/write buffer 6.In Fig. 3, the 61st, data line is used sensor amplifier, and the 62nd, write buffer.
Fig. 4 shows data with sensor amplifier control signal formation logic circuit 7.In Fig. 4, the 71st, NOR circuit, the 72nd, the illusory write buffer of using.
Utilize the sequential chart of Fig. 5, the working condition according to the duplicate circuit of the illusory storage unit of the semiconductor storage of above-mentioned formation is described.At first,, in control circuit 8, generate read operation reference signal REA, send the INADD signal to line decoder 3, select word line WL0 to be activated by this decoded signal when storer being read when requiring.So, data just transfer to bit line BL from storage unit MC.Simultaneously, data transfer to dummy DBL from illusory storage unit DMC.The current potential of 1/2 dummy DBL that is precharged to supply voltage VDD (perhaps high level) thus is bigger than so towards the cell capacitance of the stray capacitance of low level direction rising dummy BL and illusory storage unit DMC.Simultaneously, also generate peripheral circuit read operation reference signal RE.
Next; At electric charge in order to pass on from storage unit MC and illusory storage unit DMC; Postponed after the time of defined, become high level and be activated being connected sensor amplifier SA0～SAn and DSA0 on bit line BL/XBL and the dummy DBL/XDBL, signal SEN that DSA1 activates.So, bit line BL/XBL just is amplified to high level or low level respectively.Simultaneously, dummy DBL is amplified to low level.In addition, because sensor amplifier SA0～SAn and DSA0, DSA1 have eliminated the sensing operation deviation constantly of equalization, bit line and the dummy of art pattern CAD, so can use the sensor amplifier of same circuit.Sensor amplifier SA0～SAn and DSA0, DSA1 can use the different sensor amplifier of circuit structure, and this need not to put aside.
Being used for row switching signal CS0 that data with bit line BL/XBL and dummy DBL/XDBL transfer to the data line DL/XDL that is precharged to supply voltage VDD, dummy data line DDL/XDDL becomes high level and is activated; Therefore; Desirable data from bit line BL/XBL have transferred to data line DL/XDL; The low-level data of dummy DBL has transferred to dummy data line DDL; The low-level data that has amplified by sensor amplifier DSA0, at the appointed time after, make the dummy data line DDL become the current potential of 1/2VDD.Because dummy data line DDL is connected in the input of data with " non-or " circuit 71 of sensor amplifier control signal formation logic circuit 7; Be connected the transistorized conduction and cut-off level of CMOS on this input signal and be 1/2VDD (in other words; The transistorized output logic upset of CMOS); And " non-or " another input of circuit 71 becomes the energizing signal of the high level signal of peripheral circuit read operation reference signal RE.So data are with the output signal DACNT displacement high level of sensor amplifier control signal formation logic circuit 7, duplicate circuit EO.
Next, because signal DACNT becomes high level, so data line is activated with sensor amplifier 61, the data of data line DL/XDL are exaggerated, and the result is to become high level and low level respectively.The data of the data line DL that is exaggerated are transferred to output D O through buffer circuit, carry out read operation.
At last, read operation reference signal REA and peripheral circuit read operation reference signal RE during certain after, become low level, thereby become the stand-by state that the internal circuit of storer is got ready for next operation.
As stated, pass on the potential change brought at electric charge and surpass under the situation of threshold value, desired procedure can not carry out the second time; And; In order to the startup of sensor amplifier that the data of the changeless bit line of load capacity are amplified constantly, for example use transistor delay circuit such regulation time delay, use sensor amplifier by the electric current transfer of data; After the certain hour, be bound to obtain desirable current potential like this.Under the situation that load capacity alters a great deal owing to memory span; Through using, then under the situation that for example memory span diminishes, that is to say by the output signal that is the duplicate circuit that constitutes of the dummy of having duplicated storage unit, bit line, sensor amplifier, row switch and data line, sensor amplifier, row switch, dummy data line and " non-or " such simple level sensitive circuit of circuit basically; Data line shortens; Under the situation that circuit load lightens, the time that the dummy data line reaches the current potential of 1/2VDD shortens, therefore; Data line accelerates with the startup of sensor amplifier; So output data that is to say at high speed, can realize the high speed of access.For example, under the big situation of memory span change, that is to say; The data line load becomes under the situation about weighing; For data line is amplified, official hour is elongated, so by the moment generative circuit that has used the delay circuit that receives process deviation, external condition influence easily; Just can realize stable and the startup of data line sensor amplifier at a high speed, be effective means.
In addition, in Fig. 4, used " non-or " circuit 71, but so long as the circuit structure that the transistorized conduction and cut-off function of CMOS etc. lean on simple circuit operation just can realize can use.This is a matter of course.And, different therewith, append again on the dummy data line and have and the structure of data line with the same load transistor of sensor amplifier 61, be very important to moment optimization.
Through letting storage unit and illusory storage unit be made up of a transistor and a capacitor, the high speed the when data of being accumulated are dynamic data is exactly effectively.But,, for example can constitute etc. by two transistors and two capacitors so long as accumulation has the structure of dynamic data to get final product in storage unit.
Through making shared same the word line of the word line that is connected storage unit and illusory storage unit, then need not to reconstitute the dummy word line that is used for duplicate circuit.So; Circuit area is reduced, simultaneously, because be same word line; So can activate by the grid with the access transistor of storage unit and illusory storage unit in the identical moment, thereby the moment that makes data transferred to bit line and dummy is a synchronization.That is to say, become the moment of the best as the operation of duplicate circuit constantly.Needed the refreshing of capacitor unit described, because be connected on the same word line, so, when storage unit is refreshed, also can illusory storage unit be refreshed.The result is; Because illusory storage unit need not be merely its special refresh operation; So only have illusory storage unit not need special refreshing, so that to be connected shared same the word line of the word line of storage unit and illusory storage unit be effective means.In addition, can also be that storage unit is connected the structure on the different word lines with illusory storage unit, this is a matter of course.
Bit line and dummy, data line and dummy data line laterally arrange respectively, so compare with dummy, data line and the vertically arranged situation of dummy data line with bit line, the load of dummy data line and the load of data line are equated.So, generating the amplification moment optimization that can make data line constantly by the duplicate circuit that comprises the dummy data line, therefore laterally arrange respectively bit line and dummy, data line and dummy data line are effective.In addition; In this instructions, mentioned the relation of bit line and data line, but so long as become the duplicate circuit structure behind the static data; Even the data line that is connected with bit line through switch, the duplicate circuit structure of the data line that is connected with this data line through switch also is fine.
As shown in Figure 1; Adjacent at illusory memory array 2 and line decoder 3 and under the situation of establishing,, then compare in this place in addition with illusory storage unit through comprising the delay circuit that data are regulated with the output time of the output signal DACNT of sensor amplifier control signal formation logic circuit 7; For example; Illusory storage unit is compared in the situation of leaving line decoder 3 place farthest, and circuit operation becomes the fastest action, so can make the moment till the output the fastest.Therefore, very effective to the high speed of storer.And, the countermeasure that prevents misoperation as output time when too early is the most effective to the delay circuit that constantly carries out fine adjustment on the layout.In addition, because need not to change mask etc., utilizing these delay circuits such as fuse, nonvolatile memory just can regulate, so consider on the one hand from this, also is effectively means.
Through letting the neighboring capacitors of illusory storage unit be connected together mutually, the quantity of electric charge that then reads on the bit line just increases.Therefore, can realize stable sense amplifier operation.Therefore, the action as duplicate circuit guarantees it is effectively.In addition, certain, so long as the capacitor of the illusory storage unit structure bigger than the capacitor of storage unit gets final product.Under the situation that the electric pole short circuit that utilizes capacitor is realized, also can constitute new capacitor.
As shown in Figure 1, through arranging quantity identical memory array 1 and illusory memory array 2, then can start duplicate circuit, so be the effective means that generates the best time from the place of the position that meets each array physically with word line of having selected.And through letting memory array 1 and illusory memory array 2 common word line, then illusory storage unit and memory cell data are just read from selected word line, thereby can generate the best moment.Besides; If only being become, it arranges the structure of illusory memory array 2 at a for example place; Just can eliminate optimized obstacle constantly, can also eliminate the unbalanced caused process deviation of pattern owing to storage unit, and; The place that does not have illusory memory array has also just been eliminated the additional quantity of area by wasted spaceization.
Illusory storage unit is made up of a transistor; Transistorized source node is connected on the power supply; So, just need not to consider the defect problem of the capacitor in the illusory storage unit, and; Need not write needed data when reading, so be effective means to illusory storage unit yet.In addition, be to constitute illusory storage unit here by a transistor, also be fine but constitute illusory storage unit by plural transistor, need not to put aside.
As shown in Figure 6, output one side of logical circuit 7 comprises latch cicuit 73, therefore; Even the row switch that is connected on the illusory sensor amplifier breaks off; Between high period, peripheral circuit read operation reference signal RE also can be with output data latch, so be effective means between high period.
Next, utilize Fig. 7 the structure that plural sensor amplifier is connected on the dummy data line to be described to utilizing switch.As shown in Figure 7, be connected two sensor amplifier DSA0 and DSA1 on the dummy data line DDL/XDDL, be the structure that couples together by the N channel transistor 20,21,22,23 of control signal DCS control respectively via grid.Therefore, compare the speed sense data that the dummy data line DDL/XDDL of illusory storage unit can be enough 2 times with the data line DL/XDLX of storage unit.The result is; When being under 1: 2 the situation with the connection of " non-or " circuit 71 of sensor amplifier control signal formation logic circuit 7/at data line by the necessary potential difference with sensor amplifier 61 amplification data line DL/XDL necessary potential differences and data; Can make the data line of duplicate circuit of equal value with the moment of the amplification usefulness of sensor amplifier 61, so be effective means with the generation moment and the data line of sensor amplifier enabling signal.
Make the control signal various structure of row switch of control signal and the illusory sensor amplifier of its row switch that becomes sensor amplifier; So; The row switch of sensor amplifier just can irrespectively be controlled with the column decoding input, so be easy to a plurality of illusory sensor amplifiers are connected on the dummy data line.Even the number change of illusory sensor amplifier can not influence the driving moment, driving force of the row switch of sensor amplifier etc. yet, is effective therefore.
Then, utilize Fig. 8 to explain that the dummy data line is not a complement line, with the wiring of dummy data line arranged adjacent be the structure of power lead.As shown in Figure 8, dummy data line DDL is connected on sensor amplifier DSA0 and the DSA1 by the N channel transistor 20,21 that row switching signal CS0 and CS1 drive through grid.The N channel transistor 22,23 that is connected on a sensor amplifier DSA0 and the DSA1 makes grid become the VSS power supply, makes source electrode open (not connecting).Under this structure; Because a side of the complementation of dummy data line is the VSS power lead; Have screening effect so not only duplicate circuit is moved the read operation of needed dummy data line, become one, also be hopeful to make institute's consumed current to reduce through making the heavy dummy data line of load.In addition, explanation be the VSS power lead, certainly the VDD power lead also is fine.Under the situation of using vdd line, can take to be connected on the transistorized source node, make gate node and means such as the VSS power supply is connected.
In addition, after above variety of way combined, just can receive further good effect.This is a matter of course.
(variation of first embodiment)
Fig. 9 is the block scheme that shows the primary structure of the semiconductor storage in the variation of first embodiment of the present invention.Particularly, data different with in sensor amplifier control signal formation logic circuit 9 and first embodiment, particular circuit configurations is shown in Figure 10.In Figure 10, the 91st, " non-or " circuit bank, the 92nd, the illusory write buffer group of using, the 93rd, OR circuit is with the logic of many dummy data line DDL < 0 >～DDL < n>with as the control signal DACNT of data line with sensor amplifier 61.
According to this variation; Logic through getting many dummy data lines with; Even then illusory storage unit has one bad phenomenon to occur; Also can the data from remaining dummy data line be transferred to data with sensor amplifier control signal formation logic circuit 9, so be the effective means that can realize the action of desirable duplicate circuit.Generally, can the trade off relation of additional quantity of the incidence of considering defective on the technology and circuit area decides the quantity of this dummy data line.And the data of the dummy data line more than two are identical logical values, and this is a matter of course.
In addition, after this embodiment and first embodiment combined, just can receive further good effect.This is a matter of course.
(second embodiment)
Figure 11 is the block scheme that shows the primary structure of the semiconductor storage in second embodiment of the present invention.In Figure 11,10,11 is respectively memory array and the illusory memory array that comprises redundant word line RWL0.The 12nd, comprise when memory array 10 and illusory memory array 11 have had defective, can switch to the line decoder of the redundant decoding scheme of redundant word line.
In pressing the semiconductor storage of above-mentioned formation; When the storage unit on the WL0 that is connected memory array 10 has had defective; For example specify the address of the word line that utilizes redundancies such as fusing function; If defective word line WL0 has just in time been hit in access, then switch to the such control of the illusory redundant word line RWL0 of access by redundant decoding scheme, data are transferred to bit line BL from redundant storage unit.So just, can save defective unit.
Equally, had under the situation of defective, then switched to the such control of the illusory redundant word line RWL0 of access, so also can save illusory storage unit 11 by redundant decoding scheme in the illusory storage unit of the WL0 that is connected illusory memory array 11.
So; Through the present existing redundant circuit of redundant storage unit and redundant word line that comprises is applied in the illusory memory array; Illusory exactly storage unit has had defective; Also can save it,, can also effectively utilize the wasted space in the illusory memory array by being provided with of redundant storage unit so not only can realize the stable of duplicate circuit.Therefore, be effective means.
In addition, after the variation of this embodiment and first embodiment and first embodiment combined, just can receive further good effect.This is a matter of course.
(the 3rd embodiment)
Next, the 3rd embodiment of the present invention is described.The primary structure of the semiconductor storage of this embodiment such as Fig. 1 with reference to the sequential chart of Figure 12, explain the data write operation to illusory memory array to shown in Figure 4.
At first,, in control circuit 8, generate write operation reference signal WEA, generate peripheral circuit write operation reference signal WE when storer being write when requiring.So, data input signal DI just is written into impact damper 6 and drives, and data are transferred to data line DL/XDL.Simultaneously, transfer to dummy data line DDL/XDDL by data with the write buffer 72 illusory input signal DDI of sensor amplifier control signal formation logic circuit 7.The INADD signal sends line decoder 3 to by write operation reference signal WEA, selects word line WL0 to be activated by decoded signal.Afterwards, read into bit line the data on BL/XBL and the dummy DBL/XDBL are amplified by sensor amplifier activation signal SEN from being connected storage unit and illusory storage unit on the selected word line WL0.Next, the row switching signal CS0 that drives the grid of the N channel transistor that data line and sensor amplifier, dummy data line and sensor amplifier are coupled together is activated, and the data on the data line DL/XDL are passed through the sensor amplifier write storage unit.Equally, the data of dummy data line DDL/XDDL also are written into illusory storage unit through sensor amplifier.
At last, write operation reference signal WEA and peripheral circuit write operation reference signal WE during certain after, become low level, thereby become the stand-by state that the internal circuit of storer is got ready for next operation.
As stated, make it have following function, promptly; When having come to write when requiring; With desirable data write storage unit, simultaneously, desirable data are write in the illusory storage unit; So, just can make from illusory storage unit to dummy, the data of sensor amplifier and dummy data line become desirable data value.Therefore be effective means.Because when storage unit writes, the initialization or the desirable data of carrying out illusory storage unit write, so be an effective means that the excessive action of circuit is eliminated.
The input signal DDI that is connected the write buffer 72 of dummy data line DDL/XDDL is connected on VDD power supply or the earthing potential; After doing like this, new input signal be not appended under the situation of storer, just can looking writing requirement; Fixed data is write in the illusory storage unit that is connected on the desirable address; Therefore, from the angle of the quantity of the pin that reduces storer, also be effective.
Can change the logical value of the input signal DDI that is connected the write buffer 72 on the dummy data line DDL/XDDL from the outside; And; Even change the logic level of input signal DDI, the logic level in the time of also can making data with the output signal DACNT activation of sensor amplifier control signal formation logic circuit 7 is constant.Though do not show; It is had for example by selecting circuit that a phase inverter is made two signal path; The function of switching with the potential level of input signal DDI; So can eliminate because unbalanced (for example, compare, low level read easily etc.) of the read operation of the illusory storage unit that process conditions, external condition etc. cause with high level; To the data value of for example reading easily, just can realize comprising the operating stably of the duplicate circuit of illusory storage unit through same.
Make it have all word lines, be connected sensor amplifier on all illusory storage unit, be connected the switch activated functional that sensor amplifier and dummy data line on all illusory storage unit couple together, duplicate circuit moves desirable data and is just write illusory storage unit in the lump.Therefore, for example in the vacant time of initial when ordering of storer, standby mode etc., can carry out effectively.Through being the mode initialization function with this function setting; In time beyond by the write operation in the lump of mode initialization the time; For example use write buffer to quit work to write the dummy data line; Then writing normally to storer when requiring, the write operation of the illusory storage unit that comprises the dummy data line just is being restricted, therefore receiving the effect that the consumption electric current is reduced.Because need not to carry out simultaneously with common action, so for example make frequency of operation slow fully, carry out write operation to illusory storage unit with certain tolerance limit, just can realize the news steady operation of duplicate circuit.
In addition, after this embodiment and said each embodiment combined, just can receive further good effect.This is a matter of course.
(variation of the 3rd embodiment)
Figure 13 is the block scheme of the primary structure of the semiconductor storage in the variation of the 3rd embodiment of the present invention.Below, explain data are write the data write operation in the illusory memory array 102 set in the memory array 101 of the semiconductor storage that constitutes by Figure 13.
Be used to be activated at the flag I NT of mode register 111 regulations to the data write operation of illusory memory cell array 102 from outside control signal CNT.After write buffer 110 is activated, just dummy data line input signal DDI is transferred to dummy data line DDL.In selecting circuit 112,,, the counting of refresh counter 113 is increased gradually so selected repetition high level and low level input signal DCLK under the some cycles because flag I NT is a high level.The address signal selected of operation that increases by this refresh count 113 is deciphered in line decoder 103, so what carry out is exactly the same when refreshing, all word lines are by the action of selecting in regular turn.The same with this word line action; Being connected the sensor amplifier of selecting on the word line also is activated; Though do not show; The switch that is connected on the selecteed sensor amplifier in the switch that the sensor amplifier and the dummy data line DDL that are connected on the illusory memory array 102 are coupled together also is activated, and so just can desirable data be write illusory memory array 102.This action proceeds to refresh counter 113 always and turns back to initial value, and all data that just can accomplish illusory memory array 102 write.
To the common requirement that refreshes, because flag INT is in unactivated state, so be to receive refresh command signal REF, the structure of refresh counter 113 work.
As stated; Utilize the memory circuitry of both having deposited; Need not resemble illusory memory array 102 is carried out the operation that lets instantaneous large-current flow the write operation in the lump, and can carry out the initialization of illusory memory array 102, simultaneously in the moment different with common operation; Can realize the refresh operation of memory array 101 and illusory memory array 102 simultaneously, so can realize all most suitable circuit in view of circuit operation, consumption electric current and circuit area.
Further, as an example, note that, with the use of the mode register 111 determines a mode setting Xie dummy write operation the memory array 102 is the situation can be achieved as long as the use of the refresh counter 113 is written to the dummy memory array 102 operation circuit structure, what kind of circuit structure can be.
(the 4th embodiment)
Figure 14 is the block scheme that shows the primary structure of the semiconductor storage in the variation of the 4th embodiment of the present invention.In Figure 14; The 13rd, output select circuit; Under this circuit structure; Can utilize mode select signal MODE, the output signal PDO during with test switches to from the test output of the data output DO of storage unit and data and exports with the output signal DDO of sensor amplifier control signal formation logic circuit 7 and with them.
Data read operation to by the illusory storage unit of the semiconductor storage of above-mentioned formation describes.
If signal DANCT becomes high level under duplicate circuit action shown in Figure 5, and is then as shown in Figure 4, data also become high level with another output signal DDO of sensor amplifier control signal formation logic circuit 7.If this moment, mode select signal MODE was a high level, then the data of high level have been exported to output signal PDO.
As mode select signal MODE when being low level, be exported to test output signal PDO from the output signal DO of storage unit.Like this, just, can whether switch with the output of the output DDO of sensor amplifier control signal formation logic circuit 7 data.
As stated, output to outside means, so can check to the defective of the duplicate circuit that comprises illusory storage unit through the data of utilizing pattern to come the test result of selection memory just to have illusory storage unit.The result is, not only can confirm the bad place of storage unit, can also confirm the bad place of illusory storage unit, can also implement the such storer relief measure of redundant relief.
In addition, explanation be, data with the output DDO of sensor amplifier control signal formation logic circuit 7 via the situation of selecting the output of signal former state, but so long as the circuit structure that obtains stable external output result according to the structure that latchs output DDO get final product.
Under data with the output DDO of sensor amplifier control signal formation logic circuit 7 are a plurality of situation; Through using part or all path of data output; The common lead-out terminal that then need not when confirming the data use test of illusory storage unit to increase especially lead-out terminal, just can read out the data from illusory storage unit.Therefore, from reducing number of terminals, the circuit area of storer, all be effective means.
Make data line and dummy data line have pre-charge circuit respectively, make the precharge potential of data line different with the precharge potential of dummy data line.An example is such; If the precharge potential of dummy data line is the VDD current potential; The startup that utilizes the sensor amplifier that transistorized conduction and cut-off characteristic paired data in next life line amplifies constantly, the precharge potential that makes data line is the 1/2VDD current potential, so; Compare with the VDD precharge potential, can the electric power that a lot of data line in the storer is consumed be suppressed at 1/2.The result is, is effective means to the low-power consumption of storer.
In addition, after this embodiment and above-mentioned each embodiment combined, just can receive further good effect.This is a matter of course.
Semiconductor storage involved in the present invention; Through determining theoretically constantly to the startup of the sensor amplifier that changes according to memory span and amplify from the heaviest data line of access time load; Have and to realize access at a high speed; And can realize the effect of various storer specifications at an easy rate, of great use to system LSI that the many storeies of the big and specification of quantity will be installed etc.
Claims (27)
1. semiconductor storage is characterized in that:
Comprise:
Storage unit,
Word line that is connected with said storage unit and bit line,
First sensor amplifier that is connected with said bit line,
Illusory storage unit,
The dummy that is connected with said illusory storage unit,
Second sensor amplifier that is connected with said dummy,
The data line that is connected with said first sensor amplifier,
First pre-charge circuit that is connected with said data line,
The third reading that is connected with said first pre-charge circuit go out amplifier,
The dummy data line that is connected with said second sensor amplifier,
Second pre-charge circuit that is connected with said dummy data line and
The logical circuit that is connected with said second pre-charge circuit,
The output signal of said logical circuit is to start the input signal that said third reading goes out amplifier.
2. semiconductor storage according to claim 1 is characterized in that:
Said logical circuit; With utilizing the current potential on the said dummy data line to detect the signal that the static data that in said second sensor amplifier that the dynamic data that reads into said dummy is amplified, generates has surpassed transistorized conduction and cut-off current potential and output, as starting the input signal that said third reading goes out amplifier.
3. semiconductor storage according to claim 1 is characterized in that:
Output one side at said logical circuit comprises latch cicuit.
4. semiconductor storage according to claim 1 is characterized in that:
Comprise: the device that the signal of the dummy data line of the input that becomes said logical circuit is latched according to the logical value of the output signal of said logical circuit.
5. semiconductor storage according to claim 1 is characterized in that:
Said storage unit is made up of a transistor and a capacitor, and said illusory storage unit is made up of a transistor and a capacitor.
6. semiconductor storage according to claim 1 is characterized in that:
The word line that is connected with said illusory storage unit is same wiring with the word line that is connected with said storage unit.
7. semiconductor storage according to claim 1 is characterized in that:
Said bit line and said dummy arrange that in parallel to each other said data line and said dummy data line are arranged in parallel to each other.
8. semiconductor storage according to claim 1 is characterized in that:
Said illusory storage unit is with to contain the line decoder of word driver adjacent and establish, and said semiconductor storage has the delay circuit that the output time of said logical circuit is regulated.
9. semiconductor storage according to claim 1 is characterized in that:
The neighboring capacitors of said illusory storage unit is connected together.
10. semiconductor storage according to claim 1 is characterized in that:
To each memory array that comprises said storage unit, said word line, said bit line and said first sensor amplifier, be provided with an illusory memory array that comprises said illusory storage unit, said dummy and said second sensor amplifier.
11. semiconductor storage according to claim 1 is characterized in that:
Said illusory storage unit is made up of a transistor, and this transistorized source node is connected on the power supply.
12. semiconductor storage according to claim 1 is characterized in that:
The structure that is had is that plural said second sensor amplifier is connected on the said dummy data line through switch.
13. semiconductor storage according to claim 12 is characterized in that:
The control signal of the switch that said data line and said first sensor amplifier are coupled together is different with the control signal of the switch that said dummy data line and said second sensor amplifier are coupled together.
14. semiconductor storage according to claim 1 is characterized in that:
Said dummy data line is not a complement line, with said dummy data line adjacent wirings be power lead.
15. semiconductor storage according to claim 1 is characterized in that:
Said logical circuit have the logic of getting the said dummy data line more than two and function.
16. semiconductor storage according to claim 15 is characterized in that:
The data of said dummy data line more than two are identical logical values.
17. semiconductor storage according to claim 1 is characterized in that:
Further comprise:
Redundant storage unit,
Be connected redundant word line on the said redundant storage unit,
Be connected bit line on the said redundant storage unit,
Redundant illusory storage unit and
Be connected the dummy on the illusory storage unit of said redundancy.
18. semiconductor storage according to claim 17 is characterized in that:
Said logical circuit; With utilizing current potential on the said dummy data line to detect the signal that the static data that generates in said second sensor amplifier that the dynamic data in the illusory storage unit of said redundancy amplifies has surpassed transistorized conduction and cut-off current potential and output, as starting the input signal that said third reading goes out amplifier.
19. semiconductor storage according to claim 1 is characterized in that:
Further comprise:
Be connected first write buffer on said first pre-charge circuit,
Be connected second write buffer on said second pre-charge circuit, and
When carrying out the write operation that writes to said storage unit, also to data be write the device of said illusory storage unit.
20. semiconductor storage according to claim 19 is characterized in that:
The input terminal of said second write buffer is connected on power supply or the earthing potential.
21. semiconductor storage according to claim 19 is characterized in that:
Said semiconductor storage has and can be from the outside logical value of the input data of said second write buffer be changed, and the constant function of the output logic of said logical circuit.
22. semiconductor storage according to claim 19 is characterized in that:
Further comprise: the write device in the lump that writes in the lump to all illusory storage unit.
23. semiconductor storage according to claim 19 is characterized in that:
Further comprise:
Refresh counter is controlled refreshing, and
Write device writes data and is connected the said illusory storage unit of utilizing on the said word line that said refresh counter selects.
24. semiconductor storage according to claim 1 is characterized in that:
Comprise that further the output with said logical circuit reads into outside device.
25. semiconductor storage according to claim 24 is characterized in that:
Has output to the output of the outside of said logical circuit/the do not export function of switching.
26. semiconductor storage according to claim 24 is characterized in that:
When from said logical circuit when export the outside, use part or all path of the data output of said storage unit.
27. semiconductor storage according to claim 1 is characterized in that:
The precharge potential of said data line is different with the precharge potential of said dummy data line.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007285136 | 2007-11-01 | ||
| JP2007285136 | 2007-11-01 | ||
| JP2007-285136 | 2007-11-01 | ||
| JP2007337073 | 2007-12-27 | ||
| JP2007337073A JP5127435B2 (en) | 2007-11-01 | 2007-12-27 | Semiconductor memory device |
| JP2007-337073 | 2007-12-27 |
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| CN101425329A CN101425329A (en) | 2009-05-06 |
| CN101425329B true CN101425329B (en) | 2012-11-21 |
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| CN2008101311642A Expired - Fee Related CN101425329B (en) | 2007-11-01 | 2008-07-30 | Semiconductor storage device |
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| JP5442562B2 (en) * | 2009-11-05 | 2014-03-12 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
| CN101944391A (en) * | 2010-09-21 | 2011-01-12 | 深圳市国微电子股份有限公司 | Test method of one time programmable read-only memory and one time programmable read-only memory |
| KR102548599B1 (en) * | 2016-06-17 | 2023-06-29 | 삼성전자주식회사 | Memory device including buffer-memory and memory module including the same |
| EP3449482A4 (en) * | 2016-06-27 | 2019-12-11 | Apple Inc. | Memory system having combined high density, low bandwidth and low density, high bandwidth memories |
| CN106504787B (en) * | 2016-10-24 | 2019-07-23 | 上海华力微电子有限公司 | A kind of embedded flash memory and its electric current compare reading circuit |
| JP2021039809A (en) * | 2019-09-04 | 2021-03-11 | キオクシア株式会社 | Semiconductor storage device |
| CN112750476A (en) * | 2019-10-29 | 2021-05-04 | 深圳市国微电子有限公司 | Configuration memory bit line control circuit and FPGA bit line control system |
| CN114582398B (en) * | 2020-11-30 | 2023-07-07 | 无锡华润上华科技有限公司 | Semiconductor memory |
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| US6359805B1 (en) * | 2000-10-17 | 2002-03-19 | Mitsubishi Denki Kabushiki Kaisha | Thin film magnetic memory device capable of easily controlling a data write current |
| CN1487526A (en) * | 2002-09-30 | 2004-04-07 | ������������ʽ���� | Non-volatile memory and semi-conductor integrated circuit device |
| JP2005064141A (en) * | 2003-08-08 | 2005-03-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and semiconductor memory device |
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| JPH0325792A (en) * | 1989-06-22 | 1991-02-04 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPH06176568A (en) * | 1992-12-07 | 1994-06-24 | Fujitsu Ltd | Semiconductor memory |
| JPH11203873A (en) * | 1998-01-16 | 1999-07-30 | Hitachi Ltd | Semiconductor integrated circuit and data processing system |
| JP2002074970A (en) * | 2000-08-31 | 2002-03-15 | Matsushita Electric Ind Co Ltd | Semiconductor memory |
| JP2002230980A (en) * | 2001-01-31 | 2002-08-16 | Mitsubishi Electric Corp | Semiconductor memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6359805B1 (en) * | 2000-10-17 | 2002-03-19 | Mitsubishi Denki Kabushiki Kaisha | Thin film magnetic memory device capable of easily controlling a data write current |
| CN1487526A (en) * | 2002-09-30 | 2004-04-07 | ������������ʽ���� | Non-volatile memory and semi-conductor integrated circuit device |
| JP2005064141A (en) * | 2003-08-08 | 2005-03-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and semiconductor memory device |
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| JP5127435B2 (en) | 2013-01-23 |
| CN101425329A (en) | 2009-05-06 |
| JP2009134840A (en) | 2009-06-18 |
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