CN101399266B - Modified capacitor and method for manufacturing same - Google Patents
Modified capacitor and method for manufacturing same Download PDFInfo
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- CN101399266B CN101399266B CN2007100466849A CN200710046684A CN101399266B CN 101399266 B CN101399266 B CN 101399266B CN 2007100466849 A CN2007100466849 A CN 2007100466849A CN 200710046684 A CN200710046684 A CN 200710046684A CN 101399266 B CN101399266 B CN 101399266B
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Abstract
The invention provides an improved capacitor and a manufacturing method thereof. The capacitor which adopts an MIM structure or a PIP structure in the prior art has the problems of large storage space, and the like, thereby not being capable of complying with the development demands of miniaturization of semiconductor devices. The capacitor is arranged in a semiconductor device with a pre-metal dielectric and a first metal layer which are manufactured, an electrode groove and a contact hole which are communicated are arranged in the pre-metal dielectric, the capacitor comprises upper and lower electrodes and an insulating dielectric layer which is clamped and arranged between the two electrodes, the lower electrode is made of polysilicon and is arranged in the electrode groove, the lower electrode is connected to a silicon substrate of the semiconductor device through a polysilicon plug which is arranged in the contact hole, and the upper electrode is arranged in the first metal layer. The manufacturing method of the capacitor firstly photoengraves and etches the contact hole and the electrode groove, then the polysilicon is deposited, then the chemical mechanical polishing is carried out to form the polysilicon plug and the lower electrode and finally, the insulating dielectric layer and the upper electrode are manufactured. The development demands of the miniaturization of the semiconductor devices can be complied by the capacitor and the manufacturing method.
Description
Technical field
The present invention relates to capacitor element, relate in particular to a kind of modified model electric capacity and manufacture method thereof.
Background technology
For complying with the demand of the portable development of electronic product, employed semiconductor device is also in the development that is sent to towards microminiaturization in the electronic product.In the process of semiconductor device miniature development, except the volume that constantly dwindles metal-oxide-semiconductor, some are integrated with the emphasis that also becomes semiconductor device miniature research that dwindles of electric capacity volume in the semiconductor device (for example cmos image sensor) of electric capacity.Employed electric capacity adopts insulator/metal dielectric layer/metal (Metal/dielectric/metal) structure usually in the existing semiconductor device, this structure is used the bottom electrode of the metal level of device inside as electric capacity usually, on this bottom electrode, deposit insulating medium layer and metal level then, then carry out insulating medium layer and the top electrode that photoetching and etching obtain this electric capacity according to the electric capacity figure, but electrically connect for ease of other devices and this electric capacity, need on this top electrode, make one deck again and be used for the metal level that other devices of confession are connected with this electric capacity, so will increase size of semiconductor device, may aggravate the manufacture difficulty of some devices in addition, hinder its development to microminiaturized direction.
For overcoming the variety of problems that electric capacity brought that adopts mim structure, industry has proposed the electric capacity of a kind of employing polysilicon/insulating medium layer/polysilicon (Poly/dielectric/Poly) structure then, the upper/lower electrode of this electric capacity is polysilicon, how the polysilicon of this bottom electrode forms in silicon gate in the lump at the manufacturing metal-oxide-semiconductor usually, on this bottom electrode, deposit insulating medium layer and polysilicon then, then carry out insulating medium layer and the polysilicon top electrode that photoetching and etching obtain this electric capacity according to the electric capacity figure, use the electric capacity of this kind structure can reduce the thickness of semiconductor device, but can be manufactured on the area that can influence other funtion parts of semiconductor device before the metal in the medium because of this kind electric capacity, for example in cmos image sensor, can influence the area of pel array.
Therefore, how to provide a kind of modified model electric capacity and manufacture method thereof, become the technical problem that industry needs to be resolved hurrily to produce the electric capacity that adapts to the semiconductor device miniature growth requirement.
Summary of the invention
The object of the present invention is to provide a kind of modified model electric capacity and manufacture method thereof, can comply with microminiaturized growth requirement by described electric capacity and manufacture method thereof.
The object of the present invention is achieved like this: a kind of modified model electric capacity, it is arranged in the semiconductor device of having made preceding medium of metal and the first metal layer, this electric capacity comprises upper/lower electrode and is folded in insulating medium layer between upper/lower electrode, wherein, this bottom electrode is a polysilicon, be provided with the electrode groove and the contact hole of connection before this metal in the medium, this bottom electrode is arranged in this electrode groove and by being arranged on the silicon substrate that polysilicon plug in this contact hole is connected to semiconductor device, this top electrode is arranged in this first metal layer.
In above-mentioned modified model electric capacity, the cross-sectional area of this electrode groove is greater than the maximum cross-section area of this contact hole.
In above-mentioned modified model electric capacity, make this bottom electrode and this polysilicon plug by low-pressure chemical vapor deposition process.
In above-mentioned modified model electric capacity, medium is a silica before this metal.
In above-mentioned modified model electric capacity, this insulating medium layer is silicon nitride or silica.
The present invention also provides a kind of above-mentioned modified model method for producing capacitor, and this electric capacity is manufactured on the semiconductor device of having made medium before the metal, and this method may further comprise the steps: (1) photoetching also etches the contact hole of polysilicon plug correspondence; (2) photoetching and etch the electrode groove of bottom electrode correspondence; (3) by chemical vapour deposition (CVD) deposit spathic silicon in this contact hole and electrode groove; (4) carry out chemico-mechanical polishing to form polysilicon plug and bottom electrode; (5) insulating medium layer of manufacturing electric capacity; (6) top electrode of manufacturing electric capacity.
In above-mentioned modified model method for producing capacitor, in step (3), by the low-pressure chemical vapor deposition process deposit spathic silicon.
In above-mentioned modified model method for producing capacitor, this step (5) may further comprise the steps: (50) are by chemical vapor deposition method deposition insulating medium layer; (51) carry out photoetching and etching to obtain the insulating medium layer of electric capacity.
In above-mentioned modified model method for producing capacitor, this step (6) may further comprise the steps: (60) are by chemical vapor deposition method deposition ground floor metal; (61) carry out photoetching and etching to obtain the top electrode of electric capacity.
In above-mentioned modified model method for producing capacitor, the step of making metal plug in the medium before between step (4) and step (5), also being included in metal.
Adopt MIM or PIP structure with electric capacity of the prior art and make electric capacity can't satisfy the semiconductor device miniature growth requirement to compare, modified model electric capacity of the present invention and manufacture method thereof adopt the bottom electrode/insulating medium layer/top electrode of electric capacity respectively the structure of polysilicon/insulating medium layer/metal, and the polysilicon of bottom electrode is connected to the substrate of semiconductor device by polysilicon plug, top electrode is arranged in the first metal layer, so can utilize the first metal layer of semiconductor device and need not to make extra connection metal level, this electric capacity is manufactured on top of media before the metal so can not influence the making of other funtion parts of semiconductor device in addition, therefore can obtain complying with the electric capacity of the demand of semiconductor device miniature development by the present invention.
Description of drawings
Modified model electric capacity of the present invention and manufacture method thereof are provided by following embodiment and accompanying drawing.
Fig. 1 is the cutaway view with semiconductor device of modified model electric capacity of the present invention;
Fig. 2 is the flow chart of modified model method for producing capacitor of the present invention.
Embodiment
Below improvement of the present invention type electric capacity and manufacture method thereof are described in further detail.
Referring to Fig. 1, modified model electric capacity 10 of the present invention, it is arranged in the semiconductor device 1 of having made preceding medium 11 of metal and the first metal layer 12, be provided with the electrode groove and the contact hole (not shown) of connection before the described metal in the medium 11, and the cross-sectional area of described electrode groove is greater than the maximum cross-section area of described contact hole.Described electric capacity 10 comprises upper/lower electrode 100,101 and is folded in the insulating medium layer 102 of 100,101 of upper/lower electrodes, described top electrode 100 is arranged in the described the first metal layer 12, described bottom electrode 101 is arranged in the described electrode groove and it is polysilicon, and described bottom electrode 101 is also by being arranged on the silicon substrate 13 that polysilicon plug 110 in the described contact hole is connected to semiconductor device 1.
In the present embodiment, described semiconductor device 1 is a cmos image sensor; Described bottom electrode 101 and described polysilicon plug 110 are made simultaneously by low-pressure chemical vapor deposition process; Medium 11 is a silica before the described metal; Described insulating medium layer 102 is silicon nitride or silica; Described the first metal layer 12 is an aluminium; Also have the metal plug 111 that links to each other with ground floor metal 12 in the medium 11 before the described metal, and be provided with the metal plug contact hole (not shown) that is used to be provided with described metal plug 111.
It should be noted that, electric capacity 10 its first metal layers 12 that directly utilize semiconductor device shown in Fig. 1 are as its top electrode 100, so need not to make in addition again for the connected connection metal level of other device, moreover, described electric capacity 10 is arranged on the top of the preceding medium 10 of metal, can not influence the arranging of other function element of semiconductor device 1, electric capacity of the present invention 10 like this can reduce electric capacity 10 shared volume in semiconductor device 1 to greatest extent, has complied with the demand of semiconductor device 1 microminiaturized development.
Referring to Fig. 2, in conjunction with referring to Fig. 1, electric capacity 10 described in the modified model method for producing capacitor of the present invention is manufactured on the semiconductor device 1 of having made the preceding medium 11 of metal, described method for producing capacitor at first carries out step S20, photoetching and etch the contact hole of polysilicon plug 110 correspondences on the medium 11 before metal.
Then continue step S21, photoetching also etches the electrode groove of bottom electrode 101 correspondences.
Then continue step S22, by chemical vapour deposition (CVD) deposit spathic silicon in described contact hole and electrode groove.In the present embodiment, by low-pressure chemical vapor deposition (LPCVD) process deposits polysilicon.
Then continue step S23, carry out chemico-mechanical polishing to form polysilicon plug 110 and bottom electrode 101.
Then continue step S24, before metal, make metal plug 110 in the medium 11, its detailed process is: at first photoetching and etch the metal plug contact hole, then by chemical vapor deposition method deposition plug metal, carry out chemico-mechanical polishing at last to form metal plug 111.In the present embodiment, described plug metal is a tungsten.
Then continue step S25, make the insulating medium layer 102 of electric capacity 10, its detailed process is: at first by chemical vapor deposition method deposition insulating medium layer 102; Photoetching and etch the insulating medium layer 102 of electric capacity 10 then.
Then continue step S26, make the top electrode 100 of electric capacity 10, its detailed process is: at first by chemical vapor deposition method deposition ground floor metal 12; Photoetching and etch the top electrode 100 of electric capacity 10 then.
It should be noted that the sequencing of above-mentioned steps S20 and S21 can exchange.
In sum, modified model electric capacity of the present invention and manufacture method thereof adopt the bottom electrode/insulating medium layer/top electrode of electric capacity respectively the structure of polysilicon/insulating medium layer/metal, and the polysilicon of bottom electrode is connected to the substrate of semiconductor device by polysilicon plug, top electrode is arranged on the first metal layer, so can utilize the first metal layer of semiconductor device and need not to make extra connection metal level, described in addition electric capacity is manufactured on top of media before the metal so can not influence the making of other funtion parts of semiconductor device, therefore can obtain complying with the electric capacity of the demand of semiconductor device miniature development by the present invention.
Claims (9)
1. modified model electric capacity, it is arranged in the semiconductor device of having made preceding medium of metal and the first metal layer, this electric capacity comprises upper/lower electrode and is folded in insulating medium layer between upper/lower electrode, wherein, this bottom electrode is a polysilicon, it is characterized in that, be provided with the electrode groove and the contact hole of connection before this metal in the medium, this bottom electrode is arranged in this electrode groove and by being arranged on the silicon substrate that polysilicon plug in this contact hole is connected to semiconductor device, this top electrode is arranged in this first metal layer.
2. modified model electric capacity as claimed in claim 1 is characterized in that the cross-sectional area of this electrode groove is greater than the maximum cross-section area of this contact hole.
3. modified model electric capacity as claimed in claim 1 is characterized in that, this bottom electrode and this polysilicon plug are made by low-pressure chemical vapor deposition process.
4. modified model electric capacity as claimed in claim 1 is characterized in that, medium is a silica before this metal.
5. modified model electric capacity as claimed in claim 1 is characterized in that, this insulating medium layer is silicon nitride or silica.
6. described modified model method for producing capacitor of claim 1, this electric capacity are manufactured on the semiconductor device of having made medium before the metal, it is characterized in that this method may further comprise the steps: (1) photoetching also etches the contact hole of polysilicon plug correspondence; (2) photoetching and etch the electrode groove of bottom electrode correspondence; (3) by chemical vapour deposition (CVD) deposit spathic silicon in this contact hole and electrode groove; (4) carry out chemico-mechanical polishing to form polysilicon plug and bottom electrode; (5) insulating medium layer of manufacturing electric capacity; (60) by chemical vapor deposition method deposition the first metal layer; (61) carry out photoetching and etching to obtain the top electrode of electric capacity.
7. modified model method for producing capacitor as claimed in claim 6 is characterized in that, in step (3), by the low-pressure chemical vapor deposition process deposit spathic silicon.
8. modified model method for producing capacitor as claimed in claim 6 is characterized in that, this step (5) may further comprise the steps: (50) are by chemical vapor deposition method deposition insulating medium layer; (51) carry out photoetching and etching to obtain the insulating medium layer of electric capacity.
9. modified model method for producing capacitor as claimed in claim 6 is characterized in that, the step of making metal plug in the medium also be included in metal between step (4) and step (5) before.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100466849A CN101399266B (en) | 2007-09-29 | 2007-09-29 | Modified capacitor and method for manufacturing same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100466849A CN101399266B (en) | 2007-09-29 | 2007-09-29 | Modified capacitor and method for manufacturing same |
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| Publication Number | Publication Date |
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| CN101399266A CN101399266A (en) | 2009-04-01 |
| CN101399266B true CN101399266B (en) | 2010-08-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2007100466849A Expired - Fee Related CN101399266B (en) | 2007-09-29 | 2007-09-29 | Modified capacitor and method for manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104867911B (en) * | 2014-02-26 | 2018-07-27 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6583460B1 (en) * | 2000-08-29 | 2003-06-24 | Micron Technology, Inc. | Method of forming a metal to polysilicon contact in oxygen environment |
| US7015532B2 (en) * | 1993-04-02 | 2006-03-21 | Micron Technology, Inc. | Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same |
| CN1988181A (en) * | 2005-12-21 | 2007-06-27 | 东部电子股份有限公司 | Capacitor in the semiconductor device and method of fabricating the same |
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- 2007-09-29 CN CN2007100466849A patent/CN101399266B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7015532B2 (en) * | 1993-04-02 | 2006-03-21 | Micron Technology, Inc. | Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same |
| US6583460B1 (en) * | 2000-08-29 | 2003-06-24 | Micron Technology, Inc. | Method of forming a metal to polysilicon contact in oxygen environment |
| CN1988181A (en) * | 2005-12-21 | 2007-06-27 | 东部电子股份有限公司 | Capacitor in the semiconductor device and method of fabricating the same |
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| CN101399266A (en) | 2009-04-01 |
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