CN101359596B - Slot filling method and manufacturing method for shallow slot isolation - Google Patents
Slot filling method and manufacturing method for shallow slot isolation Download PDFInfo
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- CN101359596B CN101359596B CN2007100445607A CN200710044560A CN101359596B CN 101359596 B CN101359596 B CN 101359596B CN 2007100445607 A CN2007100445607 A CN 2007100445607A CN 200710044560 A CN200710044560 A CN 200710044560A CN 101359596 B CN101359596 B CN 101359596B
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Abstract
Disclosed is a groove filling method, including the following steps: providing a semiconductor structure with a groove; performing a first stage chemical vapor deposition process so as to develop a first film layer on the surface of the semiconductor and the surface of the groove; wherein the thickness of the first film layer is smaller than the depth of the groove; processing oxygen plasma treatment to the first film layer; performing a second stage chemical vapor deposition process on the first film layer so as to develop a second film layer on the first film layer; the second film layer at least fills the groove full; and processing oxygen plasma treatment to the second film layer. The invention further provides a shallow groove isolation fabrication method. The invention produces no or few SRO particles during the filling process.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of fill method of groove and shallow trench isolation from manufacture method.
Background technology
Along with the continuous development of semiconductor integrated circuit manufacturing technology, size of semiconductor device is more and more littler, and integrated level is more and more higher; The isolation technology of semiconductor device and device also by original silicon carrying out local oxide isolation (Local Oxidation of Silicon, LOCOS) develop into shallow trench isolation from (Shallow Trench Isolation, STI).Shallow trench isolation is from by forming groove on Semiconductor substrate, and the technology of filled media material forms in groove.
Publication number be the Chinese patent application file of CN1649122A disclose a kind of shallow trench isolation from manufacture method; As Fig. 1 to generalized section shown in Figure 5:
As shown in Figure 1, provide Semiconductor substrate 12, on described Semiconductor substrate 12, form pad oxide 12A; Then, on described pad oxide 12A, form first hard mask layer 14, on described first hard mask layer 14, form the second hard mask layer 14B;
On the described second hard mask layer 14B, form photoresist layer 16A, and the described photoresist layer 16A of patterning forms the opening 16B that the described second hard mask layer 14B is exposed in the bottom;
As shown in Figure 2, the second hard mask layer 14B, first hard mask layer 14 and the pad oxide 12A of the described opening 16B of etching bottom form opening 16C, and the surface of described Semiconductor substrate 12 is exposed in the bottom of described opening 16C;
As shown in Figure 3, remove described photoresist layer 16A, the Semiconductor substrate 12 of the described opening 16C of etching bottom forms groove 18 in described Semiconductor substrate 12;
As shown in Figure 4, form cushion oxide layer 20 on described groove 18 surfaces, fill oxide 22 in described groove 18, and remove the described second hard mask layer 14B by cmp and go up unnecessary oxide layer 22, and remove the described second hard mask layer 14B;
Remove described first hard mask layer 14 and pad oxide 12A, form fleet plough groove isolation structure as shown in Figure 5.
Described shallow trench isolation from manufacturing process in, after forming groove 18, usually use high density plasma CVD (HDPCVD) technology to fill groove 18 being carried out oxide, to improve filling capacity, reduce the generation in cavity to groove;
In the technology of existing a kind of HDPCVD filling groove, adopt O
2And SiH
4As reacting gas, be used to generate silica, etching gas adopts H
2, under the effect of high energy radio frequency source, O
2, SiH
4Be ionized the formation high-density plasma, and at the flute surfaces generation silicon oxide film that reacts, simultaneously, the H that is ionized
2Plasma carries out etching to described silicon oxide film, and etch rate is less than the speed of deposition;
After yet described HDPCVD method forms membranous layer of silicon oxide in groove 18 and on the Semiconductor substrate beyond the groove 18, silica (the Silicon RichOxide that is rich in silicon is usually arranged in this membranous layer of silicon oxide, SRO) particle, and the hardness of SRO wants the hardness of ratio silicon oxide to want big; To the judgement of grinding endpoint, can't judge comparatively accurately whether cmp is finished when the SRO particle can influence follow-up chemical mechanical milling tech, easily on the second hard mask layer 14B, form the residual defective of silica.
Summary of the invention
The invention provides a kind of fill method of groove and shallow trench isolation from manufacture method, the present invention can not produce or produce less SRO grain defect to trench fill the time.
The fill method of a kind of groove provided by the invention comprises:
Semiconductor structure with groove is provided;
Carry out the phase I chemical vapour deposition (CVD), form first rete at described semiconductor structure and flute surfaces, the thickness of described first rete is less than the degree of depth of described groove;
Described first rete is carried out oxygen gas plasma to be handled;
Carry out the second stage chemical vapour deposition (CVD), form second rete on described first rete, this second rete fills up described groove at least;
Described second rete is carried out oxygen gas plasma to be handled.
Optionally, described phase I chemical vapour deposition (CVD) comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, and wherein, high density plasma CVD and oxygen gas plasma are handled and hocketed.
Optionally, described phase I chemical vapour deposition (CVD) comprises the steps:
Carry out first step high density plasma CVD;
The execution oxygen gas plasma is handled;
Carry out the second step high density plasma CVD.
Optionally, described second stage chemical vapour deposition (CVD) comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, and wherein, high density plasma CVD and oxygen gas plasma are handled and hocketed.
Optionally, described second stage chemical vapour deposition (CVD) comprises the steps:
Carry out the 3rd step high density plasma CVD;
The execution oxygen gas plasma is handled;
Carry out the 4th step high density plasma CVD.
Optionally, the reacting gas in the described high density plasma CVD comprises O
2, SiH
4, etching gas is H
2
Optionally, the reacting gas in the described high density plasma CVD comprises O
2, SiH
4, etching gas is He or Ar.
Optionally, described phase I high density plasma CVD, oxygen gas plasma are handled, the second stage high density plasma CVD can original position carry out or carry out respectively in different process cavity.
The present invention also provide a kind of shallow trench isolation from manufacture method, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, has the pad oxide and the hard mask layer that form successively, in described Semiconductor substrate, be formed with groove, in described pad oxide and hard mask layer, have opening with the corresponding position of groove;
Carry out the phase I chemical vapour deposition (CVD), form first rete at described hard mask layer and flute surfaces, the thickness of described first rete is less than the degree of depth of described groove;
Described first rete is carried out oxygen gas plasma to be handled;
Carry out the second stage chemical vapour deposition (CVD), form second rete on described first rete, this second rete fills up described groove and opening at least;
Described second rete is carried out oxygen gas plasma to be handled;
Remove second rete and first film material on the described hard mask layer by flatening process;
Remove described hard mask layer and pad oxide.
Optionally, described phase I chemical vapour deposition (CVD) comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, and wherein, high density plasma CVD and oxygen gas plasma are handled and hocketed.
Optionally, described second stage chemical vapour deposition (CVD) comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, and wherein, high density plasma CVD and oxygen gas plasma are handled and hocketed.
Optionally, the reacting gas in the described high density plasma CVD comprises O
2, SiH
4, etching gas is H
2
Optionally, described O
2Flow be 30 to 40sccm, SiH
4Flow be 11 to 18sccm, H
2Flow be 300 to 800sccm.
Optionally, the reacting gas in the described high density plasma CVD comprises O
2, SiH
4, etching gas is He or Ar.
Optionally, the flow of oxygen of plasma of producing oxygen during described oxygen gas plasma is handled is 225 to 275sccm.
Optionally, described phase I high density plasma CVD, oxygen gas plasma are handled, the second stage high density plasma CVD can original position carry out or carry out respectively in different process cavity.
Compared with prior art, the present invention has the following advantages:
Undertaken by being divided into two stages the chemical vapor deposition method of trench fill, and after each stage finishes, carry out oxygen gas plasma and handle, silicon among oxygen gas plasma and the SRO reacts, generate silica, thereby can reduce or eliminate the SRO particle, make that the membrane uniformity and the compactness that are filled in the groove are better;
Because at deposition process depositional coating in groove not only, the surface deposition rete of semiconductor structure that also can be between groove, also can reduce or eliminate SRO particle in this lip-deep rete by oxygen gas plasma, when needs are removed described lip-deep film material by cmp, the detection of etching terminal in the time of can reducing or eliminate the bigger SRO particle of hardness to cmp, improved the controllability of chemical mechanical milling tech, help to reduce to grind residual defective, improve the stability of product;
In addition, if to shallow trench isolation from trench fill the time, be divided into two stages by the technology of will fill, and after each stage finishes, carry out oxygen gas plasma and handle, can reduce the SRO particle in the membranous layer of silicon oxide that is filled in the groove, improve the uniformity and the compactness of membranous layer of silicon oxide, thereby can improve insulating capacity, reduce leakage current; Also can reduce influence that the etching terminal of follow-up cmp is detected, help to reduce to grind residual.
Description of drawings
Fig. 1 to Fig. 5 be a kind of shallow trench isolation of the prior art from the generalized section of each step corresponding construction of manufacture method;
Fig. 6 is the flow chart of embodiment of the fill method of groove of the present invention;
Fig. 7 to Fig. 9 is the generalized section of each step corresponding construction of embodiment of the fill method of groove of the present invention;
Figure 10 to Figure 18 be shallow trench isolation of the present invention from the generalized section of each step corresponding construction of embodiment of manufacture method.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 6 is the flow chart of the embodiment of the fill method of groove of the present invention, and Fig. 7 to 9 figure is the generalized section of each step corresponding construction of embodiment of the fill method of groove of the present invention.
Step S100 provides the semiconductor structure with groove.
Generalized section as shown in Figure 7 provides semiconductor structure 100, has groove 102 in described semiconductor structure 100;
Described semiconductor structure 102 can be the Semiconductor substrate with groove, also can be the combination of Semiconductor substrate and other semiconductor device or interconnection structure; Described groove 102 can be one or more (groove only is shown among Fig. 7); Spacing between a plurality of grooves 102 can be identical or different.
Step S110 carries out the phase I chemical vapour deposition (CVD), forms first rete at described semiconductor structure and flute surfaces, and the thickness of described first rete is less than the degree of depth of described groove.
Among the embodiment therein, described chemical vapour deposition (CVD) is a high density plasma CVD.
In high density plasma CVD technology, reacting gas generates high-density plasma under the effect of high-energy incentive source, this high-density plasma directly touches the surface of semiconductor structure and groove under environment under low pressure, and the generation deposition reaction, form film;
Simultaneously, the plasma that etching gas produces bombard described film under bias effect, described film is carried out etching, and avoiding when the filling groove, the groove top open part is covered by film and blocks, and produces empty in groove; Wherein, speed of etching is less than the speed of deposition; The driving source that provocative reaction gas and etching gas produce plasma can be radio frequency source or microwave source.
Described semiconductor structure 100 is placed the processing chamber of the depositing device of high density plasma CVD, and in described processing chamber, feed reacting gas and the etching gas that is used for etching;
Open radio frequency source, under the effect of radio frequency source, reacting gas and etching gas are excited and ionization, form plasma, the plasma of reacting gas reacts and film former on the surface of described semiconductor structure 100 and groove 102, is deposited on the surface of described semiconductor structure 100 and groove 102;
Simultaneously, apply bias voltage between plasma and semiconductor structure 100, under the effect of described bias voltage, the plasma of etching gas quickens to the film movement that forms, and this film is bombarded etching; The thickness of this film is reduced;
By the flow of conditioned reaction gas and etching gas, the speed of feasible deposition is greater than the speed of etching; Along with the increase in reaction time, the thickness of film also constantly increases, first rete 104 in the generalized section of formation Fig. 8.
Among the embodiment therein, described reacting gas is O
2And SiH
4, described etching gas is H
2, wherein, O
2Flow be 30 to 40sccm, SiH
4Flow be 11 to 18sccm, H
2Flow be 300 to 800sccm, first rete 104 of formation is a silica, and the thickness of this first rete is less than the degree of depth of described groove 102.
In other embodiments, described etching gas also can be He or Ar.
Step S120 carries out oxygen gas plasma to described first rete and handles.
When forming first rete 104, can produce the SRO particle at first rete 104 of silica material; Handle by first rete 104 is carried out oxygen gas plasma, the silicon in oxygen gas plasma and the described SRO particle reacts, and generates silica, thereby can reduce or eliminate the SRO particle, makes first rete, 104 membrane uniformities of formation better.
Among the embodiment therein, the flow of the oxygen of the plasma that produces oxygen is 225 to 275sccm, and the driving source of the plasma that produces oxygen is a radio frequency source, and the power of this radio frequency source is 7000 to 9000W, and the time that oxygen gas plasma is handled is 5 to 15s; The time of described processing can be different according to the thickness of described first rete 104.
After the 104 execution oxygen gas plasmas processing of described first rete, execution in step S130.
Step S130 carries out the second stage chemical vapour deposition (CVD), forms second rete on described first rete, and this second rete fills up described groove at least.
Carry out chemical vapour deposition (CVD) once more, described groove 102 is filled, form second rete 106 on described first rete 104, as shown in Figure 9, described second rete 106 fills up described groove 102 at least.
Described second rete 106 can adopt technology and the reaction condition identical with forming first rete 104, adopts high density plasma CVD; Described reacting gas is O
2And SiH
4, described etching gas is H
2, wherein, O
2Flow be 30 to 40sccm, SiH
4Flow be 11 to 18sccm, H
2Flow be 300 to 800sccm.
In other embodiments, described etching gas can also be He or Ar.
Step S140 carries out oxygen gas plasma to described second rete and handles.
After forming described second rete 106, fill up described groove 102, described second rete 106 is carried out oxygen gas plasma handle the SRO particle that removal or minimizing produce when generating second rete 106 of silica material; Make that second rete 106 that forms is comparatively even, fine and close, membrane uniformity is better.
Can be identical to the technological parameter of the oxygen gas plasma of second rete 106 with technological parameter to the oxygen gas plasma of first rete 104.
Among the embodiment therein, the flow of the oxygen of the plasma that produces oxygen is 225 to 275sccm, and the driving source of the plasma that produces oxygen is a radio frequency source, and the power of this radio frequency source is 7000 to 9000W, and the time that oxygen gas plasma is handled is 5 to 15s.
In addition, described phase I high density plasma CVD, oxygen gas plasma are handled, the second stage high density plasma CVD can original position carry out, and also can carry out respectively in different process cavity.
Undertaken by being divided into two stages the high density plasma CVD technology that groove 102 is filled, and after each stage finishes, carry out oxygen gas plasma and handle, can reduce or eliminate the SRO particle in the rete of silica material of deposition, form the rete of even compact;
Owing to not only in described groove 102, understand the rete of cvd silicon oxide material in deposition process, also can be at the rete of the surface deposition silica material of the semiconductor structure 102 outside the described groove 102, can reduce or eliminate described SRO particle by oxygen gas plasma, in the time need the rete on described semiconductor structure 102 surfaces being removed by cmp, the detection of etching terminal in the time of can reducing or eliminate the bigger SRO particle of hardness to cmp, improve the controllability of chemical mechanical milling tech, help to reduce to grind residual defective, improve the stability of product.
In a further embodiment, the chemical vapour deposition (CVD) of described phase I is a high density plasma CVD, can comprise the steps:
At first, carry out first step high density plasma chemical vapor deposition, reacting gas is O
2, SiH
4, etching gas is H
2, form thin membranous layer of silicon oxide;
Then, described thin membranous layer of silicon oxide is carried out oxygen gas plasma handle, reduce or eliminate the SRO particle in this thin membranous layer of silicon oxide;
Then, carry out the second step high density plasma CVD, process conditions are identical with described first step high density plasma CVD, form first rete of silica material;
Also promptly, it is to carry out in two steps that the chemical vapour deposition (CVD) of phase I is torn open, and inserts oxygen gas plasma and handle between two steps, thereby can further reduce or eliminate the SRO particle in described first rete, improves the compactness and the uniformity of first rete.
In a further embodiment, the chemical vapour deposition (CVD) of described phase I comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, and wherein, high density plasma CVD and oxygen gas plasma hocket; Further to reduce or to eliminate SRO particle in first rete, improve the uniformity of rete.
In a further embodiment, the chemical vapour deposition (CVD) of described second stage is a high density plasma CVD, can comprise the steps:
At first, carry out the 3rd step high density plasma chemical vapor deposition, reacting gas is O
2, SiH
4, etching gas is H
2, form thin membranous layer of silicon oxide;
Then, described thin membranous layer of silicon oxide is carried out oxygen gas plasma handle, reduce or eliminate the SRO particle in this thin membranous layer of silicon oxide;
Then, carry out the 4th step high density plasma CVD, process conditions are identical with described the 3rd step high density plasma CVD, form second rete of silica material;
Also promptly, it is to carry out in two steps that the chemical vapour deposition (CVD) of second stage is torn open, and inserts oxygen gas plasma between two steps, thereby can further reduce or eliminate the SRO particle in described second rete, improves the compactness and the uniformity of second rete.
In a further embodiment, described second stage chemical vapour deposition (CVD) comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, wherein, high density plasma CVD and oxygen gas plasma are handled and are hocketed; Further to reduce or to eliminate SRO particle in second rete.
The present invention also provide a kind of shallow trench isolation from manufacture method, Figure 10 to Figure 18 be shallow trench isolation of the present invention from the generalized section of each step corresponding construction of manufacture method.
As shown in figure 10, provide Semiconductor substrate 200, form pad oxide 210 on described Semiconductor substrate 200, the method that forms described pad oxide 210 can be that high temperature furnace pipe oxidation, rapid thermal oxidation, original position steam produce a kind of in the oxidizing process; Described pad oxide 210 is as the sticking and layer between hard mask layer that forms in the subsequent technique and Semiconductor substrate 200 surfaces, be used to increase the caking property between hard mask layer and Semiconductor substrate 200 surfaces, and the stress between balance hard mask layer and described Semiconductor substrate 200 surfaces.
Form hard mask layer 220 on described pad oxide 210, hard mask layer described in the present embodiment 220 is a silicon nitride; The method that forms described hard mask layer 220 can be chemical vapour deposition (CVD); Described hard mask layer 220 is as the hard mask of etching groove in described Semiconductor substrate 200, and as the layer that stops of the cmp planarization of the dielectric material of in groove, filling.In other embodiments, described hard mask layer can be a multilayer.
As shown in figure 11, spin coating photoresist layer 230 on described hard mask layer 220, and form first opening 240 by exposure imaging technology, the surface of described hard mask layer 220 is exposed in the bottom of described first opening 240.
In other embodiments, before the described photoresist layer 230 of spin coating, can form the anti-reflecting layer (not shown) on described hard mask layer 220, described anti-reflecting layer can be an inorganic material, for example silicon oxynitride, or organic material; And then form photoresist layer 230 on described anti-reflecting layer, and exposure imaging forms first opening 240.
As shown in figure 12, the hard mask layer 220 and the pad oxide 210 of described first opening of etching 240 bottoms form second opening 250, and the surface of described Semiconductor substrate 200 is exposed in the bottom of described second opening 250; Described etching is the plasma dry etching, and the etching gas of this plasma dry etching can be CF
4
As shown in figure 13, the Semiconductor substrate 200 of described second opening of etching 250 bottoms forms groove 260 in described Semiconductor substrate 200; The method of the described groove 260 of etching is the plasma dry etching, the etching gas that described plasma dry etching is selected for use will make the sidewall of described groove 260 comparatively smooth, have less silicon crystal lattice defective, and make the corner, bottom of described groove 260 comparatively level and smooth.
The etching gas of described etching can be Cl
2Or HBr, or the mist of HBr and other gas, for example can be HBr and O
2And Cl
2Mist, or HBr and NF
3Mist with He.The degree of depth of the groove 160 that etching forms is by the time control of etching.
Etching forms the technology of described groove 260 and can carry out respectively in different etching apparatuss with the technology that etching forms described second opening 250, also can original position carry out in same etching apparatus.
If etching forms the technology of described groove 260 and carries out respectively in different etching apparatuss with the technology that etching forms described second opening 250, can before etching forms described groove 260, remove described photoresist layer 230, also can after the etching of finishing described groove 260, remove described photoresist layer 230 by the oxygen gas plasma ashing; If original position is carried out, after the etching of finishing described groove 260, remove described photoresist layer 230.
As shown in figure 14, clean the surface of described groove 260, generate layings 280 with thermal oxidation method on described groove 260 surfaces then with hydrofluoric acid solution.
Then, carry out the phase I chemical vapour deposition (CVD), form first membranous layer of silicon oxide 300 at described hard mask layer 220 and groove 260 surfaces, as shown in figure 15, the thickness of described first membranous layer of silicon oxide 300 is less than the degree of depth of described groove 260.
Among the embodiment therein, described chemical vapour deposition (CVD) is a high density plasma CVD; Described Semiconductor substrate 200 is placed the processing chamber of high density plasma CVD depositing device;
In described processing chamber, feed reacting gas that forms membranous layer of silicon oxide and the etching gas that is used for etching, open radio frequency source, under the effect of radio frequency source, reacting gas and etching gas are excited and ionization, form plasma, the plasma of reacting gas reacts and film former on the surface of hard mask layer 220 and groove 260, and is deposited on the surface of hard mask layer 220 and groove 260;
Simultaneously, under the effect of the bias voltage between plasma and the Semiconductor substrate 200, the etching gas plasma quickens to the film movement that forms, and this film is bombarded etching; The thickness of this film is reduced;
By the flow of conditioned reaction gas and etching gas, the speed of feasible deposition is greater than the speed of etching; Along with the increase in reaction time, the thickness of film also constantly increases, and forms first membranous layer of silicon oxide 300.
Among the embodiment therein, described reacting gas is O
2And SiH
4, described etching gas is H
2, wherein, O
2Flow be 30 to 40sccm, SiH
4Flow be 11 to 18sccm, H
2Flow be 300 to 800sccm, first membranous layer of silicon oxide, 300 thickness of formation are less than the degree of depth of described groove 260.
Then, described first membranous layer of silicon oxide 300 is carried out oxygen gas plasma to be handled, silicon in the SRO particle in the oxygen gas plasma and first membranous layer of silicon oxide 300 reacts, generate silica, reduce or eliminate the SRO particle, improve first membranous layer of silicon oxide, 300 uniformities and compactness, thereby can improve insulating capacity, reduce leakage current.
Among the embodiment therein, the flow of the oxygen of the plasma that produces oxygen is 225 to 275sccm, and the driving source of the plasma that produces oxygen is a radio frequency source, and the power of this radio frequency source is 7000 to 9000W, and the time that oxygen gas plasma is handled is 5 to 15s.
Then, carry out the second stage chemical vapour deposition (CVD), form second membranous layer of silicon oxide 302 on described first membranous layer of silicon oxide 300, as shown in figure 16, this second membranous layer of silicon oxide 302 fills up the described groove 260 and second opening 250 at least.
Described second membranous layer of silicon oxide 302 can adopt technology and the condition identical with forming first membranous layer of silicon oxide 300; That is, described reacting gas is O
2And SiH
4, described etching gas is H
2, wherein, O
2Flow be 30 to 40sccm, SiH
4Flow be 11 to 18sccm, H
2Flow be 300 to 800sccm.
Then, described second membranous layer of silicon oxide 302 is carried out oxygen gas plasma and handle the SRO particle that removal or minimizing produce when generating second membranous layer of silicon oxide 302; Make second membranous layer of silicon oxide 302 of formation comparatively even, fine and close, membrane uniformity is better; With the shallow trench isolation that improve to form from insulating capacity, reduce leakage current.
Can be identical to the technological parameter of the oxygen gas plasma of second membranous layer of silicon oxide 302 with technological parameter to the oxygen gas plasma of first membranous layer of silicon oxide 300.
Among the embodiment therein, the flow of the oxygen of the plasma that produces oxygen is 225 to 275sccm, and the driving source of the plasma that produces oxygen is a radio frequency source, and the power of this radio frequency source is 7000 to 9000W, and the time that oxygen gas plasma is handled is 5 to 15s.
In addition, described phase I high density plasma CVD, oxygen gas plasma processing, second stage high density plasma CVD can original position carry out or carry out respectively in different process cavity.
Undertaken by being divided into two stages the high density plasma CVD technology that groove 260 is filled, and after each stage finishes, carry out oxygen gas plasma and handle, can reduce or eliminate the SRO particle in first membranous layer of silicon oxide 300 and second membranous layer of silicon oxide 302, form the rete of even compact;
In addition, because at deposition process cvd silicon oxide in described groove 260 not only, also at the surface deposition of described hard mask layer 220 silica, handle the SRO particle in the silica also can reduce or eliminate on the hard mask layer 220 by oxygen gas plasma, need the silica on the described hard mask layer 220 removed by cmp, can reduce or eliminate of the influence of the bigger SRO particle of hardness to the etching terminal detection of chemical mechanical milling tech, improve the controllability of chemical mechanical milling tech, help to reduce to grind residual defective, improve the stability of product.
In a further embodiment, the chemical vapour deposition (CVD) of described phase I comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, and wherein high density plasma CVD and oxygen gas plasma hocket; Further to reduce or to eliminate SRO particle in first membranous layer of silicon oxide 300 that forms.
In a further embodiment, described second stage chemical vapour deposition (CVD) comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, wherein, high density plasma CVD and oxygen gas plasma are handled and are hocketed; Further to reduce or to eliminate SRO particle in second membranous layer of silicon oxide 302 that forms.
After forming described second membranous layer of silicon oxide 302, carry out chemical mechanical milling tech, remove the silica material on the described hard mask 220, and keep the silica material 303 in the described groove 260 and second opening 250, as shown in figure 17.
Remove described hard mask layer 220 and pad oxide 210; The method of removing described hard mask layer 220 is the wet etching of phosphoric acid solution; The method of removing described pad oxide 210 is the wet etching of hydrofluoric acid solution.Promptly form fleet plough groove isolation structure as shown in figure 18.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (14)
1. the fill method of a groove is characterized in that, comprising:
Semiconductor structure with groove is provided;
Carry out the phase I chemical vapour deposition (CVD), form first rete at described semiconductor structure and flute surfaces, the thickness of described first rete is less than the degree of depth of described groove; Described phase I chemical vapour deposition (CVD) comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, and wherein, high density plasma CVD and oxygen gas plasma are handled and hocketed;
Described first rete is carried out oxygen gas plasma to be handled;
Carry out the second stage chemical vapour deposition (CVD), form second rete on described first rete, this second rete fills up described groove at least;
Described second rete is carried out oxygen gas plasma to be handled.
2. the fill method of groove as claimed in claim 1 is characterized in that, described phase I chemical vapour deposition (CVD) comprises the steps:
Carry out first step high density plasma CVD;
The execution oxygen gas plasma is handled;
Carry out the second step high density plasma CVD.
3. the fill method of groove as claimed in claim 1, it is characterized in that: described second stage chemical vapour deposition (CVD) comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, wherein, high density plasma CVD and oxygen gas plasma are handled and are hocketed.
4. the fill method of groove as claimed in claim 1 is characterized in that, described second stage chemical vapour deposition (CVD) comprises the steps:
Carry out the 3rd step high density plasma CVD;
The execution oxygen gas plasma is handled;
Carry out the 4th step high density plasma CVD.
5. as the fill method of the described groove of the arbitrary claim of claim 1 to 4, it is characterized in that: the reacting gas in the described high density plasma CVD comprises O
2, SiH
4, etching gas is H
2
6. as the fill method of the described groove of the arbitrary claim of claim 1 to 4, it is characterized in that: the reacting gas in the described high density plasma CVD comprises O
2, SiH
4, etching gas is He or Ar.
7. as the fill method of the described groove of the arbitrary claim of claim 1 to 4, it is characterized in that: described phase I high density plasma CVD, oxygen gas plasma are handled, the second stage high density plasma CVD can original position carry out or carry out respectively in different process cavity.
A shallow trench isolation from manufacture method, it is characterized in that, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, has the pad oxide and the hard mask layer that form successively, in described Semiconductor substrate, be formed with groove, in described pad oxide and hard mask layer, have opening with the corresponding position of groove;
Carry out the phase I chemical vapour deposition (CVD), form first rete at described hard mask layer and flute surfaces, the thickness of described first rete is less than the degree of depth of described groove; Described phase I chemical vapour deposition (CVD) comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, and wherein, high density plasma CVD and oxygen gas plasma are handled and hocketed;
Described first rete is carried out oxygen gas plasma to be handled;
Carry out the second stage chemical vapour deposition (CVD), form second rete on described first rete, this second rete fills up described groove and opening at least;
Described second rete is carried out oxygen gas plasma to be handled;
Remove second rete and first film material on the described hard mask layer by flatening process;
Remove described hard mask layer and pad oxide.
9. shallow trench isolation as claimed in claim 8 from manufacture method, it is characterized in that: described second stage chemical vapour deposition (CVD) comprises multistep high density plasma CVD and at least one step oxygen gas plasma processing, wherein, high density plasma CVD and oxygen gas plasma are handled and are hocketed.
As claimed in claim 8 or 9 shallow trench isolation from manufacture method, it is characterized in that: the reacting gas in the described high density plasma CVD comprises O
2, SiH
4, etching gas is H
2
11. shallow trench isolation as claimed in claim 10 from manufacture method, it is characterized in that: described O
2Flow be 30 to 40sccm, SiH
4Flow be 11 to 18sccm, H
2Flow be 300 to 800sccm.
12. as claimed in claim 8 or 9 shallow trench isolation from manufacture method, it is characterized in that: the reacting gas in the described high density plasma CVD comprises O
2, SiH
4, etching gas is He or Ar.
13. as the described shallow trench isolation of the arbitrary claim of claim 8 to 9 from manufacture method, it is characterized in that: the flow of the oxygen of the plasma that produces oxygen during described oxygen gas plasma is handled is 225 to 275sccm.
14. as claimed in claim 8 or 9 shallow trench isolation from manufacture method, it is characterized in that: described phase I high density plasma CVD, oxygen gas plasma are handled, the second stage high density plasma CVD can original position carry out or carry out respectively in different process cavity.
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| CN101359596B true CN101359596B (en) | 2010-06-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102024741B (en) * | 2009-09-17 | 2013-03-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation structure |
| CN102446757A (en) * | 2011-10-12 | 2012-05-09 | 上海华力微电子有限公司 | Method for manufacturing aluminum liner of double-layer passivation protection layer |
| CN104555893B (en) * | 2013-10-17 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | The method that inductive material film is formed in deep trench |
| CN105097491B (en) | 2014-04-30 | 2018-09-21 | 无锡华润上华科技有限公司 | A kind of CMP process based on silicon oxynitride anti-reflective layer |
| US9978634B2 (en) * | 2015-02-26 | 2018-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating shallow trench isolation and semiconductor structure using the same |
| CN115537765A (en) * | 2022-09-27 | 2022-12-30 | 盛吉盛(宁波)半导体科技有限公司 | Plasma chemical vapor deposition device and small-size groove filling method |
| CN116110920A (en) * | 2023-02-20 | 2023-05-12 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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|---|---|---|---|---|
| US5872058A (en) * | 1997-06-17 | 1999-02-16 | Novellus Systems, Inc. | High aspect ratio gapfill process by using HDP |
| US6211040B1 (en) * | 1999-09-20 | 2001-04-03 | Chartered Semiconductor Manufacturing Ltd. | Two-step, low argon, HDP CVD oxide deposition process |
| CN1200455C (en) * | 2001-07-12 | 2005-05-04 | 旺宏电子股份有限公司 | Process for preparing shallow-channel isolating structure |
| CN1979797A (en) * | 2005-12-05 | 2007-06-13 | 中芯国际集成电路制造(上海)有限公司 | STI channel filling method |
-
2007
- 2007-07-31 CN CN2007100445607A patent/CN101359596B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5872058A (en) * | 1997-06-17 | 1999-02-16 | Novellus Systems, Inc. | High aspect ratio gapfill process by using HDP |
| US6211040B1 (en) * | 1999-09-20 | 2001-04-03 | Chartered Semiconductor Manufacturing Ltd. | Two-step, low argon, HDP CVD oxide deposition process |
| CN1200455C (en) * | 2001-07-12 | 2005-05-04 | 旺宏电子股份有限公司 | Process for preparing shallow-channel isolating structure |
| CN1979797A (en) * | 2005-12-05 | 2007-06-13 | 中芯国际集成电路制造(上海)有限公司 | STI channel filling method |
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