CN101341593B - 多晶片集成电路封装及形成其的方法 - Google Patents

多晶片集成电路封装及形成其的方法 Download PDF

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CN101341593B
CN101341593B CN 200680045001 CN200680045001A CN101341593B CN 101341593 B CN101341593 B CN 101341593B CN 200680045001 CN200680045001 CN 200680045001 CN 200680045001 A CN200680045001 A CN 200680045001A CN 101341593 B CN101341593 B CN 101341593B
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insulator
integrated
provided
vias
leadframes
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CN 200680045001
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CN101341593A (zh )
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罗伯特·F·华莱士
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桑迪士克股份有限公司
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Abstract

本发明揭示一种用于集成电路的多晶片封装。提供绝缘体层且在其内形成一个或一个以上通路。可在不具有通路的情况下提供所述绝缘体,且稍后形成通路。提供至少一个集成电路且将其电耦合到上覆于所述绝缘体层的一个表面上的第一引线框架的至少一个引线。提供至少一个第二集成电路且将其电耦合到上覆于所述绝缘体层的第二表面上的第二引线框架。通过将所述第一及第二引线框架的至少一个引线彼此耦合而在选定位置处穿过所述绝缘体进行所述两个引线框架与所述第一及第二集成电路之间的电连接。可通过焊接工艺将所述第一及第二引线框架的引线物理耦合到所述绝缘体中的通路内。还说明一种可抽换式存储卡封装。

Description

多晶片集成电路封装及形成其的方法

[0001] 相关_请交叉参考案

[0002] 本申请案涉及与本申请案同一日期提出申请且标题为“用于多晶片集成电路封装的方法(Methods for a Multiple Die Integrated Circuit Package) ” 的第 11/264, 556号(代理人案号为SAND-01109US0)共同待决美国专利申请案。

[0003] 技术领域

[0004] 本发明及所说明的各实施例大体来说涉及制作包含多于ー个集成电路装置的封装式半导体装置,且更特定来说涉及制作具有“多个”集成装置的封装以形成封装式系统、存储器或存储器卡存储装置。

[0005] 背景技术

[0006] 在电子技术中,将半导体装置提供在保护并提供与集成电路的外部连接的封装中。对装置的集成性及先进功能性的需求已致使在单个封装中提供多个集成电路,其有时称为芯片或晶片(dies)。可以各种方式及各种材料形成封装,包含用热硬化或热固化材料形成的模制封装,例如“圆顶封装体”或环氧封装、预形成的塑料或陶瓷或者金属主体及类似物。所使用的材料保护小且易碎的半导体集成电路或“晶片”免受物理及某程度的湿气损坏,且为用于将外部端子(通常为金属或其它导电触点)耦合到集成电路上的导电接合垫(其为集成电路的外部电连接)的导电引线或电线提供保护。

[0007] 经常,在半导体封装技术中使用引线框架,以提供机械支撑并在集成电路与封装式装置的外部电触点或引线之间进行电连接。引线框架由导电材料(经常为铜或合金,或例如合金42的铁镍合金,经常将其涂布以增加与例如金、钌、钯及类似物等材料的导电性及可软焊性)组成,且额外涂层或镍、铜或其它材料的合金可用于改善连接的可软焊性及可制造性。导电材料上的塑料涂层可用于形成引线框架。可将引线加以软焊或镀敷以在装配之前或在完成的封装的装配之后进行软焊。通常以集成带形式提供引线框架,且可将所述引线框架蚀刻或冲压成形,引线框架带是以带形式连接以便于装配及制造的若干引线框架,且然后在稍后的制造阶段将所述弓I线框架分离。

[0008]弓丨线框架通常提供多个弓I线(经常为手指状,但也使用其它形状),其从将成为所需的成品封装的外部边界的区域外部伸延到经布置以接纳集成电路的内部区域。在现有技术中,已知使用其中引线框架的ー个区域提供中心支撑的布置,所述区域称为“晶片垫”,其用于接纳矩形或正方形半导体晶片,且引线指状元件在所述晶片垫的ー个或ー个以上侧上延伸到接近于所述集成电路晶片的外部边缘的区域。将引线框架指状元件固定成远离所述晶片并穿过经囊封的封装的计划外部边界而延伸。在现有技术的其它布置中,所述引线指状元件可在晶片上方(芯片上引线或“L0C”型引线框架)或晶片下方(芯片下引线或“LUC”型引线框架)延伸,其中所述引线提供机械支撑以及电路径。

[0009] 涂层或胶带形式的绝缘体粘合剂可用于将晶片固定到引线,或通过将引线固定在一起并在装配过程期间维持其位置来使引线稳定。可使用晶片附着粘合剂将晶片粘合到晶片垫,所述粘合剂可以是导电或绝缘材料且可以是树脂或热硬化材料。

[0010] 不管使用何种类型的引线框架,有必要提供耦合机构以将集成电路电耦合到引线框架。通常使用接合线。通过线接合エ艺将这些微型线施加到半导体装置;通常在通过毛细管施加线时将其分配。线接合エ艺使用热及压力且有时使用其它能量(例如,超声波能量)以通过将线附着到集成电路接合垫来形成接合,且然后使所述接合线在集成电路上方且远离集成电路而延伸到引线框架的引线指状元件的端上方的区域,然后所述毛细管再次使用热及压力来形成所述接合线到所述引线框架的第二连接。另ー选择为,所述接合线可以在相反方向上形成,从而首先附着到所述引线框架指状元件并向上延伸到所述集成电路上方并附着到接合垫。经常加热经切割的线以在所述接合线的端上形成球,然后其用于到所述集成电路晶片的下一接合(“球”接合),所述接合线的附着到所述引线框架的不具有球的端可称为“跳点接合”。如果需要,多个接合线可从集成电路的不同垫延伸到引线框架的单个引线,举例来说,可以此方式进行集成电路的电源或接地连接。所述接合线可以是金或其它已知的导体材料,其具有充足的延展性及挠性以允许此类型的处置并可用于球接合及跳点接合步骤而不存在有害的中断。所述线接合エ艺可高度自动化,且通常在非常高的速率下执行。

[0011] 在装配过程中,在将集成电路晶片线接合到引线框架之后,可将所述引线框架及晶片放置在模制装备(举例来说,在转移模制机器中)中,其中分配液体或熔化模制化合物材料以将所述引线框架与集成电路囊封在一起,以如上所说明向所述晶片提供机械保护及某程度的湿气抵抗力。其它替代性方案包含使用注模、环氧及树脂(例如,“圆顶封装体”)材料且可使用用于集成电路囊封的其它已知材料。代替模制的是,可改为将引线框架与晶片组合件安装到陶瓷、金属或塑料主体中,然后可随后使用盖子及粘合剂或其它物品通过囊封剂来将所述主体密封。引线框架的引线的外端可自己形成封装式装置(例如,在DIP、四方扁平包装、SOP或其它引线式封装中)的外部触点,或可使用额外连通技术,例如球栅格阵列(“BGA”)或引脚栅格阵列(“PGA”)封装及类似物。引线框架可结合其它互连插入物技术来使用,例如印刷电路板、基于以膜为基础的材料的挠性电路、用于半导体制造的市售膜(例如,卡普顿(Kapton)、宇部兴产(Upilex)、迈拉(Mylar)及类似物),或可使用陶瓷衬底材料。为可在现有技术中使用复杂的衬底布置,经常将多个层插入物与将外部连接器耦合到集成电路的所形成金属层一起使用。举例来说,底表面上的端子可穿过衬底或插入物中的多个层及通路耦合到插入物的上表面上的引线框架或线接合平台端子。这些插入物或衬底通常为层压结构,其中绝缘体层形成于各个导电层上。一旦装配完成,那么可将这些层压物进行过模制以提供密封的封装式装置或可将所述组合件放置于被密封的主体中。

[0012] 随着不断需要在封装式装置中提高集成性,在所属技术中也已知提供MCM或多芯片模块,其中在封装式装置内提供多于ー个集成电路晶片。举例来说,可将存储器装置与控制器封装在一起以形成此种模块。处理器与存储器也可形成模块。另ー选择为,这些装置可以是相同装置以(举例来说)形成大的存储器集成电路(例如,商品DRAM或非易失性存储器装置),可将多个相同的晶片放置在一个封装中,其中将此类装置的共用端子与封装的外部触点并联地耦合在一起。

[0013] 为将多个集成电路在系统配置中耦合在一起,使用各种技术。可形成挠性电路,其具有提供在挠性衬底的一个或两个侧上的金属化图案,这些图案从而用作用于将两个集成电路连接在一起的互连层。可使用多个金属层及层间通路技术来形成层压物(例如FR-4 或BT树脂卡),这些层压插入物再次用作用于将集成电路连接在一起的微型电路板并提供用于外部连通的迹线(例如,端子)。

[0014] 当要将相同的装置耦合在一起以提高集成性(举例来说,在DRAM装置的情况下)时,可使用晶片堆叠。接合线可从引线框架的引线延伸到若干晶片,举例来说,DRAM封装的地址引线可接线到堆叠的若干DRAM集成电路。晶片的堆叠可包含晶片之间的间隔物以使线接合装备能够接近个别堆叠式集成晶片的晶片垫。

[0015] 当要将相同的装置耦合在一起以提高集成性(举例来说,在DRAM装置的情况下)时,可采用晶片堆叠。可使用各种方法,例如在“朝上”布置中提供多个晶片,且可形成线接合以使用接合线将每一晶片耦合到共用引线框架从而将其并联耦合。已知采用背对背关系将晶片放置在引线框架上,然而,为维持共用的接合垫覆盖区域,在使用背对背关系时,经常需要“镜像晶片”,以便将晶片的朝上的一个侧上的端子定位在与朝下的对应晶片上相同的位置及次序。对“镜像晶片”的需求大大增加制造的复杂性、库存控制及成本,并需要每ー封装式装置包含具有相同功能的两个不同晶片。另ー选择为,可以使用插入物或层压电路以实现两个相同功能晶片的背对背定位,此层压插入物也对成品装置増加成本及复杂性。

[0016] 近年来増加商业重要性的特定封装式装置类型为可抽换式非易失性存储卡,其允许在各种电子装置之间进行数据传送。此非易失性存储器或存储卡可用于各种格式,包含小型快闪(Compact FLASH)、安全数字或SD、迷你SD、存储器棒、USB驱动器、多媒体卡或MMC及其它格式。为提供強健、可靠且稳定的数据存储格式,在单个封装式装置中连同智能控制器一起提供非易失性EEPROM或快闪存储器装置。智能控制器提供数据错误校正及检测、测试、高速缓冲存储及冗余支持功能,以便即使非易失性存储器装置内的某些存储位置预期会出现故障且在产品的使用寿命期间的确出现故障,仍正确地存储及检索用户数据且用户或系统不知晓不再使用存储器阵列内的某些位置;智能控制器用冗余存储器位置来取代这些位置并维持可用位置的映射,其用于维持数据的适当存储及一致性。对于用户系统来说,装置看似大的存储器阵列,控制器及自动错误校正特征及冗余支持为用户提供透明自动存储器控制操作,此不影响装置的使用。这些可抽换式存储卡已得到使用并将继续用于其中存储数据的许多应用,尤其针对蜂窝式电话、数码相机、数字媒体存储(例如,用于音乐播放器、视频播放器、电子游戏、个人数字助理或PDA装置的MP3音乐及视频),针对病历存储、智能卡、信用卡及类似物。

[0017]图I描绘典型的可抽换式存储卡封装的外部表面。此卡可以是(举例来说)颁 发给本申请案的发明者华莱士(Wallace)的第6,410,355号美国专利中所说明的类型,所述专利以引用的方式并入本文中。在图Ia中,描绘卡(举例来说,安全数字或SD格式卡)的接触侧,其中导电端子101经布置以接触封装100内的集成电路。图Ib描绘封装100的相对侧,其不具有电触点,但通常携载具有用于用户的视觉检查及參考的信息、商标名称、媒体大小及类似物的标签。端子的数量及所使用连接的类型随格式而变化,举例来说,对于安全数字或SD,图Ia所示的端子为典型端子,且使用仅几个外部端子。对于经常用于数码相机的小型快闪或“CF”卡来说,端子的数量更大,且所述端子为定位在封装的侧的ー个端上的阴插座。相机或读卡器具有插槽,其用于使用插槽内的阳端子或引脚接纳CF封装的同一端,当将小型快闪卡插入所述插槽时,所述阳端子或引脚进入对应的阴插座,从而完成连接。可使用其它连接,举例来说,可将USB端ロ用作所述连接。

[0018] 用于可抽换式存储卡装置的现有技术封装通常包含以多层层压印刷电路板或“ PC板”形式的复杂插入物或衬底,其为控制器集成电路及存储器装置或装置提供物理支撑及装置间的连通。可以是BT树脂、FR4或玻璃纤维或类似物的板通常是层压结构,其并入有金属层,所述金属层经图案化以形成导体迹线、耦合各个层以进行电连接的通路及用于线接合以将板表面上的迹线耦合到集成电路晶片或其它组件、安装到所述板的封装式或裸晶片组件的平台。举例来说,可并排提供多个存储器装置或将所述多个存储器装置提供为堆叠,或可使用单个存储器装置,但在任何情况下如现有技术封装的存储卡是复杂的封装式装置,其中至少两个装置封装在其内并耦合在一起。图2以截面视图描绘典型的布置。在图2中,将现有技术的存储卡200图解说明为具有安装在层压衬底208的同一表面上的集成电路晶片204及205。接合线203将集成电路晶片的有源表面或正面上的接合垫连接到所述衬底的上表面上的导电区域或平台206。将两个此类接合线显示为通过在平台206上连接集成电路的两个晶片垫而将其电耦合,所述集成电路从而被电耦合并可以是(举例来说)存储器及控制器集成电路。使用晶片附着材料209来将晶片204、205固定到衬底208。在 形成接合线203并将其附着到集成电路晶片204及205以及衬底上的平台206的常规半导体封装装配过程之后,在可以是热硬化或室温模制化合物或其它囊封材料的囊封剂211中囊封所述接合线与集成电路晶片。所述封装可以外壳201 (其可以是塑料)完成,从而覆盖衬底与模制材料。在另一方法中,颁发给本发明的发明者华莱士(Wallace)的第6,639,309号美国专利(也以引用的方式并入本文中)描绘可抽换式存储卡,其通过线接合连接及过模制囊封而在多层PC板材料的相对表面上并入有存储器装置及控制器装置。

[0019] 封装半导体集成电路的其它方法可并入有耦合在一起的多个引线框架或多层引线框架。举例来说,颁发给卡斯托(Casto)的第5,147,815号美国专利(其以引用的方式并入本文中)描绘两个集成电路晶片及两个引线框架,其装配并提供在单个模制双列直插式塑料或“DIP”封装中。将集成电路晶片及其相应的引线框架布置为背对背关系且通过使用接合线来将每一晶片耦合到相应的引线框架,另ー选择为,在插入物的相对侧上将集成电路布置为面对面关系且在倒装芯片(Flip Chip)布置中将所述集成电路耦合到其相应的引线框架,将所述两个集成电路独立地耦合到布置在封装式装置的相对侧上的外部引线且所述两个集成电路并非彼此电通信。颁发给吉田(Yoshida)等人的第6,603,197号美国专利(也以引用的方式并入本文中)提供耦合到至少两个不同集成电路装置的多个引线框架,将所述两个不同集成电路装置耦合到所述引线框架的各引线以形成模块,其中某些共用引线(举例来说,电源引线)在封装的外部物理及电耦合在一起,使得两个集成电路装置可接收信号。同样,颁发给帕克(Park)等人的第6,316,825号美国专利(也以引用的方式并入本文中)提供堆叠封装以将两个相同的集成电路装置(例如,存储器装置)堆叠在具有两个在所述封装的外部物理耦合的引线框架的模制封装中,使得耦合到外部引线的每一信号物理及电耦合到以并联方式连接的两个相同存储器装置中的每ー者。

[0020] 所属技术中已知的其它布置提供耦合到多层引线框架的单个集成电路,举例来说,颁发给麦克沙恩(McShane)的第5,220,195号美国专利(也以引用的方式并入本文中)提供单个集成电路,其线接合到多层引线框架并包含封装内的多层引线框架的部分之间的物理连接及所形成的通孔通路,其中接合线延伸到所述通路中以物理接触定位在集成电路下面的引线框架层,从而使得能够在所述封装式装置内形成多个电压层。

[0021] 虽然存在用于多个集成电路的现有技术封装,但不断需要多晶片封装,其在維持封装的可靠性的同时提供降低的生产成本。

[0022] 因此,需要经改善的多集成电路封装及用于封装多个集成电路的方法,所述方法简单且可靠,允许各集成电路装置之间任意连接,不需要昂贵的插入物、印刷电路板或衬底,且制造成本低于现存封装及方法。

发明内容

[0023] 本发明的各优选实施例提供一种用于多半导体集成电路或晶片的封装,其电连接ー个或ー个以上集成电路,提供对所述集成电路的机械支撑,提供设施以在所述集成电路之间进行任意连接,且提供到封装式装置的外部连接的电连通。本发明的封装不需要现有技术中所使用的类型的插入物或衬底,且材料使用与半导体处理工业中已知的现存装备及自动化工厂机器兼容的常规线接合及引线框架技木;使得使用及构建本发明不需要重组或专门装备。

[0024] 在本发明的第一实施例中,提供第一引线框架且其经定位而上覆于简单的绝缘体层上。所述绝缘体层具有为在某些位置中形成的开ロ的通路且引线框架的某些引线上覆于所述通路。引线框架的其它引线可延伸到所述绝缘体的外部边界或延伸出所述绝缘体的边缘。引线框架的某些引线可以不延伸到外部连接器。提供第一集成电路晶片且其经定位而接近于引线框架的内部端,在某些实施例中,引线框架可具有提供在内部的开ロ且可将晶片放置在所述内部开口中。在其它实施例中,晶片可座落在引线框架的引线上方,或在引线框架的引线下方。在优选实施例中,将晶片线接合到引线框架以将集成电路的所述引线中的一者或一者以上电连接到所述引线框架的所述引线。在其它优选实施例中,可使用如所属技术中已知的倒装芯片技术将引线框架的引线连接到晶片。

[0025] 然后,第二引线框架经放置而上覆于绝缘体的第二(相対)表面上。第二引线框架的某些引线经定位而上覆于绝缘体的通孔通路上,以用于且对应于第一引线框架的某些引线。第二引线框架的其它引线可延伸到绝缘体层的外部以与完成的装置进行外部电连接,并可延伸出绝缘体的外部边界。第二集成电路晶片经放置而接近于第二引线框架的内部引线。第二引线框架可在邻近引线框架的引线的内部端的中心部分中具有用于接纳晶片的空间,或可使用芯片下引线或芯片上引线引线框架布置。进行从第二集成电路上的晶片垫端子到第二引线框架的所述引线中的至少ー者的电连接(例如,接合线连接或倒装芯片连接)。在典型的应用中,存在从集成电路延伸到引线框架的若干且有时许多接合线。另ー选择为,可在将任一晶片附着到其对应的引线框架之前将第一及第ニ引线框架彼此附着。

[0026] 有利地,穿过绝缘体中的通路来电耦合第一及第ニ引线框架的某些引线。本发明的此方面使得通过穿过所述绝缘体进行所述两个引线框架之间的电连接的设施来将所述第一与第二集成电路晶片电耦合在任意位置中成为可能。在第一优选实施例中,通过使第一及第ニ引线的引线框架引线物理变形到绝缘体中的通路内的空间中,且然后在通路内的两个引线之间进行物理接触,便可实现连接。在优选实施例中,从而在两个引线框架之间进行导电焊接。举例来说,可使用通过热施加的能量、电能量、超声波能量、激光能量及类似物进行焊接。在其它优选实施例中,可通过提供定位在通路内的导电材料(例如,用作电连接的导电膏,且所述连接可使用热或电能量来完成)来在两个引线框架之间进行电连接。

[0027] 在其它优选实施例中,绝缘体可由各向异性导电材料形成,所述材料最初在所有方向上用作绝缘体,但当在一区域中施加压カ或热能量或两者时,所述材料在垂直方向上变为选择性导电,同时在平面方向上仍然为绝缘体。一般来说,通路是其中在邻近绝缘体的顶表面的导体与邻近绝缘体的底表面的导体之间实现电连通的区域。

[0028] 集成电路晶片可经定位而上覆于绝缘体的相对表面上,使得所述集成电路晶片可以是背对背关系。不同于现有技术的背对背布置,当使用本发明时不需要镜像晶片,因为本发明提供的穿过绝缘体形成电连接的方法允许两个装置的端子的任意连接。至于现有技术封装中的某些封装,不需要对准或反射两个集成电路晶片的端子。

[0029] 此外,在某些实施例中,对于DRAM、EEPR0M、快闪或其它动态或非易失性存储器装置来说,集成电路晶片可以是相同的,其中可通过将多个相同的集成电路晶片耦合在一起而创建较大的封装式装置。在其它优选实施例中,晶片可具有不同的功能(例如存储器控制器与存储器装置、模拟电路与数字装置、感测器与控制器装置及类似物)以在完成的封装式装置中提供集成功能。

[0030] 在替代性优选实施例中,本发明可提供:具有形成于所选定位置中的通路的绝缘 体、上覆于所述绝缘体层的ー个表面上的第一引线框架、上覆于相对的绝缘体层上的第二引线框架、使用已知的倒装芯片技术耦合到所述第一引线框架的第一集成电路,其中集成电路接合垫经定位而在物理上接近于所需的引线且形成焊料球或焊料垫,然后使用能量来回流所述焊料球或焊料垫以在晶片垫与引线的内部之间形成机械及电连接;如以前完成的装置具有穿过绝缘体中的通路在所述第一与第二集成电路之间进行的电连接一祥,可使用倒装芯片技术同样地将第二集成电路耦合到所述第二引线框架。因为第一及第ニ晶片两者在此优选实施例中使用倒装芯片技术耦合到所述引线框架,因此可以面对面关系来布置所述集成电路装置。

[0031] 涵盖于本发明及随附权利要求书内的替代性实施例包含将倒装芯片连接与线接合连接组合以便(举例来说)可使用倒装芯片技术将ー个晶片耦合到第一引线框架,且可使用线接合将第二晶片耦合到第二引线框架。

[0032] 在另ー优选实施例中,使用本发明的封装设备及方法形成可抽换式存储卡;提供具有形成于所选定位置中的通路的绝缘体层,第一引线框架经定位而上覆于所述绝缘体上且具有上覆于所述绝缘体中的通路上的某些引线,作为非易失性存储器装置的第一集成电路经定位而接近于所述第一引线框架且在所述非易失性集成电路与所述引线框架之间进行至少ー个电连接,接近于第二引线框架提供第二集成电路,其经定位而上覆于所述绝缘体的相对表面上并具有某些引线,所述引线上覆于所述绝缘体中的通路上,所述第二集成电路是用于操作所述非易失性存储器装置的控制器电路,所述第二集成电路电连接到所述第二引线框架。

[0033] 通过使用本发明的方法穿过所述绝缘体中的通路在所述第一与第二引线框架之间形成电连接来在所述存储器控制器电路与所述非易失性存储器之间进行电连接。可通过过模制或囊封所述绝缘体、第一及第ニ集成电路及所述第一及第ニ引线框架的部分来完成所述存储卡,所述第一及第ニ引线框架的剰余外部部分用于形成完成的存储卡的外部连接。

[0034] 有利地,用于本发明的优选实施例的绝缘体可包括各种已知材料。因为在绝缘体内或绝缘体上不需要电连接、复杂的多层布线或金属化图案,因此绝缘体可用将所述第一与第二引线框架彼此电绝缘的任何材料形成且还可具有在其内形成的通孔通路。可使用塑料、玻璃、陶瓷、玻璃纤维、树脂、PC板、胶带、膜、纸及其它绝缘体。化学蚀刻、光刻法、激光钻孔或机械钻孔エ艺可形成所述通路。可使用塑料或树脂模制来形成其中形成有通路的绝缘体。所述绝缘体可形成为各种厚度并可视需要而为刚性或挠性材料。可过模制所述绝缘体以完成所述封装式装置,另一选择为,可将所述绝缘体、集成电路及弓I线框架组合件定位 在外壳的空腔中或预形成的主体结构内,随后使用盖子或层以粘合剂或密封剂来密封所述结构。

[0035] 在另ー优选实施例中,可通过并入有绝缘体的任ー侧上的多个集成电路晶片而在单个封装中提供集成系统,将所述多个晶片线接合到引线框架,所述引线框架穿过所述绝缘体中的通路而耦合以在所述集成电路之间进行任意连接,其中用于系统的封装式组合件包含无源元件,例如电阻器、电容器或感应器。然后可将整个组合件过模制成使用本发明的方法提供的完成封装式系统。

[0036] 本发明的实施例的优点包含提供使用与现存工具兼容的常规线接合或倒装芯片技术及封装模制方法并使用与现存自动化半导体封装基础构造兼容的材料来形成包含彼此电耦合的多集成电路装置的多集成电路模块而无需现有技术的复杂插入物、挠性电路、层压衬底或图案化印刷电路板的设备及方法。

[0037] 以上说明已相当广泛地概述了本发明的实施例的特征与技术优点,以便可更好地了解以下对本发明的详细说明。所属技术中的技术人员应了解,可容易地将所掲示的概念及具体实施例用作修改或设计用于实行本发明的相同目的的其它结构或エ艺的依据。所属技术中的技术人员还应认识到,此类等效构造并不背离如所附权利要求书论述的本发明的精神及范围。

附图说明

[0038] 为更完全地了解本发明及其优点,现在參考以下结合附图所作的说明,所述附图是出于易于了解的目的而提供的代表性例示且并非按比例绘制,所述附图中:

[0039] 图I以图Ia的俯视图及图Ib的仰视图描绘现有技术可抽换式存储卡封装;

[0040] 图2描绘如图I所图解说明的包含存储器装置及控制器装置的现有技术可抽换式存储卡的截面图;

[0041] 图3描绘可并入到本发明的优选实施例中的具有通孔通路的绝缘体层的俯视图;

[0042] 图4描绘图3的绝缘体层的截面图;

[0043] 图5描绘例如图3、4中的具有定位在所述绝缘体上的引线框架及集成电路的绝缘体层的俯视图;

[0044] 图6以截面图描绘图5的装置,后跟额外的处理步骤;

[0045] 图7a、7b以截面图描绘本发明的绝缘体层的额外优选实施例;

[0046] 图8描绘作为本发明的优选实施例的完成封装式装置的截面图;

[0047] 图9描绘作为本发明的另ー优选实施例的另ー完成封装式装置的截面图;

[0048] 图10描绘图9的装置的俯视图,及

[0049] 图11描绘作为本发明的另ー优选实施例的另ー完成封装式装置的截面图。

[0050] 不同图式中的对应编号及符号通常指代对应的部件,除非另有指示。绘制所述图式以清楚地图解说明优选实施例的相关方面且所述图式不必按比例绘制。

具体实施方式

[0051] 下文详细说明目前优选实施例的操作及制作。然而,所说明的实施例及实例并非本发明所涵盖的仅有应用或使用。所论述的具体实施例仅例示用以制造及使用本发明的具体方式,而不限制本发明的范围。所述图式是出于说明的目的而非按比例绘制。

[0052] 图3描绘用于本发明的优选实施例中的绝缘体层300的俯视图。绝缘体层300可包括与半导体处理步骤兼容的许多绝缘材料中的任一者,例如迈拉(Mylar)、宇部兴产(Upilex)、卡普顿(Kapton)及其它膜、绝缘纸、树脂、聚酰亚胺、玻璃、玻璃纤维及类似物,其在所属技术中已熟知。层300是电绝缘且优选地具有与某些热エ艺(例如,转移模制)兼容的物理特性。所述绝缘层中的通孔通路301在如下文详述的预定位置处形成,并提供形成于绝缘层300中的通孔。通孔通路可以是任何大小但在优选实施例中直径约为3-10密耳且优选地直径约为5密耳。在将要说明的第一优选实施例中,所述通路是开放性通孔,在下文所说明的其它实施例中,所述通路可用导电膏或粘合剂加以填充。

[0053] 图4以截面图描绘图3的绝缘层。在图4中,将通孔通路301显示为延伸穿过绝缘层300。举例来说,可通过激光钻孔、机械钻孔、蚀刻、冲孔或使用其它手段来形成通孔通路301以在材料(例如,模制)中形成孔。如在所属技术中所熟知,可使用光刻法来将所述表面上具有用于界定所述孔的位置及尺寸的正或负抗蚀剂的抗腐蚀层图案化,可施加选择性蚀刻来移除所述材料,且然后可剥离所述图案层。

[0054] 图5描绘本发明的优选实施例在已完成多个装配步骤之后的俯视图。在图5中,绝缘体层300已具有形成于所选定位置中的通孔通路301。引线框架具有引线502并包含上覆于通孔通路位置301上的某些引线。集成电路晶片303经定位而接近于引线502的内部端。形成接合线505并将接合垫507电耦合到引线502。虽然在图5中所描绘的视图中不可见,但执行对称操作以将第二引线框架及第ニ集成电路晶片定位在绝缘体层300的相对表面上,其中将第二引线框架的某些引线定位在通孔通路301下方。

[0055] 图6描绘本发明的优选实施例在装配的中间阶段的截面图。在图6中,将集成电路晶片303显示为定位在绝缘体层300的第一表面上方。以截面图显示引线框架引线502,且将接合线505显示为将集成电路晶片的接合垫连接到引线框架引线502。显示通孔通路301在绝缘体层300中的所选定位置处形成。

[0056] 将引线框架601显示为定位在绝缘体层300下面并在通孔通路301下面延伸。使用接合线605将集成电路晶片604从接合垫603耦合到引线框架601引线。

[0057] 如图6所图解说明,可将引线框架引线耦合在一起以穿过绝缘体而在通孔通路位置301内形成物理及电连接。在图6中,使用焊接工具607在通孔通路301中将引线502与602挤压在一起并使其变形,且施加能量以使所述两个引线变为焊接在一起。可使用超声波、电及/或热能量来形成所述焊接,所涵盖的方法包含使用电阻焊接、电容放电或激光焊接。在某些实施例中,可在装配之前用材料涂布所述弓I线框架弓I线以通过点镀敷或其它方法帮助形成所述焊接。此耦合操作是在每一通孔通路位置301中执行的。通过适当地设 计所述引线框架及绝缘体层300,可在如图5及图6所示的两个集成电路之间的任何所需位置处进行电连接。[0058] 在优选方法中,使用工具(例如,图6中的工具607)在上与下引线框架引线之间形成焊接并同时在绝缘体层300中形成通孔通路301,即所述绝缘体最初并没有形成于其中的孔,将所述引线框架定位在彼此相対的任ー侧上,且定位在需要将来自所述上及下引线框架的引线耦合在一起的位置处。在此优选方法中,焊接工具607用于将能量(例如,热)施加于需要连接的位置处的引线,绝缘体材料响应于所述能量而熔化或蒸发且在移除所述绝缘体材料时形成通孔通路301,使所述引线物理变形到通孔通路301中且然后在单个连续操作中将所述引线焊接在一起。在此方法中,因为绝缘体不需要图案化或设计,因此可在大大地降低绝缘体层的成本。

[0059] 图7a及7b描绘用于在绝缘体层300中的通孔通路位置301处连接上与下引线框架引线的替代性方法。在图7a中,描绘用于本发明的封装的具有填充有导电材料705的通孔通路301的绝缘体层300的一部分。将导电材料(例如,导电膏)沉积在通孔通路301中且随后随着装配过程的继续而将所述导电材料定位在引线框架引线之间。所述导电材料完成如图6的两个集成电路装置之间的电连接。如所属技术中所熟知,所述导电材料可以是筛分于所述通路中的导电膏或导电油墨,举例来说,可从新泽西州(New Jersey)的落基山(Rocky Hill)的派利克(Parelec)购得的商品名为帕莫德VLT(Parmod VLT)的导电油墨材料;且可通过丝网印刷、激光研磨及填充或喷墨印刷工艺来施加此材料。可施加热或其它能量来完成导电路径并将引线物理接合到所述导电材料。

[0060] 图7b描绘用作绝缘体层300的各向异性导电材料。此材料最初在平面水平及垂直方向上绝缘。所述材料包含导电丝,其在经受压力及/或热或其它能量时在选择性区域中在垂直方向上变为导电。因此,在图7b中,导电路径707在位于两个引线框架引线之间的位置处形成,一个引线来自上引线框架且ー个引线来自下引线框架,此引线路径用于代替图5及6的通孔通路301而在任意选定位置处连接所述弓I线框架引线。明尼苏达州(Minnesota)的圣保罗(St. Paul)的3M公司提供作为各向异性导体的压敏粘合剂转移胶带,3M胶带9703是可使用的实例性产品。用于实施例的各向异性膜及导电膏(例如图7b(膜)或图7a(膏))也可从其它商业卖主(例如,德国杜塞尔多夫(Diisseldorf)的汉高(Henkel)技木)购得。这些材料可与其它膜一起使用或単独使来提供绝缘体层300。

[0061]图8描绘使用倒装芯片技术以将集成电路晶片耦合到引线框架的替代性优选实施例。在图8中,使用上覆于绝缘体层300的任一侧上并保护其内的装置及引线框架的囊封剂803来形成封装801。通孔通路301在绝缘体层300中形成并耦合如上所说明的来自上及下引线框架的引线502。通过以下步骤将可以是存储器控制器装置的集成电路晶片303倒装芯片接合到上引线框架:首先执行熟知的晶片或晶圆凸点エ艺,其在集成电路的晶片垫上形成焊料块、球或柱,然后将焊料凸点的晶片与引线框架引线的内部端对准且将所述晶片固定为“朝下”以将晶片垫耦合到所述引线框架引线,使用热能来回流所述焊料并完成到所述引线框架的连接。同样,也将可以是(举例来说)非易失性存储器(例如,快闪存储器装置)的集成电路809倒装芯片安装到下引线框架,且形成焊接(例如,807)以在通孔通路301中将上与下引线框架耦合在一起。图8还描绘本发明在封装内的两个或更多个集成 电路之间进行任意定位连接的能力,晶片不必相同或甚至几乎大小相同。

[0062]图9描绘使用线接合连接的替代性优选实施例的完成封装901,其将芯片下引线或“LUC”引线框架用于所述上及下引线框架。同样地在图9中,引线延伸穿过囊封剂边界并提供到封装的外部连接。以截面图描绘如以前在绝缘体层300的任ー侧上提供有囊封剂903的封装901,再次说明,所述囊封剂保护集成电路晶片、引线框架及线接合免受损坏及湿气。集成电路晶片303经提供而上覆于上引线框架的引线502上且可使用胶带或环氧晶片附着物609而有利地安装到所述引线框架。使用如以前的线接合将上及下集成电路的接合垫606线接合连接到引线框架引线502,接合线505延伸并耦合到所述引线框架引线。显示焊接807在通孔通路301中将上与下引线框架引线耦合。引线502延伸穿过囊封剂边界以形成外部端子并(举例来说)通过使用插槽装置来启用到封装901的外部连接。在此实施例中,来自上引线框架的引线出现在封装的一个侧上且来自下引线框架的引线出现在封装的另ー侧上。

[0063] 图10以俯视图描绘图9的封装901。将绝缘体层300显示为具有形成于其上的囊封剂903。将引线502显示为上覆于绝缘体层300上。将焊接807显示为位于在某些引线502下面形成的通路中。将集成电路晶片303定位在引线502上方,使得引线框架为LUC或 芯片下引线布置,可通过胶带或环氧附着所述晶片以提供支撑。通过线接合505将所述集成电路上的接合垫耦合到引线框架引线502。在此视图中不可见的是位于绝缘体层300下面并通过焊接807耦合到上引线框架的第二集成电路与引线框架组合件。

[0064] 图11显示另一优选实施例,其中在封装的一个侧上将引线502中的某些形成为向下且囊封剂903包围整个组合件,但允许选定引线502的底表面101上的区域暴露以进行外部电连接。可如图I所示或以所属技术中的技术人员将明了的其它类似图案来定位这些外部连接区域。

[0065] 可改变用于实践本发明的方法且将这些变更涵盖于本发明及随附权利要求书的范围内。举例来说,可将引线框架与绝缘体层300装配在一起作为预形成的组合件并将集成电路晶片定位位邻近对应的引线框架,使用线接合或倒装芯片耦合来完成到所述晶片的连接,且然后可执行过模制或圆顶封装体囊封。另ー选择为,可以带形式提供引线框架,可定位集成电路晶片并执行线接合或倒装芯片处理以在使用或不使用粘合剂或胶带的情况下将所述集成电路耦合到所述引线框架;然后将引线框架组合件定位在绝缘体层300的相应相对表面上方,已通过提前将绝缘体层300图案化而提供通孔通路301,且然后通过焊接,使用如以上所说明的导电膏或焊料或各向异性导体连接来将所述引线框架耦合在一起。最后,可对完成的组合件进行过模制或圆顶封装体囊封,从而完成所述封装。可在另ー替代性方法中提供不具有形成于其内的通孔通路301的如上说明的绝缘体层300,且可使用工具焊接并同时在绝缘体层300中形成通孔通路301。

[0066] 虽然在本文中详细说明本发明的某些优选实施例及其优点,但应了解,可在不背离如随附权利要求书所界定的本发明的精神及范围的情况下对所说明的实施例做出各种改变、替换及变更。此外,本申请案的范围并非既定限定为本说明书中所说明的电路、结构、方法及步骤的特定实施例。因此,随附权利要求书既定在其范围内包含利用本发明的那些エ艺,机器,制造、事件的组成、构件、方法或步骤以及利用本发明的所属技术中的技术人员所明了的变动与解决方案。

Claims (26)

1. 一种多晶片半导体封装,其包括: 绝缘体,其具有第一表面、与所述第一表面相対的第二表面及预定位置处的ー个或ー个以上通孔通路; 第一引线框架,其至少部分地上覆于所述第一表面上并具有多个引线,上覆于ー个或ー个以上通孔通路的引线的部分变形到所述ー个或ー个以上通孔通路中; 第一集成电路晶片,其邻近并电耦合到所述第一引线框架的所述多个引线中的至少ー者; 第二引线框架,其至少部分地上覆于所述第二表面上并具有多个引线;及 第二集成电路晶片,其邻近并电耦合到所述第二引线框架的所述多个引线中的至少ー者; 其中所述第一引线框架的所述多个引线中的至少ー者穿过所述绝缘体中的所述通孔通路中的一者而电耦合到所述第二引线框架的所述多个引线中的对应ー者。
2.如权利要求I所述的封装,其中所述封装进ー步包括囊封剂,其至少部分地囊封所述绝缘体、所述第一及第ニ集成电路晶片及所述第一及第ニ引线框架。
3.如权利要求I所述的封装,其中所述第一及第ニ集成电路晶片是相同的。
4.如权利要求I所述的封装,其中所述第一及第ニ集成电路晶片分别包括控制器集成电路及存储器阵列集成电路。
5.如权利要求4所述的封装,其中所述存储器阵列集成电路包括非易失性存储器装置。
6.如权利要求I所述的封装,其中所述第一及第ニ集成电路晶片通过接合线分别电耦合到所述第一及第ニ引线框架。
7.如权利要求I所述的封装,其中所述第一及第ニ集成电路晶片通过倒装芯片连接分别电耦合到所述第一及第ニ引线框架。
8.如权利要求6所述的封装,其中所述第一与第二集成电路晶片呈背对背关系。
9.如权利要求7所述的封装,其中所述第一与第二集成电路晶片呈面对面关系。
10.如权利要求I所述的封装,其中所述通孔通路中填充有导电材料,所述材料物理接触所述第一引线框架的所述至少ー个弓I线。
11.如权利要求I所述的封装,其中所述绝缘体在所述ー个或ー个以上通孔通路位置处包括各向异性导电材料,且通过致使所述各向异性导电材料在所述ー个或ー个以上通孔通路处变为导电而形成电连接。
12.如权利要求I所述的封装,其中所述第一及第ニ引线框架中的每ー者的至少ー个引线在所述绝缘体中的所述通孔通路中的至少ー者内被彼此物理焊接。
13.如权利要求I所述的封装,其中上覆于ー个或ー个以上通孔通路的所述第二引线框架的引线的部分变形到所述ー个或ー个以上通孔通路中,所述第一及第ニ引线框架引线中的每ー者的所述至少ー个引线变形并进入所述通孔通路,然后所述引线在所述通孔通路中被彼此焊接。
14. 一种用于形成多晶片集成电路封装的方法,其包括以下步骤: 提供具有第一表面及与所述第一表面相対的第二表面的绝缘体层; 在所述绝缘层中在所需位置处形成一个或ー个以上通孔通路;提供具有至少部分地上覆于所述第一表面上的多个引线的第一引线框架; 提供具有至少部分地上覆于所述第二表面上的多个引线的第二引线框架; 将第一集成电路晶片耦合到所述第一引线框架的至少ー个引线; 将第二集成电路晶片耦合到所述第二引线框架的至少ー个引线; 在覆盖一通孔通路的位置,将所述第一引线框架的一引线的一部分变形到所述通孔通路中; 穿过所述绝缘体层中的所述通孔通路将经变形到所述通路中的所述引线的所述部分电连接到所述第二引线框架的ー对应引线; 从而将所述第一与第二集成电路晶片彼此电耦合。
15.如权利要求14所述的方法,且其进一歩包括以下步骤: 至少部分地囊封所述绝缘体层、所述第一及第ニ集成电路晶片以及所述第一及第ニ引线框架。
16.如权利要求14所述的方法,其进ー步包括以下步骤: 将所述第二引线框架的所述对应引线的一部分形成到所述通孔通路中。
17.如权利要求16所述的方法,其中所述电连接步骤包括在所述通孔通路内的所述第一引线框架的所述引线的所述部分与所述第二引线框架的所述对应引线的所述部分之间形成物理焊接。
18.如权利要求16所述的方法,其中所述电连接步骤包括在所述通孔通路内的所述第一引线框架的所述引线的所述部分与所述第二引线框架的所述对应引线的所述部分之间提供导电粘合剤。
19.如权利要求14所述的方法,其中所述将第一及第ニ集成电路晶片与所述第一及第ニ引线框架耦合的步骤包括耦合相同的集成电路晶片。
20.如权利要求14所述的方法,其中所述将第一及第ニ集成电路晶片耦合到所述第一及第ニ引线框架的步骤包括将存储器阵列集成电路晶片耦合到所述第一引线框架并将控制器集成电路晶片耦合到所述第二引线框架。
21.如权利要求20所述的方法,其中所述将所述存储器阵列集成电路晶片耦合到所述第一引线框架的步骤包括耦合非易失性存储器阵列集成电路晶片。
22.如权利要求21所述的方法,且其进一歩包括在所述非易失性存储器阵列集成电路晶片上方堆叠额外的非易失性存储器集成电路晶片的步骤。
23.如权利要求14所述的方法,其中所述将所述第一及第ニ集成电路晶片耦合到所述第一及第ニ引线框架的步骤包括在所述第一及第ニ集成电路晶片与所述第一及第ニ引线框架之间形成线接合。
24.如权利要求23所述的方法,其中所述耦合所述第一与第二集成电路晶片的步骤进一歩包括将所述集成电路晶片以背对背关系放置的步骤。
25.如权利要求14所述的方法,其中所述将所述第一及第ニ集成电路晶片耦合到所述第一及第ニ引线框架的步骤包括在所述第一及第ニ集成电路晶片与所述第一及第ニ引线框架之间形成倒装芯片连接。
26.如权利要求25所述的方法,其中所述将所述第一及第ニ集成电路晶片耦合到所述第一及第ニ引线框架的步骤进一歩包括将所述第一及第ニ集成电路晶片以面对面关系放置。
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US7939920B2 (en) 2011-05-10 grant
US20080315382A1 (en) 2008-12-25 application
CN101341593A (zh) 2009-01-07 application
US8030135B2 (en) 2011-10-04 grant
US20070096265A1 (en) 2007-05-03 application
US7511371B2 (en) 2009-03-31 grant
US20090239340A1 (en) 2009-09-24 application

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