CN101290918A - Chip packaging structure - Google Patents

Chip packaging structure Download PDF

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Publication number
CN101290918A
CN101290918A CNA200710101330XA CN200710101330A CN101290918A CN 101290918 A CN101290918 A CN 101290918A CN A200710101330X A CNA200710101330X A CN A200710101330XA CN 200710101330 A CN200710101330 A CN 200710101330A CN 101290918 A CN101290918 A CN 101290918A
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CN
China
Prior art keywords
chip
line layer
patterned line
adhesion coating
packaging structure
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Granted
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CNA200710101330XA
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Chinese (zh)
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CN101290918B (en
Inventor
潘玉堂
周世文
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Priority to CN200710101330XA priority Critical patent/CN101290918B/en
Publication of CN101290918A publication Critical patent/CN101290918A/en
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Publication of CN101290918B publication Critical patent/CN101290918B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

The invention discloses a chip package structure, which comprises a patterned wire layer, an outer frame, a first adhesive layer, a plurality of pins, an insulating adhesive layer, a chip, a plurality of first leads, a plurality of second leads and a package colloid, wherein, the outer frame and the pins are arranged outside the patterned wire layer and the first adhesive layer fixes the patterned wire layer and the outer frame; the insulating adhesive layer is arranged between the pins and the outer frame; the chip provided with a plurality of weld pads is arranged on the first adhesive layer; the first leads are respectively and electrically connected with the weld pads and the patterned wire layer; the second leads are respectively and electrically connected with the pins and the patterned wire layer, and the weld pads are electrically connected to the pins through the first leads, the patterned wire layer and the second leads; and the package colloid covers the patterned wire layer, the outer frame, the first adhesive layer, the pins, the insulating adhesive layer, the chip, the first leads and the second leads. The chip is arranged on the patterned wire layer which can be used as transmit points of jumping wires, thereby the configuration relation between the weld pads and the pins has larger elasticity.

Description

Chip-packaging structure
Technical field
The invention relates to a kind of semiconductor device, and particularly relevant for a kind of chip-packaging structure with patterned line layer.
Background technology
In semiconductor industry, (integrated circuits, production IC) mainly can be divided into three phases to integrated circuit: the making (IC process) of the design of integrated circuit (IC design), integrated circuit and the encapsulation (IC package) of integrated circuit.
In the making of integrated circuit, chip (chip) is to finish via wafer (wafer) making, formation integrated circuit and cutting crystal wafer steps such as (wafer sawing).Wafer has an active surface (activesurface), the surface with active member (active device) of its general reference wafer.After the integrated circuit of wafer inside was finished, the active surface of wafer also disposed a plurality of weld pads (bonding pad), can outwards be electrically connected at a carrier (carrier) via these weld pads so that finally cut formed chip by wafer.Carrier for example is a lead frame (lead frame) or a base plate for packaging (packagesubstrate), and can have a plurality of contacts.The mode that chip can routing engages (wire bonding) or chip bonding (flip chip bonding) is connected to contact, so these weld pads of chip can be electrically connected at pin, to constitute a chip-packaging structure.
With lead bond pad and contact the time, the same side that mutual weld pad that electrically connects and contact need be positioned at chip usually engages distance to shorten.Thus, the allocation position of weld pad and pin is limited, and on the line design bigger elastic space can't be arranged.In addition, owing to only is connected with lead between pin and the chip, so the heat that chip produced is difficult for conducting to the external world, so cause dispel the heat bad.
Summary of the invention
The invention provides a kind of chip-packaging structure, with the elasticity of the configuration that improves weld pad and pin.
For addressing the above problem, the present invention proposes a kind of chip-packaging structure, comprises a patterned line layer, a housing, one first adhesion coating, a plurality of pin, an insulation adhesion coating, a chip, many first leads, many second leads and a packing colloid.Housing and pin configuration is in the patterned line layer outside, and housing and patterned line layer can form simultaneously by same metal layer, and first adhesion coating fixed pattern line layer and the housing, and expose partially patterned line layer.The insulation adhesion coating is disposed between pin and the housing, with fixedly pin and housing.Chip configuration is on first adhesion coating, and chip has a plurality of weld pads.First lead electrically connects weld pad and patterned line layer respectively, and second lead then electrically connects pin and patterned line layer respectively, and weld pad is electrically connected to pin via first lead, patterned line layer and second lead.Packing colloid coats part, insulation adhesion coating, chip, first lead and second lead of patterned line layer, housing, first adhesion coating, each pin.
In chip-packaging structure of the present invention, above-mentioned pin configuration is on housing.
In chip-packaging structure of the present invention, above-mentioned housing is a metal level.
In chip-packaging structure of the present invention, above-mentioned weld pad is positioned at a side of chip.
In chip-packaging structure of the present invention, above-mentioned first lead and second lead are positioned at a side of chip.
In chip-packaging structure of the present invention, above-mentioned first lead and second lead are positioned at the both sides of chip.
In chip-packaging structure of the present invention, above-mentioned first adhesion coating is disposed on patterned line layer and the housing.
In chip-packaging structure of the present invention, above-mentioned first adhesion coating is an adhesive tape.
In chip-packaging structure of the present invention, also comprise one second adhesion coating, be disposed at the below of patterned line layer and housing.
In chip-packaging structure of the present invention, above-mentioned second adhesion coating is an adhesive tape.
In chip-packaging structure of the present invention, also comprise a fin, be fixed in second adhesion coating below.
In chip-packaging structure of the present invention, above-mentioned packing colloid exposes the part fin.
In chip-packaging structure of the present invention, above-mentioned packing colloid coats fin.
In chip-packaging structure of the present invention, above-mentioned first adhesion coating passes patterned line layer, and part first adhesion coating is between chip and patterned line layer, and part first adhesion coating is positioned at the patterned line layer below.
In chip-packaging structure of the present invention, also comprise a fin, be fixed on first adhesion coating of patterned line layer below.
In chip-packaging structure of the present invention, above-mentioned packing colloid exposes the part fin.
In chip-packaging structure of the present invention, above-mentioned packing colloid coats fin.
In chip-packaging structure of the present invention, above-mentioned first adhesion coating is welding cover layer or glue-line.
In chip-packaging structure of the present invention, the material of above-mentioned glue-line is solidified glue for the B rank.
For addressing the above problem, the present invention proposes another kind of chip-packaging structure, comprises a patterned line layer, a housing, one first adhesion coating, a plurality of pin, an insulation adhesion coating, one first chip, many first leads, many second leads, at least one second chip, many privates and a packing colloid.Housing and pin configuration are in the patterned line layer outside, and first adhesion coating fixed pattern line layer and the housing, and expose partially patterned circuit.The insulation adhesion coating is disposed between pin and the housing, with fixedly pin and housing.First chip configuration is on first adhesion coating, and first chip has a plurality of first weld pads.First lead electrically connects first weld pad and patterned line layer respectively, and second lead then electrically connects pin and patterned line layer respectively, and first weld pad is electrically connected to pin via first lead, patterned line layer and second lead.Second chip configuration is in first chip top, and exposes first weld pad, and second chip has a plurality of second weld pads, and privates electrically connects second weld pad and first weld pad respectively.Packing colloid coats part, insulation adhesion coating, chip, first lead, second lead and the privates of patterned line layer, housing, first adhesion coating, each pin.
In chip-packaging structure of the present invention, above-mentioned pin configuration is on housing.
In chip-packaging structure of the present invention, above-mentioned housing is a metal level.
In chip-packaging structure of the present invention, above-mentioned first weld pad is positioned at a side of first chip, and second weld pad is positioned at the side of second chip near first weld pad.
In chip-packaging structure of the present invention, above-mentioned first lead and second lead are positioned at a side of first chip
In chip-packaging structure of the present invention, above-mentioned first lead and second lead are positioned at the both sides of first chip.
In chip-packaging structure of the present invention, above-mentioned first adhesion coating is disposed on patterned line layer and the housing.
In chip-packaging structure of the present invention, above-mentioned first adhesion coating is an adhesive tape.
In chip-packaging structure of the present invention, also comprise one second adhesion coating, be disposed at the below of patterned line layer and housing.
In chip-packaging structure of the present invention, above-mentioned second adhesion coating is an adhesive tape.
In chip-packaging structure of the present invention, also comprise one the 3rd chip, many privates and many articles the 5th leads.The 3rd chip configuration is in second adhesion coating below, and the 3rd chip has a plurality of the 3rd weld pads, and privates electrically connect the 3rd weld pad and patterned line layer respectively.The 5th lead electrically connects pin and patterned line layer respectively, and the 3rd weld pad is electrically connected to pin via the 5th lead, patterned line layer and privates.
In chip-packaging structure of the present invention, above-mentioned the 3rd weld pad is positioned at a side of the 3rd chip.
In chip-packaging structure of the present invention, above-mentioned privates and the 5th lead are positioned at a side of the 3rd chip.
In chip-packaging structure of the present invention, above-mentioned privates and the 5th lead are positioned at the both sides of the 3rd chip.
In chip-packaging structure of the present invention, also comprise at least one four-core sheet and many articles the 6th leads.The four-core sheet is disposed at the 3rd chip below, and exposes the 3rd weld pad, and the four-core sheet has a plurality of the 4th weld pads.The 6th lead electrically connects the 4th weld pad and the 3rd weld pad respectively.
In chip-packaging structure of the present invention, above-mentioned the 4th weld pad is positioned at the side of four-core sheet near the 3rd weld pad.
In chip-packaging structure of the present invention, also comprise a fin, be fixed in second adhesion coating below.
In chip-packaging structure of the present invention, above-mentioned packing colloid exposes the part fin.
In chip-packaging structure of the present invention, above-mentioned packing colloid coats fin.
In chip-packaging structure of the present invention, above-mentioned first adhesion coating passes patterned line layer, and part first adhesion coating is between first chip and patterned line layer, and part first adhesion coating is positioned at the patterned line layer below.
In chip-packaging structure of the present invention, also comprise one the 3rd chip, many privates and many articles the 5th leads.The 3rd chip configuration is on first adhesion coating of patterned line layer below, and the 3rd chip has a plurality of the 3rd weld pads.Privates electrically connect the 3rd weld pad and patterned line layer respectively.The 5th lead electrically connects pin and patterned line layer respectively, and the 3rd weld pad is electrically connected to pin via the 5th lead, patterned line layer and privates.
In chip-packaging structure of the present invention, above-mentioned the 3rd weld pad is positioned at a side of the 3rd chip.
In chip-packaging structure of the present invention, above-mentioned privates and the 5th lead are positioned at a side of the 3rd chip
In chip-packaging structure of the present invention, above-mentioned privates and the 5th lead are positioned at the both sides of the 3rd chip.
In chip-packaging structure of the present invention, also comprise at least one four-core sheet and many articles the 6th leads.The four-core sheet is disposed at the 3rd chip top, and exposes the 3rd weld pad, and the four-core sheet has a plurality of the 4th weld pads.The 6th lead electrically connects the 4th weld pad and the 3rd weld pad respectively.
In chip-packaging structure of the present invention, above-mentioned the 4th weld pad is positioned at the side of four-core sheet near the 3rd weld pad.
In chip-packaging structure of the present invention, also comprise a fin, be fixed on first adhesion coating of patterned line layer below.
In chip-packaging structure of the present invention, above-mentioned packing colloid exposes the part fin.
In chip-packaging structure of the present invention, above-mentioned packing colloid coats fin.
In chip-packaging structure of the present invention, above-mentioned first adhesion coating is welding cover layer or adhesive-layer.
In chip-packaging structure of the present invention, the material of above-mentioned adhesive-layer is solidified glue for the B rank.
Based on above-mentioned, on patterned line layer, and this patterned line layer can be used as the transit point of wire jumper with chip configuration in the present invention, so the configuration relation between weld pad and the pin has bigger elasticity.In addition, because pin directly is disposed on the housing, makes heat that chip produced more directly to conduct to pin and improve the radiating effect of chip-packaging structure.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Figure 1A is the front view of the chip-packaging structure of first embodiment of the invention.
Figure 1B is the profile of Figure 1A chips encapsulating structure.
Fig. 1 C is the generalized section of the configuration of another kind of first lead and second lead among first embodiment.
Fig. 1 D is the generalized section of the connected mode of another kind of weld pad and pin among first embodiment.
Fig. 2 is the profile of second embodiment of the invention chips encapsulating structure.
Fig. 3 is the generalized section of the configuration of another kind of packing colloid among second embodiment.
Fig. 4 A is the front view of third embodiment of the invention chips encapsulating structure.
Fig. 4 B is the profile of Fig. 4 A chips encapsulating structure.
Fig. 5 is the generalized section of the configuration of another kind of packing colloid among the 3rd embodiment.
Fig. 6 is the profile of fourth embodiment of the invention chips encapsulating structure.
Fig. 7 is the profile of fifth embodiment of the invention chips encapsulating structure.
Fig. 8 is the profile of sixth embodiment of the invention chips encapsulating structure.
Fig. 9 is the profile of seventh embodiment of the invention chips encapsulating structure.
Embodiment
First embodiment
Figure 1A is the front view of the chip-packaging structure of first embodiment of the invention, and Figure 1B is the profile of Figure 1A chips encapsulating structure.Please refer to Figure 1A and Figure 1B, chip-packaging structure 100 comprises a patterned line layer 110, a housing 120, one first adhesion coating 132, a plurality of pin 140, an insulation adhesion coating 150, a chip 160, many first lead 170a, many second lead 170b and a packing colloid 180.
Housing 120 for example is a metal level, wherein housing 120 can be formed by same metal layer simultaneously with patterned line layer 110, it is fixed in the outside of patterned line layer 110 by first adhesion coating 132, and first adhesion coating 132 exposes partially patterned line layer 110, and wherein first adhesion coating 132 for example is an adhesive tape.Chip 160 is disposed on first adhesion coating 132, and the first lead 170a electrically connects the partially patterned line layer 110 that each weld pad 162 on the chip 160 and first adhesion coating 132 are exposed respectively.The second lead 170b electrically connects each pin 140 and patterned line layer 110 respectively, and each weld pad 162 electrically connects by the first lead 170a, the second lead 170b and patterned line layer 110 respectively with each pin 140.Pin 140 is disposed at patterned line layer 110 outsides, and in the present embodiment, pin 140 for example is to be fixed on the housing 120 by insulation adhesion coating 150, and the material of the adhesion coating 150 that wherein insulate can be insulating radiation glue material.Pin 140 is not limited to be disposed on the housing 120, and those skilled in the art also can be disposed at other positions with pin 140, for example the outside that pin 140 is disposed housings 120.Packing colloid 180 coats a part, insulation adhesion coating 150, chip 160, the first lead 170a and the second lead 170b of patterned line layer 110, housing 120, first adhesion coating 132, each pin 140.
In the present embodiment, weld pad 162 is positioned at a side of chip 160, and the first lead 170a and the second lead 170b lay respectively at the both sides of chip 160.Specifically, weld pad 162 is electrically connected to a side of patterned line layer 110 by the first lead 170a, and the second lead 170b then electrically connects the opposite side of pin 140 and patterned line layer 110.In other words, the pin 140 that is connected with weld pad 162 of weld pad 162 is positioned at the both sides of chip 160.In addition, weld pad 162 also can otherwise dispose with the pin 140 that weld pad 162 is connected.
Fig. 1 C is the generalized section of the configuration of another kind of first lead and second lead among first embodiment, and Fig. 1 D is the generalized section of the connected mode of another kind of weld pad and pin among first embodiment.Please refer to Fig. 1 C and Fig. 1 D, can find out that from Fig. 1 C the pin 140 that weld pad 162 is connected with weld pad 162 is positioned at the homonymy of patterned line layer 110, and in Fig. 1 D, chip-packaging structure 100b also has a privates 170c, and privates 170c directly connects weld pad 162 and pin 140.
Because chip-packaging structure 100 of the present invention has a patterned line layer 110, therefore, the pin 140 that weld pad 162 is connected with weld pad 162 is except the homonymy that can be positioned at chip 160, and the pin 140 that weld pad 162 is connected with weld pad 162 is positioned at the not homonymy of chip 160.In other words, present embodiment utilizes patterned line layer 110 to change the transmission path of signal, therefore makes the configuration relation between weld pad 162 and the pin 140 that bigger elasticity be arranged.In addition, because pin 140 is disposed on the housing 120 with insulating radiation glue material, so the heat that chip 160 is produced can directly conduct to pin 140 by housing 120, and then improves the radiating effect of chip-packaging structure 100.
Second embodiment
Fig. 2 is the profile of second embodiment of the invention chips encapsulating structure.What need explanation earlier is that second embodiment and first embodiment are roughly the same, and in second embodiment and first embodiment, same or analogous element numbers is represented same or analogous element.Below will illustrate that in detail something in common just repeats no more at two embodiment differences.
Please refer to Fig. 2, in the present embodiment, chip-packaging structure 100a has one second adhesion coating 134, and second adhesion coating 134 is disposed at the below of patterned line layer 110 and housing 120, and second adhesion coating 134 for example is all adhesive tape with first adhesion coating 132.In addition, chip-packaging structure 100a also can have a fin 190, and fin 190 is fixed in second adhesion coating, 134 belows, and the heat that can allow chip 160 produce directly conducts to fin 190 and more effective heat radiation by housing 120.In the present embodiment, fin 190 is by coming out in the packing colloid 180, but those skilled in the art also can otherwise dispose.Fig. 3 is the generalized section of the configuration of another kind of packing colloid among second embodiment.Please refer to Fig. 3, by finding out among Fig. 3, packing colloid 180 coats fin 190.
The 3rd embodiment
Fig. 4 A is the front view of third embodiment of the invention chips encapsulating structure, and Fig. 4 B is the profile of Fig. 4 A chips encapsulating structure.What need explanation earlier is that the 3rd embodiment and first embodiment are roughly the same, and in the 3rd embodiment and first embodiment, same or analogous element numbers is represented same or analogous element.Below will illustrate that in detail something in common just repeats no more at two embodiment differences.
Please refer to Fig. 4 A and Fig. 4 B, first adhesion coating 132 ' of chip-packaging structure 100b for example is glue-line or welding cover layer, and it passes patterned line layer 110 and coats patterned line layer 110 and the two sides of housing 120, and exposes partially patterned line layer 110.In the present embodiment, chip-packaging structure 100c also can have a fin 190 as chip-packaging structure 100a.Fin 190 is disposed at first adhesion coating 132 ' of patterned line layer 110 belows, and packing colloid 180 exposes the fin 190 of a part.The packing colloid 180 of present embodiment also can otherwise dispose, and Fig. 5 is the generalized section of the configuration of another kind of packing colloid among the 3rd embodiment.Please refer to Fig. 5, by finding out among Fig. 5, the packing colloid 180 ' of chip-packaging structure 100d does not expose fin 190, but coats fin 190.
The 4th embodiment
Fig. 6 is the profile of fourth embodiment of the invention chips encapsulating structure.What need explanation earlier is that the 4th embodiment and first embodiment are roughly the same, and in the 4th embodiment and first embodiment, same or analogous element numbers is represented same or analogous element.Below will illustrate that in detail something in common just repeats no more at two embodiment differences.
Please refer to Fig. 6, in the chip-packaging structure 200 of present embodiment, the first chip 260a with a plurality of first weld pad 262a is disposed on first adhesion coating 232, and the second chip 260b then is disposed on the first chip 260a, and exposes the first weld pad 262a.Chip-packaging structure 200 also has many privates 270c, and the second chip 260b has a plurality of second weld pad 262b, and the second weld pad 262b is electrically connected to the first weld pad 262a respectively by privates 270c.It should be noted that, though in Fig. 6, be the example explanation with a plurality of second chip 260b, but the present invention does not limit the quantity of the second chip 260b, and those skilled in the art is the second chip 260b of configurable other quantity also, for example only disposes one second chip 260b.
The 5th embodiment
Fig. 7 is the profile of fifth embodiment of the invention chips encapsulating structure.What need explanation earlier is that the 5th embodiment and the 4th embodiment are roughly the same, and in the 5th embodiment and the 4th embodiment, same or analogous element numbers is represented same or analogous element.Below will illustrate that in detail something in common just repeats no more at two embodiment differences.
The chip-packaging structure 200a of present embodiment also has one the 3rd chip 260c, many privates 270d and many articles the 5th lead 270e.The 3rd chip 260c is disposed on second adhesion coating 234, and the 3rd chip 260c has a plurality of the 3rd weld pad 262c, and privates 270d electrically connects the 3rd weld pad 262c and patterned line layer 210, the 5th lead 270e then connects patterned line layer 210 and pin 240, so that the 3rd weld pad 262c can be electrically connected to pin 240 by privates 270d, the 5th lead 270e and patterned line layer 210.In addition, chip-packaging structure 200a also can have a plurality of four-core sheet 260d and many articles the 6th lead 270f.Four-core sheet 260d has a plurality of the 4th weld pad 262d, and four-core sheet 260d is disposed on the 3rd chip 260c, and exposes the 3rd weld pad 262c, and the 6th lead 270f electrically connects the 3rd weld pad 262c and the 4th weld pad 262d.
It should be noted that, though in Fig. 7, be the example explanation with a plurality of four-core sheet 260d, but the present invention does not limit the quantity of four-core sheet 260d, and those skilled in the art is the four-core sheet 260d of configurable other quantity also, for example only disposes a four-core sheet 260d.In addition, the configuration of privates 270d and the 5th lead 270e is not limited to illustrate among Fig. 7, also privates 270d and the 5th lead 270e can be disposed at the same side of the 3rd chip 260c.
The 6th embodiment
Fig. 8 is the profile of sixth embodiment of the invention chips encapsulating structure.What need explanation earlier is that the 6th embodiment and the 4th embodiment are roughly the same, and in the 6th embodiment and the 4th embodiment, same or analogous element numbers is represented same or analogous element.Below will illustrate that in detail something in common just repeats no more at two embodiment differences.
In the present embodiment, first adhesion coating 232 ' for example is glue-line or welding cover layer, and it passes patterned line layer 210 and coats patterned line layer 210 and the two sides of housing 220, and exposes partially patterned line layer 210.The chip-packaging structure 200b of present embodiment also can have a fin 290, and fin 290 is disposed at first adhesion coating 232 ' that is positioned at patterned line layer 210 belows, and packing colloid 280 exposes the fin 290 of a part.Though it should be noted that the fin 290 that exposes a part with packing colloid 280 in Fig. 8 is the example explanation, the chip-packaging structure 200b of present embodiment also can make packing colloid 280 coat fin 290 as the chip-packaging structure 100b of the 3rd embodiment.
The 7th embodiment
Fig. 9 is the profile of seventh embodiment of the invention chips encapsulating structure.What need explanation earlier is, in the 7th embodiment and the 5th embodiment, same or analogous element numbers is represented same or analogous element, and the 7th embodiment and the 5th embodiment are roughly the same.Below will illustrate that in detail something in common just repeats no more at two embodiment differences.
In the present embodiment, first adhesion coating 232 ' for example is glue-line or welding cover layer, and it passes patterned line layer 210 and coats patterned line layer 210 and the two sides of housing 220, and exposes partially patterned line layer 210.The first chip 260a is disposed at first adhesion coating 232 ' that is positioned at patterned line layer 210 tops, and the 3rd chip 260c then is disposed at first adhesion coating 232 ' that is positioned at patterned line layer 210 belows.
It should be noted that in above-mentioned second to the 7th embodiment first lead and second lead can have the various configurations mode as the first lead 170a among first embodiment and the second lead 170b.For example, first lead and second lead are configurable in the homonymy of chip, also can be with first lead and second conductor configurations in the not homonymy of chip, and in other words, the pin that weld pad is connected with weld pad can be positioned at the homonymy of chip or homonymy not.In addition, also can as shown in Fig. 1 D, directly connect weld pad and pin among above-mentioned second to the 7th embodiment with lead.
In sum, the present invention utilizes patterned line layer to change the signal transmission path, and just the pin that is connected with weld pad of weld pad is positioned at the chip both sides.Perhaps, patterned line layer is as the transit point of wire jumper, and just the pin that is connected with weld pad of weld pad is positioned at chip the same side.Therefore, the configuration relation between weld pad and the pin has bigger elasticity.In addition, one or more chips can be fixed in a surface or two of patterned line layer via adhesion coating relatively on the surface, to form multi-chip stacking.In addition, because patterned line layer has high heat-conduction coefficient, so the heat that chip produced can directly conduct to pin by housing, and then promotes radiating effect.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any the technical staff in the technical field; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claims were defined.

Claims (18)

1. a chip-packaging structure is characterized in that, comprising:
One patterned line layer;
One housing is disposed at the described patterned line layer outside;
One first adhesion coating, fixing described patterned line layer and described housing, and expose partially patterned line layer;
A plurality of pins are disposed at the described patterned line layer outside;
One insulation adhesion coating is disposed between described pin and the described housing;
One chip be disposed on described first adhesion coating, and described chip has a plurality of weld pads;
Many first leads electrically connect described weld pad and described patterned line layer respectively;
Many second leads electrically connect described pin and described patterned line layer respectively, and described weld pad is electrically connected to described pin via described first lead, described patterned line layer and described second lead; And
One packing colloid coats the part of described patterned line layer, described housing, described first adhesion coating, each described pin, described insulation adhesion coating, described chip, described first lead and described second lead.
2. chip-packaging structure as claimed in claim 1 is characterized in that described pin configuration is on described housing.
3. chip-packaging structure as claimed in claim 1 is characterized in that, described housing is a metal level.
4. chip-packaging structure as claimed in claim 1 is characterized in that, described first adhesion coating is disposed on described patterned line layer and the described housing.
5. chip-packaging structure as claimed in claim 4 is characterized in that, also comprises one second adhesion coating, is disposed at the below of described patterned line layer and described housing.
6. chip-packaging structure as claimed in claim 5 is characterized in that, also comprises a fin, is fixed in described second adhesion coating below.
7. chip-packaging structure as claimed in claim 1, it is characterized in that, described first adhesion coating passes described patterned line layer, and part first adhesion coating is between described chip and described patterned line layer, and part first adhesion coating is positioned at described patterned line layer below.
8. chip-packaging structure as claimed in claim 7 is characterized in that, also comprises a fin, is fixed on first adhesion coating of described patterned line layer below.
9. a chip-packaging structure is characterized in that, comprising:
One patterned line layer;
One housing is disposed at the described patterned line layer outside;
One first adhesion coating, fixing described patterned line layer and described housing, and expose partially patterned line layer;
A plurality of pins are disposed at the described patterned line layer outside;
One insulation adhesion coating is disposed between described pin and the described housing;
One first chip is disposed on described first adhesion coating, and described first chip has a plurality of first weld pads;
Many first leads electrically connect described first weld pad and described patterned line layer respectively;
Many second leads electrically connect described pin and described patterned line layer respectively, and described first weld pad is electrically connected to described pin via described first lead, described patterned line layer and described second lead;
At least one second chip is disposed at described first chip top, and exposes described first weld pad, and described second chip has a plurality of second weld pads;
Many privates electrically connect described second weld pad and described first weld pad respectively; And
One packing colloid coats the part of described patterned line layer, described housing, described first adhesion coating, each described pin, described insulation adhesion coating, described chip, described first lead, described second lead and described privates.
10. chip-packaging structure as claimed in claim 9 is characterized in that, described first adhesion coating is disposed on described patterned line layer and the described housing.
11. chip-packaging structure as claimed in claim 10 is characterized in that, also comprises one second adhesion coating, is disposed at the below of described patterned line layer and described housing.
12. chip-packaging structure as claimed in claim 11 is characterized in that, also comprises:
One the 3rd chip be disposed at described second adhesion coating below, and described the 3rd chip has a plurality of the 3rd weld pads;
Many privates electrically connect described the 3rd weld pad and described patterned line layer respectively; And
Many articles the 5th leads electrically connect described pin and described patterned line layer respectively, and described the 3rd weld pad is electrically connected to described pin via described the 5th lead, described patterned line layer and described privates.
13. chip-packaging structure as claimed in claim 12 is characterized in that, also comprises:
At least one four-core sheet is disposed at described the 3rd chip below, and exposes described the 3rd weld pad, and described four-core sheet has a plurality of the 4th weld pads; And
Many articles the 6th leads electrically connect described the 4th weld pad and described the 3rd weld pad respectively.
14. chip-packaging structure as claimed in claim 11 is characterized in that, also comprises a fin, is fixed in described second adhesion coating below.
15. chip-packaging structure as claimed in claim 9, it is characterized in that, described first adhesion coating passes described patterned line layer, and part first adhesion coating is between described first chip and described patterned line layer, and part first adhesion coating is positioned at described patterned line layer below.
16. chip-packaging structure as claimed in claim 15 is characterized in that, also comprises:
One the 3rd chip be disposed on first adhesion coating of described patterned line layer below, and described the 3rd chip has a plurality of the 3rd weld pads;
Many privates electrically connect described the 3rd weld pad and described patterned line layer respectively; And
Many articles the 5th leads electrically connect described pin and described patterned line layer respectively, and described the 3rd weld pad is electrically connected to described pin via described the 5th lead, described patterned line layer and described privates.
17. chip-packaging structure as claimed in claim 16 is characterized in that, also comprises:
At least one four-core sheet is disposed at described the 3rd chip top, and exposes described the 3rd weld pad, and described four-core sheet has a plurality of the 4th weld pads; And
Many articles the 6th leads electrically connect described the 4th weld pad and described the 3rd weld pad respectively.
18. chip-packaging structure as claimed in claim 15 is characterized in that, also comprises a fin, is fixed on first adhesion coating of described patterned line layer below.
CN200710101330XA 2007-04-17 2007-04-17 Chip packaging structure Active CN101290918B (en)

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US5367196A (en) * 1992-09-17 1994-11-22 Olin Corporation Molded plastic semiconductor package including an aluminum alloy heat spreader
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US5757070A (en) * 1995-10-24 1998-05-26 Altera Corporation Integrated circuit package
US6900528B2 (en) * 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package

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