CN101288181A - Non-volatile memory device with improved data retention - Google Patents

Non-volatile memory device with improved data retention Download PDF

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CN101288181A
CN101288181A CN 200680037999 CN200680037999A CN101288181A CN 101288181 A CN101288181 A CN 101288181A CN 200680037999 CN200680037999 CN 200680037999 CN 200680037999 A CN200680037999 A CN 200680037999A CN 101288181 A CN101288181 A CN 101288181A
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insulating layer
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semiconductor substrate
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米切尔·斯洛特布姆
纳德尔·阿基勒
罗伯图斯·T·F·范沙耶克
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Nxp股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A non-volatile memory device on a semiconductor substrate comprises a semiconductor base, and a programmable memory transistor comprising a storage stack, a control gate, source and drain regions and a channel in between source and drain. The storage stack comprises a first insulating layer (9) , a trapping layer (10) and a second insulating layer (11) . The first layer is positioned above the channel, the trapping layer above the first layer and the second layer above the trapping layer. Next, the control gate is arranged above the storage stack. The storage stack is arranged for trapping charge in the trapping layer by tunneling of charge carriers from the channel through the first layer which comprises a high-K material. The high-K material has a relatively smaller difference between the barrier height energy for electrons and the barrier height energy for holes in comparison to the difference between the barrier height energies for electrons and for holes in silicon dioxide .

Description

提高了数据保持能力的非易失性存储器 Improving the non-volatile memory data retention capacity

技术领域 FIELD

本发明涉及非易失性存储器。 The present invention relates to a nonvolatile memory. 而且,本发明涉及制造这种非易失性存储器的方法。 Further, the present invention relates to a method of manufacturing such a nonvolatile memory. 而且,本发明涉及至少包括一个这种非易失性存储器的半导体器件。 Further, the present invention relates to a semiconductor device comprising at least one such non-volatile memory.

背景技术 Background technique

预期未来一代的非易失性半导体存储器将使用电荷存储层堆叠,该电荷存储层堆叠由电荷阻挡层组成,该电荷阻挡层位于第一层或底部层和第二层或顶部绝缘层之间。 The nonvolatile semiconductor memory is expected future generations will use the charge storage layer stack, the charge storage layer stack composed of a charge blocking layer, the charge blocking layer between the first layer and a second layer or bottom layer, or top insulating layer. 这种电荷存储层堆叠包括底部二氧化硅层、电荷阻挡氮化硅层和顶部二氧化硅层,这种堆叠还被称 This charge storage layer stack comprises a bottom silicon dioxide layer, a charge blocking layer and a top silicon dioxide layer, also known as such a stack

为0N0堆叠。 0N0 is stacked. 基于这种ONO堆叠的作为电荷存储层的半导体存储器通常被称为S0N0S (半导体-氧化物-氮化物-氧化物-半导体)存储器。 ONO stack on a semiconductor memory such as a charge storage layer is often referred to S0N0S (Semiconductor - oxide - nitride - oxide - semiconductor) memory. 在这些具有0N0层堆叠的非易失性半导体器件中,根据电子从载流沟道通过底部二氧化硅层(隧穿氧化层)直接隧穿(Fowler-Nordheim)到氮化硅层的机制,电荷可以被存储在氮化硅层中。 In the nonvolatile semiconductor device having a layer stack of 0N0, the electronic mechanism of the channel from the carrier bottom silicon dioxide layer (tunneling oxide layer) direct tunneling (Fowler-Nordheim) through the silicon nitride layer, charge may be stored in the silicon nitride layer.

氮化硅层的电荷捕获性质允许降低隧穿氧化层的厚度,这将导致较低的编程电压/擦除电压。 The charge trapping properties of silicon nitride layer allows to reduce the thickness of the tunneling oxide layer, which will result in lower programming voltage / erase voltage.

不利的是,nMOS S0N0S存储器(基于n型沟道)受到读干扰和 Disadvantageously, nMOS S0N0S memory (based on n-channel) interference, and by reading

数据保持质量低的影响。 Data hold low-quality effects.

读干扰与所谓的擦除饱和效应紧密联系在一起。 Read disturb closely linked with the so-called erase saturation effect. 以空穴隧穿通 In the through hole tunneling

过底部绝缘层和隧穿空穴与电荷阻挡层的电子的再结合来完成电荷阻挡层中的电荷(电子)擦除。 And the bottom insulating layer through the tunneling recombination of holes and electrons to complete the charge blocking layer a charge blocking layer charges (electrons) erased. 由于擦除饱和效应,从顶部绝缘层产生了寄生电子电流,并且相对大的电流流经底部和顶部绝缘层,这能使底部和顶部绝缘层损坏。 Since the erase saturation effects, generated from the top of the insulating layer of the parasitic electron current, and a relatively large current flows through the bottom and top insulating layer, which enables the bottom and top insulating layer damage. 在存储器的使用寿命期间,擦除动作会产生在绝缘层中累加的缺陷(所谓的深陷阱)。 During the life of the memory, the erasing operation will have accumulated defects in the insulating layer (a so-called deep traps). 因此,定义了存储器的存储状态或位值(是'(T还是'r ,取决于存储器的实际电压是低于还是高于阈值电压)的存储器阈值电压电平倾向于在器件的使用寿命期间逐步增大。显然,擦除导致的阈值电压变化对于存储器的读取动作具有有害的影响。 Therefore, the definition or the storage state of the memory bit values ​​(a '(T or' r, the actual voltage depends on the memory is below or above the threshold voltage) of the memory threshold voltage level during the lifetime of the device tends to gradually increases. obviously, the erase threshold voltage variation due to having a detrimental effect on the reading operation of the memory.

SONOS存储器的另一个问题涉及数据保持质量。 Another problem relates to a SONOS memory holding data quality. 为了将电荷保持 In order to maintain the charge

在电荷存储层中,绝缘层的能量势垒应该足够高以将电荷保持在电荷 In the charge storage layer, the insulating layer should be high enough energy barrier to charge retention in the charge

阻挡层中较长时期。 The barrier layer a longer period. 然而,在具有二氧化硅绝缘层的SONOS存储器中, However, in SONOS memory having a silicon dioxide insulating layer,

由于有效编程/擦除动作的原因,底部层的厚度被严格限制在大约 Due to the effective program / erase operation, the thickness of the bottom layer is strictly limited to about

2nm。 2nm. 由于底部绝缘层厚度小,所以电荷保持不理想。 Due to the small thickness of the bottom insulating layer, so that the charge remains over. 因此,为了改进所述保持,在设计阶段,理想的是定义相对较厚的底部二氧化硅层, 但是到达/从电荷阻挡层的电荷迁移仍然取决于直接隧穿机制。 Therefore, to improve the retention at the design stage, it is desirable that the definition of the bottom of a relatively thick layer of silicon dioxide, but to / charge transport layer is a charge blocking still depends directly from the tunneling mechanism. 然而, 如果增大了SONOS存储器中的底部二氧化硅层,虽可以观察到仍然可以编程,但是由于擦除是基于空穴(而不是电子)迁移穿过底部绝缘层并且空穴隧穿的势垒高度大于电子的隧穿势垒高度的事实,擦除实质上变为不可能。 However, if the bottom silicon dioxide layer is increased SONOS memory, though the programming can still be observed, but since the erasure was based holes (rather than electrons) migrate through the insulating layer and the bottom hole tunneling potential electron tunneling barrier height greater than the height of the tunneling barrier fact, becomes virtually impossible to erase.

本发明的目的是改进读干扰和数据保持问题。 Object of the present invention is to improve data retention and read disturbance problem.

发明内容 SUMMARY

本发明涉及在半导体基板上的非易失性存储器,该存储器包括半导体基层和至少一个可编程存储晶体管, The present invention relates to a semiconductor substrate on a nonvolatile memory, the memory comprising a semiconductor base layer and at least a programmable memory transistor,

所述可编程存储晶体管包括电荷存储层堆叠和控制栅; The programmable memory transistor includes a charge storage layer and a control gate stacked;

所述半导体基层包括源区和漏区,以及被定位在源区和漏区之间的载流沟道区; The semiconductor base layer includes a source region and a drain region, and is positioned between the source and drain regions of the current carrying channel region;

所述电荷存储层堆叠包括第一绝缘层、电荷阻挡层和第二绝缘层,第一绝缘层被定位在载流沟道区上,电荷阻挡层在第一绝缘层上以及第二绝缘层在电荷阻挡层上; The charge storage layer stack comprises a first insulating layer, a charge blocking layer and the second insulating layer, a first insulating layer is positioned on a current carrying channel region, a charge blocking layer on the first insulating layer and the second insulating layer charge blocking layer;

所述控制栅被定位在电荷存储层堆叠上; The control gate is positioned on the charge storage layer stack;

所述电荷存储层堆叠布置来用于通过来自载流沟道区的电荷载流子的直接隧穿通过第一绝缘层来在电荷阻挡层中捕获电荷,其中第一绝缘层包括高K材料,与二氧化硅中的电子势垒高度和空穴势垒高度之间的能级差相比,该材料具有相对较小的电子势垒高度和空穴势垒高度之间的能级差。 The charge storage layer stack to be arranged through the direct tunneling of carriers from the channel region of charge carriers through the first insulating layer by trapped charge in the charge blocking layer, wherein the first insulating layer comprises a high-K material, and the electron barrier height and a hole silica barrier height of the energy difference between the comparison, the material having a relatively small electron barrier height and the height of the potential barrier between the hole energy level difference. 有利的是,本发明允许使用相对较厚的底部绝缘层,这提高了电荷阻挡层中的电荷保持能力。 Advantageously, the present invention allows the use of relatively thick bottom insulating layer, the charge blocking layer which improves the charge retention capability. 同时,由于空穴隧穿的势垒高度的能级降低了,通过空穴隧穿通过较厚的底部绝缘层的机制来擦除存储在电荷阻挡层中的电荷的能力可以得到保持。 Meanwhile, since the level of the hole tunneling barrier height is reduced by hole tunneling to erase the charge stored in the charge capacity of the barrier layer can be maintained by mechanisms thicker bottom insulating layer. 这允许使用较低的读取电压,并且因此降低了读干扰影响。 This allows lower read voltage, and therefore reduces the read disturbance. 而且,本发明涉及在半导体基板上制造非易失性存储器的方法, 如上所述,该非易失性存储器包括半导体基层和至少一个可编程存储晶体管,其中该方法包括-淀积作为第一绝缘层(9)的高K材料,与二氧化硅中的电子和空穴的势垒高度相比,该高K材料具有相对改进的电子势垒高度和空穴势垒高度的对称性。 Further, the present invention relates to a method of manufacturing a nonvolatile memory on a semiconductor substrate, as described above, the nonvolatile memory includes a semiconductor base layer and at least a programmable memory transistor, wherein the method comprises - depositing a first insulating high-K material layer (9), as compared with the height of the potential barrier of electrons and holes in silicon dioxide, which is a relatively high-K material having improved electron barrier height and the hole barrier height symmetry. 而且,本发明涉及至少包括一个如上所述的非易失性存储器的存储阵列。 Further, the present invention relates to a memory array comprising at least a non-volatile memory as described above. 而且,本发明涉及至少包括一个如上所述的非易失性存储器的半导体器件。 Further, the present invention relates to a semiconductor device comprising at least a non-volatile memory as described above. 附图说明为了讲授本发明,下面描述了本发明的方法和器件的实施例。 In order that the teachings of the present invention, the following describes an embodiment of the method and device of the present invention. 所属领域的技术人员应该理解的是,在不脱离本发明真实精神的情况下,可以设想和实施本发明其它可替换的和等价的实施例,本发明的范围仅由所附的权利要求所限制。 Those skilled in the art will appreciate that, without departing from the true spirit of the invention, it is contemplated that other embodiments and alternative embodiments of the present invention and equivalent embodiments, the scope of the present invention is defined only by the appended claims of the limit. 图1示意示出了包括电荷层堆叠的非易失性存储器的实施例; 图2示意示出了现有技术的SONOS存储器的能量势垒图; 图3示意示出了本发明的SONOS存储器的能量势垒图; 图4示出了作为保持时间的函数的归一化阈值电压窗; 图5示出了增强型晶体管S0N0S存储器的耐久性。 FIG 1 schematically illustrates an embodiment of a nonvolatile memory comprising a charge generation layer stacked; energy FIG 2 schematically illustrates a prior art SONOS memory barrier; Figure 3 schematically illustrates a SONOS memory of the present invention energy barrier; Figure 4 shows a retention time as a function of normalized threshold voltage window; FIG. 5 illustrates durability enhancement transistor S0N0S memory. 具体实施方式图1示意示出包括电荷层堆叠的非易失性存储器的实施例。 DETAILED DESCRIPTION Figure 1 schematically shows an embodiment of a nonvolatile memory comprising a charge generation layer stacked.

作为示例示出的非易失性存储器实施例是在半导体基板2上的平面双晶体管结构1,晶体管结构1包括存取晶体管Tl和可编程存储晶体管T2。 Example nonvolatile memory is shown as an example of a double planar transistor structure on a semiconductor substrate 2, a transistor structure includes an access transistor Tl and programmable memory transistor T2.

存取晶体管Tl包括第一源/漏区3a、第二源/漏区3b、存取栅AG 4和间隔5。 Access transistor Tl comprises a first source / drain region 3a, a second source / drain region 3b, the access gate AG 4 and the spacer 5. 存取栅AG 4被定义为与第一和第二源/漏区3a、 3b 之间的沟道区Cl重叠。 Access gate AG 4 is defined as a first and a second source / drain regions 3a, 3b of the channel region between the overlapping Cl. 间隔5被定义为覆盖存取栅材料4的侧壁。 5 is defined as the interval of the access gate sidewall cover material 4. 应当注意的是,关于本发明,存取晶体管、其详细特性、和与可编程存取晶体管T2有关的配置仅作为非限制性示例示出,与本发明无关, 将不再给予进一步的描述。 It should be noted that, with regard to the present invention, an access transistor, the detailed properties, T2 configuration related to only access transistor and a programmable non-limiting example shown, irrelevant to the present invention, further description will not be given.

可编程存储晶体管T2包括控制栅CG、第二源/漏区3b和第三源/漏区3c。 Programmable memory transistor T2 includes a control gate CG, a second source / drain region 3b and the third source / drain region 3c. 控制栅CG被定义为与第二源/漏区3b和第三源/漏区3c 之间的第二沟道区C2重叠。 Control gate CG is defined as a channel region between the second and 3c a second source / drain region 3b and the third source / drain region C2 overlap. 控制栅CG包括电荷存储层堆叠CT和栅材料6。 The control gate CG includes a charge storage layer stack CT and the gate material 6. 另外,控制栅CG可以包括在栅材料6之上的接触层7。 Further, the control gate CG may include a contact layer over the gate material 6 7. 间隔8覆盖控制栅CG的侧壁。 8 covers the sidewall spacer control gates CG's. 例如,栅材料6可以是(掺杂)多晶硅。 For example, 6 may be a gate material (doped) polycrystalline silicon. 例如,接触层7可以是(掺杂)多晶硅、硅化物化合物或金属。 For example, the contact layer 7 may be (doped) polysilicon, a silicide or a metal compound.

电荷存储层堆叠CT包括底部绝缘层9、电荷阻挡层10和顶部绝缘层11。 The charge storage layer stack CT 9 comprises a bottom insulating layer, the charge blocking layer 10 and the insulating layer 11.

在相关技术中,电荷存储层CT包括作为底部绝缘层9的二氧化硅层、作为电荷阻挡层10的氮化硅层和作为顶部绝缘层11的二氧化硅层,这种结构还已知为0N0堆叠。 In the related art, the charge storage layer includes a CT bottom insulating layer of silicon dioxide layer 9, as a charge blocking layer and the silicon nitride layer as a top layer 11 of silicon dioxide insulating layer 10, this structure is also known as 0N0 stack. 因此,基于这种0N0堆叠的半导体存储器被已知为S0N0S非易失性存储器。 Thus, based on such a semiconductor memory it is known as a stack 0N0 S0N0S nonvolatile memory.

图2示意示出了现有技术的SONOS存储器的能量势垒图。 FIG 2 schematically illustrates a prior art SONOS memory barrier energy FIG.

在该图中,在水平方向上,将第二沟道区C2和电荷存储层堆叠CT中的每层9、 10、 11的位置表示为垂直条。 In this drawing, in the horizontal direction, the second channel region C2 and the charge storage layer stack each position 9, 10, 11, CT represented as vertical bars. 在垂直方向上,示意地描述了能级。 In the vertical direction, the energy level is schematically described. 示出了导带水平bl和价带水平b2。 It shows a conduction band level and the valence band level bl b2. 每条的高度表示堆叠9、 10、 11中的对应层的相对能级,每条的宽度表示各个层的厚度。 9 represents the height of each stack, the relative level of the corresponding layers 10, 11, represents a width of each of the thickness of each layer. 向上箭头表示电子的势垒高度(关于bl),向下箭头表示空穴的势垒高度(关于b2)。 Up arrow indicates the electron barrier height (about bl), the down arrow indicates the barrier height of the hole (about b2).

在S0N0S存储器1的0N0堆叠9、 10、 11中,对于从第二沟道区C2隧穿通过底部二氧化硅层9到氮化硅电荷阻挡层10的电子来说,势垒高度大约是3. leV。 In S0N0S 0N0 stack memory 9, 10, 111, for the tunnel from the second channel region C2 through the bottom silicon dioxide layer 9 by an electron to the charge blocking layer 10 of silicon nitride, the barrier height is approximately 3 . leV. 对于空穴来说,势垒高度在4和5eV之间,典型地大约为4.8eV。 For the hole, the barrier height between 4 and of 5 eV, typically about 4.8eV. 由于顶部绝缘层还包括二氧化硅层11,所以势垒高度基本上与底部二氧化硅层9的势垒高度相同。 Since the top insulating layer further comprises a silicon dioxide layer 11, the barrier height of the barrier is substantially the bottom silicon dioxide layer 9 of the same height. 显然,(氮化硅)电荷阻挡层10的能级将分别略小于底部绝缘层9和顶部绝缘层11的能级,以避免从电荷阻挡层11的(自发)的泄漏。 Obviously, the (silicon nitride) energy level of the charge blocking layer 10 are slightly smaller than the level of the bottom insulating layer 9 and a top insulating layer 11, layer 11 to avoid leakage (spontaneous) from the charge blocking. 如上所述,底部二氧化硅层9的厚度分别是电子和空穴在编程性能和擦除性能之间的折衷,不能实现最佳的电荷保持。 As described above, thickness of the bottom silicon dioxide layer 9, electrons and holes are trade-off between performance and the erasing performance of the programming, not the best charge retention. 通过增加底部二氧化硅层9的厚度,可以提高现有技术的SONOS存储器的可靠性(即更好的保持)。 By increasing the thickness of the bottom silicon dioxide layer 9, the SONOS memory can improve the reliability of the prior art (i.e., better retention). 例如,在现有技术的SONOS存储器中,典型地,底部二氧化硅层9的厚度是2.0nm。 For example, in the prior art SONOS memory, typically has a thickness, a bottom silicon dioxide layer 9 is 2.0nm. 为了提升数据保持能力,希望将氧化层厚度提高至3.0nra。 To enhance data retention, it is desirable to increase the thickness of the oxide layer to 3.0nra. 然而,这将相对严重地影响利用空穴隧穿的擦除行为, 而由于电子和空穴的势垒高度水平的不对称性,所以利用电子隧穿的编程仅受到轻微影响。 However, this would seriously affect the use of relatively erase hole tunneling behavior, and because of the asymmetry of the electron and hole barrier height levels, so the use of electron tunneling programming only slightly affected. 在此认为,减小电子的势垒高度和空穴的势垒高度之间的不对称性,将允许在较厚的底部绝缘层上的编程和擦除。 In that, the asymmetry between the electron barrier height is reduced and the barrier height of the hole, to allow programming and erasing on a thicker bottom insulating layer. 图3示意示出了本发明的SONOS存储器的能量势垒图。 FIG 3 schematically illustrates a SONOS memory of the present invention, an energy barrier of FIG. 在本发明中,高K材料至少代替了底部二氧化硅层,以下将对此进行详细描述。 In the present invention, a high-K material in place of at least the bottom silicon dioxide layer, will be described in detail. 与二氧化硅中的电子和空穴的势垒高度相比,选择至少用于底部层的高K材料,该材料具有相对改进的电子和空穴的势垒高度的对称性,或者,换句话说,选择高K材料以获得其高度差比二氧化硅中的电子和空穴的势垒高度差要小的电子隧穿势垒高度和空穴隧穿势垒高度,比如小于30%或更小。 Compared with the height of the potential barrier of electrons and holes in silicon dioxide, the high-K material selected for at least the bottom layer, the material having a relatively high degree of symmetry of the improved barrier of electrons and holes, or, in other sentences words, select the high-K material in order to obtain a difference in height than the barrier of electrons and holes in silicon dioxide height difference is smaller electron tunneling barrier height and the hole tunneling barrier height, such as less than 30% or more small. 作为改进的势垒高度对称性的结果, 通过允许增加底部高K层厚度,有利地提升了数据保持能力,而同时, 由于相对较低的空穴势垒高度,还能进行电荷擦除。 Improved barrier height as a result of the symmetry, by allowing for increased thickness of the bottom high-K layer, advantageously improves data retention, while, due to the relatively low barrier height of the hole, but also for charge erasing. 应当注意的是,为了避免电荷从电荷阻挡层11泄漏,选择的高K材料不应该呈现出太低的电子势垒高度。 It should be noted that, in order to avoid leakage of charge from the charge blocking layer 11, the high-K material chosen should exhibit low electron barrier height. 而且,这种高K材料可以被选择为具有相对宽泛的组成成分范围,这将允许根据组成成分来变化和/或调整高K材料相关属性(例如,物理的、化学的或电子的属性)。 Moreover, such a high-K material may be selected to have a relatively wide composition range, which will allow to change and / or adjustment related to high-K material properties (e.g., physical, chemical or electronic properties) depending on the composition ingredients. 在一个实施利中,电荷存储层堆叠的底部绝缘层9包含硅酸铪。 In one embodiment of interest, the charge storage layer stack comprises a bottom insulating layer 9 hafnium silicate. 应当注意的是,硅酸铪化合物可以具有化学计量构成(HfSi04)或非化学计量构成(表示为:HfSiO)。 It should be noted that the hafnium silicate compound may have a stoichiometric configuration (HfSi04) or non-stoichiometric configuration (represented as: HfSiO). 为了明确起见,在下文中将这两种构成都表示为化学计量化合物。 For clarity, hereinafter denoted as these two are configured stoichiometric compound. 可通过HfSiO化合物的硅含量来改变和调整这种HfSiO化合物的电子或空穴的势垒高度大小。 And may be varied to adjust the height of the potential barrier of electrons or holes of such size HfSiO compound by a silicon content of HfSiO compound. 在另一个实施利中,高K材料是氮化硅酸铪HfSi04 (N),通过采用氮来修饰高K材料中的缺陷,这种材料可以改进底部绝缘层9 的质量(即,物理/化学稳定性)。 In another embodiment of interest, the high-K material is nitrided hafnium silicate HfSi04 (N), is modified by using a nitrogen defects in the high-K material, such materials can improve the quality of the bottom insulating layer 9 (i.e., physical / chemical stability). 而且,可以观察到,HfSi04层的氮化进一步有利地降低了空穴隧穿的势垒高度,使其更接近电子隧穿的势垒高度水平,这使电子和针对空穴的势垒高度更加对称。 Further, it can be observed HfSi04 nitride layer is further advantageously reduces the hole tunneling barrier height, so that it is closer to the level of the barrier height of the tunneling electrons, which electrons and the barrier height for holes is more symmetry. 而且, 应当注意的是,氮化硅酸铪化合物可以具有化学计量构成或非化学计量构成。 Moreover, it should be noted that, nitrided hafnium silicate compound may have a stoichiometric or non-stoichiometric configuration configured. 在下文将这两种构成都表示为化学计量化合物。 In these two are configured hereinafter expressed as stoichiometric compounds. 更具体地说,通过改变Si含量为大约x=0. 77的硅酸铪中的Si 含量,在Hf卜xSi力2 (0《x《l)中,电子的势垒高度介于大约2.5和大约3. leV之间,空穴的势垒高度介于大约3. 0和大约3.6eV之间。 More specifically, about x = Si content of the hafnium silicate 0.77 by varying the Si content is, of Hf xSi force Bu 2 (0 "x" l), the electron barrier height between about 2.5 and between about 3. leV, the hole barrier height between about 3.0 and about 3.6eV. (注意,HfhSi力2表示具有可变Si含量的计量化合物;在本发明中具有可变Si含量的这种化合物还可以是非计量的)。 (Note that, HfhSi 2 represents a variable force stoichiometric compounds having the Si content; having a variable Si content of such compounds may also be of non-metered in the present invention). 如果(氮化)硅酸铪化合物的Si含量较低,则电子的势垒高度将变得较低,而空穴的势垒高度将变得较高。 If the Si content (nitrided) Hafnium silicate compound is low, the electron barrier height becomes low, the barrier height of the hole becomes higher. 这种HfhSi力2层(硅含量x"O. 77)的K值大约是K"6 (二氧化硅:K«^4)。 Such HfhSi force layer 2 (silicon content x ". O 77) about the value of K K" 6 (Silica: K «^ 4). 应当注意的是,在使用过程中,为了保证电位主要被限制在跨越底部(氮化)硅酸铪绝缘层,顶部绝缘层ll应该具有相似K值或较大K值。 It should be noted that, during use, is restricted in order to ensure the potential across the bottom of the main (nitrided) Hafnium silicate insulating layer, a top insulating layer ll should have similar K values ​​K value or larger. 因此,在本发明的S0N0S存储器中,顶部绝缘层11可以由高K 材料组成,该高K材料的K值大于底部绝缘层9的K值。 Thus, in the present invention, the memory S0N0S, the top insulating layer 11 may be formed of a high K material, the high-K material K value greater than the K value of the bottom insulating layer 9. 在一个实施利中,顶部高K材料是Si含量为x"0.47的HfhSi力2。这种化合物的K值大约是12。而且,顶部高K材料可以是氮化的。例如,包括具有高K绝缘层的电荷存储层堆叠的SONOS存储器可以包括底部HfnSiA (N)层9和电荷阻挡氮化硅层10,底部HfhSiA (N)层的硅含量介于x"O. 60和x"O. 90之间,并且厚度介于大约2至大约6rnn之间,电荷阻挡氮化硅层10的厚度介于大约4至10nm之间。顶部绝缘层11可以是HfhSix02 (N)层,该层的K 值等于或高于底部高K层的K值,以及该层的厚度大于底部高K层的厚度。对于顶部绝缘层11,还可以使用其它高K材料,例如Zr02和它的硅酸盐、跳、Ta205、 A1A、 HfxAlyOz和X-Sc03 (其中X是Gd、 Dy或La)。应当注意的是,选择的高K材料的势垒高度不可以太低,以便避免电荷的泄漏。作为使用诸如Hf。.23Si。.7702 (N)之类的高K材料的结果,与现有技术的二氧化硅层(K«^4)相比 In one embodiment of interest, the top high-K material is Si content x "HfhSi force 2. This compound K value of 0.47 is approximately 12. Further, the top high-K material may be a nitride of, for example, comprise a high K the insulating layer of the charge storage layer stack SONOS memory may comprise a bottom HfnSiA (N) and a charge blocking layer 9 of silicon nitride layer 10, a bottom silicon content HfhSiA (N) layer is interposed between x "O. 60 and x" O. 90 between, and a thickness of between about 2 to about 6rnn, the thickness of the charge blocking layer 10 of silicon nitride is between about 4 to 10nm. top of the insulating layer 11 may be HfhSix02 (N) layer, which is the value of K equal to or above the high-K layer on the bottom of the K value, and the thickness of the layer is greater than the thickness of the bottom high-K layer for insulating top layer 11, also other high-K material, e.g. Zr02 and its silicate, jump, Ta205, A1A, HfxAlyOz and X-Sc03 (wherein X is Gd, Dy or La). It should be noted that the high-K material barrier height can not be selected too low, in order to avoid leakage of charge. Hf used as such .. the results of the high-K material 23Si..7702 (N) or the like, with the prior art silicon dioxide layer (K ​​«^ 4) as compared to 在给定的施加电位下,跨越Hf。.23Si。.7702 (N)底部层9的电场比跨越具有相同厚度的二氧化硅层的电场小。因此,本发明的SONOS存储器的隧道电流较小。但是,与具有相同厚度的二氧化硅层的势垒高度相比,由于尤其是空穴势垒高度的相对大的减小,擦除效率提高将导致HfSi04 (N)层的阈值电压(VT)窗比二氧化硅层的阈值电压(VT)窗相对高。在这里定义的阈值电压窗是编程电压Vp和擦除电压Vs的差。较大VT窗可以被用来增加底部绝缘HfhSix02 (N)层的厚度和改进电荷阻挡层的保持。图4示出了作为保持时间的函数的归一化阈值电压窗。在图4中,对具有2. 2nm二氧化硅底部层9的S0N0S存储器和具有4. Onm (氮化)肚。.233:1。.7702的SONOS存储器进行比较。在水平方向上绘制了保持时间。在垂直方向上,绘制了归一化的阈值电压窗口△ VT。对于每种S0N0S存储器(无论是二氧化硅 Hours at a given applied potential, the electric field across Hf..23Si..7702 (N) than the bottom layer 9 having the same thickness across the field layer of silicon dioxide. Thus, tunneling current SONOS memory of the present invention is small However, compared with the barrier height of the silicon oxide layer having the same thickness, especially since a relatively large hole barrier height is reduced, erase efficiency will result in threshold voltage HfSi04 (N) layer (VT ) window window relatively higher than the threshold voltage (VT) of the silicon dioxide layer. threshold voltage window defined herein is the difference between the programming voltage Vp and the voltage Vs is erased. VT larger window may be used to increase the bottom insulating HfhSix02 (N ) thickness of the layer and improve the charge blocking layer is maintained. FIG. 4 shows a retention time as a function of normalized threshold voltage window. in FIG. 4, the silica having a bottom layer 2. 2nm memory 9 and S0N0S with 4. Onm (nitride) belly ..233:... SONOS memory 1..7702 comparing the retention time is plotted in the horizontal direction in the vertical direction, rendering the normalized threshold voltage window for △ VT each S0N0S memory (either silica 还是HfSi0作为底部绝缘层9),相对于初始VT窗值对VT窗进行归一化处理。对于具有二氧化硅层9的S0N0S存储器,AVT被绘制为虚曲线。 对于基于硅酸铪的S0N0S存储器,AVT被绘制为实曲线。将两条曲线外推至IO年的保持时间,并将外推结果绘制为点划线。如图4所示,对于每种类型的SONOS存储器,AVT随时间变化逐渐减小。 Or HfSi0 as a bottom insulating layer 9), relative to the initial value of the VT VT window normalized window processing for S0N0S memory having a silica layer 9, the AVT is plotted as a dashed curve. S0N0S hafnium silicate-based memory for , the AVT is plotted as a solid curve. the curve is extrapolated to the two outer holding time of IO, and extrapolating the results plotted as dashed-dotted line shown in Figure 4, for each type SONOS memory, over time the AVT slowing shrieking. 外推的十年的保持给出了结果窗:二氧化硅层9为45%, Hf。 Decade extrapolated results are given in the window maintained: silicon dioxide layer 9 is 45%, Hf. .23Si。 .23Si. .7702 层9为75%。 .7702 layer 9 was 75%.

图5示出了增强型晶体管SONOS存储器的耐久性。 Figure 5 illustrates the durability of the enhancement-type transistor SONOS memory.

在图5中,示出了具有4. 0nm Hf。 In FIG. 5, is shown having 4. 0nm Hf. .23Si。 .23Si. 7702底部电介质层9的S0N0S存储器的耐久性测量结果。 Durability measurements S0N0S memory 7702 of the bottom dielectric layer 9. SONOS存储器是增强型晶体管,即在栅压为OV时,器件的漏极电流为零;该器件处于截至状态。 SONOS memory enhancement mode transistor, i.e., when the gate voltage of the OV, the drain current of the device is zero; the devices in the off state.

在图5中,编程的阈值电压Vtp和擦除的阈值电压Vts被描述为编程/擦除循环PE数量的函数。 In FIG. 5, the programmed threshold voltage Vtp and the erased threshold voltage Vts is described as a program / erase cycle number of PE function. 对于0.5ms的编程时间,编程电压Vp的大小是12V。 0.5ms for the programming time, the magnitude of the programming voltage Vp is 12V. 对于0. 5ms的擦除时间,擦除电压^的大小是-13V。 0. 5ms for the erase time, the erase voltage magnitude ^ is -13V. 如所示,编程的阈值电压Vtp大约是5V,擦除的阈值电压Vts大约是2. 5V,如此,将需要使用大约3. 5V的高读取电压。 As shown, the programmed threshold voltage Vtp is approximately 5V, erased threshold voltage Vts is about 2. 5V, thus, would require the use of high read voltage of about 3. 5V.

请注意,在很多具有如图5所示条件的应用中,可以应用升压电路来获得大约3.5V的读取电压。 Note that in many applications with the conditions shown in FIG. 5, the booster circuit may be applied to obtain a read voltage of about 3.5V. 尤其对于低功率应用,这将是不利的。 Especially for low-power applications, it would be disadvantageous.

如图5所示,由于所述的擦除饱和效应,编程的阈值电压Vtp和擦除的阈值电压Vt6随着编程/擦除循环数量逐步地增加。 5, since the erase saturation effects, the programmed threshold voltage Vtp and the erased threshold voltage Vt6 with program / erase cycle number increased stepwise. 然而,VT 窗从大约2.5V逐步地变为大约1.8V (大约为72%)。 However, VT window from gradually becomes about 2.5V to about 1.8V (approximately 72%). 可以观察出, 对于大约1E6 ( —百万)PE循环,由于擦除的阈值电压Vtp和读取电压之间的差减小,所以出现了读困难。 Can be observed, for about 1E6 (- one million) PE cycle, due to the difference between the erase threshold voltage Vtp and the read voltage is reduced, so there are difficulties to read. 实际上,这个条件表示该器件寿命结束。 Indeed, this condition indicates the end of the lifetime of the device.

概括地说,关于图5,具有4. 0nm Hf。 In summary, with respect to FIG. 5, with 4. 0nm Hf. .23Si。 .23Si. .7702底部绝缘层9的增强型SONOS存储器示出了重大改进的保持。 .7702 bottom insulating layer is enhanced SONOS memory 9 shows a significant improvement in retention. 然而,虽然被改进了, 但是仍然存在读干扰(擦除饱和)的问题。 However, although improved, but there are still reading interference (erase saturation) of.

为了更加完全地克服读干扰,采用基于耗尽型晶体管的SONOS 存储器,该晶体管允许栅压为OV时的非零漏极电流的存在。 For a more complete reading overcome interference, based SONOS memory depletion type transistor, the transistor allows a non-zero drain current when gate voltage is OV.

有利的是,在耗尽型晶体管中,编程的阈值电压Vtp和擦除的阈值电压Vts都比较低,因此VT窗的上边界和下边界都将转移至较小值。 Advantageously, in the depletion type transistor, the programmed threshold voltages Vtp and the erased threshold voltage Vts are low, so the window and lower boundaries of the VT will be transferred to a smaller value.

而且,可以显著降低读电压。 Further, the read voltage can be significantly reduced. 原理上,读电压可以是0V。 In principle, the read voltage can be 0V. 出于实际原因,可以使用大约IV的读电压,这几乎不会产生任何读干扰。 For practical reasons, you can use a read voltage of about IV, which is almost does not read any interference. 而且,在65nm以及更小的一代的器件中,不需要升压电路来产生这个电压。 Further, in the 65nm generation and smaller devices, it does not need to generate the voltage boosting circuit. 对于低功率应用,省略升压电路可以显著提高在这种应用中的能源节约。 For low power applications, a booster circuit is omitted in this can significantly improve the application of energy conservation. 而且,应该注意,与应用二氧化硅底部电介质层9相比,由于在底部电介质层9和半导体沟道区C2之间的界面阱的不完全钝化, 应用高K底部电介质层9将导致较低的载流子迁移率。 Further, it should be noted that, as compared with Silica bottom dielectric layer 9, since the interface between the well bottom dielectric layer 9 and the semiconductor channel region C2 is not completely deactivated, the application of high K dielectric layer 9 at the bottom will result in a more low carrier mobility. 然而,耗尽型S0N0S存储器包括掩埋沟道区C2,在其中,在底部电介质层9和半导体基板2之间的界面的界面态上的载流子散射被大大降低。 However, the memory comprises a depletion-type buried channel region S0N0S C2, in which the carrier at the interface state of the interface between the bottom dielectric layer 2 and the semiconductor substrate 9 of scattering is greatly reduced. 实际上, 与增强型S0N0S存储器的迁移率相比,可以增大耗尽型S0N0S存储器的迁移率。 In fact, compared with the mobility enhanced S0N0S memory can be increased mobility of the depletion type S0N0S memory. 在耗尽型S0N0S存储器中,可以观察到由于耗尽型S0N0S存储器中的较高迁移率,与增强型器件相比,其最大跨导较高。 S0N0S depletion type memory, can be observed due to the higher mobility S0N0S depletion type memory, as compared with the enhancement-mode device, the higher the maximum transconductance. 通常,在增强型器件中,如果用例如高K材料的另一种电介质来代替Si02底部电介质,可以观察到迁移率将严重降低。 Typically, the enhancement devices, such as another if the high-K dielectric material instead of a bottom dielectric Si02, observed mobility severely reduced. 然而,在耗尽型器件中,这种替换将导致相对较高的读电流。 However, the depletion mode device, this replacement will lead to a relatively high read current. 因此,根据本发明的S0N0S存储器可以实施为被创造为耗尽型晶体管的可编程存储晶体管T2。 Thus, according to the present invention S0N0S memory may be implemented as a programmable memory transistor T2 is created as a depletion type transistor. 在根据本发明的S0N0S存储器中,可以通过以下方法制造电荷存储层堆叠CT,这种方法被视为制造这种非易失性存储器的非限制性示例。 S0N0S memory in accordance with the present invention, the charge storage layer stack may be manufactured by CT method, which is regarded as non-limiting examples of manufacturing such a nonvolatile memory. 提供了半导体基板2。 The semiconductor substrate 2 is provided. 在半导体基板2上,定义了有效区域(包括C2)。 2 on the semiconductor substrate, the active region is defined (including C2). 注意,有效区域C2和基板2的特征使可编程存储晶体管T2 为耗尽型晶体管。 Note, wherein the effective area C2 and the substrate 2 causes the programmable memory transistor T2 is in a depletion mode transistor. 接下来,以覆盖方式,淀积底部高K电介质9Hf卜xSix02层。 Next, the cover, the bottom electrically deposited high-K dielectric layer 9Hf Bu xSix02. 淀积技术例如可以是MOCVD (金属有机化学汽相淀积)或ALD (原子层淀积)。 Deposition techniques, for example, may be a MOCVD (metal organic chemical vapor deposition) or ALD (atomic layer deposition). HfnSi力2 (N)的组成成分是可控的,从而使硅含量x介于大约0.6和大约0.9之间。 HfnSi force components 2 (N) is controlled so that the silicon content x is between about 0.6 and about 0.9. 该层厚度可以介于大约2和大约6nm之间。 The layer thickness may be between about 2 and about 6nm. 然后,执行退火步骤,而同时将氮提供给高K层HfhSiA以形成氮化高K层HfhSix02 (N)。 Then, an annealing step while nitrogen is supplied to the high-K to form a nitride layer HfhSiA high-K layer HfhSix02 (N). 通过任何可以想象到的前驱体(例如,供应NH。供应氮。退火温度介于大约600。C和大约90(TC之间。 By any conceivable precursor (e.g., supplying NH. Nitrogen supply. Annealing temperature is between about 90 and about 600.C (between the TC.

随后,通过所属领域中任何适合的已知方法,例如通过CVD工艺或PVD工艺来淀积通常包括氮化硅的电荷阻挡层10。 Subsequently, by any method known in the art suitable, for example, typically comprises silicon nitride deposited by a CVD process or a charge blocking layer 10 PVD process. 电荷阻挡层10的厚度介于大约4nm和大约10nm之间。 The thickness of the charge blocking layer 10 is between about 4nm and about 10nm. 可替换地,在这里可以应用另外的电荷阻挡层材料,例如硅纳米晶或高K材料层。 Alternatively, where applicable additional charge blocking layer materials, such as silicon nanocrystals or a high-K material layer.

然后,淀积顶部绝缘层11。 Then, the insulating layer 11 is deposited on top. 顶部层11由例如还是HfhSL02 (N) 的另一种高K材料组成。 The top layer 11 such as another high-K material or HfhSL02 (N) of the composition. 顶部层11的厚度至少等于或大约底部高K 层9的厚度,这取决于与底部高K电介质层9的K值相比较的顶部电介质层11的K值。 Thickness of the top layer 11 or at least about equal to the thickness of the bottom high-K layer 9, depending on the K value of the top dielectric layer and the K value at the bottom high-K dielectric layer 9 compared to 11. 在Hf卜xSix02 (N)的情况下,以与底部HfnSi力2 (N)电介质层9类似的方式淀积该层。 In the case of Hf Bu xSix02 (N) of force to the bottom HfnSi 2 (N) dielectric layer 9 in a similar manner as the deposition layer. 可替换地,可以使用其它高K材料,例如Zr02和它的硅酸盐、Hf02、 Ta205、 A1203、 Hf,AlyOz和X-Sc03 (其中x是Gd、 Dy或La)。 Alternatively, other high-K material, for example, and its silicate Zr02, Hf02, Ta205, A1203, Hf, AlyOz and X-Sc03 (where x is Gd, Dy or La).

在进一步的步骤中,通过所属领域已知的方法淀积用来形成控制栅材料6的覆盖多晶硅层。 In a further step, the methods known to the art for forming a control gate material is deposited to cover the polysilicon layer 6. 可替换地,控制栅材料可以包括像金属硅化物的金属互化物,金属硅化物例如包括作为金属的钛、钽或钴, 或诸如TiN或TaN之类的金属化合物。 Alternatively, the control gate as a metal material may comprise a metal silicide intermetallic compound, the metal silicide comprising a metal, for example, titanium, tantalum, or cobalt, or a metal compound such as TiN or TaN or the like.

接下来,可以提供覆盖金属层作为接触层7。 Subsequently, a metal covering layer may be provided as a contact layer 7.

然后,通过合适的光刻处理对覆盖层形成图案来形成可编程存储晶体管T2的主体。 Then, the body is formed of a programmable memory transistor T2 is formed by an appropriate coating layer to patterned photolithography process. 另外,在可编程存储晶体管T2的主体侧壁上形成间隔8。 Further, 8 formed in the body sidewall spacer programmable memory transistor T2.

而且,如所属领域的技术人员已知,可以形成源/漏区,以及在后端处理的过程中,淀积钝化层以覆盖晶体管结构1,创建与源/漏区和与存取和控制栅的触点,通过某些金属化工艺提供互连布线。 Further, as known to the skilled person, may be formed in the source / drain region, and during the back-end processing, a passivation layer is deposited to cover the transistor structure 1, to create the source / drain region and the access control and the gate contact is provided by certain metal interconnect routing process.

Claims (20)

1. 一种在半导体基板上的非易失性存储器(1),其包括半导体基层(2)和至少一个可编程存储晶体管(T2), 所述可编程存储晶体管(T2)包括电荷存储层堆叠(CT)和控制栅(6;6、7); 所述半导体基层(2)包括源区和漏区(3b、3c)以及被定位在所述源区和漏区(3b、3c)中间的载流沟道区(C2); 所述电荷存储层堆叠(CT)包括第一绝缘层(9)、电荷阻挡层(10)和第二绝缘层(11),所述第一绝缘层(9)被定位在所述载流沟道区(C2)上,所述电荷阻挡层(10)在所述第一绝缘层(9)上以及所述第二绝缘层(11)在所述电荷阻挡层(10)上; 所述控制栅(6、7)被定位在所述电荷存储层堆叠(CT)上; 所述电荷存储层堆叠(CT)被布置用于通过将来自所述载流沟道区(C2)的电荷载流子直接隧穿通过所述第一绝缘层(9)来在所述电荷阻挡层(10)中捕获电荷;其中所述第一绝缘层(9)包括高K材料,与二氧化硅中电子的势垒 On a semiconductor substrate 1. A nonvolatile memory (1), comprising a semiconductor base layer (2) and at least a programmable memory transistor (T2), the programmable memory transistor (T2) includes a charge storage layer stack (CT) and a control gate (6; 6, 7); said semiconductor substrate (2) comprising source and drain regions (3b, 3c) and is positioned between the source and drain regions (3b, 3c) of the intermediate current carrying channel region (C2); the charge storage layer stack (CT) comprising a first insulating layer (9), a charge blocking layer (10) and a second insulating layer (11), said first insulating layer (9 ) are positioned on said carrier in the channel region (C2), the charge blocking layer (10) on said first insulating layer (9) and said second insulating layer (11) on said charge blocking layer (10); said control gate (6, 7) are positioned in the charge storage layer stack (CT); said charge storage layer stack (CT) is arranged for by carriers from the groove channel region (C2) of the charge carriers tunneling directly through said first insulating layer (9) of the trapped charge in the charge blocking layer (10); wherein said first insulating layer (9) comprises a high K material, and the electron barrier silica 度和空穴的势垒高度之间的能级差相比,所述高K材料具有相对较小的电子的势垒高度和空穴的势垒高度的能级差。 Energy difference between the barrier height of the hole and compared to the high-K material having a relatively small barrier height and the barrier height of the hole-electron energy difference.
2. 根据权利要求1所述的在半导体基板上的非易失性存储器(1),其中所述可编程存储晶体管(T2)是耗尽型晶体管。 2. On the semiconductor substrate, a nonvolatile memory (1) according to claim 1, wherein the programmable memory transistor (T2) is a depletion type transistor.
3. 根据权利要求1或2所述的在半导体基板上的非易失性存储器(1),其中所述第一绝缘层(9)的高K材料具有相对宽泛的组成成分范围,并且用于根据组成成分变化来对高k材料的势垒高度属性进行变化和/或调整。 On a semiconductor substrate according to the non-volatile memory (1) of claim 1 or claim 2, wherein said first insulating layer (9) of the high-K material having a relatively wide composition range, and for to change and / or adjust the barrier height of the high-k material properties according to changes in composition.
4. 根据前面权利要求1、 2或3中的任何一个所述的在半导体基板上的非易失性存储器(1),其中所述第一绝缘层(9)的高K材料包含硅酸铪(Hf卜xSi力2)。 4. The nonvolatile memory of any preceding claim (1) on the semiconductor substrate 1, a 2 or claim 3, wherein said first insulating layer (9) of the high-K material comprises hafnium silicate (Hf BU xSi force 2).
5. 根据权利要求4所述的在半导体基板上的非易失性存储器(1),其中相对于铪含量,改变Hf,-,Six02化合物的硅含量x,来改变和调整电子的势垒高度和空穴的势垒高度,其中0《x《1。 According to claim on a semiconductor substrate of a nonvolatile memory (1) of claim 4, wherein with respect to the hafnium content, varying Hf, -, the content of the silicon compound Six02 x, changes and modifications to the electron barrier height and a hole barrier height, wherein 0 "x" 1.
6. 根据权利要求4或5所述的在半导体基板上的非易失性存储器(1),其中所述硅酸铪化合物是氮化硅酸铪(Hf,-,SiA (N))。 According to claim on a semiconductor substrate of a nonvolatile memory (1) of claim 4 or 5, wherein said compound is a hafnium silicate nitride hafnium (Hf, -, SiA (N)).
7. 根据权利要求4至6中的任何一个所述的在半导体基板上的非易失性存储器(1),其中所述第一绝缘层(9)的硅酸铪化合物包含的硅含量介于大约x=0. 60和大约x=0. 90之间。 7. A non-volatile memory according to any of (1) on a semiconductor substrate in a 4 to 6 claim, wherein the silicon content of the Hafnium silicate compound of the first insulating layer (9) included between between about x = 0.60 and approximately x = 0. 90.
8. 根据权利要求4至7中的任何一个所述的在半导体基板上的非易失性存储器(1),其中所述第一绝缘层(9)的硅酸铪化合物包含的硅含量大约为x=0. 77。 According to claim any non-volatile memory (1) on the semiconductor substrate in one of the 4 to 7, wherein the silicon content of the first insulating layer (9) comprising a compound of hafnium silicate is approximately x = 0. 77.
9. 根据权利要求4至8中的任何一个所述的在半导体基板上的非易失性存储器(1),其中电子的势垒高度介于大约2.5eV和大约3. leV之间,空穴的势垒高度介于大约3.0eV和大约3. 6eV之间。 According to any of claims nonvolatile memory (1) on a semiconductor substrate in a 4-8, wherein the electron barrier height and between about 2.5eV to about 3. leV, holes the barrier height between approximately 3.0eV and about 3. 6eV.
10. 根据权利要求4至9中的任何一个所述的在半导体基板上的非易失性存储器(1),其中所述第一绝缘层(9)的高K材料的K 值介于K"4和K^8之间。 10. The nonvolatile memory of any of claims (1) on a semiconductor substrate in a claim 4-9, K value of the high-K material wherein said first insulating layer (9) is between K " K ^ between 4 and 8.
11. 根据前面任何一项权利要求所述的在半导体基板上的非易失性存储器(1),其中所述第二绝缘层(11)包括第二高K材料, 所述第二高K材料的K值实质上等于或大于所述第一绝缘层(9)的高K材料的K值。 According to any preceding claim in non-volatile memory on the semiconductor substrate (1), wherein said second insulating layer (11) comprises a second high-K material, the second high-K material the K value is substantially equal to or greater than the K value of the high-K material, a first insulating layer (9).
12. 根据权利要求11所述的在半导体基板上的非易失性存储器(1),其中所述第二绝缘层(11)的第二高K材料包括硅酸铪(Hf卜xSix02)。 According to claim on a semiconductor substrate of a nonvolatile memory (1) of claim 11, wherein said second insulating layer (11) of the second high-K material comprises hafnium silicate (Hf BU xSix02).
13. 根据权利要求12所述的在半导体基板上的非易失性存储器(1),其中所述第二高K材料的硅酸铪(HfhSi力2)的硅含量小于所述第一绝缘层的高K材料的硅含量。 On a semiconductor substrate 13. The non-volatile memory (1) according to claim 12, wherein the hafnium silicate second high-K material (HfhSi force 2) silicon content is less than the first insulating layer the silicon content of the high-K material.
14. 根据权利要求12或13所述的在半导体基板上的非易失性存储器(1),其中所述第二高K材料的硅酸铪(Hf卜xSix02)的硅含量大约是xi. 47。 On a semiconductor substrate 14. The non-volatile memory (1) of claim 12 or claim 13, wherein the hafnium silicate second high-K material (Hf Bu xSix02) silicon content is approximately xi. 47 .
15. 根据权利要求11所述的在半导体基板上的非易失性存储器(1),其中所述第二高K材料包括Zr02和它的硅酸盐、Hf02、 Ta205、A1203、 HfxAlyOz或X-Sc03中的一个,其中X是Gd、 Dy或La中的一个。 According to claim on a semiconductor substrate of a nonvolatile memory (1) of claim 11, wherein said second material comprises a high-K and its silicate Zr02, Hf02, Ta205, A1203, HfxAlyOz or X- a Sc03, wherein X is Gd, Dy or La a.
16. 根据权利要求4至15任何一项所述的在半导体基板上的非易失性存储器(1),其中所述第一绝缘层(9)的厚度介于大约2nm 和大约6nm之间。 16. any of claims 4 to 15 non-volatile memory (1) on a semiconductor substrate, wherein the thickness of the first insulating layer (9) is between about 2nm and about 6nm.
17. —种用于制造在半导体基板上的非易失性存储器(1)的方法,该方法包括半导体基层(2)和至少一个可编程存储晶体管(T2),所述可编程存储晶体管(T2)包括电荷存储层堆叠(CT)和控制栅(6; 6、 7);所述半导体基层(2)包括源区和漏区(3b、 3c)以及被定位在所述源区和漏区(3b、 3c)中间的载流沟道区(C2);所述电荷存储层堆叠(CT)包括第一绝缘层(9)、电荷阻挡层(10)和第二绝缘层(11),所述第一绝缘层(9)被定位在所述载流沟道区(C2)上,所述电荷阻挡层(10)在所述第一绝缘层(9) 上以及所述第二绝缘层(11)在所述电荷阻挡层(10)上;所述控制栅(6、 7)被定位在所述电荷存储层堆叠(CT)上; 所述电荷存储层堆叠(CT)被布置用于通过将来自所述载流沟道区(C2)的电荷载流子直接隧穿通过所述第一绝缘层(9)来在所述电荷阻挡层(10)中捕获电荷,其中所 17. The - method for manufacturing a nonvolatile memory (1) on the semiconductor substrate, the method comprising a semiconductor base layer (2) and at least a programmable memory transistor (T2), the programmable memory transistor (T2 ) includes a charge storage layer stack (CT) and a control gate (6; 6, 7); said semiconductor substrate (2) comprising source and drain regions (3b, 3c) and is positioned between the source and drain regions ( 3b, 3c) of the carrier intermediate the channel region (C2); the charge storage layer stack (CT) comprising a first insulating layer (9), a charge blocking layer (10) and a second insulating layer (11), said a first insulating layer (9) is positioned on said carrier in the channel region (C2), the charge blocking layer (10) on said first insulating layer (9) and said second insulating layer (11 ) on the charge blocking layer (10); said control gate (6, 7) are positioned in the charge storage layer stack (CT); said charge storage layer stack (CT) is arranged for by charge carriers from the current carrying channel region (C2), direct tunneling through the first insulating layer (9) of the trapped charge in the charge blocking layer (10), wherein 述方法包括: 可编程存储晶体管,淀积高K材料作为所述第一绝缘层(9),与二氧化硅中电子和空穴的势垒高度相比,该高K材料具有相对改进的电子的势垒高度和空穴的势垒高度的对称性。 Said method comprising: a programmable memory transistor, the high-K material is deposited as the first insulating layer (9), as compared with the height of the potential barrier of electrons and holes in silicon dioxide, the high-K material has a relatively improved electronic the barrier height and the hole barrier height of symmetry.
18. 根据权利要求17的用于制造在半导体基板上的非易失性存储器(1)的方法,其中所述方法还包括:提供作为可编程存储晶体管(T2)的耗尽型晶体管。 18. The method of claim 17 on a semiconductor substrate manufacturing a nonvolatile memory (1) is used, wherein the method further comprises: providing a depletion type transistor as a programmable memory transistor (T2) is.
19. 一种存储器阵列,其至少包括一个根据前面权利要求1至16中的任何一项所述的非易失性存储器。 19. A memory array comprising at least one non-volatile memory of any one of claims 1 to 16 in the preceding claims.
20. —种半导体器件,其至少包括一个根据前面权利要求1至16中的任何一项所述的非易失性存储器。 20. - semiconductor device, which includes at least one of the preceding non-volatile memory as claimed in any one of claim 1 to claim 16.
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