CN101263607A - Drain-extended MOSFET with diode clamp - Google Patents
Drain-extended MOSFET with diode clamp Download PDFInfo
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- CN101263607A CN101263607A CNA2005800515736A CN200580051573A CN101263607A CN 101263607 A CN101263607 A CN 101263607A CN A2005800515736 A CNA2005800515736 A CN A2005800515736A CN 200580051573 A CN200580051573 A CN 200580051573A CN 101263607 A CN101263607 A CN 101263607A
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
- H01L29/7818—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
Abstract
High side extended-drain MOS driver transistors (T2) are presented in which an extended drain (108, 156) is separated from a first buried layer (120) by a second buried layer (130), wherein an internal or external diode (148) is coupled between the first buried layer (120) and the extended drain (108, 156) to increase the breakdown voltage.
Description
Technical field
[001] relate generally to semiconductor device of the present invention more particularly, relates to the MOS transistor device of extended drain and the processing method that is used to make this device.
Background technology
[002] uses for high-power switchgear, the power semiconductor product generally by utilizing drain extended Metal-oxide-semicondutor (DEMOS) transistor device of N type or P type raceway groove, processes as laterally diffused MOS (LDMOS) device or simplification surface field (RESURF) transistor.The DEMOS device is advantageously with short channel operation and high current handling capability, relative low leakage-source conducting resistance (Rdson) with stand high blocking voltage and ability that the voltage breakdown inefficacy do not occur combines.Puncture voltage generally is measured as the puncture voltage (BVdss) of drain-to-source under grid and source shorted situation together, and wherein the design of DEMOS device usually relates between puncture voltage BVdss and Rdson and compromises.Except performance advantage, the DEMOS device fabrication relatively is easy to be integrated in the cmos process flow, is convenient to be used in the single integrated circuit (IC) and also wants in the device of processing logic circuit, low power analog circuit or other circuit.
[003] N type channel drain extended transistor (DENMOS) is the symmetrical device that generally is formed in the n trap, forms p trap (for example, being called as the p mold base sometimes) simultaneously in this n trap.Form n type source electrode in this p trap, wherein this p trap is provided at the p type channel region between this source electrode and the drain electrode of expansion n type.This extended drain generally comprises the n type drain electrode that is injected in this n trap and spread over drift region between this channel region and this drain electrode in this n trap.Mixing to provide in the low n type of drain side has the high large stretch of depletion layer that blocks voltage capability, wherein generally connect the p trap is connected to source electrode preventing p trap suspension joint by p type back of the body grid, thus stabilizing device threshold value (Vt).Device drain region and raceway groove (for example, the raceway groove of expansion) are kept apart so that provide drift region or drain extended in the n N-type semiconductor N material between them.In operation, the interval between drain electrode and the raceway groove is stretched over outside the electric field, thereby increases the breakdown voltage ratings (higher BVdss) of device.But the expansion of drain electrode has increased the resistance (Rdson) of leakage-source current path, so the design of DEMOS device often relates to the compromise between high-breakdown-voltage BVdss and low Rdson.
[004] the DEMOS device has been widely used in requiring the power switch of high blocking voltage and high electric current current capacity to use, particularly for the situation that will drive solenoid or other inductive load.In a common configuration, two or four n raceway groove DEMOS devices are arranged to half " H bridge " circuit or complete " H bridge " circuit drives load.In half H bridge is arranged, the serial of two DEMOS transistors is coupled between power supply VCC and the ground connection, simultaneously load is coupled on the ground connection from the intermediate node between two transistors.In this configuration, the transistor between intermediate node and the ground connection is called as " downside " transistor, and another transistor is called as " high side " transistor, and wherein these two transistors alternately activate to provide electric current to load.In full H bridge drive circuit, two high side driver and two low side driver are provided, wherein load is coupled between two intermediate nodes.
[005] in operation, high side DEMOS has drain electrode that is coupled with power supply and the source electrode that is coupled with load.At " conducting " state, high side driver is transmitted to load with electric current from power supply, wherein in fact source electrode by on move supply voltage to.The typical DEMOS device of processing forms silicon epitaxial layers simultaneously on this substrate on the wafer of the silicon substrate with the doping of p type, wherein makes substrate ground connection and form transistor source, drain electrode and raceway groove (for example, comprising n trap and p trap) in silicon epitaxial layers.Therefore, in the conducting state of high side DEMOS device, need and to open to prevent the punchthrough current between p trap and the substrate around the p type substrate separation of p trap below ground connection of source electrode.Although the n trap can be expanded below the p trap, the n trap generally only slightly mixes, and therefore enough potential barriers of the on-state punch-thru current from the source electrode to the substrate can not be provided.Therefore, before forming silicon epitaxial layers, in substrate, form heavily doped n type buried layer sometimes and (for example, NBL),, and therefore suppress the on-state punch-thru current from the p trap to substrate in the high side DEMOS device so that n trap and substrate isolation are opened.Therefore can this n type buried layer be connected on the drain terminal of these high side DEMOS devices by deep diffusion or injection region (sinker), and it be bound supply voltage so that prevent or suppress on-state punch-thru current.
[006] although n type buried layer can prevent on-state punch-thru current, NBL limits the off-state breakdown voltage rated value of high side DEMOS driver.At " ending " state, the source electrode of high side driver is pulled down to ground connection by actual in the time of the low side driver conducting, and the drain source voltage that wherein passes high side DEMOS is actually supply voltage VCC.In high-voltage switch was used, the leakage that has limiting device-source of the n type buried layer below the p trap punctured, because n type buried layer is tied to drain electrode at the VCC place.In this case, p trap ground connection, because source electrode is an electronegative potential in cut-off state, and in fact supply voltage VCC be lowered when passing n trap part, this n trap partly spreads between p trap bottom and the n type buried layer, and between the raceway groove side of p trap and the drain electrode.In addition, because high side driver is turned off when driving inductive load, instantaneous drain source voltage can increase to above power level VCC.
[007] in these cases, the lateral separation that can regulate between drain electrode and the p trap prevents from the p trap to the puncture that drains.But p trap bottom more is difficult to increase to the perpendicular separation between the n type buried layer.A kind of method is the thickness that increases silicon epitaxial layers.But this is expensive aspect process complexity, particularly forms deep diffusion to connect the situation of n type buried layer to drain electrode.Therefore, need improved DEMOS device and processing method, can realize the voltage breakdown ability to bear that increases, and do not increase the thickness of silicon epitaxial layers, also sacrifice device performance not by these Apparatus and method fors.
Summary of the invention
[008] the present invention relates to n raceway groove or p channel drain diffused mos (DEMOS) transistor and processing method, wherein extended drain is separated with first buried layer and is coupled mutually by inside or external diode and its.The present invention helps to increase the breakdown voltage operation of high side driver and other DEMOS device and does not need thicker silicon epitaxial layers also can oppositely not influence Rdson, in view of the above existing processing process is made minimum change, just can realize the driving operating voltage that increases.Can first buried layer and extended drain be kept apart by second buried layer, second buried layer has opposite conduction type and formed before epitaxial growth.Can in epitaxial loayer, form diode discretely, in interconnection layer or metal layer, to form connection and being connected from the negative electrode to the extended drain, perhaps form outside connection external diode is coupled between first buried layer and the extended drain from anode to first buried layer.
Description of drawings
[009] Fig. 1 illustrates the schematic diagram that utilizes two pairs of downsides and high side leakage utmost point expansion nmos device to drive the full H bridge circuit device of load, wherein can realize one or more aspect of the present invention;
[010] Fig. 2 A is the local side front view that illustrates the transistorized cross section of traditional high side DENMOS;
[011] Fig. 2 B is the lateral elevational view of traditional high-side transistor of Fig. 2 A, and it illustrates in the cut-off state in the isopotential electrical line ball of drift region and the zone that is easy to puncture under high drain source voltage;
[012] Fig. 3 is certain the regional local side front view according to one or more aspects of the present invention, it illustrates exemplary high side DENMOS transistor, this transistor has the p type buried layer that extended drain and following n type buried layer are kept apart, and the diode clamp that n type buried layer and extended drain are coupled together;
[013] Fig. 3 B is the transistorized lateral elevational view of exemplary high side DENMOS of Fig. 3 A, and it illustrates the isopotential electrical line ball in the drift region under the cut-off state;
[014] Fig. 3 C is the figure that illustrates drain current (Id) and drain source voltage (Vds) relation curve, and it illustrates the comparison breakdown voltage property at the high side DENMOS driver transistor of Fig. 2 A and Fig. 3 A;
[015] Fig. 4 is the flow chart that illustrates according to the illustrative methods of processing semiconductor device of the present invention and high side DENMOS driver transistor;
[016] Fig. 5 A-5H is the local side front view of certain part, the illustrative embodiments of the high side DENMOS driver transistor of this part diagram key diagram 3A, this driver transistor has the internal body diodes that n type buried layer and extended drain are coupled together, and this figure shows each stage of processing substantially according to the method for Fig. 4;
[017] Fig. 6 A-6D is the local side front view of certain part, another possibility execution mode of the high side DENMOS driver transistor of this part diagram key diagram 3A, this driver transistor has the outside connection that is used for being coupled external diode between n type buried layer and extended drain, and this figure shows each stage of processing substantially according to the method for Fig. 4;
[018] Fig. 6 E is a top plan view, and it illustrates the single-chip execution mode of the full H bridge circuit device of the Fig. 1 with external diode connection according to the present invention; And
[019] Fig. 6 F is a top plan view, and it illustrates the execution mode of the single high side driver transistor with the outside connection that is used for external diode according to the present invention.
Embodiment
[020] the invention provides improved DEMOS transistor and processing method thereof, can realize the high-breakdown-voltage rated value in view of the above and do not increase epitaxial silicon layer thickness, wherein buried layer is coupled by diode and extended drain.The present invention finds in the high side driver transistor of full-bridge or half-bridge circuit is used particularly useful, although transistor of the present invention and method are not limited to these application.Be that example illustrates to various aspects of the present invention and describes with the NMOS driver transistor in the back,, only p type doped region need be replaced with n type doped region and get final product that vice versa although the PMOS execution mode also is feasible.In addition, though having the semiconductor substrate of silicon substrate and covering silicon epitaxial layers, the following illustrative devices use forms, but also can utilize other semiconductor substrate, including, but not limited to standard semiconductor wafers, SOI wafer or the like, wherein all these variant execution modes all are considered to drop within the scope of the present invention and appended claims.
[021] Fig. 1 illustrates the full H bridge driver semiconductor device 102 by DC supply voltage VCC power supply, wherein can realize various aspects of the present invention.As more following about shown in Fig. 6 E and as described in, semiconductor device 102 can be built as has the single IC 102a that four driver transistor T1-T4 are connected with the outside that is used for power supply, signal and face terminals, and can optionally be provided for the connection at the external diode of high side driver T2 and/or T3.Fig. 6 F illustrates another possible device 102b, and single high side driver wherein is provided in IC, this IC have be used to drain, outside that source electrode, grid, back of the body grid are connected with the selectivity anode connects.The present invention can be used as alternate application in other integrated circuit that wherein has random number of components, needs the extended drain MOS transistor of high-breakdown-voltage in these integrated circuits.
[022] as shown in Figure 1, exemplary means 102 comprises four n channel drain diffused mos (DENMOS) device T1-T4, they have corresponding source S 1-S4, drain D 1-D4 and grid G 1-G4 respectively, and are coupled in and drive the load that is coupled between intermediate node N1 and the N2 in the H bridge.Transistor T 1-T4 is arranged to two pairs of downsides and high side driver (T1﹠amp; T2 and T4﹠amp; T3), load simultaneously is coupled between the intermediate node of two pairs of downsides and high side driver, forms " H shape " circuit thus.Can utilize transistor T 1 and T2 to realize half-bridge driver circuit, the node N2 of the right-hand side of load simultaneously is coupled on the ground connection, and wherein T3 and T4 can be left in the basket.In one example, for automobile application, mobile electronic device etc., supply voltage VCC can be the positive terminal of battery supply, and ground connection can be the negative terminal of this battery.
[023] in the left side of the H of Fig. 1 bridge, low side driver T1 and high side driver T2 are coupled between supply voltage VCC and the ground connection by polyphone, and another is connected with T3 in a similar manner to T4.High side driver transistor T2 has the drain D 2 that is coupled on the VCC and the source S 2 that is coupled mutually at load place and intermediate node N1.Low side transistors T1 has drain D 1 that is coupled to node N1 and the source S 1 that is coupled to ground connection.Node N1 between transistor T 1 and the T2 is coupled to the first terminal of load, and another face terminals N2 is coupled to another transistor to T3 and T4, and wherein load generally is not the part of device 102.High side and low side transistors grid G 1-G4 are controlled so that drive load in the mode that replaces.When transistor T 2 and T4 conducting, electric current flows through high-side transistor T2 and load along first direction (among Fig. 1 to the right), and when transistor T 3 and the equal conducting of T1, electric current flows through load and low side transistors T1 along second rightabout.
[024] in order to estimate the one or more shortcomings of traditional DEMOS transistor in using as H bridge among Fig. 1 and so on, Fig. 2 A and 2B illustrate the semiconductor device 2 with traditional high side DENMOS transistor 3, wherein Fig. 2 B illustrates the isopotential electrical line ball in the drift region of high side driver 3 under the cut-off state, so that illustrate its breakdown voltage limit.Be that example has briefly been described traditional high side driver transistor 3 so that estimate possibility advantage of the present invention with H bridge driver circuit hereinafter, wherein can be coupled DENMOS transistor 3, drive the load in the configuration of full-bridge or half-bridge driver circuit, as the T2 in the H bridge circuit of Fig. 1.
[025] shown in Fig. 2 A, device 2 comprises the silicon substrate 4 that the p type mixes, and forms silicon epitaxial layers 6 on this substrate.N type buried layer (NBL) 20 is arranged in substrate 4 below the high side device 3 and local expansion to silicon epitaxial layers 6.By injection n trap 8 in the silicon epitaxial layers 6 of n type dopant on n type buried layer 20, and in n trap 8, form p trap or p matrix 18.Form field oxide (FOX) isolation structure 34 in the top of the silicon epitaxial layers 6 between the transistor device terminals of downside and high-side transistor 1 and 3.In p trap 18, form p type back of the body grid 52 and n type source electrode 54, and in n trap 8, form n type drain electrode 56.On the channel part of p trap 18, form the grid structure, it comprises gate oxide 40 and gate electrode 42, wherein grid G 2, source S 2 and the drain D 2 to traditional high side DENMOS transistor 3 marks, as the half H bridge or the full H bridge that are coupled with the Fig. 1 that is used for illustrating above forming.
[026] in this driver applications, high side device drain 56 links to each other with supply voltage VCC and source electrode 54 is coupled at intermediate node N1 place and load.When high-side transistor 3 conductings, source electrode 54 and drain electrode 56 all are in or near supply voltage VCC, wherein n type buried layer 20 helps to prevent that punchthrough current from flowing between the p of p trap 18 and ground connection type substrate 4, and wherein n type buried layer 20 is tied to drain electrode 56 (for example, to VCC).But, when high-side transistor 3 ends, in fact source electrode 54 being pulled down to ground connection by low side transistors, the drain source voltage at high in view of the above side DENMOS 3 two ends is actually supply voltage VCC.In addition, when when conducting state is transformed into cut-off state, if load is inductive, then high side driver 3 can stand the instantaneous drain source voltage greater than VCC.Fig. 2 B illustrates the isopotential electrical line ball in the drift region of n traps 8 in the high-side transistor under the cut-off state 3.On these high drain source voltage levels, in zone 21 and 22, produce high electric field, at these regional equipotential lines at interval closely, high side driver 3 wherein shown in Figure 2 is in the Vds that only is lower than the puncture level.
[027] present inventor has realized that owing to the n type buried layer 20 to small part is positioned under the n trap 8, these zones 21 and 22 are easy to puncture when being in than high power supply voltage in high side driver cut-off state, and puncture voltage BVdss of traditional DENMOS 3 is relatively low shown in it.Therefore, though n type buried layer 20 suppresses from p trap 18 to substrate 4 on-state punch-thru current, the off-state breakdown voltage BVdss of high side driver 3 is subjected to the restriction of the existence of NBL 20.From this respect, the present inventor has recognized that the existence of the n type buried layer 20 that is in drain potential (VCC) causes the gathering of the equipotential line among Fig. 2 B on high drain source voltage level, particularly in the zone in Fig. 2 B 21 and 22.If lack design variation, then do not emit the danger of cut-off state or instantaneous voltage breakdown, just can not increase supply voltage VCC.A kind of method is that the doping content that reduces n trap 8 is improved breakdown voltage property.But this method oppositely influences on-state drive current owing to increase Rdson.Another method is the thickness that increases silicon epitaxial layers 6.But, as mentioned above, process thicker epitaxial loayer 6 and cause process complications, and to surmount certain numerical value may be infeasible.
[028] the invention provides the DEMOS transistor that is easy to improve breakdown voltage ratings and does not increase Rdson or epitaxial silicon layer thickness.Therefore the present invention is easy to use these devices in the new application that requires high power supply voltage more, these are used including, but not limited to as shown in Figure 1 full H bridge or the configuration of half H bridge, avoid simultaneously or alleviate common compromise, and can not bring remarkable change existing processing process to Rdson and BVdss in the drain extended MOS device.Fig. 3 A-3C illustrates the high side driver transistor T2 of exemplary DENMOS in the H bridge driver spare 102 of Fig. 1, wherein the n type buried layer 120 and the extended drain of device are kept apart by p type buried layer 130, and wherein between n type buried layer 120 and drain electrode, be coupled diode 148 with the increase puncture voltage, and do not need to increase epitaxial thickness.Although with the high side driver of DENMOS that forms in the semiconductor substrate with silicon substrate and covering silicon epitaxial layers is that example illustrates, but other execution mode also is possible within the scope of the present invention, for example, untapped transistor during PMOS execution mode, the device that utilizes other semiconductor-based body structure processing, other drain extended MOS transistor (for example, RESURF device etc.) and/or high side driver are used.In addition, as mentioned above, diode 148 can be integrated in the device 102 or can be in the outside.
[029] as shown in Figure 3A, form device 102 in semiconductor substrate, this semiconductor substrate comprises p type silicon substrate 104 that mixes and the silicon epitaxial layers 106 that is formed on the substrate 104.Before forming silicon epitaxial layers 106, (for example form under the high side driver zone of its expection in substrate 104, inject and diffusion) n type buried layer (NBL) 120, and on the n type buried layer in this high side driver zone, (for example form, inject) p type buried layer (PBL) 130, thereby p type buried layer 130 is placed between the high side DENMOS transistor T 2 of n type buried layer 120 and covering, wherein in the epitaxial process of silicon epitaxial layers and/or to device 102 provide heat energy with the after-processing technology step in, the p type dopant that some of p type buried layer 130 are injected into can upwards be diffused in the silicon epitaxial layers 106.In addition, in this heat treatment process, p type buried layer 130 can stop or suppress the upwards diffusion of the n type dopant of n type buried layer 120.
[030] transistor T 2 also comprises and (for example utilizes n type dopant, arsenic, phosphorus etc.) the n trap 108 that in silicon epitaxial layers 106, injects, and being formed at p trap or p matrix 118 in the n trap 108, field oxide (FOX) structure 134 is formed at silicon epitaxial layers 106 tops between transistor source, drain electrode and back of the body gate terminal simultaneously.Has other execution mode, for example, back of the body grid can be directly connected to source electrode, perhaps utilize shallow-trench isolation (STI) technology, deposited oxide to wait and form isolation structure, wherein all these substituting execution modes (for example all make first buried layer, NBL 120) with second buried layer of DEMOS by having films of opposite conductivity (for example, PBL130) keep apart, simultaneously (for example between the two, be coupled diode, diode 148), these schemes all are considered to fall within the scope of the present invention and appended claims.
[031] transistor T 2 comprises p type back of the body grid 152 and the n type source electrode 154 that is formed in the p trap 118, and is formed at the n type drain electrode 156 in the n trap, wherein drain 150 and p trap 118 between part n trap 108 drain extended or drift region are provided.Therefore, transistor T 3 comprises extended drain, and this extended drain comprises the drift region and the drain electrode 156 of n trap 108.In operation, back of the body grid 152 can but not necessarily be coupled to the source electrode 154 that covers in the metal layer (not shown).In a possible substituting execution mode,, can ignore field oxide (FOX) structure 134 between back of the body grid 152 and the source electrode 154 for of the direct connection of back of the body grid 152 to source electrode 154.On the part drift region of the channel part of p trap 118 and n trap 108, form grid structure, this grid structure comprises gate oxide 140 and gate electrode 142, wherein further expansion on the drain extended of n trap 108 or the field oxide structure 134 above the drift region in exemplary crystal pipe T2 of part gate electrode 142.
[032] in half H bridge or full H bridge load driver configuration, drain electrode 156 negative electrodes together with inside or external diode 148 is connected on the supply voltage VCC, and source electrode 154 is coupled in the load at the intermediate node N1 place among Fig. 1.In the conducting state of high side DENMOS transistor T 2, source electrode 154 by on move near supply voltage VCC, wherein n type buried layer 120 helps to prevent that punchthrough current from flowing between the p of p trap 118 and ground connection type substrate 104.In cut-off state, the major part of supply voltage VCC appears between drain electrode 156 and the source electrode 154.But, with in the high side driver of tradition with n type buried layer (for example, NBL 20 among Fig. 2 A) being coupled to drain electrode goes up and different to be, n type buried layer 120 in the exemplary means 102 (is for example kept apart by p type buried layer 130 and extended drain, open with the drain electrode 156 and the separated drift regions of n trap 108), wherein diode 148 is coupled between n type buried layer 120 and the extended drain.Therefore, the cut-off state current potential of n type buried layer 120 is lower than VCC.
[033] the lower n type buried layer current potential and the existence of inserting p type buried layer cause under cut-off state, occurring in the device with the high side driver of tradition in electric field compare the Electric Field Distribution that differs widely.Fig. 3 B illustrates the high side device T2 under high drain source voltage, this high drain source voltage will exceed about 60% and voltage breakdown do not occur than top Fig. 2 B's, here n type buried layer 120 is in than under the drain electrode 156 lower voltages, and wherein the part supply voltage appears at the two ends of diode 148.In this example, the design parameter of exemplary high side DENMOS transistor T 2 (for example, size, doping content etc.) is about the same with the traditional devices 3 among Fig. 2 A, has just added p type buried layer 130 and diode 148.Therefore, adding p type buried layer 130 makes it possible to be operated under the higher supply voltage VCC with the diode that is coupled n type buried layer 120 and extended drain, and do not experience the cut-off state voltage breakdown, wherein BVdss is enlarged markedly and is not increased epitaxial silicon layer thickness, and does not change Rdson.
[034] Fig. 3 C provides and illustrates drain current (Id) and the curve 162 of the relation of drain source voltage (Vds) and 164 figure, the traditional high side DENMOS 3 of these two curves difference corresponding diagram 2A and the exemplary high side DEMOS transistor T 2 of Fig. 3 A.From Figure 160 as can be seen, the transistor T 3 of Fig. 3 A can run on safely under the much higher voltage and not puncture, and wherein corresponding BVdss 164 exceeds than the BVdss 162 of the traditional high side DENMOS 3 of Fig. 2 A and surpasses 60%.Therefore, isolation between n type buried layer 120 and the extended drain 156,108 and be coupled diode 148 between the two at it higher puncture voltage is provided significantly, allow to utilize higher supply voltage VCC, and do not increase the thickness of silicon epitaxial layers 106, and can not produce significant oppositely influence to Rdson.
[035] in preferred embodiments, the doping content of n type buried layer 120 will be higher than the doping content of p type buried layer 130, when between p trap 118 and p type buried layer 130, exhausting, suppress on-state punch-thru current and between p trap 118 and p type substrate 104, flow with convenient n trap 108.In one example, p type buried layer 130 has more than or equal to about 5E15cm
-3With smaller or equal to about 5E17cm
-3Maximum dopant concentration, wherein n type buried layer 120 has more than or equal to about 1E17cm
-3With smaller or equal to about 1E20cm
-3Maximum dopant concentration, and n type buried layer Cmax is higher than the Cmax of p type buried layer 130.
[036] another aspect of the present invention is provided for the method for semiconductor device fabrication, and it can be used to process the device with NMOS and/or PMOS extended drain transistor, and these transistors have improved breakdown voltage property.In this one side of the present invention, in substrate, inject first buried layer with first conduction type, inject second buried layer then with second conduction type.Form silicon epitaxial layers on the substrate that is injected into, and form the drain extended MOS transistor above second buried layer in silicon epitaxial layers, the wherein transistorized extended drain and first buried layer are separated.This method can be included in the epitaxial loayer and to form diode first buried layer is coupled on the extended drain, or the outside that is formed into first buried layer and extended drain connects so that be coupled external diode between the two.
[037] Fig. 4 illustrates on the one hand according to of the present invention this and is used for processing semiconductor device and the transistorized illustrative methods 202 of DEMOS, and Fig. 5 A-5H roughly illustrates the example semiconductor device 102 of different processing stages according to the method 202 of Fig. 4 under the situation that internal body diodes 148 is provided.Fig. 6 A-6D illustrates the course of processing of another execution mode of device 102 and method 202, and the connection at external diode 148 wherein is provided.Can utilize other method of the present invention to form the PMOS device, wherein p type dopant be replaced with n type dopant, vice versa.In addition, can utilize method 202 to form device with internal body diodes, these internal body diodes are used for first buried layer is coupled to the transistorized extended drain of DEMOS, and/or utilize this method to produce device with outside available connection, these outside available connections are used for external diode is coupled between first buried layer and the extended drain, and wherein all these substituting execution modes are considered to fall within the scope of the present invention and appended claims.
[038] though below illustrative methods 202 is illustrated and is described as a series of actions or incident, should be realized that the present invention be not limited to illustrated in these actions of explanation or the ordering of incident.For example, according to the present invention, some actions can take place with different order, and/or take place simultaneously with other action or incident except that those actions shown here and/or described or incident.In addition, be not to need the step shown in all to realize a kind of method according to the present invention.In addition, both can also can realize according to method of the present invention in conjunction with device fabrication shown here and described in conjunction with unshowned other device and structure.
[039] method 202 starts from 204 among Fig. 4, then is in 206 and injects n type buried layer in the substrate (for example, NBL), n type buried layer also can optionally be spread at 208 places.In example semiconductor device 102, provide n type buried layer 120 in driver region 112 for high side device T2, also can be included in the separation n type buried layer 120a of diode area 111 at other local this n type buried layer that injects of device 102.In Fig. 5 A, NBL that the device 102 that illustrates forms on the each several part of silicon substrate 104 injects mask 302 to expose the part at the upper surface of the substrate 104 in the high side driver zone 112 of expection, covers the part in the internal body diodes zone 111 of expection simultaneously.By suitable placement mask 302 so that (for example inject n type dopant, arsenic, phosphorus etc.) carry out injection technology 304 to the expose portion of substrate 104, thereby in driver region 112, form n type buried layer 120 (first buried layers that for example, have first conduction type) and form the n type buried layer 120a that separates at diode area 111.Can optionally carry out diffusion annealing (not shown) so that driving n type dopant more is deep in the substrate 104 in step 208, thereby n type buried layer 120,120a are outwards expanded downwards and laterally from initial injection zone.
[040] second buried layer (for example, the p type buried layer 130 in the device 102) with second conduction type is injected at 210 places in Fig. 4, and it can optionally be spread at 212 places.In Fig. 5 B, form mask 312, its territory, high lateral areas 112 in expection exposes part n type buried layer 120, and carries out injection technology 314 and provide p type dopant (for example, boron etc.) in the expose portion of substrate 104.Shown in Fig. 5 B, exemplary p type buried layer 130 in the territory, high lateral areas 112 is positioned at the n type buried layer 120 of device 102, wherein can optionally carry out another time diffusion annealing at 212 places, so that laterally and downwards drive the p type dopant that injects, thus expansion p type buried layer 130.
[041] 214 places in Fig. 4 carry out epitaxial growth technology and come growth of epitaxial silicon layer 106 on substrate 104.Can utilize any suitable epitaxial growth to handle at 214 places, this is handled and form silicon epitaxial layers 106 on the upper surface of substrate 104.In Fig. 5 C, on substrate 104, form silicon epitaxial layers 106 by technology 322, wherein relevant with epitaxial growth technology 322 thermal energy causes the upwards diffusion of part p type dopant of p type buried layer 130, thereby 130 expansions of part p type buried layer enter in the silicon epitaxial layers 106.Similarly, the terminal part branch of n type buried layer 120 upwards is diffused in the outer silicon epitaxial layers 106 in high side driver zone 112, and diode region n type buried layer 120a also upwards expansion enter in the silicon epitaxial layers 106.But, among epitaxy technique 322 processes at 214 places and afterwards, p type buried layer 130 generally prevents or suppresses in the high side driver zone 112 upwards diffusion to small part n type buried layer 120, and between the DEMOS extended drain (for example, drain electrode 156 among Fig. 3 A and n trap 108) of n type buried layer 120 and formation subsequently, provide physical barrier.
[042] at 216 places, in the silicon epitaxial layers 106 in territory, high lateral areas 112, inject the n trap, then can this n trap of thermal diffusion at 218 places.Before or after 216 places form the n trap, in silicon epitaxial layers 106, form dark n type diffusion (for example, the injection region), to be provided to the connection of n type buried layer 120.In Fig. 5 D and 6A, on silicon epitaxial layers 106, form mask 324, carry out the injection 326 of n type simultaneously and be connected with the n type injection region 107 that thermal diffusion annealing (not shown) generates zone 111 to n type buried layers 120.Form mask 332 in Fig. 5 E and 6B, it exposes the high side driver of expection zone 112 all or part, and execution injection 334 generates n trap 108 (for example, n trap 108a-108c among Fig. 5 E and the n trap 108 among Fig. 6 B) therein.To in device 102, form under the situation of internal body diodes 148, shown in Fig. 5 E, mask 332 exposes two parts of diode area 111, thereby being infused in of 218 places generates negative electrode n trap 108a and the 108c that expands to n type buried layer 120a downwards in the diode area 111, and also in high side driver zone 112, generate DEMOS n trap 108b, can carry out thermal diffusion annealing after this at 218 places.
[043] at 220 places, p trap or p basal region 118 are injected in the transistor n trap 108 of part, can carry out another time thermal diffusion annealing (not shown) after this.Fig. 5 F illustrates the situation of internal body diodes 148, wherein forms mask 342 and exposes among the DEMOS n trap 108b and the expection p well area of the epitaxial loayer 106 in the diode area 112 between n trap 108a and the 108c.Carry out injection technology 344 then and generate anode p trap 118a, thereby generate internal body diodes 148 and transistor p trap 118b in the epitaxial loayer 106, wherein n trap 108b expands under the p trap 118b between p trap 118b and the p type buried layer 130.In this configuration, the n type buried layer 120a of n trap 108a and 108c and diode region is used for keeping apart with the remainder of diode p trap 118a and epitaxial loayer 106 with p substrate 104.Fig. 6 C illustrates the situation of using external diode 148, wherein generates single p trap 118, wherein mask 342 overlay areas 111 in transistor n trap 108.Can utilize any suitable injection technology to form buried layer 120,130 and trap 108,118 within the scope of the invention, selectivity is carried out special-purpose diffusion annealing after any, whole or neither one inject simultaneously, and wherein all these variant execution modes all are considered to fall within the scope of the present invention.
[044] 222 places in Fig. 4 utilize any suitable technology to form isolation structure 134, these technology such as local oxidation of silicon (LOCOS), shallow-trench isolation technology (STI), deposited oxide etc.In exemplary means 102, shown in Fig. 5 G, respectively diode area 111 and territory, high lateral areas 112 are formed field oxide (FOX) structure 134.Shown in Fig. 5 H and 6D, by, for example, thermal oxidation forms thin gate oxide 140 (for example, 224 places in method 202) at the device upper surface, and is in deposit gate polysilicon layer 142 on the thin gate oxide 140 226.Gate oxide 140 and polysilicon 142 are carried out the grid structure that patterning is expanded on the channel region that is formed on the p trap 118b (the p trap 118 among Fig. 6 D) among Fig. 5 H at 228 places.
[045] after forming the grid structure of patterning, can carry out that LDD and/or MDD inject and the lateral sidewalls along the grid structure of patterning forms sidewall spacers at 230 places.At 232 places, utilize n type dopant to inject source region 154 and drain region 156, and utilize p type dopant to inject back of the body grid 152 at 234 places, wherein can utilize any suitable mask and injection technology to form n type source electrode 154 and drain electrode 156 and p type back of the body grid 152.Carry out silication, metallization and other back-end processing respectively at 236 and 238 places then, so that before first metal on the grid 142 of DEMOS transistor T 2, source electrode 154, drain electrode 156 and back of the body grid 152 in medium (PMD) layer 174, and on p type anode 118a and n type negative electrode 118a, generate conductive metal silicide material 172 and conductivity contact plug 178 (for example, tungsten etc.) at (Fig. 5 H) under the situation of internal body diodes 148.
[046] form more metal layer (not shown) then at 240 places and generate multistage interconnected wire structures, the method among Fig. 4 202 ends at 240 places afterwards.Be schematically shown as Fig. 5 H, under the internal body diodes situation, n type buried layer 120 is coupled with anode p trap 118a by the conductivity contact plug on n type injection region 107 and injection region 107 and the anode 118a 178, n type buried layer 120 is connected to covers in the metal layer.Shown in Fig. 6 D, when utilizing external diode 148, provide the external anode of self-metallization wiring to connect, and provide external drain to connect so that link to each other with the negative electrode of diode 148 from D2 so that connect diode 148 to n type buried layer 120.
[047] Fig. 6 E and Fig. 6 F illustrate two kinds of semiconductor device 102a and 102b that may finish respectively, and its anode that is respectively external diode 148 provides outside with negative electrode and is connected.Fig. 6 E illustrates the exemplary single-chip execution mode 102a of the full H bridge circuit device of Fig. 1 according to the present invention, this full H bridge circuit device has external diode and connects, and these connections are respectively applied between the n type buried layer 120 (anode) of high side driver DEMOS transistor T 2 and T3 and extended drain (negative electrode) and are coupled diode 148a and 148b.Fig. 6 F illustrates another exemplary means 102b, and it comprises single high side driver transistor, and (for example, T2), this high side driver transistor has the external anode connection that is used at n type buried layer 120 and drains and be coupled external diode 148 between 156.
[048], also can make and change and/or revise and do not depart from scope of the present invention the example that has illustrated although the present invention is illustrated and describes by one or more execution modes.
Claims (14)
1. the MOS transistor of a drain extended, it comprises:
One has the source electrode of first conduction type, and it is formed in the semiconductor substrate;
One has the drain electrode of described first conduction type, its in described semiconductor substrate with described source electrode lateral isolation;
One has the drift region of described first conduction type, between its described drain electrode and described source electrode in described semiconductor substrate;
One has the channel region of second conduction type, and it spreads between the described drift region and described source electrode in the described semiconductor substrate, and wherein said drift region spreads between described channel region and the described drain electrode;
One is positioned at the grid on the described channel region;
One has first buried layer of described first conduction type, and it is positioned under described source electrode, described channel region and the described drift region, and described first buried layer and described drift region and described drain electrode are separated; With
One diode, its have the anode that is coupled mutually with described first buried layer and with described drift region and described drain electrode at least one negative electrode that is coupled mutually.
2. transistor according to claim 1, it further comprises second buried layer with described second conduction type, it is positioned under described source electrode, described channel region and the described drift region, wherein said second buried layer is separated described first buried layer and described drain electrode and described drift region, and wherein said diode and described second buried layer are separated.
3. transistor according to claim 2, wherein said semiconductor substrate comprises silicon substrate and the silicon epitaxial layers that is formed on the described silicon substrate, wherein said source electrode, described drain electrode, described channel region and described drift region are arranged in described silicon epitaxial layers, and wherein described second buried layer of at least a portion is arranged in described silicon substrate.
4. transistor according to claim 3, wherein said diode is formed in the described silicon epitaxial layers.
5. transistor according to claim 2, wherein said first buried layer are positioned under described second buried layer of at least a portion.
6. transistor according to claim 2, it comprises first trap with described first conduction type, it spreads in the described semiconductor substrate under described source electrode, described drain electrode and the described raceway groove, and wherein said second buried layer is positioned under described first trap.
7. transistor according to claim 6, it comprises second trap with described second conduction type, it is positioned at described first trap, and described second trap spreads under described source electrode and the described grid, and wherein described first trap of part spreads between described second trap and described second buried layer.
8. transistor according to claim 1, wherein said diode is formed in the described semiconductor substrate.
9. transistor according to claim 1, wherein said first conduction type are n types and described second conduction type is the p type.
10. transistor according to claim 1 and 2, wherein said transistor comprises the MOS transistor of drain extended.
11. the method for a processing semiconductor device, described method comprises:
Silicon substrate is provided;
In described silicon substrate, inject first buried layer with first conduction type;
In described silicon substrate, inject second buried layer with second conduction type;
After injecting described second buried layer, on described silicon substrate, form silicon epitaxial layers; With
Form the MOS transistor of drain extended on second buried layer described in the described silicon epitaxial layers, the MOS transistor of described drain extended comprises the extended drain with described first conduction type, and described extended drain and described first buried layer are separated.
12. method according to claim 11, it further comprises the outside that is formed into described first buried layer and described extended drain and connects to be used for being coupled external diode between described first buried layer and described extended drain.
13. method according to claim 11 further comprises:
Form diode in described silicon epitaxial layers, described diode comprises anode and negative electrode;
Described anode is coupled to described first buried layer; With
Described negative electrode is coupled to described extended drain.
14. method according to claim 11, wherein said first conduction type are n types and described second conduction type is the p type.
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| CNA2005800515736A CN101263607A (en) | 2005-07-18 | 2005-07-18 | Drain-extended MOSFET with diode clamp |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102054866B (en) * | 2009-11-05 | 2012-07-11 | 上海华虹Nec电子有限公司 | Transverse high-voltage MOS device and manufacturing method thereof |
| CN103187254A (en) * | 2011-12-28 | 2013-07-03 | 北大方正集团有限公司 | Fabrication method of double layer polysilicon gate |
| CN103531480A (en) * | 2012-06-29 | 2014-01-22 | 飞思卡尔半导体公司 | Semiconductor device and driver circuit with drain and isolation structure, and method of manufacture thereof |
| CN104518030A (en) * | 2013-09-27 | 2015-04-15 | 联发科技股份有限公司 | MOS device with isolated drain and method for fabricating same |
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2005
- 2005-07-18 CN CNA2005800515736A patent/CN101263607A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102054866B (en) * | 2009-11-05 | 2012-07-11 | 上海华虹Nec电子有限公司 | Transverse high-voltage MOS device and manufacturing method thereof |
| CN103187254A (en) * | 2011-12-28 | 2013-07-03 | 北大方正集团有限公司 | Fabrication method of double layer polysilicon gate |
| CN103187254B (en) * | 2011-12-28 | 2015-12-02 | 北大方正集团有限公司 | A kind of manufacture method of dual poly gate |
| CN103531480A (en) * | 2012-06-29 | 2014-01-22 | 飞思卡尔半导体公司 | Semiconductor device and driver circuit with drain and isolation structure, and method of manufacture thereof |
| CN104518030A (en) * | 2013-09-27 | 2015-04-15 | 联发科技股份有限公司 | MOS device with isolated drain and method for fabricating same |
| CN104518030B (en) * | 2013-09-27 | 2018-07-03 | 联发科技股份有限公司 | Metal-oxide-semiconductor's device and its manufacturing method with isolation drain electrode |
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