CN1012409B

CN1012409B - Bus transmitter having controlled trapezoidal slew rate

Info

Publication number: CN1012409B
Application number: CN88102666A
Authority: CN
Inventors: 戴维·S·格朗达尔斯基
Original assignee: Digital Equipment Corp
Current assignee: Digital Equipment Corp
Priority date: 1987-06-29
Filing date: 1988-05-06
Publication date: 1991-04-17
Also published as: KR890001325A; BR8802752A; KR920007097B1; CN1030834A; ATE100256T1

Abstract

The inventions concerns a transmitter circuit for transmitting a digital data signal over a bus in a digital data processing system includes a MOSFET bus driver transistor having a gate to drain capacitance CGD which substantially dominates other capacitances at the gate terminal. The bus driver transistor is driven by a buffer circuit having pull-up and pull-down transistors current through which is controlled by current sources. The gate terminal of the driver transistor is connected to, and controlled by, the node between the pull-up and pull-down transistors. The drain terminal of the driver transistor is connected to, and controls, a bus line.

Description

Bus transmitter having controlled trapezoidal slew rate

Relate generally to electronic circuit field of the present invention relates more specifically in digital data processing system to send by bus the circuit of signal.

A digital data processing system comprises many functional units, comprise: one or more processors, internal memory and such as the such input-output apparatus of mass storage, video display terminal, printer and communication equipment, by one or multiple bus with above-mentioned these device interconnectings.The signal and the various control signal of these buses transmission representative information between each unit that constitutes this system, these control signals are used in particular for the transmission of each information signal.

Usually, bus is one group of lead that some functional units can be connected in parallel thereon.When a unit sent signal by a lead in the bus, the end that this signal arrives this bus just may be reflected.Reflected signal may disturb the signal that sends by this bus subsequently, and this situation can cause the signaling error on the bus.The subject matter of signal reflex is that reflected signal makes the signal degradation that sends subsequently.Therefore, in order the interference from the signal reflection to be reduced to minimum, system designer is had to before carrying out another time transmission, provides enough time of delay after then last the transmission.

On the other hand, perhaps system designer can make reflection reduce to minimum by design bus or by the signal that bus sends, and for example, each end of some lead has the resistor network that helps to reduce reflection.The power supply of bus also can provide by these bus termination absorbing load networks.

In addition, can the conditioning signal waveform, make reflection and reduce to minimum in the cross-talk between the signal on the different bus.Particularly, signal waveform can be reasonable rectangle, makes that the voltage amplitude steeper ground between height and low level on the bus conductor changes.A kind of like this signal waveform allows to send apace signal, but yet causes signal reflex and cross-talk probably.

On the other hand, if signal is " trapezoidal ", promptly the signal voltage amplitude of this waveform with more not precipitous but still be very fast rate variation, just can reduce to contingent reflection minimum between height and low level.The transmitter that produces such signal should be able to be " rate of change " (Slew rate) at the voltage changing rate on the selected limit inner control lead.This problem is complicated, because in most systems, bus should be able to handle be attached thereto, the very wide unit of number of variations scope, like this, then the situation that causes capacity load in wide range, to change, thereby may change the rate of change of the signal that sends by bus conductor.

At present, the transmitter that can produce trapezoidal signal waveform can be made by discrete resistors and other element that high-precision is controlled in conjunction with the electric parameter value with bipolar transistor.Most of circuit that constitutes the functional unit of digital data processing system is made with MOSFET device (MOSFET), bipolar transmitter circuit then is separate with other element that constitutes these unit and make separately, occupies sizable space on the printed circuit board (PCB) of the circuit element that these unit of formation are housed.In addition, because these bipolar transmitters are discretes, ambipolar and separate with other device,, cause to send the extra delay of signal so they need very big electrical power.

British patent document EP-A-0083504 is a prior art related to the present invention; not reason output short-circuit and damage transistorized MOS type output driving circuit of a kind of protection has been described in the document; this driver utilizes the MOS transistor npn npn of two serial connections as output stage; drive circuit also comprises a protective circuit in order to protect these output transistors when exporting ground short circuit to, wherein is no lack of the design of the feedback network of employing.Do not adopt the metal-oxide-semiconductor occupy ascendancy to leak the design that electric capacity between a grid provides feedback network but but relate in this prior art.

The invention provides a kind of improved transmitter circuit that make with the MOSFET device, new, in order to produce by bus signal that send, that have trapezoidal waveform.

Put it briefly, this new bus transmitter circuit comprises a MOSFET bus driver transistor, and the buffer circuits that this transistor leads on having by, the pull-down transistor electric current passes through is encouraged, and this electric current is controlled by constant-current source.Capacitor C between the grid-leakage of driver transistor _GDBasically greater than other electric capacity at gate terminal place.The driver transistor gate end is connected to the node that leads between the drop-down two transistor, and is controlled by this node.The drain electrode end of driver transistor is connected to bus line, and it is controlled.In order on bus line, to establish a signal, on lead transistor and be switched on, according to a speed electric current is sent into node by current source control, this makes the magnitude of voltage of node increase.When the node voltage value reached the threshold value of driver transistor, driver transistor began conducting, and the magnitude of voltage of bus line is descended.Simultaneously, electric current is by the grid-drain capacitance of driver transistor, begins to flow into node from bus line, thereby limited the node voltage value, and limited the electric current of the driver transistor of flowing through thus.Thereby, electric current in the mode that is subjected to the control of magnitude of voltage rate of change on the bus line to a certain extent from the bus line driver transistor of flowing through, thereby realize the trapezoidal variation of signal on bus line.On bus line signal is become in the process of anti-(negale), working condition is similar, and electric current flows out node by electric capacity between the grid-leakage of pull-down transistor and driver transistor.

With reference to description, can understand the above-mentioned and further advantage of the present invention preferably below in conjunction with accompanying drawing.In these accompanying drawings:

Fig. 1 is by the deliver letters circuit sketch plan of device of the digital data bus that the present invention constitutes;

Fig. 2 is 2 signal waveforms of locating in circuit shown in Fig. 1, and it helps to understand the transmitter shown in Fig. 1.

With reference to Fig. 1, the transmitter 10 that constitutes according to the present invention comprises a bus driver transistor 11, and the gate terminal of transistor 11 receives the buffer output digital data signal BUT OUT from the buffer circuits 12 that is connected into the inverter form.In response to (being high level) buffer output signal BUF OUT from the establishment of buffer circuits 12, the bus driver transistor turns sends out a BUS OUT(L by bus line 14) bus (low level of establishment) output digital data signal.Bus driver transistor 11 has the drain electrode end of always receiving bus line 14 in succession and one to be connected in fact to be in earthy power supply V _SSSource terminal.Bus driver transistor 11 is n-type metal oxide semiconductor field-effect transistors (MOSFET).

Buffer circuits 12 comprises and leads transistor 16 and a n-type pull-down transistor 17 on the p-type that is connected between constant-current source 20 and 21.Constant-current source 20 is connected to power supply V _DD, and the electric current that leads transistor 16 drain electrode ends is coupled in control.On lead the source terminal link node 22 of transistor 16, node 22 is connected to the drain electrode end of pull-down transistor 17.The source terminal of pull-down transistor 17 is connected to current source 21, and current source 21 controls flow to power supply V by it from node 22 _SSElectric current.The BUF OUT inverter output signal that is coupled to bus driver transistor 11 gate terminal by on node 22 places of leading between the drain electrode end of the source terminal of transistor 16 and pull-down transistor 17 provide.See transistor 11 back, with at node 22 places other electric capacity compare, transistor 11 it gate terminal and drain electrode end between exist a big electric capacity (in Figure 11 with C _GDRepresent), so grid-drain capacitance C _GDAmong each electric capacity at node 22 places, play significant feature in fact.

On lead transistor 16 and pull-down transistor 17 gate terminal by (being asserted high level) output signal SIG OUT(H from inverter 13) with cascade system control, inverter 13 will be from (being asserted low level) output signal SIG OUT(L of other circuit (not shown)) carry out paraphase.Be somebody's turn to do (being asserted low level) output signal SIG OUT(L) also control a p-transistor npn npn 15, the drain electrode end of transistor 15 is connected to node 22, and its source terminal is connected to power supply V _SS

Originally, (be asserted) output signal SIG OUT(H low level) in (opposite) low-voltage state.As a result, transistor 15 conductings.Inverter 13 should (be asserted) output signal SIG OUT(H low level) paraphase, so that (being asserted low level) output signal SIG OUT(L of (opposite) high-voltage value to be provided), it transfers again transistor 17 to be maintained at conducting state, and transistor 16 is maintained at cut-off state.At this moment, transfer to power supply V by current source 21 from the electric charge of node 22 _SS(promptly) is so buffer output signal BUF OUT is in low voltage value.In addition, because driver transistor 11 ends, so bus (being asserted low level) output signal BUS OUT(L) be to be in high-voltage value (thereby a signal with opposite logic levels is provided), as (Fig. 2) shown in the time A.

As (being asserted high level) output signal SIG OUT(H) during from (high voltage) state that opposite (low-voltage) state exchange becomes to determine, transistor 15 ends.In addition, inverter 13 will (be asserted high level) output signal SIG OUT(H) paraphase, forming (being asserted a low level) output signal SIG OUT(L who is in low-voltage (establishment) state).As a result, transistor 17 ends, and cuts off from node 22 and passes through current source 21 to power supply V _SSCurrent path.In addition, (being asserted low level) output signal SIG OUT(L) make transistor 16 conductings, thus set up one from power supply V _DDBy the path of current source 20 to node 22.

Because transistor 16 conductings, thus buffer output signal BUF OUT(as among Fig. 2 since time A to shown in the time B) rise.At time B(Fig. 2), the magnitude of voltage of buffer output signal BUF OUT has risen to threshold voltage, so the 11 beginning conductings of bus driver transistor.This then make electric current flow through bus driver transistor 11 again from the line 14 of bus, cause bus (being asserted low level) output signal BUS OUT(L) magnitude of voltage descend, as among Fig. 2 and then behind the time B shown in.Yet, because the grid of bus driver transistor 11 a drain capacitance C _GDOccupy the sizable ratio of total capacitance on the node 22, so electric current also passes through grid one drain capacitance C from the line 14 of bus _GDInject node 22.Therefore, grid one drain capacitance C _GDProvide a feedback network, so that bus (being asserted low level) output signal BUS OUT(L) influence the magnitude of voltage of node 22.

Because this moment two sources, promptly current source 20(by on lead transistor 16) and the line 14(of bus pass through the grid one drain capacitance C of bus driver transistor 11 _GD), force electric current to enter node 22 the other way around, so node 22 (is power supply V with respect to ground _SSMagnitude of voltage) magnitude of voltage, promptly the magnitude of voltage of node 22 is constant, as among Fig. 2 between time B and the C shown in.Therefore, the magnitude of voltage on bus driver transistor 11 gate terminal approximately maintains on the threshold value, thereby transistor 11 is kept conducting, and its conducting degree is such: promptly the magnitude of voltage of the line 14 of bus is at this moment to fall under the speed that is controlled.That is exactly bus (being asserted low level) output signal BUS OUT(L) in a time interval, change to low value, the grid one drain capacitance C of it and bus driver transistor 11 from the high value _GDWith provide by current source 20 current related.

Bus on the line 14 in bus (being asserted low level) output signal BUS OUT(L) when finishing downward transition change, electric current passes through grid one drain capacitance C from the line 14 of bus _GDThe speed of injecting node 22 also descends.As a result, from current source 20, by on lead the electric current that transistor 16 injects nodes 22 and play a major role at node 22 places, and the magnitude of voltage of node 22 begins to increase once more, shown in time C to D among Fig. 2.This growth rate depends on and comprises grid one drain capacitance C _GDAt the electric capacity of interior node 22 and by the electric current of current source 20 for supply.At time D (Fig. 2), node 22 is charged to maximum voltage value.At this moment, bus driver transistor 11 complete conductings, and node 22 is charged fully, as among Fig. 2 shown in the high buffer output signal BUF OUT in time D place.In addition, during to time D, bus (being asserted low level) output signal BUS OUT(L) be determined fully, promptly it is at minimum voltage value.

Buffer output signal BUF OUT remains on high-voltage value, and bus (being asserted low level) output signal BUS OUT(L) remain on low voltage value, till time E.At time E, (being asserted high level) output signal SIG OUT(H) be opposite, promptly it is energized to a low voltage value.As a result, inverter 13 is with (being asserted high level) output signal SIG OUT(H of this low value) paraphase, so that (being asserted low level) output signal SIG OUT(L of a high value to be provided).(being asserted low level) output signal SIG OUT(L of this high value) again then lead transistor 16 on going to end, thereby, cut-out is 22 path from current source 20 to node, and conducting pull-down transistor 17, thus provide one from node 22 to current source 21 current path.

In addition, (being asserted high level) output signal SIG OUT(H of high value) make transistor 15 conductings, this directly is provided with one at node 22 with by source electrode power supply V _SSCurrent path between the ground that is provided.This current path by transistor 15 allows node 22 between time E and F (Fig. 2) to be discharged to the threshold voltage of transistor 15 apace.At transistor 15 is in the certain embodiments of n one transistor npn npn, and the magnitude of voltage that transistor 15 allows nodes 22 falls from 5 volts of states of complete charged state reduces to about 2.5 volts.During this period, also also have electric current to flow out node 22, but main current path is a transistor 15 by pull-down transistor 17 and current source 21.Flowed out enough big electric current at node 22, after making the magnitude of voltage of node 22 reach the threshold value of bus driver transistor 11, bus driver transistor 11 begins to end, make bus (being asserted low level) output signal BUS OUT(L) magnitude of voltage rise, thereby make bus (being asserted low level) output signal BUS OUT(L) become anti-.

In the front and back of time F, when the drain electrode end of transistor 15 dropped into the threshold value of transistor 15 to the potential difference between the gate terminal, transistor 15 ended basically.Yet electric current still tends to continue flow out node 22 by pull-down transistor 17 and current source 21.Simultaneously, electric current continues in the other direction (promptly to pass through the grid one drain capacitance C of driver transistor 11 _GD) outflow node 22.Because electric current is constant to flow out from node 22 in the other direction so the magnitude of voltage of the node 22 of buffer output signal BUF OUT is provided, shown in the G, the size of the magnitude of voltage that this is constant enough makes transistor 11 keep conducting under controlled level as time F among Fig. 2.This permission bus (being asserted low level) output signal BUS OUT(L) magnitude of voltage increased with a kind of speed of stable control in this time interval, as shown in Figure 2.

At time G, grid one drain capacitance C _GDStop to draw electric charge from node 22, thus electric charge just the transistor 17 by still conducting, flow out from node 22 with the speed of being controlled by current source 21.Therefore the magnitude of voltage of node 22 drops into the V of source electrode supply _SSValue, the i.e. earth potential of transmitter circuit 10.Therefore, buffer (being asserted low level) output signal BUF OUT(L) (Fig. 2) falls with an in check speed between time G-H, as shown in Figure 2.

Will recognize that the effect that transistor 15 is set is in order to shorten E to the F time period, be during this period of time for the magnitude of voltage that makes node 22 drop to driver transistor 11 begin by the time magnitude of voltage required.Under the situation that does not have transistor 15, electric current changes from pull-down transistor 17 and current source 21 and flows through, but because current source 21 has limited the circulation of electric current, so need the long time to make the voltage of node 22 finally reach the value that driver transistor 11 begins to end.

In addition, will recognize big grid one drain capacitance C _GDA feedback network is provided in fact, has made bus (being asserted low level) output signal BUS OUT(L) control the magnitude of voltage of node 22 to a certain extent, this is again then controlled the rising and the decline of signal.This just causes bus (being asserted low level) output signal BUS OUT(L) have suitable rising, the forward position of fall time (B to C is between the moment in Fig. 2) and back along (F-G is between the moment in Fig. 2), thus " trapezoidal " signal is provided.The sort signal shape, make in having very short rising, the signal of fall time (being rectangular signal) intrinsic ringing and other noises reduce greatly.The sort signal shape is by means of big grid one drain capacitance C _GDRealize capacitor C _GDConcerning the total capacitance at driver transistor gate end place, occupy main status in fact, make electric current at bus (being asserted low level) output signal BUS OUT(L) transition change during, as described above like that, easily by grid one drain capacitance C _GD

The description of front is limited to a certain embodiments of the present invention.But clearly, might do various changes and modification and have the part or all of advantage that the present invention reaches the present invention.So, claim of the present invention need cover all with the real spirit and scope of the present invention in relevant various changes and modification.

Claims

1, a kind of bus transmitter circuit (10) comprises a driver and a controller buffer of operating this driver in response to data input signal; It is characterized in that:

A. described driver comprises a mosfet driver transistor (11), this transistor (11) has drain electrode end, gate terminal that is coupled to a control node (22) and the source terminal that is used for being coupled to the source electrode power supply that is used for being coupled to bus (14), described mosfet driver transistor (11) has the intrinsic big electric capacity between described gate terminal and drain electrode end, this electric capacity is compared with other electric capacity of described gate terminal and is occupied ascendancy in fact, thereby a feedback network between described drain electrode end and the control node (22) is provided; With

B. described controller buffer (12) comprise one by on lead transistor (16) and on lead conversion hysteria that current source (20) forms on lead the pull device of the conversion hysteria that device and is made up of pull-down transistor (17) and pull-down current source (21), lead transistor (16) on described and pull-down transistor (17) is coupled to described control node (22), and leading transistor (16) and pull-down transistor (17) on described also is coupled so that receive described data input signal, control the control node (22) of described driver according to the state of described data input signal, by leading on described that transistor (16) and pull-down transistor (17) flow to described control node (22) thus electric current be subjected to corresponding current source control to make described driver conducting in a controlled manner or end

Described feedback network is for providing the bi-directional path of electric current between described control node and the described bus, so that optionally control the voltage of signals level at described control node place, thereby and remove the rate of change controlling described driver conducting and end according to described data input signal.

2, bus transmitter circuit as claimed in claim 1, it is characterized in that also comprising a driver pull-down transistor that is coupled to described control node, this transistor is subjected to control with a drop-down control signal of described data input signal complementation, thereby when described data input signal switching levels, described control node is set on the selected level, so that impel described driver transistor to end fast.

3, bus transmitter circuit as claimed in claim 1 is characterized in that leading transistor on wherein said is different conductivity type with pull-down transistor.

4, a kind of bus transmitter circuit (10) comprises a driver and a controller buffer of operating this driver in response to data input signal, it is characterized in that:

A. described driver comprises a mosfet driver transistor (11), this transistor (11) has drain electrode end, gate terminal that is coupled to control node (22) and the source terminal that is used for being coupled to the source electrode power supply that is used for being coupled to bus, described mosfet driver has the intrinsic big electric capacity between described gate terminal and drain electrode end, this electric capacity is compared with other electric capacity of described gate terminal and is occupied ascendancy in fact, thereby a feedback network between described drain electrode end and the control node is provided;

B. described controller buffer (12) comprising:

ⅰ. lead device on the conversion hysteria, this device comprises:

A. pull-up current source (20) with controlled speed supplying electric current;

B. pull up transistor (16) with selecteed conductivity type, this transistor has the drain electrode end that is coupled to described pull-up current source, the source terminal that is coupled to described control node and gate terminal;

ⅱ. the pull device of a conversion hysteria, this device comprises:

A. pull-down current source (21) with in check speed supplying electric current;

B. one has and is different from the pull-down transistor (17) that leads transistorized conductivity type on described, and described pull-down transistor has the drain electrode end that is coupled to described pull-down current source, the source terminal that is coupled to described control node, and gate terminal;

The gate terminal of leading on described with pull-down transistor all is coupled so that receive described data input signal, led current source control on described by leading the electric current of transistor on described to described control node, and controlled by described pull-down current source by above-mentioned pull-down transistor to the electric current of described control node, thereby make described driver conducting in a controlled manner and end

Thereby described feedback network for providing the bi-directional path of electric current between described control node and the described bus so that the rate of change of optionally controlling the voltage of signals level at described control node place and controlling described driver conducting and end according to described data input signal; With

C. driver pull-down transistor, this transistor has drain electrode end and the gate terminal that is coupled to the control node, be subjected to control with the drop-down control signal of described data input signal complementation, thereby when described data input signal switching levels, described control node is set on the selected level, so that impel described driver transistor to end fast.

5, bus transmitter circuit as claimed in claim 2 is characterized in that also comprising being used for receiving described drop-down control signal and being used for producing a inverter as the described data input signal of the complementary signal of described drop-down control signal.

6, bus transmitter circuit as claimed in claim 4 is characterized in that also comprising being used for receiving described drop-down control signal and being used for producing a inverter as the described data input signal of the complementary signal of described drop-down control signal.

7, a kind of bus transmitter circuit (10) comprises a driver and a controller buffer of operating described driver in response to data input signal, it is characterized in that:

The transistor of described driver (11) has an output that is used to be coupled to bus, and comprises a reference edge that is coupled to power supply and an input that is coupled to control node (22),

Described buffer (12) is controlled the control node of described driver according to the state of its received described data-signal, so as to make described driver transistor in a controlled manner conducting or end and

An electric capacity that is configured between described input and the output, other electric capacity of this this input end of capacity ratio are much bigger, so that, thereby thereby optionally be controlled at the voltage of signals level at described control node place and control the rate of change that described driver transistor is logical in response to described data-signal and end for the bidirectional current between described control node and described bus is provided at feedback network between described output and described control node.

8, bus transmitter circuit as claimed in claim 7 is characterized in that described electric capacity is a natural capacity between described input and the described output, and this natural capacity is compared with other natural capacities of described input end and occupied ascendancy in fact.

9, bus transmitter circuit as claimed in claim 8 it is characterized in that wherein said driver transistor is a field-effect transistor, and described input is the gate terminal of this field-effect transistor.

10, bus transmitter circuit as claimed in claim 7, thus it is characterized in that wherein said buffer comprises that the electric current that is used for controlling described control node place makes described driver transistor with controlled mode conducting or the current source circuit that ends.

11, bus transmitter circuit as claimed in claim 7, it is characterized in that also comprising a driver pull-down transistor, the input that this transistor has an output that is linked to described control node and is subjected to control with the drop-down control signal of described data-signal complementation, thereby when described data-signal changes level, will control node and be set to a selected level, so that impel described driver transistor to end fast.