CN101202243A - Method for etching suspending type etch blocking layer contact hole in embedded flash memory device - Google Patents

Method for etching suspending type etch blocking layer contact hole in embedded flash memory device Download PDF

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CN101202243A
CN101202243A CN 200610119567 CN200610119567A CN101202243A CN 101202243 A CN101202243 A CN 101202243A CN 200610119567 CN200610119567 CN 200610119567 CN 200610119567 A CN200610119567 A CN 200610119567A CN 101202243 A CN101202243 A CN 101202243A
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etching
step
contact hole
torr
flash memory
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CN100524691C (en )
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吕煜坤
函 王
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上海华虹Nec电子有限公司
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Abstract

The invention discloses an etching method for contact holes of a suspended type etching barrier layer of an embedded flash memory device and comprises the following steps: the first step is the etching of top silicon oxy-nitride; the second step is the fast main etching of an oxide film; the third step is the slow main etching of the oxide film: in the step, the selectivity-ratio of silicon oxide to silicon nitride is bigger than 20:1, while the etching rate is relatively slower; the fourth step is to remove polymers which are produced in the previous three steps and are left at bottom parts of the contact holes; the fifth step is to remove the suspended type etching barrier layer of the nitride silicon; the sixth step is the etching of the oxide film at the bottom part. The invention solves the problem of excessive loss of metal contact silicide on the top part of a poly gate due to no etching barrier layer; at the same time, the invention can effectively avoid excessive etching and communication of the poly gate and an isolated edge of a shallow groove caused by deviation of exposing positions, thus the loss of electric leakage of the device can be reduced.

Description

嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法技术领域 TECHNICAL FIELD etching the contact hole barrier layer suspension etching embedded flash memory device

本发明涉及一种集成电路半导体制造工艺方法,尤其涉及一种嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法。 The present invention relates to a process for manufacturing a semiconductor integrated circuit, particularly to a method of etching a contact hole in an embedded flash memory device suspended etch stop layer.

背景技术 Background technique

在嵌入式闪存器件射频器件制造工艺中,需要在金属前介质(PMD) 中制作接触孔(Contact),为有源区和第一层金属层之间提供电学通道。 RF devices in embedded flash memory device manufacturing process, it is necessary contact holes (Business Card) in the pre-metal dielectric (PMD) provided for the electrical path between the active region and the first metallic layers.

如图1所示,现有的接触孔的制作工艺为:在完成有源区的金属接触(silicide)工艺之后,依此淀积作为金属前介质的氧化硅(APM)、氮化硅(SiN)、硼磷硅玻璃(BPSG)、常压氧化硅(TEOS)和顶部氮氧化硅(SiON, 即DARC)。 1, the conventional manufacturing process of the contact hole is: after completion of the active metal contact region (silicide) process, so as silicon oxide is deposited before the metal medium (the APM), silicon nitride (SiN ), borophosphosilicate glass (BPSG), silicon oxide pressure (TEOS) and a top silicon oxynitride (the SiON, i.e. DARC). 然后涂布光刻胶(PR),对掩膜曝光制作图形,最后进行等离子干法刻蚀。 Then applying the resist (PR), the production of mask exposure pattern, the last plasma dry etching. 对于所有的器件工艺来说,接触孔需要同时落在多晶栅和有源区上。 For all of the device process, the contact holes need to fall on the poly gate and the active region. 由于两者之间存在高度差,有源区的接触孔要更深一些。 Due to the height difference between them, the contact holes to active region deeper.

嵌入式闪存器件接触孔刻蚀中常见的问题为: Embedded flash memory device contact hole etched common problems:

1、和多晶栅上的接触孔相比,有源区通孔需要刻蚀得更深。 1, and the contact hole on the gate polycrystalline compared to the active region through hole deeper etching is required. 考虑到各层金属前介质淀积时,各成膜机长膜的厚度变化以及硅片面内均匀性不断累积,同时接触孔刻蚀机本身刻蚀速率的漂移以及面内均匀性的变化, 为了保证有源通孔被充分刻开,而不会导致电路断路,这就要求增加足够的氧化膜过刻蚀。 When considering the pre-metal dielectric deposition of each layer, and thickness variations within the wafer plane uniformity of the film forming film accumulating commander, drift change while contacting the inner surface of the hole of a uniform etching rate and etching machine itself, in order to ensure the through hole is sufficiently active engraved apart, without causing disconnection circuit, which requires a sufficient increase in over-etching the oxide film. 但是如果没有刻蚀阻挡层的话,大量的过刻蚀会导致多晶栅顶部的金属接触硅化物(silicide)被大量的损失,极端情况会把这 But if not, then the etch stop layer, a large amount of over-etching leads to the loss of large quantities of metal in contact with the top of the poly gate silicide (silicide), which in extreme cases would

些低接触电阻的金属硅化物全部刻蚀掉,从而导致接触电阻变大,影响器 These low contact resistance metal silicide all etched away resulting in high contact resistance, an impact

件的RC (接触孔电阻)的电学性能,如图2所示,由于没有刻蚀阻挡层, 过刻蚀导致金属接触硅化物在多晶栅顶部和有源区均有过量损失,尤其在多晶栅顶部。 RC element (contact hole resistance) electrical properties, shown in Figure 2, since there is no etch stop layer, resulting in over-etching the metal silicide contacts in both excessive loss of top of the gate poly and the active region, especially in a multi- crystal top of the gate. 同时,由于器件尺寸不断縮小和集成度的提高,许多图形曝光的套准精度标准设定得很小。 Meanwhile, since the device dimensions shrink and improve the degree of integration of many registration precision pattern exposure standards set small. 在实际生产中,经常会有曝光位置偏移, 这时接触孔刻蚀时会沿着多晶栅和浅槽隔离边缘往下继续刻蚀,从而导致器件严重的漏电效应,如图3所示,由于有曝光位置偏移和缺少刻蚀阻挡层,接触孔刻蚀时会沿着多晶栅和浅槽隔离边缘往下刻通很多。 In actual production, there is often the exposure position offsets, then will continue down along the etched poly gate and the edge of shallow trench isolation etching contact holes, resulting in severe leakage effect device shown in Figure 3 , due to lack of exposure misalignment and etch stop layer, isolates the poly gate and along the edges of the shallow groove when the contact hole is etched down through many engraved. 所以在加入刻蚀阻挡层的同时,也需要精确计算过刻蚀的比例,控制刻蚀时间。 Therefore, while the addition of the etch stop layer, but also requires precise ratio calculated etching, control of etching time.

2、另一方面,嵌入式闪存器件和其他逻辑器件相比,对氮化硅做刻蚀阻挡层比较敏感。 2, on the other hand, compared to the silicon nitride etch stop layer made sensitive embedded flash memory device, and other logic devices. 因为氮化硅对有源区的载流子具有一定的捕获、定匝能力,而闪存器件对此更为敏感。 Because silicon nitride has a certain trapping of charge carriers in the active region, given the ability to turn, but this is more sensitive to the flash memory device. 所以为了不影响器件的擦写速度和性能, 不能直接将氮化硅淀积在有源区表面,而需在其下面预先淀积一层氧化硅,即是所谓悬浮式刻蚀阻挡层。 Therefore, in order not to affect the performance of the device and erase speed, a silicon nitride can not be directly deposited on the surface of the active region, and a silicon oxide is deposited to be pre thereunder, i.e. so-called suspension-type etch stop layer. 因此,在刻蚀完氮化硅阻挡层后还需刻蚀底部的氧化硅,这就使得接触孔的刻蚀工艺更为复杂。 Thus, the need to etch the silicon oxide at the bottom of the finished silicon nitride barrier layer etching, the contact hole etching process which makes more complicated.

发明内容 SUMMARY

本发明要解决的技术问题是提供一种嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,解决因为没有刻蚀阻挡层而带来的多晶栅顶部和有源区的金属接触硅化物过量损失。 The present invention is to solve the technical problem of the contact hole etching method of etching the barrier layer to provide a suspension embedded flash memory device, there is no solution because the metal etch stop layer brought on top of the poly gate and the active region excessive loss of contact with the silicide.

为解决上述技术问题,本发明提供一种嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,包括如下步骤- To solve the above problems, the present invention provides a method of etching a contact hole is embedded flash memory device suspended etch stop layer, comprising the steps of -

第一步:顶层氮氧化硅的刻蚀;第二步:氧化膜主刻蚀之快速刻蚀:采用刻蚀速率为7500-7800埃/ 分钟,氧化硅对氮化硅的选择比为10:1-13:1,精确计算刻蚀时间,控制该步在悬浮式刻蚀阻挡层上1000-1200埃停止; The first step: etching silicon oxynitride top layer; Step: rapid etching of main etching the oxide film: The etching rate was 7500-7800 angstroms / min, a silicon oxide nitride selection ratio of 10: 1-13: 1, the etching time accurate calculation, at the step of controlling the suspension 1000-1200 angstroms stop etch stop layer;

第三步:氧化膜主刻蚀之慢速刻蚀:该步氧化硅对氮化硅的选择比〉20:1,刻蚀速率为5200-5400埃/分钟; The third step: The oxide film is etched slow main etch: The step of silicon oxide silicon nitride selection ratio of> 20: 1, the etching rate was 5200-5400 angstroms / min;

第四步:去除由前三步刻蚀带来的残留于接触孔底部的聚合物; The fourth step: removing the first three steps brought about by the polymer etch residues in the bottom of the contact hole;

第五步:去除悬浮式氮化硅刻蚀阻挡层; Fifth step: removing the silicon nitride etch stop layer suspension;

第六步:底部氧化膜刻蚀。 Step Six: etching the bottom oxide film.

第一步刻蚀的主要参数为:压力30-90毫托;上/下电极功率: The first step of etching the main parameters: pressure of 30-90 mtorr; upper / lower electrode power:

800-1200/800-1200瓦;氩气150-250sccm;三氟甲垸15-25sccm; 氧气5-25sccm;背部氦气压力:中部4-12托,边缘10-20托。 800-1200 / 800-1200 W; argon 150-250sccm; trifluoromethanesulfonic embankment 15-25sccm; oxygen 5-25sccm; back pressure helium gas: central 4-12 Torr, the edges 10-20 Torr.

第二步刻蚀的主要参数为:压力30-90毫托;上/下电极功率: 1500-2400/800-1600瓦;氩气500-1000sccm;八氟五碳5-15sccm; 氧气8-25sccm; 背部氦气压力:中部4-12托,边缘10-20托。 The main parameters for the second step of etching: 30-90 mTorr pressure; upper / lower electrode power: 1500-2400 / 800-1600 W; argon 500-1000sccm; octafluoro five carbon 5-15sccm; oxygen 8-25sccm ; back pressure helium gas: central 4-12 Torr, the edges 10-20 Torr.

第三步刻蚀的主要参数为:压力30-90毫托;上/下电极功率: 1500-2400/800-1600瓦;氩气500-1000sccm;八氟五碳6-20sccm; 氧气8-20sccm;背部氦气压力:中部4-12托,边10-20托。 The main parameter of the third etching step are: 30-90 mTorr pressure; upper / lower electrode power: 1500-2400 / 800-1600 W; argon 500-1000sccm; octafluoro five carbon 6-20sccm; oxygen 8-20sccm ; back pressure helium gas: central 4-12 torr, while 10-20 Torr. 第三步中可以追加50%的过刻蚀。 The third step may be added a 50% overetching.

第四步刻蚀的主要参数为:压力15-35毫托;上/下电极功率: 700-1400/100-300瓦;氩气100-300sccm;氧气10-30sccm; 背部氦气压力:中部4-12托,边缘10-30托。 The main parameters of the fourth etching step of: pressure 15-35 mTorr; upper / lower electrode power: 700-1400 / W 100-300; 100-300 argon; oxygen 10-30sccm; back pressure helium gas: central 4 -12 Torr, 10-30 edge care.

第五步刻蚀的主要参数为:压力30-50毫托;上/下电极功率: A fifth step of etching the main parameters: pressure of 30-50 mtorr; upper / lower electrode power:

700-1500/100-300瓦;氩气100-300sccm;三氟甲烷8-25sccm; 氧气10-30sccm; 背部氦气压力:中部4-15托,边缘10-30托。 700-1500 / W 100-300; 100-300 argon; trifluoromethane 8-25sccm; oxygen 10-30sccm; back pressure helium gas: central 4-15 Torr, the edges 10-30 Torr.

第六步釆用和第二步相同的条件:保持刻蚀速率为7500-7800埃/分钟,氧化硅对氮化硅的选择比为10:1-13:1。 And a sixth step preclude the use of the same conditions as the second step: holding the etching rate of 7500-7800 Å / min, a silicon oxide nitride selection ratio of 10: 1-13: 1. 第六步刻蚀的主要参数为: 压力30-80毫托;上/下电极功率:1500-2500/800-1800瓦;氩气500-1000sccm;八氟五碳5-15sccm; 氧气8-25sccm; 背部氦气压力: 中部4-15托,边缘10-30托。 The main parameters for the etching sixth step: a pressure 30-80 mTorr; upper / lower electrode power: 1500-2500 / 800-1800 W; argon 500-1000sccm; octafluoro five carbon 5-15sccm; oxygen 8-25sccm ; back helium pressure: 4-15 Torr central edge 10-30 Torr.

本发明具有以下有益效果:在第三步氧化膜主刻蚀软着陆时,因为氧 The present invention has the following advantages: In the third step the primary oxide film is etched soft landing, because oxygen

化膜对氮化膜的高选择比(〉20:1),可以确保将氧化膜充分刻蚀掉,并且停在氮化膜上;并且即使多晶栅顶部的氮化硅也损失很少,基本和有源区上氮化硅厚度相近,这样可以确保在随后去除剩余的氮化硅和底部氧化硅之后,金属接触硅化物损失会比较少。 Membrane selection of a nitride film of high ratio (> 20: 1), to ensure that sufficient oxide film is etched away, and stops at the nitride film; and even a top-gate polycrystalline silicon has little loss, and substantially similar to the thickness of the silicon nitride on the active region, which ensures that after subsequent removal of the remaining silicon oxide, silicon nitride and a bottom, the metal silicide contacts will be relatively small losses. 在第六步底部氧化膜刻蚀时,由于厚度较薄,所以即使加50%的过刻蚀,刻蚀时间也会控制的比较少。 When the sixth step bottom oxide film is etched, since the thickness is thin, even if the increase of 50% over-etching, the etching time will be less controlled. 这样有利于大量减少多晶栅和浅槽隔离边缘刻下的深度,从而减少器件的漏电损失。 This facilitates a significant reduction in poly gate and a shallow trench isolation depth edges carved, so as to reduce the leakage loss of the device. 在保证足够的工艺窗口的基础上,采用本发明方法,多晶栅顶部和有源区的金属接触硅化物的损失大幅减少,其中,多晶栅顶部从原来的多晶栅顶部270埃降到60埃;有源区从200埃降到<50埃,大幅降低了器件的RC。 Ensuring a sufficient process window on the basis of the method of the present invention, the metal top of the gate poly and the active region of the silicide contact loss significantly reduced, which falls from the top of the gate poly original top of the gate poly 270 Å 60 Å; 200 angstroms from the active region down to <50 Å, the RC device is significantly reduced. 采用本发明方法,由于曝光位置偏移,多晶栅和浅槽隔离边缘的刻穿深度显著减小,其中,多晶栅边缘刻穿的深度从2400埃大幅减小到400埃;浅槽隔离边缘刻穿的深度从1000埃降低到〈200埃,从而降低 Using the method of the present invention, since the exposure position shift, engraved poly gate and the edge of the shallow trench isolation depth of wear is significantly reduced, wherein the edge of the gate poly etch through substantially reduced from the depth of 400 Angstroms to 2400 Angstroms; shallow trench isolation etching through the edges is reduced from the depth of 1000 Å to <200 Å, thereby reducing

了器件的漏电损耗。 The loss of the device leakage. 附图说明图1是现有的具有接触孔的金属前介质层的结构示意图; 图2是采用现有的刻蚀方法导致金属接触硅化物损失的示意图; 图3是釆用现有方法刻蚀接触孔导致多晶栅和浅槽隔离边缘刻穿的示意图; BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic structural diagram of a conventional pre-metal dielectric layer having a contact hole; FIG. 2 is a schematic view of an etching method using a conventional metal silicide contacts lead to loss; FIG. 3 is etched by conventional methods preclude a contact hole leading to poly gate and a shallow trench isolation etching through a schematic view of an edge;

图4是采用本发明方法降低金属接触硅化物损失的示意图; Figure 4 is a schematic view of the method of the present invention contacts metal silicide loss decreases;

图5是采用本发明方法降低多晶栅和浅槽隔离边缘刻穿深度的示意图。 FIG 5 is a method of the present invention reduces the poly gate and the edge of shallow trench isolation depth of etching through a schematic view.

具体实施方式 detailed description

以下结合附图及实施例对本发明作进一步的阐述- Conjunction with the drawings and embodiments of the present invention will be further illustrated -

由于接触孔的刻蚀从上到下要依次刻DARC (SiON) /TE0S/ BPSG/ SiN/APM (见图l),所以针对不同材料的膜,用相应的刻蚀条件。 Since the contact hole etched sequentially from top to bottom to be engraved DARC (SiON) / TE0S / BPSG / SiN / APM (Figure L), so that for films of different materials, with the appropriate etching conditions.

第一步:顶层氮氧化硅的刻蚀。 The first step: etching of the top silicon nitride oxide. 如果不把这层膜刻干净(有氮氧化硅残留),将会影响到氧化膜的刻蚀,发生开孔中途停止(etch stop)。 If this layer is engraved film is not clean and (with residual silicon oxynitride), will affect the etching of the oxide film occurs midway stop openings (etch stop). 该步主要参数:压力30-90毫托;上/下电极功率:800-1200/800-1200瓦; 氩气150-250sccm;三氟甲烷15-25sccm; 氧气5-25sccm; 背部氦气压力:中部4-12托,边缘10-20托。 In this step, main parameters: pressure of 30-90 mtorr; upper / lower electrode power: 800-1200 / 800-1200 W; 150-250sccm argon gas; trifluoromethane 15-25sccm; oxygen 5-25sccm; helium gas back pressure: central 4-12 Torr, 10-20 edge care.

第二步:氧化膜主刻蚀之快速刻蚀。 Step Two: Fast etching of main etching the oxide film. 考虑的生产效率的要求,这一步采用较高刻蚀速率和对氮化硅较低选择比的条件。 Requires consideration of production efficiency, this step using a higher etch rate and lower selectivity for silicon nitride conditions. 采用刻蚀速率为7500-7800埃/分钟,氧化硅对氮化硅的选择比为10:1-13:1。 Using the etch rate was 7500-7800 angstroms / min, a silicon oxide nitride selection ratio of 10: 1-13: 1. 根据刻蚀计算,精确计算刻蚀时间,控制该步在悬浮式刻蚀阻挡层上1000-1200埃停止,例如约lk埃左右停止。 The etch calculation, accurate calculation of the etching time, the control step stops at 1000-1200 Angstroms suspension etch stop layer, for example, stopping about lk angstroms. 该步主要参数:压力30-90毫托;上/下电极功率:1500-2400/800-1600瓦;氩气500-1000sccm;八氟五碳5-15sccm; In this step, main parameters: pressure of 30-90 mtorr; upper / lower electrode power: 1500-2400 / 800-1600 W; argon 500-1000sccm; octafluoro five carbon 5-15sccm;

氧气8-25sccm; 背部氦气压力:中部4-12托,边缘10-20托。 Oxygen 8-25sccm; back pressure helium gas: central 4-12 Torr, the edges 10-20 Torr.

第三步:氧化膜主刻蚀之慢速刻蚀。 The third step: The oxide film is etched slow main etch. 通过调整C5Fs和02的比例,使该步氧化硅对氮化硅的选择比很高(大于20: 1),而刻蚀速率相对慢一些(5200-5400埃/分钟)。 By adjusting the proportion C5Fs and 02, so that the step of selecting the silicon nitride oxide ratio is very high (greater than 20: 1), and the relatively slow etch rate (5200-5400 angstroms / min). 考虑到各层金属前介质淀积时,各成膜机长膜的厚度变化以及硅片面内均匀性不断累积,同时接触孔刻蚀机本身刻蚀速率的漂移以及面内均匀性的变化,为了确保硅片面内所有有源通孔都被充分刻开,追加50%的过刻蚀。 When considering the pre-metal dielectric deposition of each layer, and thickness variations within the wafer plane uniformity of the film forming film accumulating commander, drift change while contacting the inner surface of the hole of a uniform etching rate and etching machine itself, to ensure that all of the active surface of the wafer through holes are fully opened engraved, an additional 50% overetching. 因为对氮化硅的高选择比,即使是多晶栅顶部的氮化硅也损失很少,基本和有源区上氮化硅厚度相近。 Because of the high selection ratio of the silicon nitride, even a top-gate polycrystalline silicon has little loss, and on the active region substantially similar to the thickness of the silicon nitride. 这样可以确保在随后去除剩余的氮化硅和底部氧化硅之后,金属接触硅化物损失会比较少。 This ensures that after the subsequent removal of the remaining silicon nitride and the bottom silicon oxide, metal silicide contacts will be relatively small losses. 该步主要参数:压力30-90毫托;上/下电极功率:1500-2400/800-1600 瓦;氩气500-1000sccm;八氟五碳6-20sccm; 氧气8-20sccm; 背部氦气压力:中部4-12托,边10-20托。 In this step, main parameters: pressure of 30-90 mtorr; upper / lower electrode power: 1500-2400 / 800-1600 W; 500-1000sccm argon gas; octafluoro five carbon 6-20sccm; oxygen 8-20sccm; helium back pressure : central 4-12 Torr, while 10-20 Torr.

第四步:去处通孔底部的聚合物。 Step Four: place the polymer through the bottom hole. 为了确保刻蚀继续顺利的进行,以及刻蚀CD (尺寸)的控制,去除残留于通孔底部由前三步刻蚀带来的聚合物。 In order to ensure smooth etching is continued, and control of etching CD (size), removing the polymer remaining in the bottom of the via etching caused by the first three steps. 该步主要参数:压力15-35毫托;上厂F电极功率:700-1400/100-300 瓦;氩气100-300sccm;氧气10-30sccm; 背部氦气压力:中部4-12 托,边缘10-30托。 In this step, main parameters: pressure of 15-35 mtorr; F upper electrode of the power plant: 700-1400 / 100-300 W; 100-300sccm argon gas; oxygen 10-30sccm; helium gas back pressure: 4-12 Torr central edge 10-30 torr.

第五步:悬浮式氮化硅刻蚀阻挡层刻蚀。 Step Five: suspension etching the silicon nitride etch stop layer. 通过速率计算,去掉充当阻挡层的氮化硅。 By calculating the rate to remove the silicon nitride acts as a barrier layer. 该步主要参数:压力30-50毫托;上/下电极功率: In this step, main parameters: pressure of 30-50 mtorr; upper / lower electrode power:

700-1500/100-300瓦;氩气100-300sccm;三氟甲烷8-25sccm; 氧气10-30sccm;背部氦气压力:中部4-15托,边缘10-30托。 700-1500 / W 100-300; 100-300 argon; trifluoromethane 8-25sccm; oxygen 10-30sccm; back pressure helium gas: central 4-15 Torr, the edges 10-30 Torr.

第六步:底部氧化膜刻蚀。 Step Six: etching the bottom oxide film. 釆用和第二步相同的条件。 Preclude the use of the same conditions as the second step. 由于厚度较薄, Since the thin,

所以即使加50%的过刻蚀,刻蚀时间也会控制的比较少。 Plus 50% even if the over-etching, the etching time will be less controlled. 这样有利于大量减少多晶栅和浅槽隔离边缘刻穿的深度,从而减少器件的漏电损失。 This facilitates a significant reduction in poly gate and a shallow trench isolation etching through the depth edges to reduce the leakage loss of the device. 该步主要参数:压力30-80毫托;上/下电极功率:1500-2500/800-1800瓦; 氩气500-1000sccm;八氟五碳5-15sccm; 氧气8-25sccm; 背部氦气压力:中部4-15托,边缘10-30托。 In this step, main parameters: pressure of 30-80 mtorr; upper / lower electrode power: 1500-2500 / 800-1800 W; 500-1000sccm argon gas; octafluoro five carbon 5-15sccm; oxygen 8-25sccm; helium back pressure : central 4-15 Torr, 10-30 edge care.

如图4所示,采用本发明方法,多晶栅顶部和有源区的金属接触硅化物的损失大幅减少,其中,多晶栅顶部从原来的多晶栅顶部270埃降到60埃;有源区从200埃降到〈50埃,大幅降低了器件的接触孔电阻。 4, the method of the present invention, the metal top of the gate poly and the active region in contact with the silicide losses substantially reduced, wherein the top of the poly gate from the original top of the gate poly 270 Å down to 60 Å; the a source region of from 200 Å down to <50 Å, significantly reducing the contact resistance of the device hole. 如图5所示,采用本发明方法,由于曝光位置偏移,多晶栅和浅槽隔离边缘的刻穿深度显著减小,其中,多晶栅边缘刻穿的深度从2400埃大幅减小到400埃;浅槽隔离边缘刻穿的深度从1000埃降低到〈200埃,从而降低了器件的漏电损耗。 5, the method of the present invention, since the exposure position shift, engraved poly gate and the edge of the shallow trench isolation depth of wear is significantly reduced, wherein the edge of the gate poly etch through a depth substantially reduced from 2400 angstroms to 400 angstroms; etching through the edge of the shallow trench isolation depth is reduced from 1000 angstroms to <200 Å, thereby reducing the leakage loss of the device.

Claims (9)

  1. 1、一种嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,其特征在于,包括如下步骤: 第一步:顶层氮氧化硅的刻蚀; 第二步:氧化膜主刻蚀之快速刻蚀:采用刻蚀速率为7500-7800埃/分钟,氧化硅对氮化硅的选择比为10∶1-13∶1,精确计算刻蚀时间,控制该步在悬浮式刻蚀阻挡层上1000-1200埃停止; 第三步:氧化膜主刻蚀之慢速刻蚀:该步氧化硅对氮化硅的选择比>20∶1,刻蚀速率为5200-5400埃/分钟; 第四步:去除由前三步刻蚀带来的残留于接触孔底部的聚合物; 第五步:去除悬浮式氮化硅刻蚀阻挡层; 第六步:底部氧化膜刻蚀。 1. A method of etching a contact hole is embedded blocking layer suspension etching flash memory device, characterized by comprising the steps of: first step: etching the top silicon oxynitride; Step: oxide film main facets rapid erosion of etching: the etching rate was 7500-7800 angstroms / min, a selection ratio of silicon oxide to silicon nitride 10:1-13:1, accurate calculation of the etching time, controlling the etching step was suspended in 1000-1200 angstroms stop on the barrier layer; the third step: the oxide film is etched slow main etch: the step of silicon oxide silicon nitride selection ratio of> 20:1 etch rate was 5200-5400 angstroms / min ; fourth step: removing the first three steps brought about by the polymer etch residues in the bottom of the contact hole; fifth step: removing the silicon nitride etch stop layer suspension; sixth step: etching the bottom oxide film.
  2. 2、 如权利要求1所述的嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,其特征在于,第一步刻蚀的主要参数为:压力为30-90毫托;上/下电极功率为800-1200/800-1200瓦;氩气为150-250sccm;三氟甲烷为15-25sccm;氧气为5-25sccm;背部氦气压力为中部4-12托,边缘10-20托。 2, the embedded flash memory device as claimed in claim 1 in suspension etching method for etching the contact hole barrier layer, characterized in that the first step of etching the main parameters are: pressure of 30 to 90 mTorr; the / bottom electrode power 800-1200 / 800-1200 W; argon gas 150-250sccm; trifluoromethane of 15-25sccm; oxygen-5-25sccm; back central 4-12 torr of helium pressure, the edges 10-20 care.
  3. 3、 如权利要求1所述的嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,其特征在于,第二步刻蚀的主要参数为:压力为30-90毫托; 上/下电极功率为1500-2400/800-1600瓦;氩气为500-1000sccm;八氟五碳为5-15sccm;氧气为8-25sccm;背部氦气压力为中部4-12托,边缘10-20托。 3, the embedded flash memory device as claimed in claim 1 in suspension etching method for etching the contact hole barrier layer, characterized in that the second step of etching the main parameters are: pressure of 30 to 90 mTorr; the / 1500-2400 bottom electrode power / 800-1600 W; argon gas 500-1000sccm; octafluoro five carbon 5-15sccm; oxygen-8-25sccm; back central 4-12 torr of helium pressure, the edge of 10- 20 Torr.
  4. 4、 如权利要求1所述的嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,其特征在于,第三步刻蚀的主要参数为:压力为30-90毫托;上/下电极功率为1500-2400/800-1600瓦;氩气为500-1000sccm;八氟五碳为6-20sccm;氧气为8-20sccm;背部氦气压力为中部4-12托,边缘10-20托。 4, the embedded flash memory device as claimed in claim 1 in suspension etching method for etching the contact hole barrier layer, characterized in that the third step of etching the main parameters are as follows: a pressure of 30-90 mtorr; the / 1500-2400 bottom electrode power / 800-1600 W; argon gas 500-1000sccm; octafluoro five carbon 6-20sccm; oxygen-8-20sccm; back central 4-12 torr of helium pressure, the edge of 10- 20 Torr.
  5. 5、 如权利要求1所述的嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,其特征在于,第三步中追加50%的过刻蚀。 5, an etching method as claimed in contact hole blocking layer suspension etching embedded flash memory device according to claim 1, characterized in that the third step is added a 50% overetching.
  6. 6、 如权利要求1所述的嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,其特征在于,第四步刻蚀的主要参数为:压力为15-35毫托; 上/下电极功率为700-1400/100-300瓦;氩气为100-300sccm;氧气为10-30sccm;背部氦气压力为中部4-12托,边缘10-30托。 6, the embedded flash memory device as claimed in claim 1 in suspension etching method for etching the contact hole barrier layer, characterized in that the fourth step of etching the main parameters are: pressure of 15 to 35 mTorr; the / bottom electrode power 700-1400 / W 100-300; 100-300 argon gas; oxygen-10-30sccm; back central 4-12 torr of helium pressure, the edges 10-30 Torr.
  7. 7、 如权利要求1所述的嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,其特征在于,第五步刻蚀的主要参数为:压力为30-50毫托; 上/下电极功率为700-1500/100-300瓦;氩气为100-300sccm;三氟甲烷为8-25sccm;氧气为10-30sccm;背部氦气压力为中部4-15托,边缘10-30 托。 7, an embedded flash memory device as claimed in claim 1 in suspension etching method for etching the contact hole barrier layer, characterized in that the fifth step of etching the main parameters are as follows: a pressure of 30-50 mtorr; the / 700-1500 bottom electrode power / W 100-300; 100-300 argon gas; trifluoromethane of 8-25sccm; oxygen-10-30sccm; back central 4-15 torr of helium pressure, the edges 10-30 care.
  8. 8、 如权利要求1所述的嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,其特征在于,第六步采用和第二步相同的条件:保持刻蚀速率为7500-7800埃/分钟,氧化硅对氮化硅的选择比为10:1-13:1。 8, an etching method as claimed in contact hole blocking layer suspension etching embedded flash memory device according to claim 1, characterized in that the sixth step and the second step using the same conditions: the etching rate is kept 7500- 7800 Å / min, a silicon oxide nitride selection ratio of 10: 1-13: 1.
  9. 9、 如权利要求1所述的嵌入式闪存器件中悬浮式刻蚀阻挡层接触孔的刻蚀方法,其特征在于,第六步刻蚀的主要参数为:压力为30-80毫托; 上/下电极功率为1500-2500/800-1800瓦;氩气为500-1000sccm;八氟五碳为5-15sccm;氧气为8-25sccm;背部氦气压力为中部4-15托,边缘10-30托。 9, the embedded flash memory device as claimed in claim 1 suspended in an etching method of etching the contact hole barrier layer, characterized in that the sixth step of etching the main parameters are: pressure of 30 to 80 mTorr; the / 1500-2500 bottom electrode power / 800-1800 W; argon gas 500-1000sccm; octafluoro five carbon 5-15sccm; oxygen-8-25sccm; back central 4-15 torr of helium pressure, the edge of 10- 30 Torr.
CN 200610119567 2006-12-13 2006-12-13 Method for etching suspending type etch blocking layer contact hole in embedded flash memory device CN100524691C (en)

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CN101625993B (en) 2008-07-08 2011-05-11 中芯国际集成电路制造(上海)有限公司 Dual-damascene structure and manufacturing method thereof
CN102403218A (en) * 2010-09-09 2012-04-04 上海华虹Nec电子有限公司 Etching method for contact holes
CN102623396A (en) * 2012-04-17 2012-08-01 上海华力微电子有限公司 Method for forming connection holes
CN102683273A (en) * 2012-05-04 2012-09-19 上海华力微电子有限公司 Method for forming contact holes
CN103633106A (en) * 2013-11-28 2014-03-12 上海华力微电子有限公司 CMOS (complementary metal oxide semiconductor) contact hole etching method and CMOS manufacturing method
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US6326300B1 (en) 1998-09-21 2001-12-04 Taiwan Semiconductor Manufacturing Company Dual damascene patterned conductor layer formation method
US6420752B1 (en) 2000-02-11 2002-07-16 Advanced Micro Devices, Inc. Semiconductor device with self-aligned contacts using a liner oxide layer
US7259050B2 (en) 2004-04-29 2007-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of making the same
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CN101625993B (en) 2008-07-08 2011-05-11 中芯国际集成电路制造(上海)有限公司 Dual-damascene structure and manufacturing method thereof
CN102403218A (en) * 2010-09-09 2012-04-04 上海华虹Nec电子有限公司 Etching method for contact holes
CN102403218B (en) 2010-09-09 2013-07-24 上海华虹Nec电子有限公司 Etching method for contact holes
CN103828029A (en) * 2011-09-29 2014-05-28 东京毅力科创株式会社 Deposit removal method
CN103828029B (en) * 2011-09-29 2016-06-15 东京毅力科创株式会社 Deposit removal method
CN102623396A (en) * 2012-04-17 2012-08-01 上海华力微电子有限公司 Method for forming connection holes
CN102683273A (en) * 2012-05-04 2012-09-19 上海华力微电子有限公司 Method for forming contact holes
CN103633106A (en) * 2013-11-28 2014-03-12 上海华力微电子有限公司 CMOS (complementary metal oxide semiconductor) contact hole etching method and CMOS manufacturing method
CN103633106B (en) * 2013-11-28 2016-06-29 上海华力微电子有限公司 Cmos sensing device and a method of etching a contact hole cmos sensor device manufacturing method

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