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CN101176189B - 低介电常数隐晶层及纳米结构 - Google Patents

低介电常数隐晶层及纳米结构 Download PDF

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CN101176189B
CN101176189B CN 200680017063 CN200680017063A CN101176189B CN 101176189 B CN101176189 B CN 101176189B CN 200680017063 CN200680017063 CN 200680017063 CN 200680017063 A CN200680017063 A CN 200680017063A CN 101176189 B CN101176189 B CN 101176189B
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S·卡勒姆
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土耳其科学和技术研究委员会
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Abstract

本发明提供一种用于在现有技术半导体晶片上制造应用特性低介电常数(低k)隐晶层和用于由隐晶制造有机化的纳米结构的方法,并涉及到光学和电子器件,其可由这些材料获得。在此公开的结果表明使用化学汽相处理(CVP)的单晶基质的结构和化学成分的改性导致高质量隐晶层,所述隐晶层是均质的且与半导体晶片形成光滑界面。通过该方法,对于介电隐晶层形成可实现1μm/小时那样高的生长速度。本发明还提供一种方法,用于通过将隐晶转变成有机化的系统制造微米和纳米线。通过该方法,能制造尺寸从几纳米到1000纳米且长度达50微米的纳米线。隐晶、纳米线和有机化的结构可用在未来的互连中作为级间和金属间电介质,用在制造超高密度存储单元中,用在信息安全中作为密钥产生器,用在制造光电部件和传感器中。

Description

低介电常数隐晶层及纳米结构技术领域

[0001] 本发明涉及一种低介电常数隐晶,其可与下一代集成电路和器件结合使用。这些 隐晶通过化学汽相处理(CVP)方法[S. Kalem 和 0. Yavuz,OPTICS EXPRESS 6,7(2000)]来 生长,其包括将硅表面暴露于酸性混合物蒸汽。隐晶表示一种如此精细地成粒状以致在光 学显微镜下不能分辨出不同的颗粒的材料。具有这种微小晶体的以这种方式设置的物质的 状态称作隐晶。这种类型的晶体能显示出特别的介电特性,其可用于多种领域中。背景技术

[0002] 关于上述光学特性介电氟化X铵隐晶在文献中没有报道。

[0003] 当氟化铵NH4F与晶片表面上的Si反应时显示在硅晶片上形成了氟化硅铵(ASiF) 材料[M. Niwano, K. Kurita, Y. Takeda 禾口 N.Miyamoto, Applied Physics Letters 62, 1003(1993)]。

[0004] 如在另一文献中说明的,在等离子体辅助半导体清洗和沉积处理期间在真空室 的壁上和真空排气线中发现了氟化硅铵[S. Munley, I. McNaught, D. Mrotek,和C. Y. Lin, Semiconductor International,10/1, (2001)]。

[0005] 也已经表明,使用HF/HN03能从多孔硅获得氟化硅铵的发光粉末[M. Saadoun, B.Bessais, N. Mliki, M. Ferid, H/Ezzaouia 禾口 R. Bennaceur, Applied Surface Science 210,240(2003)] ο

[0006] 相^以地,[H. 0gawa,T. Arai,M. Yanagisawa,Τ. Ichiki禾口Y. Horiike,Jpn. J. Applied Physics 41,5349(2002)]已经示出,当剩余的天然(natural)氧化物与晶片表面上的热铵 (NH3)和氟化氮(NF3)反应时,氟化硅铵形成于硅晶片上。

[0007] 而且,报道了当HF和NH3气体于真空下在SiO2上反应时形成了氟化硅铵 [P. D. Agnello, IBM J.of Research and Development 46,Number 2/3,2002)]。

[0008] 在上述文献中没有应用特性隐晶结构。而且,在这些文献中,获得的是一种无意 的、无规则的、杂乱且被产物污染的氟化硅铵。

[0009] 文献中没有关于氟化X铵的微米和纳米线的报道。

[0010] 关于氟化X铵隐晶的介电常数能在很大范围内被调节且其可用作绝缘体的事实 没有报道。

[0011] 微电子线路和纳电子线路是本发明最重要的应用领域。根据hternational Road Map for Semiconductors (ITRS)[C. Case, Solid StateTechnology, Jan. ,47(2004)] [P. Zeitzoff, R. W. Murto, H. R. Huff, Solid StateTechnology, 71 (2002)],半导体工业需要 一种低介电常数(k)的金属间绝缘体,其介电常数大大低于k = 3. O。工业上期待低k解决 方案。因此,开发一种与下一代集成电路(IC)制造相兼容的低k电介质是非常重要的。另 一方面,继续努力寻找一种用于栅绝缘的高k电介质。

[0012]根据历史上的摩尔定律[G. E. Moore, Electronics 38,114(1965)] [G. Ε. Moore, IEDM Technical Digest, Washington DC,11 (1975)],在 CMOS 技术中继续按比例缩小。需要多级金属化以适应多个有源元件的信号集成。这些金属互连中的电阻和寄生电容是限制 下一代系统中ic性能的重要因素。这引起工业从铝/SiO2R移向铜/低k结构。虽然铜 降低了线电阻,但是低k电介质降低了金属线之间的寄生电容。

[0013] 为了克服晶体管尺寸的按比例缩小中的困难,每单位面积的电容要保持恒定。 因此,需要一种高k值电介质。这些电介质可以是氧化物和硅酸盐如A1203、ZrO2, HFO20 C. J. Parker, G. Lucovsky 禾口 J. R. Hauser, IEEE Electron. Device Lett. (1998) ;Y. Wu 禾口 G.Lucovsky, IEEEElectron. Device Lett (1998) ;H.Yang 禾口 G. Lucovsky, IEDM Digest, (1999)已经提出了使用这些材料的解决方案。然而,对于克服关于经济成本和界面缺陷数 量存在非常困难的挑战。本发明的隐晶技术能提供该领域中的潜在解决方案。例如,保持 原生(native)栅极氧化物的优点,可以使用隐晶形成高k电介质。

[0014] 集成电路中的金属线通过介电绝缘体相互电绝缘。随着IC尺寸变得更小,金属线 之间的距离降低,由此导致增加的电容。这导致RC延迟,功率损失,电容感应信号或串扰。

[0015] 使用具有低于SW2的介电常数的介电常数的聚合物作为互连绝缘体。但是,聚合 物不坚固的事实是重要的缺点。

[0016] 掺杂碳的氧化物是低k电介质的解决方案。可以获得具有小于3. O的介电常数的 氧化物。然而,关于使用寿命其表现出很大的缺点。

[0017] IC制造中通过降低有源电路元件的尺寸获得的性能特性在互连和封装元件中可 能会损失。在这种情况下,不是晶体管的速度而是互连的RC延迟变得重要。而且,随着降 低尺寸,需要更深的金属线,由此使得金属间电容比级间电容更重要。为了克服这些困难, 需要极好的低k电介质和新的制造方法。当前的低k电介质由氧化物和聚合物构成。隐晶 可以是潜在的解决方案。由此,能通过避免相邻电路之间的串扰实现高性能IC。

[0018] 一种解决方案是使用气隙降低电容的方法[B. Shieh等人,IEEEElectron Device Letters,19, no.1, p.16-18 (1998)][D. L. ffollesen, Lowcapacitance interconnection, 美国专利号No :5, 900, 668,1999年5月4日提交]。在这些解决方案中,SiO2已经用作级 间和金属间电介质。美国专利号Nos. US 5,470,802,US 5,494,858、US 5,504,042和US 5,523,615专利涉及通过气隙降低电容的可能性。但是在这些方法中,粗糙的(harsh)化 学物质应当用于形成气隙。隐晶技术在制造气隙中可提供更简单、无损伤、低成本的解决方 案。发明内容

[0019] 本发明涉及ASiF隐晶,其介电值能通过几种方法调节并且能在Si和Si基晶片上 合成。通过扩散,ASiF隐晶的介电常数能从其最小值1. 50调节到较高得多的值(所需的)。 由此,隐晶能具有其它特性如铁电体性和光发射。

[0020] 本发明对于低成本和高性能的低k技术提供一种重要的替换方案。因为其是从潜 在的集成电路晶片获得的并具有低于2. 00的介电常数。该值比2007年及之后的ITRS所 预测的更小。

[0021] 本发明在Si CMOS技术和GaAs技术中、在增加异质结双极型晶体管(HBT)特性、 高密度信息存储和信息安全、微电子封装、光电部件制造、IC系统冷却、技术集成和传感器 制造方面具有重要的应用。附图说明

[0022] 以下的图涉及到隐晶特性、隐晶层制造方法和能使用隐晶层的器件。

[0023] 图1,隐晶制造装置,其由聚四氟乙烯制成,由包含液体的腔室、样品夹具 (holder)、蒸汽排气通道和加热器构成。

[0024] 图2,其中设置了晶片的样本夹具的详细绘图。

[0025] 图3,在极化光学显微镜下获得的用上述装置生长的隐晶层的表面图像。

[0026] 图4,利用扫描电子显微镜(SEM)在3. 000放大倍数下获得的隐晶层的截面显微照 片。隐晶结构的细节与图3相比能更好地看到。该隐晶层的厚度是21 μ m。

[0027] 图5,用7. 500的放大倍数以SEM看到的隐晶和晶片之间的界面。清楚地示出了表 面质量和隐晶从晶片的衍生。存在相对光滑的界面且隐晶层很好地贴附到晶片。

[0028] 图6,X射线衍射分析示出了层是(NH4)2SiF6,且晶体属于具有Fm;3m空间群的 (4/m-32/m)等足巨六乂V 面体(isometric hexoctahedral)系[W. L. Roberts, G. R. Rapp 禾口 Τ· J. Cambe 11, Enc. of Minerals, 2ndEd. ,Kluwer Academic Publishers, Dordrecht, 1990]。

[0029] 图7,示出了在退火之后表面处的变化。尽管在退火期间没有保护该表面,但是在 200°C之后仍有一部分隐晶层没有分解且仍粘着到该表面。而且,在该表面上形成大晶体。

[0030] 图8,可以选择性地写到晶片表面上来形成光刻结构而不使用光刻。该图示出了这 种试验的结果。

[0031] 图9,隐晶的另一个重要特征在于其能被转变成微米和纳米线。可以形成直的线且 尺寸在从几纳米到IOOOnm的范围内,如图中所示。通过该方法,可以制造长度高达100 μ m 的直的线。

[0032] 图10,X射线衍射分析的结果已经借助通过存在(NH4)2SiF6分组的振动模式的 FIlR分析而被证实。该分析表示所观察的在480cm-l、725cm-l、1433cm-l和3327cm_l的振 动模式属于N-H和Si-F结合(bonding)。

[0033] 图11,该图示出了在基极-集电极和源极-集电极之间的电容可以怎样使用隐晶 方法被降低。

[0034] 图12,用于产生随机数的隐晶芯片。作为窗口的隐晶层正好位于激光器或者LED 腔前面。

[0035] 图13,通过隐晶层的激光散射和物理单向函数(one-way function)的产生。

[0036] 以下给出图中的数字和其相应部分:

[0037] 1.晶片或衬底

[0038] 2.气体排气通道

[0039] 3.聚四氟乙烯容器

[0040] 4.蒸汽室

[0041] 5.化学混合物

[0042] 6.温度计

[0043] 7. Ph 计

[0044] 8.聚四氟乙烯块

[0045] 9.液体提取阀[0046] 10.氮闪蒸阀(flashing valve)

[0047] 11.工艺室口

[0048] 12. ASiF 隐晶

[0049] 13.晶片和隐晶界面

[0050] 14. (111)主衍射峰

[0051] 15.单 ASiF 晶体

[0052] 16.选择性形成于Si上的隐晶点

[0053] 17. ASiF微米和纳米线

[0054] 18. N-H振动模式

[0055] 19. Si-O 振动模式

[0056] 20. Si-F 振动模式

[0057] 21.变形模式

[0058] 22.晶体管栅极金属

[0059] 23.晶体管源极金属

[0060] 24.源极

[0061] 25.漏极金属

[0062] 26.漏极

[0063] 27.栅极氧化物层(SiO2)

[0064] 28. HBT 集电极

[0065] 29.隐晶HBT源区

[0066] 30.隐晶HBT漏区

[0067] 31.异质双极型晶体管(HBT)基区

[0068] 32. VECSEL 有源区

[0069] 33.保护层

[0070] 34.绝缘体

[0071] 35.顶部布拉格反射器

[0072] 36.底部布拉格反射器

[0073] 37.隐晶透明窗口

[0074] 38.通过隐晶的He-Ne激光散射具体实施方式

[0075] 已经研究出一种用于在硅(Si)和Si基晶片上合成氟化硅铵(ASiF)的方法。在该 方法中,我们使用我们已经研究出的汽相生长技术[S. Kalem和OJavuz,OPTICS EXPRESS 6,7 (2000)]。通过该方法,我们通过使氢氟酸(HF)和硝酸(HNO3)的蒸汽在晶片表面上反 应来生长隐晶层。具有白粒状颜色的隐晶层在晶片上以Iym/小时的生长速度合成。

[0076] 该技术的优点是:i)不需要电接触,ii)可以在表面上选择性写入,iii)层是同质 的,iv)能控制厚度,V)可以形成扩散阻挡,Vi)与其它常规技术相比节省成本。

[0077] 当常规化学制剂的混合物蒸汽在晶片上反应时,隐晶氟化硅铵层 (NH4)2SiF6(ASiF)形成于现有技术晶片上。该方法称作化学汽相处理(CVP)并包括以下步骤:

[0078] a)准备聚四氟乙烯生长室和超声清洗工艺;

[0079] b)制备包含比率为G-10) : (1-8)的HF、HNO3的化学制剂混合物和25-50%的 氢氟酸(HF)以及55-75%的硝酸(HNO3);

[0080] c)用氮气冲洗该混合物并以一片晶片共腾(priming)该混合物10秒;

[0081] d)用待处理的晶片完全封闭室口 ;

[0082] e)确保反应产物通过排气通道从腔室中排空;

[0083] f)控制Ph和温度;

[0084] g)通过在晶片上HF和HNO3种类之间的遵循以下反应式的硅居间耦合反应,隐晶 层形成于晶片上:

[0085] X+6HF+2HN03 — (NH4) 2XF6+302

[0086] 其中X可以是Si、Ge或C。

[0087] h)晶片Wlym的速度被转变成隐晶层;

[0088] i)可以退火隐晶层并且能增强其强度和密度;

[0089] j)在氮气氛下在50°C以上将隐晶转变为纳米结构且特别是微米和纳米线。

[0090] 这里是在隐晶层制造中使用的晶片特性:

[0091] 1.在5-10欧姆-cm之间的电阻率

[0092] 2. ρ型、硼掺杂、(100)和(111)取向的Si

[0093] 3. η型、磷掺杂、(100)和(111)取向的Si

[0094] 4.在硅Si02/Si上的硅原生氧化物(热氧化物)

[0095] 5.化学计量的硅上 Si3N4(Si/Si3N4)

[0096] 6. SihxGex, χ < 0. 3 (Si 上 Si1^xGex)

[0097] 隐晶制造装置由衬底(1)、用于产物(2)反应的气体排气通道、聚四氟乙烯容器 (3)、蒸汽处理室(4)、化学制剂混合物(5)、Ph计(7)、化学制剂提取门(9)、加热器(8)和 温度控制器(6)、室口和样品夹具(11)以及氮闪蒸(10)。

[0098] 隐晶层由不可辨别的颗粒(1¾形成,如通过光学极性显微镜和甚至通过扫描电 子显微镜(SEM)表明的。此外,其具有光滑界面(13)并且很好地集成到晶片上,如SEM界 面研究所表明的。

[0099] X射线衍射分析表明隐晶优先在<111>方向(14)上生长。衍射峰及其相对强度在 表1中总结。

[0100] 表1,总结在ASiF隐晶中观察到的衍射峰的X射线衍射数据。其中,teta、d和I/ Il分别是衍射角度、平面之间的距离和标准化的衍射强度。

[0101]峰编号: 2Teta(度) d (埃=I(T8Cm) I/I11 18.3401 4. 83355 1002 21. 2009 4. 18734 198

Figure CN101176189BD00091

[0102] 具有白色的隐晶(12)以规则薄层形式形成于晶片(1)上。退火试验表明ASiF停 留在高达约150°C的表面上。其在该温度以上分解。

[0103] 根据退火温度,ASiF的体晶(15)形成于该表面上。这些晶体的尺寸可以高达 15 μ mX 30 μ m。

[0104] 隐晶可选择性地实现为晶片上的点(16)。

[0105] 制造尺寸从几纳米直到一微米且长度高达50 μ m的纳米线(17)。而且,制造多种 纳米结构且特别是纳米支路。

[0106] ASiF隐晶的室温光学特性显示出振动峰,如表2中所总结的。频率与ASiF中 N-H(IS)、Si-O (19)和(ve)Si-W20)的各种结合结构的振动相关。Si-O振动与界面处氧化 物层的存在有关。

[0107] 表2,ASiF隐晶的FTIR数据总结,其中VS :非常坚固,S :坚固,M :中间,W :弱,Vff :非常弱。

[0108]

Figure CN101176189BD00092

[0109] FTIR 分析表明 ASiF 在 3 μ m(18)、7 μ m(18)、13· 6 ym(20)和 20. 8 ym(21)具有强吸收凹槽,且由此其可用在光学应用中。

[0110] 在本发明的另一应用中,隐晶层位于(异质双极型晶体管,HBT)晶体管中的源 极03)-集电极08)和漏极05)-集电极08)之间,以降低电容并由此提高HBT的高 频性能。上述电容在III-V族化合物半导体基(GaAs/AlGaAs bazl》HBT[Μ· Mochizuki, Τ· Nakamura,Τ· Tanoue 禾口 H. Masuda,Solid State Electronics 38,1619 (1995)]禾口 SiGe基 HBT[U.K5nig和 H. Dambkes,Solid State Electronics 38,1595(1995)]中起到非常重要 的作用。在这种器件中,隐晶层位于基区(31)的两侧和源区09)和漏区(30)的下方。在 该结构中,在形成晶体管结构之后,基极的两侧已经使用上述方法被转变成隐晶。

[0111] 通过增加对超高密度和高速应用的需要,对新的高性能信息存储系统有增加的 兴趣[H. Coufal 和 G. W. Burr, International Trends in Optics, 2002][美国专利号 No. 6,846,434]。在本发明的另一应用中,我们提供了解决高性能信息存储的替换解决方 案。使用隐晶,可以在电子晶片上获得高密度存储单元00)。在该应用中,已经可以在硅 基晶片上通过形成隐晶单元(16)选择性写入。隐晶在相对低的温度下可能具有相位变化 (16)的事实提供了擦除和改写的可能性。由此,低温下的快速相位变化特征能实现快速写 入应用。而且,通过ASiF隐晶的8. 5nm单位单元尺寸,可获得数量级为Tb/cm2的信息存储 密度。在该领域中由隐晶技术引入的新颖性在于:i)可以在微电子晶片上写入而不进行光 刻,ii)以Tb/cm2的范围提供高密度信息存储,iii)高速擦除和改写。

[0112] 在信息安全应用中,隐晶用在垂直腔激光器或者LED中[A. C. Tpper, H. D. Foreman, A. Garnache, K. G. Wilcox, S. H. Hoogland, J. Phys, D :Appl. Phys. 37, R75 Q004)],正好在有源区(32)和顶部布拉格反射器(35)上方形成隐晶窗口(37)。由此, 激光器或LED表面已经被转变成透明窗口。在此,ASiF必须通过帽盖层(33)保护。利用 这种激光器/LED芯片能产生物理单向函数。He-Ne激光器自ASiF(38)的散射示出了可行 性。该散射表明存在随机结构。这证明在信息安全中隐晶可用于产生安全密钥。与CMOS 应用[A. Fort, F. Cortigiani, S. Rocchi 禾口 V. Vignoli, Analog Integrated Circuits and Signal Processing34,97 (2003)]和使用无源元件的其它光学应用[R. Pappu,B. Recht, J. Taylor和N. Gershenfeld, Science 297,2026(2002)]相比,该方法更加节省成本且能够 更好地集成到IC。

[0113] 本发明能用于将两个晶片结合在一起。该方法包括通过CVP和在高温在H20、氮气 和氢气(H2)下按压两个晶片在两个晶片的表面上形成隐晶层。

Claims (11)

1. 一种晶片结合方法,包括以下步骤:a)冲洗HF和HNO3的化学制剂混合物,并在聚四氟乙烯容器(3)中形成化学制剂蒸汽, 其中[HF]/[HN03]体积比率被调整为G-10) : (1-8),b)以一片硅晶片共腾混合物10秒,c)用待处理的晶片覆盖反应室的室口,d)确保通过排气通道排空反应产物和反应室中的过压,e)调整温度在10°C -50°C之间(6),这导致隐晶生长速度为1 μ m/h,f)以Si或Ge或C居间反应使HF和HN03、H2O的蒸汽在晶片X表面上反应,由此在晶 片表面上形成具有平滑界面的同质隐晶层,其中X为Si、Ge或C,g)在吐0、氮气或氢气下在高温下按压晶片表面。
2.如权利要求1所述的方法,其中隐晶层在50°C -200°C的热处理下在氮气氛中被转变 成微米和纳米线。
3.如权利要求1所述的方法,其中所使用的酸是电子级的且按重量为25% -50%氢氟 酸和55% -75%硝酸。
4.如权利要求1所述的方法,其中所述晶片是SihGe^
5.如权利要求4所述的方法,其中Ge的成分比率χ在0. 01和0. 50之间。
6.如权利要求1所述的方法,其中隐晶是无机物且其介电常数是可调的。
7.如权利要求1所述的方法,其中隐晶的介电常数能通过蒸发和扩散调整。
8.如权利要求1所述的方法,其中隐晶的介电常数低于2.0且根据应用,所述介电常数 能通过元素结合被设置在所需值。
9.如权利要求1所述的方法,其中所述隐晶通过扩散能够具有磁性和光学发射特性。
10.如权利要求1所述的方法,进一步包括在形成隐晶层之后在隐晶层上在50-400°C 之间执行退火。
11.如权利要求10所述的方法,其中退火通过热加热和辐射实现。
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US5470802A (en) * 1994-05-20 1995-11-28 Texas Instruments Incorporated Method of making a semiconductor device using a low dielectric constant material
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JPH10158010A (ja) * 1996-11-26 1998-06-16 Matsushita Electric Works Ltd 酸化珪素被膜の製造方法
US6468927B1 (en) * 2000-05-19 2002-10-22 Applied Materials, Inc. Method of depositing a nitrogen-doped FSG layer
JP2002039927A (ja) * 2000-07-19 2002-02-06 Toshiba Ceramics Co Ltd シリコンウェーハ表層の部分分析方法
JP2004123484A (ja) * 2002-10-04 2004-04-22 Crystal System:Kk 金属酸化物膜およびその用途
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Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
JP昭64-10614A 1989.01.13
M.Saadoun et al..Vapour-etching-based porous silicon: a new approach.Thin Solid Films405 1-2.2002,30-31.
R.W.Fathauer et al..Visible luminescence from silicon wafers subjuctedto stainetches.Applied Physics Letters60 8.1992,995-997.
S.Kalem et al..Possibility of fabricating light-emitting porous silicon from gasphase etchants.Optics Express6 1.2000,7-11.
S.Kalem.possible low-k solution and other potential applications.European Semiconductor26 7.2004,31-34.
S.Kalem.Synthesis of ammonium silicon fluoride cryptocrystals onsilicon by dry etching.Applied Surface Science236 1-4.2004,336-341.

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