CN101174801A - Less-switch five-power level voltage source type inverter and control method thereof - Google Patents

Less-switch five-power level voltage source type inverter and control method thereof Download PDF

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CN101174801A
CN101174801A CNA2007101445233A CN200710144523A CN101174801A CN 101174801 A CN101174801 A CN 101174801A CN A2007101445233 A CNA2007101445233 A CN A2007101445233A CN 200710144523 A CN200710144523 A CN 200710144523A CN 101174801 A CN101174801 A CN 101174801A
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igbt1
igbt3
igbt6
igbt5
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CN100566111C (en
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曾繁鹏
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HEILONGJIANG BUSINESS VOCATIONAL TECHNOLOGY COLLEGE
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HEILONGJIANG BUSINESS VOCATIONAL TECHNOLOGY COLLEGE
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Abstract

A five-level voltage source inverting device with few switches and a control method thereof relate to the technological field of a multilevel voltage source inversion, aiming to solve the problem that the complicated topological structure and the control method of a prior multilevel power conversion circuit limit the application of the multilevel inverter in actual usage. The tandem connected C1 and C2 are in bridge connection with the two output ends of the rectifier bridge B, one output end of which is connected with one input end of an H type bridge component consisting of an IGBT3-6 through a voltage control component consisting of an IGBT1-2, the other input end of the H type bridge component is connected with the other output end of the rectifier bridge B. The method and the procedures are as follows, set t0-t18, and t1'-t18' as the time when the positive half, the negative half of a sine wave and a triangular wave cross. A DSP circuit (1) controls the IGBT1-6 through a driving/ photoelectric isolation circuit (2) to conduct or close according to the time t0-t18, and t1'-t18'. The circuit structure of the present invention uses fewer components, the control method is simple and reacts rapidly, and therefore the present invention can be widely promoted.

Description

A kind of less-switch five-power level voltage source type inverter and control method thereof
Technical field
The present invention relates to the technical field of a kind of voltage with multiple levels source type inversion.
Background technology
In recent years, along with the development in an all-round way of power electronics and control technology, power electronic equipment is widely used.People are more and more stronger to the requirement of the high pressure of power electronic equipment, high-power, high frequencyization, low harmonic disturbance.Multi-electrical level inverter has characteristics such as power capacity is big, switching frequency is low, output harmonic wave is little, response speed is fast, Electro Magnetic Compatibility is good.And can make the lower all-controlling power electronics device of withstand voltage reliably be applied to the high-power field, and effectively reduce PWM and control the high order harmonic component that produces, but, the topological structure of many level power translation circuit and control method be comparatively complicated, suppressed multi-electrical level inverter promoting the use of in practice.
Summary of the invention
The topological structure and the control method that the objective of the invention is in order to solve existing many level power translation circuit are comparatively complicated, and have suppressed the problem that multi-electrical level inverter is promoted the use of in practice.And then provide a kind of less-switch five-power level voltage source type inverter and control method thereof.
The inventive system comprises rectification full-bridge B, electrochemical capacitor C1, electrochemical capacitor C2, IGBT1, IGBT2, IGBT3, IGBT4, IGBT5, IGBT6, inductance L, DSP circuit 1, driving/photoelectric isolating circuit 2;
Two ac input ends of rectification full-bridge B connect ac power output, the positive terminal of rectification full-bridge B, the positive terminal of electrochemical capacitor C1 connects the collector electrode of IGBT1, the negative pole end of electrochemical capacitor C1, the emitter of IGBT2 connects the positive terminal of electrochemical capacitor C2, the collector electrode of IGBT2, the emitter of IGBT1, the collector electrode of IGBT3 connects the collector electrode of IGBT5, the emitter of IGBT3, the collector electrode of IGBT4 connects an end of inductance L, the other end of inductance L is first output, the emitter of IGBT5 connects the collector electrode of IGBT6 and is second output, the emitter of IGBT4, the emitter of IGBT6, the negative pole end of electrochemical capacitor C2 connects the negative pole end of rectification full-bridge B, the grid of IGBT1, the grid of IGBT2, the grid of IGBT3, the grid of IGBT4, the grid of IGBT5, the grid of IGBT6 connects six drive control signal outputs of driving/photoelectric isolating circuit 2 respectively, and the control signal input bus end of driving/photoelectric isolating circuit 2 connects the control signal output bus end of DSP circuit 1.
Less-switch five-power level voltage source type inversion controlling method step of the present invention is:
Step 1, whole device power up startup, establish t 0~t 18Be the moment that the positive half wave and the triangular wave of sine wave intersects, t 1'~t 18' be the negative half-wave of sine wave and the moment that triangular wave intersects;
Step 2, at moment t 0The time, DSP circuit 1 is by 2 control IGBT4 and the IGBT6 conductings of driving/photoelectric isolating circuit, and IGBT1, IGBT2, IGBT3 and IGBT5 end, and remain to t constantly 1The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 2The time DSP circuit 1 by 2 control IGBT4 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT2, IGBT3 and IGBT5 end, and remain to moment t 3The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 4The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 5The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 6The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 7The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 8The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and reach the maximum of the positive half wave of sine wave;
Step 3, remain to t constantly 9The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 10The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 11The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 12The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 13The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 14The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 15The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 16The time DSP circuit 1 by 2 control IGBT4 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT2, IGBT3 and IGBT5 end, and remain to moment t 17The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 18The time DSP circuit 1 by 2 control IGBT4 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT2, IGBT3 and IGBT5 end, and reach sinusoidal wave positive half wave to the zero crossing of bearing half-wave;
Step 4, remain to t constantly 1In ' time, DSP circuit 1 is by 2 control IGBT2, IGBT4 and the IGBT5 conductings of driving/photoelectric isolating circuit, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 2In ' time,, DSP circuit 1 was controlled IGBT3 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT2, IGBT4 and IGBT6 end, and remain to t constantly 3In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 4In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 5In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 6In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 7In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 8In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 9In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and reach the maximum of the negative half-wave of sine wave;
Step 5, remain to t constantly 10In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 11In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 12In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 13In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 14In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 15In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 16In ' time,, DSP circuit 1 was controlled IGBT3 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT2, IGBT4 and IGBT6 end, and remain to t constantly 17In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 18In ' time,, DSP circuit 1 was controlled IGBT3 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT2, IGBT4 and IGBT6 end, and reach the zero crossing of the negative half-wave of sine wave to positive half wave;
Step 6, return operating procedure two.
The employed component number of circuit structure of the present invention is few, and its control method is simple, response speed is fast, and has realized long, the advantage of Maintenance and Repair easily of cheap for manufacturing cost, life-span, and then can large-scale popularization use.Main feature of the present invention is:
1, the desired power switching device is few.This invention is to increase by two power switchs on the basis of traditional H bridge voltage source inventer.Like this, by these six power switchs, just can be implemented in five kinds of different level of AC side output.
2, need not clamp diode and clamp capacitor.The circuit topological structure that the present invention proposes does not need clamp diode and clamp capacitor.Reduce the usage quantity of device, simplified circuit structure.
3, control is simple.Because switching device is few, do not have characteristics such as clamp diode and clamp capacitor, and this circuit topological structure can be divided into two parts: the first that forms by IGBT1 and IGBT2; Traditional H bridge type inverter of forming by IGBT3, IGBT4, IGBT5 and IGBT6.The effect difference of these two parts, wherein first is responsible for control inverter ac output end voltage for ± E or be ± 2E; And concrete output polarity (promptly+,-number choose) be responsible for control by second portion.So the control to this circuit is fairly simple, according to different needs, control respectively.
Description of drawings
Fig. 1 is the integrated circuit structural representation of apparatus of the present invention, and Fig. 2 is t in the control method of the present invention 0~t 18, t 1'~t 18The selection rule schematic diagram of ' moment point, Fig. 3 are the output voltage waveforms of instantiation (inverter), and Fig. 4 is the voltage oscillogram at the load resistance two ends of instantiation (inverter).
Embodiment
Embodiment one: 1 present embodiment is described in conjunction with the accompanying drawings, present embodiment is made up of rectification full-bridge B, electrochemical capacitor C1, electrochemical capacitor C2, IGBT1 (igbt), IGBT2, IGBT3, IGBT4, IGBT5, IGBT6, inductance L, DSP circuit 1, driving/photoelectric isolating circuit 2;
Two ac input ends of rectification full-bridge B connect ac power output, the positive terminal of rectification full-bridge B, the positive terminal of electrochemical capacitor C1 connects the collector electrode of IGBT1, the negative pole end of electrochemical capacitor C1, the emitter of IGBT2 connects the positive terminal of electrochemical capacitor C2, the collector electrode of IGBT2, the emitter of IGBT1, the collector electrode of IGBT3 connects the collector electrode of IGBT5, the emitter of IGBT3, the collector electrode of IGBT4 connects an end of inductance L, the other end of inductance L is first output, the emitter of IGBT5 connects the collector electrode of IGBT6 and is second output, the emitter of IGBT4, the emitter of IGBT6, the negative pole end of electrochemical capacitor C2 connects the negative pole end of rectification full-bridge B, the grid of IGBT1, the grid of IGBT2, the grid of IGBT3, the grid of IGBT4, the grid of IGBT5, the grid of IGBT6 connects six drive control signal outputs of driving/photoelectric isolating circuit 2 respectively, and the control signal input bus end of driving/photoelectric isolating circuit 2 connects the control signal output bus end of DSP circuit 1.
Its less-switch five-power level voltage source type inversion controlling method step is:
Step 1, whole device power up startup, establish t 0~t 18Be the moment that the positive half wave and the triangular wave of sine wave intersects, t 1'~t 18' be the negative half-wave of sine wave and the moment that triangular wave intersects;
t 0~t 18, t 1'~t 18' selection rule be (in conjunction with the accompanying drawings 2 explanation): adopt four and have same frequency f cTriangular wave (a with identical peak-to-peak value 1, a 2, b 1, b 2) with a frequency be f m, amplitude is A mSine wave compare; Triangular wave a 1, a 2Amplitude greater than zero, a 2Minimum value equal a 1Maximum, and simultaneously begin forward and increase by separately mean point; Triangular wave b 1And b 2Amplitude less than zero, b 2Maximum equal b 1Minimum value, and simultaneously begin negative sense and increase by mean point, in the sinusoidal wave moment that intersects with carrier wave, be t 0~t 18, t 1'~t 18';
Step 2, at moment t 0The time, DSP circuit 1 is by 2 control IGBT4 and the IGBT6 conductings of driving/photoelectric isolating circuit, and IGBT1, IGBT2, IGBT3 and IGBT5 end, and remain to t constantly 1The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 2The time DSP circuit 1 by 2 control IGBT4 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT2, IGBT3 and IGBT5 end, and remain to moment t 3The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 4The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 5The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 6The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 7The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 8The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and reach the maximum of the positive half wave of sine wave;
Step 3, remain to t constantly 9The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 10The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 11The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 12The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 13The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 14The time DSP circuit 1 by 2 control IGBT1, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 15The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 16The time DSP circuit 1 by 2 control IGBT4 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT2, IGBT3 and IGBT5 end, and remain to moment t 17The time DSP circuit 1 by 2 control IGBT2, IGBT3 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 18The time DSP circuit 1 by 2 control IGBT4 and the IGBT6 conductings of drivings/photoelectric isolating circuit, IGBT1, IGBT2, IGBT3 and IGBT5 end, and reach sinusoidal wave positive half wave to the zero crossing (simulating the positive half wave of complete sine wave) of bearing half-wave;
Step 4, remain to t constantly 1In ' time, DSP circuit 1 is by 2 control IGBT2, IGBT4 and the IGBT5 conductings of driving/photoelectric isolating circuit, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 2In ' time,, DSP circuit 1 was controlled IGBT3 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT2, IGBT4 and IGBT6 end, and remain to t constantly 3In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 4In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 5In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 6In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 7In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 8In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 9In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and reach the maximum of the negative half-wave of sine wave;
Step 5, remain to t constantly 10In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 11In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 12In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 13In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 14In ' time,, DSP circuit 1 was controlled IGBT1, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT2, IGBT3 and IGBT6 end, and remain to t constantly 15In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 16In ' time,, DSP circuit 1 was controlled IGBT3 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT2, IGBT4 and IGBT6 end, and remain to t constantly 17In ' time,, DSP circuit 1 was controlled IGBT2, IGBT4 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT3 and IGBT6 end, and remain to t constantly 18In ' time,, DSP circuit 1 was controlled IGBT3 and IGBT5 conductings by driving/photoelectric isolating circuit 2, and IGBT1, IGBT2, IGBT4 and IGBT6 end, and reach the zero crossing (simulate the positive half wave of complete sine wave) of the negative half-wave of sine wave to positive half wave;
Step 6, return operating procedure two.
Embodiment two: 1 present embodiment is described in conjunction with the accompanying drawings, present embodiment increases on the basis of embodiment one current transformer L1, current transformer L2, current overload protection circuit 3;
Current transformer L1 is arranged on the negative pole end of rectification full-bridge B; current transformer L2 is arranged on second output of inverter; the signal output part of the signal output part of current transformer L1, current transformer L2 connects two signal input parts of current overload protection circuit 3 respectively, and the control signal output ends of current overload protection circuit 3 connects the overcurrent protection signal input end of DSP circuit 1.
Present embodiment can realize the current overload of IGBT1, IGBT2, IGBT3, IGBT4, IGBT5, IGBT6, the protection of rush of current; when the output load short circuits, close IGBT1, IGBT2, IGBT3, IGBT4, IGBT5, IGBT6, burn and protect it not to be damaged.
The model that described IGBT1, IGBT2, IGBT3, IGBT4, IGBT5, IGBT6 select for use all is the insulated gate bipolar transistor IGBT module 2MBI25L-120 of Fuji, the model that DSP circuit 1 is selected for use is TMS320F2812, and the model that driving/photoelectric isolating circuit 2 is selected for use is the M57962 of Mitsubishi.
Instantiation: IGBT1~6 modules of choosing Fuji for power switch pipe are 2MBI25L-120, and maximum pressure-bearing is 1200 volts, and maximum overcurrent is 25 peaces.Driving/photoelectric isolating circuit 2 main the M57962 that adopt Mitsubishi, and make up driving and protective circuit thereof on this basis.The filter inductance L of inverter is 10mH, and the dc voltage of rectification full-bridge B is Ed C1=E Dc2=150V, switching frequency are 1075Hz.DSP circuit 1 control unit core is made of TMS320F2812.In conjunction with Fig. 3, Fig. 4 explanation, have five kinds of level outputs of not expecting (0, ± 150V, ± 300V).And it is done spectrum analysis, and calculate 19 subharmonic, through calculating its THD=9.50%, its harmonic wave mainly concentrates on 15 times and 17 times.Relatively approached sine through the load resistance voltage behind the filter inductance as seen from Figure 4.Voltage waveform shown in Figure 4 is done spectrum analysis, and higher harmonics analyzes 19 subharmonic, through calculating its THD=4.06%.

Claims (4)

1. less-switch five-power level voltage source type inverter, it comprises rectification full-bridge B, electrochemical capacitor C1, electrochemical capacitor C2, IGBT1, IGBT2, IGBT3, IGBT4, IGBT5, IGBT6, inductance L, DSP circuit (1), driving/photoelectric isolating circuit (2);
Two ac input ends that it is characterized in that rectification full-bridge B connect ac power output, the positive terminal of rectification full-bridge B, the positive terminal of electrochemical capacitor C1 connects the collector electrode of IGBT1, the negative pole end of electrochemical capacitor C1, the emitter of IGBT2 connects the positive terminal of electrochemical capacitor C2, the collector electrode of IGBT2, the emitter of IGBT1, the collector electrode of IGBT3 connects the collector electrode of IGBT5, the emitter of IGBT3, the collector electrode of IGBT4 connects an end of inductance L, the other end of inductance L is first output, the emitter of IGBT5 connects the collector electrode of IGBT6 and is second output, the emitter of IGBT4, the emitter of IGBT6, the negative pole end of electrochemical capacitor C2 connects the negative pole end of rectification full-bridge B, the grid of IGBT1, the grid of IGBT2, the grid of IGBT3, the grid of IGBT4, the grid of IGBT5, the grid of IGBT6 connects six drive control signal outputs of driving/photoelectric isolating circuit (2) respectively, and the control signal input bus end of driving/photoelectric isolating circuit (2) connects the control signal output bus end of DSP circuit (1).
2. a kind of less-switch five-power level voltage source type inverter according to claim 1 is characterized in that its increase has current transformer L1, current transformer L2, current overload protection circuit (3);
Current transformer L1 is arranged on the negative pole end of rectification full-bridge B; current transformer L2 is arranged on second output of inverter; the signal output part of the signal output part of current transformer L1, current transformer L2 connects two signal input parts of current overload protection circuit (3) respectively, and the control signal output ends of current overload protection circuit (3) connects the overcurrent protection signal input end of DSP circuit (1).
3. less-switch five-power level voltage source type inversion controlling method is characterized in that its method step is:
Step 1, whole device power up startup, establish t 0~t 18Be the moment that the positive half wave and the triangular wave of sine wave intersects, t 1'~t 18' be the negative half-wave of sine wave and the moment that triangular wave intersects;
Step 2, at moment t 0The time, DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT4 and IGBT6 conducting, and IGBT1, IGBT2, IGBT3 and IGBT5 end, and remain to t constantly 1The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT2, IGBT3 and IGBT6 conducting, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 2The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT4 and IGBT6 conducting, IGBT1, IGBT2, IGBT3 and IGBT5 end, and remain to moment t 3The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT2, IGBT3 and IGBT6 conducting, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 4The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT1, IGBT3 and IGBT6 conducting, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 5The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT2, IGBT3 and IGBT6 conducting, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 6The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT1, IGBT3 and IGBT6 conducting, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 7The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT2, IGBT3 and IGBT6 conducting, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 8The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT1, IGBT3 and IGBT6 conducting, IGBT2, IGBT4 and IGBT5 end, and reach the maximum of the positive half wave of sine wave;
Step 3, remain to t constantly 9The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT2, IGBT3 and IGBT6 conducting, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 10The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT1, IGBT3 and IGBT6 conducting, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 11The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT2, IGBT3 and IGBT6 conducting, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 12The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT1, IGBT3 and IGBT6 conducting, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 13The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT2, IGBT3 and IGBT6 conducting, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 14The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT1, IGBT3 and IGBT6 conducting, IGBT2, IGBT4 and IGBT5 end, and remain to moment t 15The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT2, IGBT3 and IGBT6 conducting, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 16The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT4 and IGBT6 conducting, IGBT1, IGBT2, IGBT3 and IGBT5 end, and remain to moment t 17The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT2, IGBT3 and IGBT6 conducting, IGBT1, IGBT4 and IGBT5 end, and remain to moment t 18The time DSP circuit (1) by drivings/photoelectric isolating circuit (2) control IGBT4 and IGBT6 conducting, IGBT1, IGBT2, IGBT3 and IGBT5 end, and reach sinusoidal wave positive half wave to the zero crossing of bearing half-wave;
Step 4, remain to t constantly 1In ' time, DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT2, IGBT4 and IGBT5 conducting, and IGBT1, IGBT3 and IGBT6 end, and remains to t constantly 2' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT3 and IGBT5 conducting, and IGBT1, IGBT2, IGBT4 and IGBT6 end, and remains to t constantly 3' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT2, IGBT4 and IGBT5 conducting, and IGBT1, IGBT3 and IGBT6 end, and remains to t constantly 4' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT1, IGBT4 and IGBT5 conducting, and IGBT2, IGBT3 and IGBT6 end, and remains to t constantly 5' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT2, IGBT4 and IGBT5 conducting, and IGBT1, IGBT3 and IGBT6 end, and remains to t constantly 6' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT1, IGBT4 and IGBT5 conducting, and IGBT2, IGBT3 and IGBT6 end, and remains to t constantly 7' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT2, IGBT4 and IGBT5 conducting, and IGBT1, IGBT3 and IGBT6 end, and remains to t constantly 8' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT1, IGBT4 and IGBT5 conducting, and IGBT2, IGBT3 and IGBT6 end, and remains to t constantly 9' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT2, IGBT4 and IGBT5 conducting, and IGBT1, IGBT3 and IGBT6 end, and reaches the maximum of the negative half-wave of sine wave;
Step 5, remain to t constantly 10' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT1, IGBT4 and IGBT5 conducting, and IGBT2, IGBT3 and IGBT6 end, and remains to t constantly 11' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT2, IGBT4 and IGBT5 conducting, and IGBT1, IGBT3 and IGBT6 end, and remains to t constantly 12' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT1, IGBT4 and IGBT5 conducting, and IGBT2, IGBT3 and IGBT6 end, and remains to t constantly 13' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT2, IGBT4 and IGBT5 conducting, and IGBT1, IGBT3 and IGBT6 end, and remains to t constantly 14' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT1, IGBT4 and IGBT5 conducting, and IGBT2, IGBT3 and IGBT6 end, and remains to t constantly 15' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT2, IGBT4 and IGBT5 conducting, and IGBT1, IGBT3 and IGBT6 end, and remains to t constantly 16' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT3 and IGBT5 conducting, and IGBT1, IGBT2, IGBT4 and IGBT6 end, and remains to t constantly 17' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT2, IGBT4 and IGBT5 conducting, and IGBT1, IGBT3 and IGBT6 end, and remains to t constantly 18' time DSP circuit (1) is by driving/photoelectric isolating circuit (2) control IGBT3 and IGBT5 conducting, and IGBT1, IGBT2, IGBT4 and IGBT6 end, and reaches the zero crossing of the negative half-wave of sine wave to positive half wave;
Step 6, return operating procedure two.
4. a kind of less-switch five-power level voltage source type inversion controlling method according to claim 3 is characterized in that t described in its method step one 0~t 18, t 1'~t 18' selection rule be: adopt four and have same frequency f cTriangular wave (a with identical peak-to-peak value 1, a 2, b 1, b 2) with a frequency be f m, amplitude is A mSine wave compare; Triangular wave a 1, a 2Amplitude greater than zero, a 2Minimum value equal a 1Maximum, and simultaneously begin forward and increase by separately mean point; Triangular wave b 1And b 2Amplitude less than zero, b 2Maximum equal b 1Minimum value, and simultaneously begin negative sense and increase by mean point, in the sinusoidal wave moment that intersects with carrier wave, be t 0~t 18, t 1'~t 18'.
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