CN101162405A - Method for dynamic reducing CPU power consumption - Google Patents
Method for dynamic reducing CPU power consumption Download PDFInfo
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- CN101162405A CN101162405A CNA2006101621103A CN200610162110A CN101162405A CN 101162405 A CN101162405 A CN 101162405A CN A2006101621103 A CNA2006101621103 A CN A2006101621103A CN 200610162110 A CN200610162110 A CN 200610162110A CN 101162405 A CN101162405 A CN 101162405A
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Abstract
The invention discloses a method for dynamically reducing the CPU power consumption; the method is invented aiming at resolving the problem existing in prior art that the CPU power consumption can not be adjusted based on the service processing capacity. The method for dynamically reducing the CPU power consumption can dynamically adjust the directive operation speed of the CPU according to the CPU occupancy. When the CPU works, if the CPU occupancy is lower than the set lower limit value, the directive operation speed of the CPU is lowered; if the CPU occupancy is higher than the set upper limit value, the directive operation speed of the CPU is increased; wherein the adjustment on the directive operation speed is realized by opening or closing the data cache interface and the directive cache interface and changing the transmission delay. The invention is mainly applied to the CPU design of the embedded system, particularly the CPU design of the base station veneer in the communication field.
Description
Technical field
The present invention relates to CPU, particularly reduce the method for CPU power consumption.
Background technology
For the purpose of energy savings, be applied to the field of communication in the application of embedded system, particularly embedded system, each producer more and more pays close attention to the power consumption of product, all in the power consumption that reduces product by every means.Now a lot of electronic equipment mosts of the time in use all are in holding state, for example mobile phone, portable computer etc., generally all can be in holding state, if can allow the power consumption of equipment under ideal case reduce, that will save the energy greatly, and desktop computer is because the CPU power consumption is bigger, equally can save a lot of energy if can reduce the power consumption of CPU when not busy, be a problem that faces at present so equipment can be moved with lower power consumption under the not busy situation of business.
At present, in embedded device, when CPU moved under higher instruction operation speed, the power consumption of CPU was just bigger, and CPU moves under the fully loaded state, by reducing the instruction operation speed of CPU, just can reduce the power consumption of CPU.Present all kinds of CPU provides the method that reduces the cpu instruction execution speed, for example make CPU be in dormant state, but at moving communicating field, the designing requirement equipment of used server system can respond user's business demand at any time fast, even so do not have at night under the situation of customer service, CPU can not operate under the low-power consumption modes such as dormancy, can only remain on the same state operation down heavy traffic time the on daytime, prepare to respond at any time user's business demand, so these methods generally are not used at moving communicating field.In addition, because the chip design aspect of CPU, CPU moves the reliability of CPU for a long time under high power consumption and bigger reduction is arranged serviceable life, thereby increases equipment supplier's maintenance cost and the serviceable life of reducing equipment.So the another one problem that we face now is how under the situation that does not influence business demand, and CPU was operated under the low-power consumption mode in the long as far as possible time.
Summary of the invention
For overcoming above-mentioned defective, the object of the present invention is to provide and a kind ofly can under the less situation of business, reduce the CPU power consumption, and do not influence the method for the dynamic reduction CPU power consumption of business demand.
To achieve the above object of the invention, the present invention's method of dynamically reducing the CPU power consumption comprises:
(1) the instruction operation speed of reduction CPU when the CPU occupation rate is lower than lower limit;
(2) the instruction operation speed of raising CPU when the CPU occupation rate is higher than higher limit.
Wherein, described step (1) is specially:
(11) calculate CPU occupation rate benchmark;
(12) utilize the CPU occupation rate benchmark that calculates to calculate the CPU occupation rate;
(13) judge whether the CPU occupation rate is lower than lower limit, if the CPU occupation rate is lower than lower limit, execution in step (14); If the CPU occupation rate is not less than lower limit, return execution in step (12);
(14) the instruction operation speed of reduction CPU.
Wherein, described step (2) is specially:
(21) recomputate CPU occupation rate benchmark;
(22) utilize the CPU occupation rate benchmark that recalculates to calculate the CPU occupation rate;
(23) judge whether the CPU occupation rate is higher than higher limit, if the CPU occupation rate is higher than higher limit, execution in step (24); If the CPU occupation rate is not higher than higher limit, return execution in step (22);
(24) the instruction operation speed of raising CPU;
(25) return execution in step (1).
Wherein, described step (14) is specially: close data cache interface and command cache interface, increase the read-write time delay between processor cores and the Cache.
Wherein, described step (24) is specially: open data cache interface and command cache interface, reduce the read-write time delay between processor cores and the Cache.
Wherein, described CPU occupation rate higher limit and lower limit are by default.
Method by the dynamic reduction CPU power consumption described in the technique scheme is periodically calculated the CPU occupation rate, and the operation of modification CPU is configured to reach the instruction operation speed that reduces CPU when the CPU occupation rate is lower than lower limit, and the operation of recovery CPU is configured to reach the instruction operation speed of recovering CPU when the CPU occupation rate is higher than higher limit.The method of the instruction execution speed by this dynamic adjustment CPU, be in when can make free time of CPU under the pattern of low-power consumption and move, and the veneer of the mobile communication base station of the overwhelming majority had 50% time to be in idle condition, under the situation that does not influence system performance and application, make the veneer of these base stations be under the low-power consumption mode operation by the instruction execution speed that reduces CPU and can save a lot of energy, in addition, after the power consumption of CPU reduces, the CPU heat radiation can obviously descend, prevent that CPU is in hot environment for a long time to operation, thereby improve the serviceable life of CPU.
Description of drawings
Fig. 1 is the simplest Organization Chart of the embedded type CPU system of moving communicating field;
Fig. 2 dynamically reduces the schematic diagram of the method for CPU power consumption for the present invention;
Fig. 3 dynamically reduces the concrete implementing procedure figure of method on communication single-board CPU of CPU power consumption for the present invention.
Embodiment
Be illustrated in figure 1 as the simplest Organization Chart of the embedded type CPU system of moving communicating field, the minimum processor cores that comprises of moving communicating field embedded type CPU system, Cache (cache) and random access memory parts such as (RAM), wherein Cache is the high-speed cache that processor cores is followed interface between the peripheral hardware, and RAM is the volatile memory that is used for depositing programmed instruction or data in the cpu system.
Processor cores is a high-speed interface with the interface between the Cache, processor cores and Cache have interface with external RAM respectively, but all be interface than low speed, wherein the generation type of the low-speed interface between processor cores and the external RAM is: passage of suitable what when Cache closes has directly coupled together processor cores and external RAM; When Cache opened, it was a high-speed cache, from external RAM reading command or data to Cache buffer memory get up, directly take for CPU.CPU needs from external RAM instruction and data to be moved to the Cache in the high-speed cruising process, visits Cache to reach the high-speed cruising of instruction and data by processor cores.
In order to reduce the CPU power consumption, but do not influence the regular traffic demand of CPU, the method basic thought that the present invention dynamically reduces the CPU power consumption is: the instruction operation speed that reduces CPU when the CPU occupation rate is lower than lower limit; When being higher than higher limit, the CPU occupation rate improves the instruction operation speed of CPU.
Above-mentioned thought can realize by following operation: under the fewer situation of the business processing of CPU, such as evening,, allow processor cores communicate by RAM low-speed interface with the outside by closing, can realize reducing the cpu instruction travelling speed, thereby reduce the power consumption of CPU; When the business processing of CPU more for a long time, can make the instruction operation speed of CPU accelerate, to satisfy the demand of business processing by opening Cache or improving processor cores with the interface rate between the Cache.Wherein what of CPU business processing represent by the occupation rate of CPU that generally the CPU occupation rate is high more, CPU business processing just many more.Being explained as follows of CPU occupation rate: CPU is the disposal system business demand sometimes in the instruction operation process, be to be in Idle state (idle condition) sometimes, wait disposal system business, we add up, and the CPU disposal system business demand time accounts for the fixedly ratio of timing statistics in the set time, just is called the CPU occupation rate.
The present invention is lower than under the situation of certain threshold value in the occupation rate of CPU by the CPU occupation rate of software for calculation, reduce the travelling speed of CPU, recomputate the occupation rate of CPU, be higher than under the situation of certain threshold value in new CPU occupation rate, improve the travelling speed of CPU, reach the purpose of the instruction operation speed of dynamic adjustment CPU, thereby realize reducing the CPU power consumption.
As shown in Figure 2, it is as follows that the present invention dynamically reduces the method flow of CPU power consumption:
The first step: system power-up starts back CPU normally to be moved, and moves the employed operating system of this hardware;
Second step: calculate CPU occupation rate benchmark, CPU occupation rate benchmark is meant when CPU does not manage business function, just CPU is in idle condition, carry out the time of certain fixed function, just drew the benchmark of CPU occupation rate with 1 second divided by this time, the unit that is to say CPU occupation rate base station is for time/second;
The 3rd step: utilize CPU occupation rate benchmark cycle dynamics calculating CPU occupation rate, when the CPU occupation rate is lower than lower limit A, preserve the current operation configuration of CPU, and revise the operation configuration of CPU, the operation configuration of this modification back CPU must be able to reduce the instruction operation speed of CPU;
The 4th step: recomputate the benchmark of CPU occupation rate, utilize the benchmark of the method calculating CPU occupation rate in second step;
The 5th step: utilize the CPU occupation rate benchmark cycle dynamics calculating of recomputating and detect CPU occupation rate situation, when the CPU occupation rate is higher than higher limit B, recovers to go on foot the CPU operation configuration of preserving, thereby recover the instruction operation speed of CPU the 3rd; The operation configuration of CPU can be made amendment once more in the time of its tangible practical operation, but this modification need be towards the direction adjustment of the instruction operation speed of accelerating CPU;
The 6th step: returned for second step and carry out, can repeatedly change the instruction operation speed of CPU to guarantee this method.
By carrying out above-mentioned flow process, can adjust the instruction operation speed of CPU according to the busy-idle condition of CPU, thereby make CPU some time to be in the low rate running status, reach the effect that reduces power consumption, and prolong the serviceable life of CPU.
In the 3rd step of above-mentioned flow process, can be adjusted into: when the occupation rate of CPU all is lower than lower limit A above a default number of times continuously, preserve the current operation configuration of CPU, and revise the operation configuration of CPU.The modification in the requirement of revising CPU operation configuration here and the 3rd original step requires the same, promptly must be able to reduce the instruction operation speed of CPU.Can avoid having changed the instruction execution speed of CPU like this, cause the CPU needs repeatedly to change the operation configuration continually, increase the workload of CPU on the contrary, increase the power consumption of CPU because the once accidental occupation rate of CPU reduces.
In above-mentioned flow process the 5th goes on foot, also can go to adjust the operation configuration of CPU according to the 3rd step like that later on again at certain number of times, but do not advise such execution generally speaking, mainly be to prevent owing to cross the too high speed attenuating that causes business processing of long CPU occupation rate, influence business demand, worse situation might occur and crash exactly.
Dynamically reduce the specific implementation process of using on the PPC755CPU of method communication single-board in certain mobile communication base station of CPU power consumption below by introducing the present invention.
The CPU that this communication single-board adopts is that model that Freescale (Freescale Semiconductor) produces is that the CPU of PPC755 or model that IBM (International Business Machine Corporation (IBM)) produces are 750 CPU (this two CPU that the PPC755 that describes below refers to), this piece veneer mainly is to handle with the relevant software of audio call to realize, along with the increase of online calling party's number, the CPU occupation rate also increases accordingly.But in the base station of remote districts relatively, have every year the CPU occupation rate that surpasses 99% time PPC755 to be lower than 10%, in the city and the surrounding area thereof of heavy traffic, at 12 in evening to 7 of mornings, the CPU occupation rate of PPC755 also was lower than 10% during this period of time.
In this embodiment, we are decided to be 10% with the lower limit A of CPU occupation rate, and the higher limit B of CPU occupation rate is decided to be 80%, and the cycle that will calculate the CPU occupation rate is decided to be 2 seconds.After the Board Power up operation, calculate the CPU occupation rate reference value of PPC755, calculate one time the CPU occupation rate per 2 seconds, if find CPU occupation rate continuous 30 times (just 60 seconds, this is to be to be in idle condition for a long time in order to ensure CPU, prevent that some from occurring the instruction operation speed that low CPU occupation rate changes CPU once in a while) less than 10%, close Data Cache and the instruction Cache of PPC755, increase by 15 clocks of read-write time delay (clock) between processor cores and the Cache, can realize the increase of read-write time delay by the value of setting that increases ICTC (Instructions Cache throttling control register) register.The ICTC register is the register (bit0～bit31) of 32bit, bit23～the bit31 of this register value of 9bit altogether is effective, wherein bit23～bit30 is total to the time interval (just reading and writing time delay) that 8bit represents the preceding wait of each instruction fetch in the CPU operational process, minimum is 0, maximum is to wait for 255 clock period earlier before each instruction fetch, and Bit31 represents whether the setting of bit23 ~ bit30 is effective.Recomputate the base station value of CPU occupation rate, calculate one time the CPU occupation rate per two seconds, if find the CPU occupation rate, by being set, the ICTC register reduces 15 clock of read-write time delay between processor cores and the Cache equally in case, open Data Cache and instruction Cache greater than 80%.
The operation steps of this specific embodiment as shown in Figure 3.
The at first higher limit and the lower limit of the good CPU occupation rate of this default enter following controlled step then:
101, Vxworks operating system was normally moved after PPC755CPU powered up;
102, after entering the usrAppInit function, calculates by software CPU occupation rate benchmark on the PPC755, this CPU occupation rate benchmark is meant when CPU does not manage business function (just CPU is in idle condition), carry out the time of certain fixed function (such as being function A), with the benchmark that just drew the CPU occupation rate in 1 second divided by this time, the unit that is to say CPU occupation rate base station supposes that for time/second be X this reference time;
103, watch-dog (Monitor) per 2 seconds detects and calculates one time the CPU occupation rate, concrete grammar is in CPU normal process business procedure, in case the CPU free time gets off just to carry out function A, by add up continuous unit interval such as 2 second inner function A execution number of times (if being Y), Y is exactly the CPU occupation rate divided by X multiply by 100%;
When 104, watch-dog is judged that the CPU occupation rate is whether continuous and is lower than 10% 30 times, if the CPU occupation rate is lower than 10%, execution in step 105 continuous 30 times; If the CPU occupation rate is not to be lower than 10% continuous 30 times, return execution in step 103;
105, preserve the present operation configuration of CPU, close Data Cache and instruction Cache then, the ICTC register is set, increase the time-delay of processor cores with 15 clock of read-write between the Cache; The present operation configuration of preservation CPU herein mainly is a state of preserving data cache and command cache, the setting of ICTC register, and processor cores is with the time-delay of the read-write between the Cache;
106, recomputate the benchmark that PPC755 goes up the CPU occupation rate, the same in method step and the step 102;
107, watch-dog (Monitor) per two seconds detects and calculates the CPU occupation rate one time, utilizes the method for the CPU occupation rate benchmark that calculates in 106 steps and step 103 kind to calculate the CPU occupation rate;
108, watch-dog judges whether the CPU occupation rate is higher than 80%, if the CPU occupation rate is higher than 80%, execution in step 109; If the CPU occupation rate is not higher than 80%, return execution in step 107;
109, recover the previous operation configuration of preserving of CPU, promptly open Data Cache and instruction Cache, reset the ICTC register, the value of ICTC register is returned to the state of preserving in step 105, reduce the time-delay of processor cores with 15 clock of read-write between the Cache;
110, return execution in step 102.
Present embodiment is in that the CPU occupation rate is continuous when being lower than lower limit 10% 30 times, the operation of revising CPU is configured to reach the instruction operation speed that reduces CPU, and the operation of recovery CPU is configured to reach the instruction operation speed of recovering CPU when the CPU occupation rate is higher than higher limit 80%.Can reduce the power consumption of CPU effectively by the instruction operation speed method of this control CPU, particularly be in for a long time in the CPU utilization of idle condition at some, can save a large amount of energy, and after the power consumption of CPU reduces, the CPU heat radiation can obviously descend, prevent that CPU is in hot environment for a long time to operation, thereby improve the serviceable life of CPU.The method of the instruction operation speed of wherein used reduction CPU is: close Data Cache and instruction Cache, the ICTC register is set, increase the time-delay of processor cores with 15 clock of read-write between the Cache.
Claims (6)
1. a method that dynamically reduces the CPU power consumption is characterized in that comprising the steps:
(1) the instruction operation speed of reduction CPU when the CPU occupation rate is lower than lower limit;
(2) the instruction operation speed of raising CPU when the CPU occupation rate is higher than higher limit.
2. according to the method for the described dynamic reduction CPU power consumption of claim 1, it is characterized in that: described step (1) is specially:
(11) calculate the CPU occupation rate;
(12) judge whether the CPU occupation rate is lower than lower limit, if the CPU occupation rate is lower than lower limit, execution in step (13); If the CPU occupation rate is not less than lower limit, return execution in step (11);
(13) the instruction operation speed of reduction CPU.
3. according to the method for the described dynamic reduction CPU power consumption of claim 2, it is characterized in that: described step (2) is specially:
(21) recomputate the CPU occupation rate;
(22) judge whether the CPU occupation rate is higher than higher limit, if the CPU occupation rate is higher than higher limit, execution in step (23); If the CPU occupation rate is not higher than higher limit, return execution in step (21);
(23) the instruction operation speed of raising CPU;
(24) return execution in step (11).
4. according to the method for the described dynamic reduction CPU power consumption of claim 2, it is characterized in that: described step (13) is specially: close data cache interface and command cache interface, increase the read-write time delay between processor cores and the Cache.
5. according to the method for the described dynamic reduction CPU power consumption of claim 3, it is characterized in that: described step (23) is specially: open data cache interface and command cache interface, reduce the read-write time delay between processor cores and the Cache.
6. according to the method for claim 2 or 3 described dynamic reduction CPU power consumptions, it is characterized in that: described CPU occupation rate higher limit and lower limit are by default.
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