CN101136629B

CN101136629B - Driving circuit and driving method for charge pump

Info

Publication number: CN101136629B
Application number: CN2007101628643A
Authority: CN
Inventors: 陈忠君
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2007-10-16
Filing date: 2007-10-16
Publication date: 2010-10-06
Anticipated expiration: 2027-10-16
Also published as: CN101136629A

Abstract

This invention discloses a drive circuit device and a driving method for charge pumps including a de-frequency device, a drive buffer and a buffer, in which, the de-frequency device generates drive time pulse signals, the drive buffer can output a drive time pulse signal to the charge pump to generate two different operational voltages, the buffer is coupled between the de-frequency device and the drive buffer for increasing the voltage position of the drive time pulse signal then to be sent to the drive buffer and the operation voltages are fed back to the buffer to decide position sphere ofthe voltage. The method includes: generating a time pulse signal and transmitting it to a buffer to increase the voltage position of the drive time pulse signal by the two operation voltages of the buffer and transmitting the signal to a drive buffer and driving a charge pump to generate said operation voltages.

Description

The drive circuit of charge pump and driving method thereof

Technical field

The present invention relates to a kind of driving circuit device of charge pump, relate in particular to the driving circuit device of charge pump and the driving method of charge pump with the device that can enlarge clock signal voltage level scope.

Background technology

(Low Temperature Poly-silicon, LTPS) LCD is mainly used in height integration characteristic and high image quality display to the low temperature compound crystal silicon.Because the lifting of process stabilizing degree and element characteristic significantly improves in display equipment indoor design complicated circuit feasibility at present.In response to the trend of following display equipment internal integration signal processing circuit, improve simultaneously that image signal processing system is integrated and reliability, for more whippy display equipment design platform and application space widely will be provided future.

Conventional charge pump (Charge Pump) must use one group of extra complementary pair frequency signal, mainly provides the charge pump circuit operation required.Yet,, must rely on existing signal and produce this signal if there is not this extra complementary frequency signal at set standard platform.Because charge pump provides whole system required current potential energy, so the driving force of charge pump enjoys test.How to provide the big driving frequency of driving force to become the ultimate challenge of the charge pump of built-in frequency control signal generator.The mode of traditional design roughly can be divided into two kinds of Design Modes.Please refer to Figure 1A, the design of drive circuit of its prior art.Triggering signal is through behind the frequency eliminator 102, directly use drive buffer 104 amplification driving frequencies (CLK, XCLK).Figure 1B adopts the position two groups of design of drive circuit that drive clock signal.Earlier the charge pump under non-loaded 106 is operated default voltage quasi position (VDD), next again driving frequency is switched to the driving clock signal of another group heavy load operation.Directly test the driving force of drive circuit especially because of the inside resistance of switching required switch 108.Owing to still keep the design that increases driving force step by step, so still can't avoid oversize problem.

Therefore, need a kind of new drive circuit structure, can improve the shortcoming of above two kinds of circuit frameworks, available less transistor size can increase the driving force that drives buffer simultaneously.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of driving circuit device and driving method thereof of charge pump, can improve the shortcoming of foregoing circuit framework, can increase the driving force that drives buffer with less transistor size.

For achieving the above object, the driving circuit device that the invention provides a kind of charge pump comprises frequency eliminator, drives buffer and buffer.Frequency eliminator can produce the driving clock signal.Drive the exportable driving clock signal of buffer to charge pump, make charge pump produce two kinds of different operating voltages.Buffer is coupled to frequency eliminator and drives between the buffer, in order to improve the voltage level that drives clock signal, and the driving clock signal that will improve behind the voltage level is sent to the driving buffer, and wherein operating voltage feeds back to buffer, the voltage level scope that is improved with decision.Described buffer comprises a position quasi displacement circuit, in order to improve the voltage level of this driving clock signal according to described two kinds of different operating voltages; One latch circuit is in order to this driving clock signal behind the breech lock raising voltage level; And a buffer circuit, in order to being sent to this driving buffer by the driving clock signal of breech lock.

And for achieving the above object, the present invention also provides a kind of driving method of charge pump, comprises: produce one and drive clock signal; Should drive clock signal and be sent to a buffer, and improve the voltage level of this driving clock signal by two operating voltages of this buffer; Driving clock signal after the voltage level raising is sent to one drives buffer; And the driving clock signal that is provided by this driving buffer drives charge pump and produces described two operating voltages.

One embodiment of the invention produce the driving clock signal of high voltage level scope in the mode of feedback voltage, via driving buffer the driving frequency voltage level are returned back to original needed voltage level more at last.When operating voltage feeds back to buffer, can increase the accurate scope in voltage output voltage position of buffer.When the accurate scope in the voltage output voltage position of buffer increased, its driving force also can increase.

Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.

Description of drawings

Figure 1A is the design of drive circuit figure of prior art;

The design of drive circuit figure of Figure 1B for adopting two groups to drive clock signal;

Fig. 2 is a kind of circuit block diagram according to the embodiment of the invention;

Fig. 3 is a kind of start-up circuit schematic diagram according to the embodiment of the invention;

Fig. 4 is the flow chart according to the driving method of a kind of charge pump of the embodiment of the invention.

Wherein, Reference numeral:

102: frequency eliminator 104: drive buffer

106: charge pump 108: switch

202: frequency eliminator 204: drive buffer

206: buffer 208: charge pump

210: position quasi displacement circuit 212: latch circuit

214: buffer circuit 216: inferior position quasi displacement circuit

218: inferior position quasi displacement circuit 302: start-up circuit

402: step 404: step

406: step 408: step

Embodiment

Fig. 2 illustrates the circuit block diagram of one embodiment of the invention.Driving circuit device 200 comprises frequency eliminator 202, drives buffer 204 and buffer 206.Frequency eliminator 202 is in order to produce frequency signal.Frequency eliminator 202 can by a triggering signal produce the needed voltage level of charge pump (VDC) the complementary drive clock signal (CLK, XCLK).For example, VDC can be 3V, and the complementary drive clock signal that frequency eliminator 202 is exported is then between 0V and 3V.

The complementary drive clock signal that frequency eliminator 202 is produced can be sent to after by buffer 206 and drive buffer 204.Driving 204 in buffer can be in order to export complementary frequency signal to charge pump 208, make charge pump 208 produce two different operating voltages (VDD, VSS).For example, VDD can be 6V, and VSS can be-3V.VDD that charge pump 208 is produced and VSS then are sent to buffer 206 in the mode of feedback, with the accurate scope in output voltage position of definition buffer 206.

Buffer 206 is coupled to frequency eliminator 202 and drives between the buffer 204, drives the voltage level of clock signal in order to raising, and the driving clock signal that will improve behind the voltage level is sent to driving buffer 204.Buffer 206 can comprise position quasi displacement circuit 210, latch circuit 212 and buffer circuit 214.Position quasi displacement circuit 210 can improve the voltage level scope that drives clock signal according to operating voltage VDD and VSS.Position quasi displacement circuit 210 also can be divided into position quasi displacement circuit 216,218 two times, in order to increase the voltage level scope that drives clock signal respectively.Inferior position quasi displacement circuit 216 can upwards be promoted to VDD by VDC with the voltage level that drives clock signal.For example, the voltage level scope of the driving clock signal that script frequency eliminator 202 is provided is 0V～3V, through rising to 0V～6V behind time position quasi displacement circuit 216.Moreover inferior position quasi displacement circuit 218 can extend downward VSS by GND with the voltage level that drives clock signal.For example, behind time position quasi displacement circuit 216, the voltage level scope that drives clock signal can be extended to by 0V～6V-3V～6V.Therefore, by a cathode voltage (VDD) and a cathode voltage (VSS), the voltage level that drives clock signal can enlarge to the two poles of the earth symmetry.

Next, latch circuit 212 improves driving clock signal behind the voltage level in order to breech lock, and latch circuit 212 can stably provide and drive clock signal to buffer circuit 214, makes driving frequency can effectively locate its voltage level.

Buffer circuit 214 can be in order to transmit by the driving clock signal of breech lock to driving buffer 204.The driving clock signal that buffer circuit 214 is transmitted can more effectively drive at driving buffer 204 after amplifying.The driving clock signal that the driving buffer will be enhanced behind the voltage level returns to original voltage level (VDC), to meet the demand of charge pump.

Please refer to Fig. 3, it illustrates the schematic diagram of start-up circuit embodiment according to the present invention.Driving circuit device 200 can comprise a start-up circuit 302 in addition, is connected between voltage level VDD and the VDC, also can be connected between voltage level VSS and the GND.Start-up circuit 302 can make that driving clock signal produces more stable in order to described two operating voltage initial voltage value to be provided.

Fig. 4 is for illustrating the flow chart of the driving method of charge pump according to the present invention.Please be simultaneously with reference to Fig. 2 and Fig. 4.This method comprises the following step:

At first, trigger frequency eliminator 202 by triggering signal and produce driving clock signal (step 402).

Then, frequency eliminator 202 transmits and drives clock signal to buffer 206, and buffer 206 improves the voltage level (step 404) that drives clock signal according to operating voltage then.

Thereafter, this after buffer 206 improves voltage level drives clock signal and is sent to driving buffer 214 (step 406).

Then, the driving clock signal that drives after buffer 214 improves voltage level returns to original voltage level, drives buffer 214 then and will drive clock signal and be sent to charge pump 208, is used for driving charge pump 208 generation operating voltages (step 408).

The layout area that the above driving circuit device can significantly dwindle circuit design and consumed, and more fast and stable and high efficiency power supply supply are provided.Embodiments of the invention can access the demand that is fit to the built-in driving frequency generator of actual state charge pump, do not need the operation of two groups of complicated driving frequency generators, the driving clock signal of the driving force of expection can be provided at limited layout area again, main dependence operating voltage provides the amplification of coherent signal, and reliable start-up circuit design requirement, therefore be more suitable for different design conditions and practical application.

Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.

Claims

1. the driving circuit device of a charge pump is characterized in that, comprises:

One frequency eliminator drives clock signal in order to produce one;

One drives buffer, in order to export this driving clock signal to charge pump, makes charge pump produce two kinds of different operating voltages; And

One buffer, be coupled between this frequency eliminator and this driving buffer, in order to improve the voltage level of this driving clock signal, and the driving clock signal that will improve behind the voltage level is sent to this driving buffer, wherein said two kinds of different operating voltages feed back to this buffer, with the voltage level scope that determines to be improved;

Wherein said buffer comprises:

One position quasi displacement circuit is in order to improve the voltage level of this driving clock signal according to described two kinds of different operating voltages;

One latch circuit is in order to this driving clock signal behind the breech lock raising voltage level; And

One buffer circuit will be in order to being sent to this driving buffer by the driving clock signal of breech lock.

2. driving circuit device according to claim 1 is characterized in that, described two kinds of different operating voltages are provided to this position quasi displacement circuit, this latch circuit and this buffer circuit.

3. driving circuit device according to claim 1 is characterized in that other comprises a start-up circuit, in order to described two kinds of different operating voltages one initial voltage value to be provided.

4. driving circuit device according to claim 1 is characterized in that, described two kinds of different operating voltages are respectively a positive polarity voltage and a reverse voltage.

5. driving circuit device according to claim 1 is characterized in that, this frequency eliminator produces this driving clock signal by a triggering signal.

6. driving circuit device according to claim 1 is characterized in that, this driving clock signal that this driving buffer will improve behind the voltage level returns to original voltage level.

7. the driving method of a charge pump is characterized in that, comprises:

Produce one and drive clock signal;

Should drive clock signal and be sent to a buffer, and improve the voltage level of this driving clock signal by two operating voltages of this buffer;

Driving clock signal after the voltage level raising is sent to one drives buffer; And

The driving clock signal driving charge pump that is provided by this driving buffer produces described two operating voltages;

Wherein said buffer comprises:

One position quasi displacement circuit is in order to improve the voltage level of this driving clock signal according to described two operating voltages;

8. driving method according to claim 7 is characterized in that, other comprises provides described two operating voltages, one initial voltage value.

9. driving method according to claim 7 is characterized in that, described two operating voltages are respectively a positive polarity voltage and a reverse voltage.

10. driving method according to claim 7 is characterized in that, this driving clock signal triggers a frequency eliminator by a triggering signal and produces.

11. driving method according to claim 7 is characterized in that, this driving clock signal that this driving buffer will be enhanced behind the voltage level returns to original voltage level.

12. driving method according to claim 7 is characterized in that, improves the voltage level of the voltage level of this driving clock signal with two these driving clock signals of position quasi displacement circuit symmetry raising.