CN101122865B - Computer mainboard quick suspending and recovery device using phase-change memory - Google Patents
Computer mainboard quick suspending and recovery device using phase-change memory Download PDFInfo
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- CN101122865B CN101122865B CN200710154015.3A CN200710154015A CN101122865B CN 101122865 B CN101122865 B CN 101122865B CN 200710154015 A CN200710154015 A CN 200710154015A CN 101122865 B CN101122865 B CN 101122865B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
Abstract
The invention discloses a computer mainboard rapid suspension and recovery device using a phase-change memorizer. The operation system image is memorized in the PCM memorizer module and is stilled reserved after suspension due to the nonvolatile PCM. A microprocessor is able to direct read the reserved operation system image in the PCM memorizer module but not necessary to copy the operation system image from the HD to the main memorizer. The microprocessor is unnecessary to fetch out the start loading program for starting ROM when suspending/recovering. A VRAM could be PCM, which allows the frame buffer to maintain therein, and is directly addressed by the microprocessor when suspending/recovering. The frame buffer display is rapidly activated when suspending/recovering because the frame buffer is unnecessary to be reconstituted. The PCM unit applies the crystalline state and non-crystalline state of the variable resistance to memorize the data.
Description
Technical field
The present invention relates to a kind of computing machine, refer in particular to a kind of quick hang-up recovery device that uses phase transition storage.
Background technology
Personal computer (PC) worldwide has been widely used in commerce and family.At present popular PC uses based on the microprocessor of X86 framework and the operation operating system as Microsoft Windows or Linux.Because the X86 structure is relatively older, therefore for modern computer, the start-up routine ideal that also is nowhere near.
How behind the PC pending operation apace recovery operation begin to become a special problem.Come down in perfect condition, hang-up/recovery should be more faster than restarting PC (needing several minutes usually).But unfortunately, hardware technology and PC software are not supported to hang up fast/recover.
Figure 1A has represented a PC of technology formerly.CPU22 is a central processing unit as x86 microprocessor.SRAM high-speed cache 24 can be the instruction and data high-speed cache that is integrated into same chip with CPU22, also can be static RAM (SRAM) high-speed cache of outside expansion.CPU22 takes out data and instruction from dynamic RAM (DRAM) module 30, and with data and instruction storage in SRAM high-speed cache 24.The image that these instructions may change display 26 by the frame buffer zone that video data is write a video memory 32 shows.Video memory 32 can be the video-ram on DRAM independently or the graphics card, also can be the part of DRAM module 30.
But CPU22 directly address on local bus 40 as storeies such as video-ram 32 and DRAM modules 30.Storer that other is slower and peripheral hardware are separated by I/O coprocessor 28 and local bus 40.The order that I/O coprocessor 28 receives from CPU22 by local bus 40, and transmit these and ask peripheral bus 42,43 to visit external unit.For example, FLASH storer 36 just can be a flash drive that inserts USB (universal serial bus) (USB), and 34 of hard disk drives visit by IDE or SATA bus.
Starting ROM38 is a FLASH ROM (read-only memory), and it has comprised after the energising or first instruction that CPU need carry out after restarting.Can be reset after I/O coprocessor 28 energising connects CPU22 to starting ROM38, or the hardware state machine of I/O coprocessor 28 or other position can copy in the DRAM memory module 30 and carries out to CPU22 starting instruction among the ROM38.Start ROM38 and also can directly place on the local bus 40, but from start ROM38, load the speed that may reduce local bus 40.
In start-up course, the OS image 44 ' of operating system copies to DRAM module 30 from hard disk 32 and forms the OS image 44 that CPU22 can direct access.Because hard disk drive 32 is data storage high capacity storage facilitiess in the sector, so OS image 44 ' only can the piece addressing, and can not randow addressing.Therefore OS image 44 ' must be copied in the DRAM module 30 and by reconstruct so that CPU22 can directly address OS image 44.
In Figure 1B, PC is arranged in and hangs up back rejuvenation.After PC hung up, some key state information was copied in the hardware driver 34 from DRAM module 30 apace.For example, OS image 44 copies to hard disk drive 34 from DRAM module 30 becomes OS image 44 '.When PC electric power disconnection when hanging up, volatile memory will be lost their data.All data on the DRAM module 30 comprise that OS image 44 will lose, and SRAM high-speed cache 24 and video memory 32 also all can be lost, as the X among Figure 1B * * mark shown in.Display 26 is no longer to the buffering of the frame in user's display video storer 32 image.
PC after hang-up during recovery operation electric power be resumed, DRAM memory module 30, video memory 32 and SRAM high-speed cache 24 all are empty, are perhaps comprising junk data.Enabled instruction in the recovery routine copies to CPU22 from starting ROM38 by I/O coprocessor 28.The startup loader that these enabled instructions have comprised a CPU22 execution duplicates more data to DRAM memory module 30.For example, OS image 44 ' reads out and is copied to from hard disk drive 34 and rebuilds OS image 44 in the DRAM memory module 30.OS image 44 can be carried out by CPU22, allows the user to run application on PC again.
Processor reads enabled instruction from start ROM38, it is relatively slow to duplicate from hard disk drive 34 in OS image 44 to the DRAM modules 30, can cause hanging up/recovers on experiencing the good of not instant unlatching like this.The size of OS image 44 can be very big, is particularly suited for having the newer operating system of the code of a large amount of new features and expansion.
Nonvolatile memory has been used a lot of years, even if this nonvolatile memory power down can obliterated data yet.For example starting ROM38 is exactly the nonvolatile memory of a NOR FLASH.But nonvolatile memory for example NAND flash storer is generally used for mass-memory unit rather than randow addressing equipment.Mass-memory unit because the sector be 512 or more multibyte write simultaneously or read as a piece, so relative complex.Because CPU22 may write single byte, 64 or byte still less, therefore jumbo addressing method is inadvisable.Complicated direct memory access (DMA) (DMA) is commonly used in hardware or software industry.In addition, the ability that is written into of slow relatively access speed and bus has also limited the time-delay of using nonvolatile memory and increasing hang-up/recovery.
Therefore need a personal computer that has quick hang-up/recovery, and then need the PC mainboard of a fast quick-recovery of primary support, therefore need an improved PC framework.
Summary of the invention
The invention provides a kind of improved personal computer motherboard.Ensuing description all is to use ordinary skill to realize or uses the described invention that requires of the application's document and it.Based on the embodiment of mentioning may be because of than the modification that occurs various presentations in the scope of this area, the principle of this place definition also is applicable to other embodiment.Therefore, the present invention is not limited to described specific implementations, but keeps on a large scale the most conforming according to principle disclosed herein and novelty.
The inventor recognizes that it is because troublesomely the operating system image information is copied in the volatile main memory that the performance of the hang-up/recovery of PC is limited to from hard disk drive at a slow speed.If primary memory is non-volatile, just duplicating of then this operating system image do not needed, thereby the performance of hang-up/recovery will improve.
A kind of phase transition storage (Phase-Change-Memory is called for short PCM) mainboard comprises:
One primary memory, be used for instruction and data is stored in phase transition storage, wherein, instruction and data still keeps when power supply is removed primary memory, phase transition storage comprises a large amount of PCM unit, each unit contains: first logic state (first logical state) that has the potpourri (alloy) of crystalline state (crystalline phase), second logic state (second logical state) with the potpourri that has amorphous state (amorphous phase), wherein, the resistance ratio crystalline state of amorphous state potpourri is mixed object height;
One processor is connected to primary memory, is used to obtain and carry out the instruction of primary memory, and writes data to primary memory;
One video memory (video memory) writes by the processor connection, is used to store the pixel frame buffer device (frame buffer) that treated device upgrades, and this frame buffer comprises the pixel data that is used for the user is produced visible demonstration;
One cache memory is connected to processor, is used to store the zero access instruction and data copy of primary memory;
One mass-memory unit is used for storage instruction piece and data block, and mass-memory unit is the piece addressing, wherein, single instruction can not be independent of in the instruction block other instruction and by access;
One input and output coprocessor (I/O coprocessor) is located between mass-memory unit and the primary memory, is used for from mass-memory unit read block and instruction block, and data block and instruction block are write in the primary memory;
One operating system image (operating system image) is stored in the phase transition storage of primary memory, is used for the instruction and the systematic parameter of processor controls when being included in user's routine operation;
One hang-up/recovery routine (suspend/resume routine), as instruction storage in the phase transition storage of primary memory, when user's pending operation, before power supply disconnects from primary memory, the extensive again hang-up/recovery routine of carrying out immediately of the power supply of processor; When user's recovery operation, after primary memory was multiple, processor was carried out hang-up/recovery routine immediately; With
One substrate (substrate) is used for supporting and being electrically connected primary memory, processor, video memory, input and output coprocessor;
Thus, hang-up/recovery routine is stored in the phase transition storage of primary memory and is performed.
Wherein, video memory comprises the phase transition storage of a large amount of PCM unit, and wherein, when the power supply of video memory disconnected, frame buffer still was retained, and after hang-up/recovery operation, when power up, also can not regenerated by processor.
Wherein, video memory comprises the part of phase transition storage in the primary memory, and wherein, video memory and primary memory are for sharing the part of phase transition storage.
Wherein, cache memory comprises static RAM (SRAM); Wherein, hang-up/recovery routine also comprises:
One high-speed cache illegal instruction (cache-disable instruction) is used for disabling cache storer when hanging up;
One high-speed cache cleaning instruction (cache-flush instruction) is used to delete the instruction and data that is stored in cache memory;
One cache enabling order (cache-enable instruction) when the recovery operation of carrying out after the high-speed cache cleaning is instructed, is used to make cache memory can be written into the instruction and data that reads in primary memory again;
Thus, cache memory is cleared up and is written into again through hang-ups/recovery operation, and primary memory still reserve statement and data in hang-up/recovery operation process.
Wherein, cache memory comprises the phase transition storage of being made up of a large amount of PCM unit; Wherein, when outage took place in the pending operation process, cache memory is the copy of reserve statement and data still; At this moment, cache memory is not cleared up in hang-up/rejuvenation.
Described PCM mainboard also comprises:
One local bridging chip (local bridge chip), be connected between processor and the primary memory, be used for obtaining instruction from primary memory by memory bus, and the instruction that will take out by processor bus sends to processor, thus, processor and primary memory link together by local bridging chip.
Wherein, the independent instruction and data of processor direct access primary memory, wherein, phase transition storage is randow addressing.
Wherein, a PCM unit in a large amount of PCM unit comprises:
One transistor selector switch (select transistor) by gate circuit (gate) connective word circuit (word line), is the passage between bit line (bit line) and the cell node (cell node);
One potpourri resistance (alloy resistor) is made up of potpourri, is connected between cell node and the array voltage (array voltage);
Wherein, when the potpourri of potpourri resistance is in crystalline state, the PCM unit is positioned at first logic state, and potpourri resistance is Low ESR (resistance), can increase the induction current by the transistor selector switch;
Wherein, when the potpourri of potpourri resistance is in amorphous state, the PCM unit is positioned at second logic state, and potpourri resistance is high impedance, can reduce the induction current by the transistor selector switch;
Wherein high impedance is than the low-resistance Chinese People's Anti-Japanese Military and Political College, so induction current can be realized changing by conversion between crystalline state and the amorphous potpourri.
Wherein, phase transition storage also comprises:
One is connected to the configuration current feedback circuit (set current generator) of bit line, be used for coming drive arrangements electric current (set current) through time configuration cycle (set period oftime) by transistor selector switch and potpourri resistance, write PCM unit to the first logic state, a corresponding write data inputs to first logic state;
One is connected to the resetting current generator (reset current generator) of bit line, be used for driving resetting current (resetcurrent) through time reset cycle by transistor selector switch and potpourri resistance, write PCM unit to the second logic state, a corresponding write data inputs to second logic state;
One reset timer (reset timer) is used to judge time reset cycle; With
One configuration timer (set timer) is used to judge time configuration cycle;
Wherein, more than the twice of resetting current for the configuration electric current, the configuration electric current is more than the faradic twice;
Wherein, time configuration cycle is more than the twice of time reset cycle, therefore, the PCM unit by reduced-current, continue cycle long period and finish configuration, and by high current, continue cycle short period and finish and reset.
Wherein, potpourri is the chalcogenide glass layer (chalcogenide glasslayer) that fusing point is higher than crystallization point.
Wherein, potpourri is the potpourri of germanium (Ge), antimony (Sb) and tellurium (Te).
A kind of non-volatile computer comprises:
Processor device (processor means) is used to obtain and execution command and write data;
Phase-changing storage device (phase-change memory means), be used to store the instruction and data of binary digit, wherein every binary digit is represented a chalcogenide glass layer higher than crystallization point temperature, and this of chalcogenide glass layer formation changes faradic variable resistor (variable resistor) when reading binary digit;
Wherein, variable-resistance crystalline state representative is stored in first binary logic state of binary digit in the phase-changing storage device, and variable-resistance amorphous state is then represented second binary logic state that is stored in binary digit in the phase-changing storage device.
Local bus control's device (local bus controller means), be used to receive the address of from processor device, from the phase-changing storage device that is stored in the from processor unit address, obtain instruction, corresponding data address from phase-changing storage device is carried out data transmission between processor device and phase-changing storage device.
Configuration electric current timer device (set current timer means) connects phase-changing storage device, when binary digit is written into first binary logic state, is used for producing a configuration electric current by a configuration cycle, and variable resistor is configured to crystalline state;
Resetting current timer device (reset current timer means), connect phase-changing storage device, when binary digit is written into second binary logic state, be used for producing a resetting current by a reset cycle, variable resistor is reset to amorphous state;
Wherein, resetting current is flowed through more than the variable-resistance faradic twice when disposing electric current for read operation for more than 2 times of electric current of configuration;
Wherein configuration cycle is more than the twice of reset cycle;
That is to say, variable resistor by reduced-current, continue cycle long period and finish configuration, by high current, continue cycle short period and finish and reset.
Described non-volatile computer also comprises:
Video phase-changing storage device (video phase-change memory means), be used to store a pixel frame buffer device that shows by display, wherein, pixel is made up of binary digit, fusing point is wanted high chalcogenide glass layer to represent bit by the crystalline state temperature, when reading binary digit, this chalcogenide glass layer forms one can change faradic variable resistor;
Wherein, variable-resistance crystalline state representative is stored in first binary logic state in the phase-changing storage device, and variable-resistance amorphous state representative is stored in second binary logic state in the phase-changing storage device;
Wherein, local bus control's device also is used for the pixel that processor device generates is written to the video phase-changing storage device;
That is to say that frame buffer pixel is stored in the phase-changing storage device.
Wherein, the pixel frame buffer device that is stored in the video phase-changing storage device is retained after power supply is hung up, and non-volatile computer enters Suspend Mode;
Wherein, when power supply is hung up, the instruction and data that is stored in phase-changing storage device will be retained, and non-volatile computer enters Suspend Mode;
That is to say that pixel frame buffer device and instruction storage are in non-volatile memory device.
Described non-volatile computer also comprises:
Local operating system's device for image (local operating system image means), the current operation status that is used to store non-volatile computer, local operating system's device for image is stored in the phase-changing storage device;
Wherein, when power supply was hung up, non-volatile computer entered Suspend Mode, and local operating system's device for image still is retained;
Recovery device (resume means) during power up, is carried out by processor device behind Suspend Mode, is used for carrying out reading command from local operating system's device for image that phase-changing storage device reads;
Wherein, processor device is by carrying out the instruction recovery operation from phase-changing storage device;
That is to say, hang up back local operating system image and still be retained in the phase-changing storage device.
Described non-volatile computer also comprises:
Peripheral bus control device (peripheral bus controller means) connects local bus control's device, is used to connect the external unit on local bus control's device and the peripheral bus;
Mass storage device connects the peripheral bus control device, is used to store addressable blocks, and wherein, addressable blocks comprises can not the independent addressing of processed apparatus but the instruction and data piece of piece addressing;
Peripheral operation system device for image (peripheral operating system image means) is used to store the copy of non-volatile computer current operation system state, and peripheral operation system device for image is stored in the mass-memory unit device;
Wherein, processor device need not to duplicate peripheral operation system device for image in the recovery operation from the mass-memory unit device;
That is to say that behind pending operation, need not from the copy of mass-memory unit device transmission current operation system state, the local operating system's device for image in the phase-changing storage device can be retained and be performed.
A kind of phase transition storage personal computer comprises:
One microprocessor (microprocessor), be used for the execution command and in local storage space write data;
One phase transition storage is present in the local storage space, the instruction and data that storage can directly be visited by microprocessor;
The memory cell array of one phase transition storage, each memory cell have the storage binary digit as solid-state potpourri resistance, and each is solid-state to have different resistance;
Wherein, when memory cell when logical one is written as logical zero, through a reset cycle, the response resetting current, thereby potpourri resistance becomes amorphous state from crystalline state;
When memory cell when logical zero is written as logical one, through a configuration cycle, response configuration electric current, thereby resistance becomes crystalline state from amorphous state;
Wherein, amorphous state has higher resistance and sensed amplifier than crystalline state and responds to;
One local bus control is used for transfer instruction and data between phase transition storage and microprocessor;
Display buffer (display buffer) connects the pixel that receives through the microprocessor renewal by local bus control, and this display buffer is used for storage pixel in the phase transition storage that is formed by the memory cell that all has potpourri resistance;
Video Controller (video controller), the pixel that is used to drive display buffer is given display, and is shown to the user;
That is to say that pixel and instruction storage are in phase transition storage.
Described phase transition storage personal computer also comprises:
One peripheral bus controller (peripheral bus controller) connects local bus control, is used for the external unit on the access peripheral bus;
One starts ROM (read-only memory) (boot read-only-memory), connects the peripheral bus controller, is used to be stored in the performed start-up routine instruction of microprocessor under the initial electric power starting situation; With
One hang-up/recovery instruction (suspend/resume routine of instruction) is stored in the phase transition storage, can directly be carried out by microprocessor when recovering power supply before hanging up power supply or after the power supply hang-up;
That is to say that the start-up routine instruction that starts ROM (read-only memory) is being carried out by microprocessor under initial electric power starting situation, hang-ups/recovery is instructed to read out from phase transition storage and is used for hang-up/recovery and carries out.
Described phase transition storage personal computer also comprises:
One mass-memory unit is on first media bus between local bus control and the peripheral bus controller;
One network controller (nerwork controller) is used to be connected to network, and network controller is positioned on first media bus.
Wherein, external unit comprises:
One flash memory is located on first peripheral bus, connects the peripheral bus controller, is used for storing data in flash memory;
One starts ROM (read-only memory), is located on second peripheral bus, connects the peripheral bus controller, and storage can be the start-up code that microprocessor is carried out when being used for electric power starting;
One Audio Controller (audio controller) is located on second peripheral bus, connects the peripheral bus controller, is used to send the sound that the user can hear.
Described phase transition storage personal computer also comprises:
One reset timer is used to judge time reset cycle; With
One configuration timer is used to judge time configuration cycle;
Wherein, more than the twice of resetting current for the configuration electric current, the configuration electric current is more than the faradic twice that is used to read;
Time configuration cycle is more than the twice of time reset cycle;
That is to say that the potpourri resistance in the memory cell is finished configuration by long period, low voltage, finish by short period, high voltage and reset.
Figure 1A is the structural representation of a technology PC embodiment formerly;
Description of drawings
Figure 1B is the synoptic diagram that returns to form after the described technology formerly of Figure 1A PC hangs up;
Fig. 2 is the structural representation of phase-changing memory unit;
Fig. 3 is current curves and the synoptic diagram of state transfer time in the phase-changing memory unit;
Fig. 4 is the structural representation of phase-change memory cell array;
Figure 5 shows that quick hang-up/restoration methods of using the individual counter of phase transition storage on the CPU local bus;
Figure 6 shows that the quick recovery method of the mainboard that uses phase transition storage;
Fig. 7 is the structural representation of phase transition storage;
Fig. 8 is the structural representation of phase transition storage module.
Fig. 2 is phase transition storage (phase-change memory is called for short PCM) unit.Flash memory is used for non-volatile memory device traditionally, and another nonvolatile memory phase transition storage was invented in nineteen sixty, is once delivered on the e-magazine in September, 1970 for paper by the founder Gordon Moore of Intel Company work.Although need a kind of like this technology of quick hang-up/recovery operation always, this technology that has had 40 years history also is not applied to solving hang-up/recovery problem of millions of PC.
Embodiment
Phase transition storage (PCM) adopt one can crystalline and non-crystalline between the chalcogenide glass layer of conversion.This chalcogenide glass layer can be the potpourri of germanium (Ge), antimony (Sb), tellurium (Te).This potpourri has high-melting-point, when be transformed into amorphous state after the fusing point cooling.Solid mixt is after the amorphous state heating, and potpourri changes crystalline state under than low-melting Tc.This heating can realize that this state exchange can take place at a gallop, for example may diminish to for 5 nanoseconds by potpourri being applied electric current.
In Fig. 2, potpourri resistance 10 is in crystalline state, and its resistance is low, and crystalline state is represented logic high or 1.Phase-changing memory unit has the potpourri resistance of being made up of a series of transistor selector switchs 12 that are positioned between bit line (bit line is called for short BL) and the voltage V.When V was low-voltage such as ground connection, word line (word line is called for short WL) was driven to high level, because the Low ESR of potpourri resistance 10, bit line voltage can break away from the high level pre-charge state by transistor selector switch 12 and potpourri resistance 10 ground connection.
When potpourri resistance 10 was in amorphous state, its resistance was high, and amorphous state is represented logic low or 0.The another one phase-changing memory unit has the potpourri resistance of being made up of a series of transistor selector switchs 12 between bit line BL and voltage V.When V is a low-voltage for example during ground connection, word line WL is driven to high level.Since the high resistant of potpourri resistance 10 limited electric current through transistor selector switch 12 ', so the voltage of bit line keeps high level or pre-charge state.
The distribution of noting logical zero and logical one state is random for crystalline state and amorphous state, and for example crystalline state can be defined as logical one or logical zero, and amorphous state is then used the another one logical value opposite with it.
When high-tension current during through potpourri resistance 10, potpourri can change amorphous state into from crystalline state, and powerful electric current makes have a resistance heating and reach fusing point rapidly of potpourri resistance 10, and causing crystal to melt becomes liquid state.In case rapidly cooling, because the time of cooling is very short, so that crystal also has little time to increase, so potpourri resistance is solidified as amorphous state.
When a lower electric current through potpourri resistance 10 and when continuing longer a period of time, will meet or exceed crystallization temperature.However, this electric current also is not enough to cause the fusing point that reaches higher.Amorphous potpourri begins crystallization in this long cycle.For example, among a small circle crystal can increase and attract other regional crystal till comprising one or seldom some crystal in potpourri resistance 10 amorphous states.
When the electric current that uses appropriateness and after continuing longer relatively a period of time, potpourri resistance 10 is converted to low-impedance crystalline state from the amorphous state of high impedance, allows crystal to increase under crystallization temperature.After using high-intensity electric current and continuing relatively short a period of time, potpourri resistance 10 is converted to the crystalline state of high impedance from low-impedance amorphous state, allows crystal to be molten into the amorphous state drop under temperature of fusion.
Fig. 3 is electric current and the time relation chart in the state conversion process of phase-changing memory unit.When a heavy current (resetting current) continues to reach amorphous state 14 after the time T (WR0).Continue to arrive at crystalline state behind the longer time T (WR1) when using a moderate current promptly to dispose electric current.When electric current is lower than moderate current, or time of continuing of electric current when falling short of, these states will remain unchanged.When full current and time do not meet the demands (for example the application configuration electric current is less than the standard configuration time) simultaneously, state variation just can take place or not exclusively change.These not exclusively are changed to bad variation.
Using an a bit of time of lower read current when phase change cells just can read safely.For example, read current is less than or equal to configuration or resetting current.The read current of read operation 18 is less than or equal to configuration or resetting current difference corresponding time T (WR1), T (WR0).For example, read time T (READ) can be less than half of reset time, read current can less than the configuration electric current half.Resetting current can be than the configuration electric current double or more, setup time can be reset time double, three, five times or more.
Figure 4 shows that the structure of phase-change memory cell array.Word line WL0～3 are applied to the grid of transistor selector switch 12, and bit line BL0～2 are connected to the drain electrode of transistor selector switch 12.A series of potpourri resistance 10 is connected between the source electrode and cell voltage V of transistor selector switch 12, and this V can be ground connection, power supply or other voltage, and can change between opening and closing, for example cuts off the electricity supply and forbids an array or piece.
Each potpourri resistance 10 can be the high impedance amorphous state, or low-impedance crystalline state.The electric current that flows out from bit line by the sensed amplifier induction in potpourri resistance 10 backs, amplification transistor selector switch 12 and the selected word line (OK), cushion the data that in the unit, read with generation.The electric current of potpourri resistance 10 of flowing through is less than or equal to read current.
In writing process, induction amplifier 20 activating position line drivers drive configuration or the potpourri resistance of resetting current through selecting on the bit line.Continue the configuration electric current or after reset time, potpourri resistance 10 is deformed into new state, as amorphous state or crystalline state at this electric current.Owing to only activate a word line at every turn, thus in every row only a unit be written into.Use resetting current on the bit line and continue week reset time after date, these row are written into 0, and the application configuration electric current also continues week setup time after date on the bit line, and these row are written into 1.
Figure 5 shows that quick hang-up/restoration methods of on the CPU local bus, using the personal computer of phase transition storage.CPU22 is reading command and data from the PCM module 50 that forms CPU primary memory piece.PCM module 50 comprises the non-volatile phase-change memory cell.Video PCM 52 has also adopted phase transition storage.High-speed cache 54 can be standard SRAM, perhaps adopts PCM equally.When high-speed cache 54 used SRAM, the content of high-speed cache 54 can be lost in hang-up or recovery routine, and is written into again from PCM module 50 after recovery.
When hang up taking place, for the purpose of safety or back compatible etc., OS image 44 can be copied to becomes OS image 44 ' in the hard disk drive 34.But because phase transition storage is non-volatile, then OS image 44 is retained in the PCM module 50.Therefore when recovering, need not again OS image 44 ' to be duplicated out from hard disk drive.The substitute is, CPU22 can directly recover to carry out instruction and data in the OS image 44 from PCM module 50, and need not to carry out the very long reproduction process from the OS image 44 ' of hard disk drive 34.Therefore greatly reduced release time.
Video PCM storer 52 also is made up of phase transition storage, therefore hangs up the back buffered frame at power supply and also still is retained in wherein.In case when recovering, display 26 can need not reconstruct and play up and just can recover the pixel that reads in the display buffer frame from video PCM storer 52.Therefore, do not regenerate buffered frame and also saved a large amount of time, display 26 can be shown to the user quickly.Because, be especially conspicuous directly so recover the demonstration time faster in the face of the user shows.
When hang-up startup ROM38 was connected to CPU22, I/O coprocessor 28 did not need configuration, has further saved the time yet.Because slower, also further be improved so handle the time of hang-up/recovery routine through relative access local bus of the bus cycles of I/O coprocessor 28 40.
Because used the non-volatile phase-change storer on the local bus 40, OS image 44 ' does not need to read from hard disk drive and duplicate, and the startup loader also need not to read from start ROM38.In some embodiments, phase transition storage may be used to replace the memory cell that starts ROM38, flash memory 36, or replace hard disk drive 34 as solid-state memory.
Fig. 6 has more specifically described the quick recovery method that uses the mainboard of phase transition storage.Though some assembly can realize on subcard or additional card that mainboard 100 can be used as the main printed circuit board (PCB) of personal computer.For example, PCM memory module 50 can be the minimum storage module card in the memory module slot that is inserted in mainboard 100, and flash storer 36 can be used as the SFP equipment that inserts the USB socket.Modem 62 also can equally with other assembly be located on the mainboard 100 or be located at additional ISA card or AT card.
CPU22 with data and instruction storage in high-speed cache 54.High-speed cache 54 can be made of phase transition storage, also can be the SRAM high-speed cache.When high-speed cache 54 was integrated in CPU22, high-speed cache 54 can be SRAM, and this depends primarily on microprocessor manufacturers.When high-speed cache 54 is PCM,, therefore may obtain to recover faster because high-speed cache 54 need not cleaning and is written into again.
North bridge controller (north bridge controller) 56 is the chip or a chipset that various local buss can be connected together, as cpu bus, the video bus that is connected to video PCM storer 52 of coming from CPU22, the memory bus 51 that is connected to PCM memory module 50.The PCM Memory Controller 58 of north bridge controller 56 produces regular hours and voltage and reads, resets, disposes memory cell in the PCM memory module 50, or these functions also can be integrated in the PCM memory chip in the memory module 50.PCM Memory Controller 58 also can place on the every PCM memory module 50, or the Memory Controller function also can be distinguished realization on PCM memory chip, memory module and north bridge controller 56 individually.
South bridge controller (south bridge controller) 62 is connected to slower bus with pci bus, as usb bus, integrated electronics (IDE) bus, serial ATA bus (SATA), ATA or Industry Standard Architecture (ISA) bus, and transmits data.Equipment component on these buses is removable, and except flash memory and DRAM storer, the equipment that may upgrade in addition also can use phase transition storage.For example, PCM solid magnetic disc 60 can be used as mass-memory unit, and the piece addressing unit also can use phase transition storage and not only be confined to flash storer or rotating disk.Start-up code also can be stored in and start among PCM68 rather than the startup ROM38 (as shown in Figure 5).
Older and slower external unit can place on the isa bus, carries out access by CPU22 or DMA by north bridge controller 56 and south bridge controller 62.Modulator-demodular unit 62, audio system 64 and super I/O66 are the examples of older external unit, can place on the independently removable ISA card or are integrated on the mainboard 100.Integrated I/O controller chip also can comprise above-mentioned all functions and directly solidify on mainboard 100.
Fig. 7 is the structural drawing of phase transition storage.The PCM chip can comprise the part or all of piece shown in Fig. 7, and other piece or partial function wherein can be finished by independent PCM controller.
The row certain applications of address are selected one group of bit line to be used for data access by 132 decodings of Y demoder in address decoder 112 then.Data buffer 126 can have the width of qualification, and as 64 bytes, and the PCM unit can have the bit line of bigger quantity, as 8 * 64 row.Row in 8 row can be selected by Y demoder 132 and connect data buffer 126.
Writing fashionablely, data buffer 126 is collected external datas and also is applied to write driver 136.Write driver 136 produces voltage or electric current can be applicable to will be written as in the PCM unit 1 bit line so that dispose electric current, and higher resetting current is applied to will be written as in the PCM unit 0 bit line.
Configuration, resetting voltage timer 138 comprise time configuration cycle, the resetting current that guarantee the lasting length of write driver application configuration electric current and continue time reset cycle of weak point.The write driver 136 of PCM unit of resetting is disabled after time reset cycle.
State machine (state machine) 122 can activate configuration, resetting voltage timer 138 and cause logic controller (control logic) 120 to pass after date disable write driver 136 in configuration and time reset cycle.State machine 122 can produce multiple internal control signal at reasonable time, enters data buffer 126 for example for bit line precharge unlatching and sensed data and latchs etc.
But command register 114 receive logic controllers, 120 decodings and the order of handling well.May also to receive in some embodiments as external commands such as reading and writing, data switch, position enable.Command register 114 can be in some embodiments as command decoder.When for example not selecting the PCM chip, the power supply that Power Management Unit 116 can be closed piece reduces power consumption.Because PCM unit 110 is non-volatile, so when power supply disconnected, data still can keep wherein.
Figure 8 shows that the structure of phase transition storage module.In some embodiments, the DRAM memory module of PCM memory module 50 alternative standards, but may need different applied voltage and different control signal and time with the DRAM of standard.
Bus interface logic device (bus interface logic) 82 sends and received signal from mainboard 100 by memory bus 51.For example, mainboard 100 can send the universal serial bus bag but not independent address and data to the PCM memory module.Bus interface logic 82 can be analyzed these bags and produce the PCM dedicated control signal, is reformatted as PCM array 88 used address and data.
PCM memory module 50 can be complete buffer storage module, has multibus and is connected to storer upstream and downstream memory module.For example, connect in the parallel continuous circuit to the specific data uplink of the circuit transmission of north bridge to the north bridge controller, or to an intermediate storage module of north bridge controller front end.Connecting can be from CPU and its north bridge controller transmission data to the daisy chain of descending reservoir module to the circuit of south bridge.
Selectable embodiment
The inventor has also conceived some other embodiment.For example, but mainboard integrated video storer, and video memory also is attachable on the video control card, or video memory can be the part of primary memory, perhaps also can directly be arranged in mainboard or the memory module.The part that video memory can be used as a high integration system chip is integrated in the video card controller.Some storer may be old-fashioned SRAM or DRAM, and other storer then is PCM.The OS image of depositing among the PCM is used to improve the performance of hang-up/recovery.Physical storage may be partitioned into some less memory cells, as video and audio frequency buffering, user, application program and operating system space.
Except above-mentioned personal computer, the computing machine of other type also can obtain advantage by quick hang-up/restoration methods of using PCM.For example, the computing machine or the mobile device of laptop computer, apple MAC machine, Linux, Unix or other type all can be used as the computing machine that uses this invention as super mobile personal computer (UMPC), mobile network appliance, PDA(Personal Digital Assistant), smart phone, hand held mobile phone, game station and game terminal.
Variable transistors composition sequence shown in the PCM unit can use maybe can increase other transistor, and for example each unit has the double port memory of 2 bit line, or two kinds of transistor selector switchs are connected to equal mixture resistance.Temperature of fusion and Tc may because of potpourri form and other factors such as purity etc. different, the shape of potpourri resistance and the big or small temperature and time cycle that also may have influence on configuration, reset in addition.
Configuration and any one logic state that resets and also can be applicable to the binary logic state.For example, configuration can be made a comment or criticism and be become logical one to logic, or refers to that reverse logic or negative logic become logical zero.Similarly, for the effective logic of low state, resetting of forward logic becomes 0, but its reverse logic then is reset to 1.Same system can use effective logic of low state and the effective logic scope of high state simultaneously, and logic relates to the mode that reads of physical state, memory chip I/O of memory cell or others etc.
Guidance quality wording as upwards, lower, upper and lower, top, the end or the like all be relative, and can change along with the rotation of equipment, upset.These wording are useful to description equipment, but and nisi.Some embodiment may have the side of the assembly of chip or other carry at circuit board, and other embodiment may be that the assembly carry is at bilateral.
Non-encapsulation die may use welding mould technology rather than be installed on a side or many sides of mainboard as encapsulated integrated circuit.Use non-encapsulation die rather than encapsulation die can reduce the size and the weight of card.The edge of mainboard can be straight line, circle shape or other shape etc.
Except usb bus, can also use other universal serial bus, as PCIE, ExpressCard, live wire (IEEE1394), serial ATA, small computer system interface (SCSI) bus or the like.For example, when PCIE was used, the additional pin of PCIE interface can be quoted or alternative USB differential data pin.The PCIE pin comprises transmission differential pair PET+, PET-and reception differential pair PER+, the data pin of PER-.But multibus protocol chip bells and whistles pin is selected available serial bus interface or the register of programming is arranged.Therefore ExpressCard has USB and PCIE bus simultaneously, wherein one or all can be present in the ExpressCard equipment.
The microprocessor assembly of Memory Controllers such as tandem engine, DMA, PCM, the transfer management method, other controller and function can be accomplished in several ways when implementing.These functions can and be carried out by CPU and the programming of other processor, or are carried out by specialized hardware, firmware or its combination.In addition, the mass part of these functions all is alternative.
Standard FLASH, DRAM or SRAM controller can be integrated in the PCM controller, allow the various storeies of access.Hang-up and recovery routine may comprise part instruction, manufacturer's specific program, advanced application or its combination of operating system/Basic Input or Output System (BIOS) (BIOS).Also may use the bus architecture of various modifications, can form by a plurality of fragments that buffering or other chip are cut apart as the various buses of local bus.
Binary data of each unit storage of above-mentioned phase transition storage.However, also conceived the multi-level-cell of many logic levels of using the definition of many resistance values potpourri.
Above-mentioned any advantage and benefit may not be all to be applied in the embodiment of the present invention.When word " device " is listed in the claims, the applicant asks this claim to belong to the 35th article of the 112nd joint of United States Code the 6th segment limit.One or more placing " device " word before is used for simplifying but and unrestricted claim.The claim of these device+functions not only covers structure or its structuring that described herein being used to finish function and is equal to, and also comprises its equivalent structure simultaneously.For example, although nail has different structures with screw, when they all are used to finish fixation equivalent structure.Do not use the claim of word " device " not belong to the 35th article of the 112nd joint of United States Code the 6th segment limit.Signal is generally electric signal, but also can be the fiber-optic signal that conducts on the optical fiber.
The description of aforesaid embodiment of the present invention all is for separating the purpose of description of mediating a settlement, and it is not to have no to omit or be restricted to the concrete form that is disclosed.According to top description, many modifications and variations all are possible.Therefore the protection domain of invention is not limited to according to describing details in the literary composition, and should judge according to relevant claim.
Claims (14)
1. phase transition storage mainboard comprises:
One primary memory, be used for instruction and data is stored in phase transition storage, wherein, instruction and data still keeps when power supply is removed primary memory, phase transition storage comprises a large amount of phase transition storage PCM unit, and each unit contains: have crystalline state potpourri first logic state and have second logic state of amorphous potpourri, wherein, the resistance ratio crystalline state of amorphous state potpourri is mixed object height;
One processor is connected to primary memory, is used to obtain and carry out the instruction of primary memory, and writes data to primary memory;
One video memory writes by the processor connection, is used to store the pixel frame buffer device that treated device upgrades, and this frame buffer comprises the pixel data that is used for the user is produced visible demonstration;
One cache memory is connected to processor, is used to store the zero access instruction and data copy of primary memory;
One mass-memory unit is used for storage instruction piece and data block, and mass-memory unit is the piece addressing, wherein, single instruction can not be independent of in the instruction block other instruction and by access;
One input and output coprocessor is located between mass-memory unit and the primary memory, is used for from mass-memory unit read block and instruction block, and data block and instruction block are write in the primary memory;
One operating system image is stored in the phase transition storage of primary memory, is used for the instruction and the systematic parameter of processor controls when being included in user's routine operation;
One hang-up/recovery routine, in the phase transition storage of primary memory, when user's pending operation, before power supply disconnected from primary memory, processor was carried out hang-up/recovery routine immediately as instruction storage; When user's recovery operation, after the power supply of primary memory recovered again, processor was carried out hang-up/recovery routine immediately; With
One substrate is used for supporting and being electrically connected primary memory, processor, video memory, input and output coprocessor;
Thus, hang-up/recovery routine is stored in the phase transition storage of primary memory and is performed;
Described video memory and primary memory are for sharing the part of phase transition storage, and when the power supply of video memory disconnected, frame buffer still was retained, and after hang-up/recovery operation, when power up, also can not regenerated by processor;
Described cache memory comprises static RAM; Wherein, hang-up/recovery routine also comprises:
One high-speed cache illegal instruction is used for disabling cache storer when hanging up;
One high-speed cache cleaning instruction is used to delete the instruction and data that is stored in cache memory;
One cache enabling order when the recovery operation of carrying out after the high-speed cache cleaning is instructed, is used to make cache memory can be written into the instruction and data that reads in primary memory again;
Thus, cache memory is cleared up and is written into again through hang-ups/recovery operation, and primary memory still reserve statement and data in hang-up/recovery operation process;
Described cache memory comprises the phase transition storage of being made up of a large amount of phase transition storage PCM unit;
Wherein, when outage took place in the pending operation process, cache memory is the copy of reserve statement and data still, and at this moment, cache memory is not cleared up in hang-up/rejuvenation.
2. a kind of phase transition storage mainboard as claimed in claim 1 also comprises:
One local bridging chip, be connected between processor and the primary memory, be used for obtaining instruction from primary memory, and the instruction that will take out by processor bus sends to processor by memory bus, thus, processor and primary memory link together by local bridging chip.
3. a kind of phase transition storage mainboard as claimed in claim 2, wherein, the independent instruction and data of processor direct access primary memory, wherein, phase transition storage is randow addressing.
4. a kind of phase transition storage mainboard as claimed in claim 1, wherein, a phase transition storage PCM unit in a large amount of phase transition storage PCM unit comprises:
One transistor selector switch by gate circuit connective word circuit, is the passage between bit line and the cell node;
One potpourri resistance is made up of potpourri, is connected between cell node and the array voltage;
Wherein, the transistor selector switch has grid, drain electrode and three tie points of source electrode, and grid is by gate circuit connective word circuit, and drain electrode connects bit line, and source electrode connects potpourri resistance;
Wherein, cell node is the source electrode of transistor selector switch;
Wherein, when the potpourri of potpourri resistance is in crystalline state, phase transition storage PCM unit is positioned at first logic state, and potpourri resistance is Low ESR, can increase the induction current by the transistor selector switch;
Wherein, when the potpourri of potpourri resistance is in amorphous state, phase transition storage PCM unit is positioned at second logic state, and potpourri resistance is high impedance, can reduce the induction current by the transistor selector switch;
Wherein high impedance is than the low-resistance Chinese People's Anti-Japanese Military and Political College, so induction current can be realized changing by conversion between crystalline state and the amorphous potpourri.
5. a kind of phase transition storage mainboard as claimed in claim 4, wherein, phase transition storage also comprises:
One is connected to the configuration current feedback circuit of bit line, be used for by transistor selector switch and potpourri resistance through a time configuration cycle drive arrangements electric current, write phase transition storage PCM unit to the first logic state, a corresponding write data inputs to first logic state;
One is connected to the resetting current generator of bit line, be used for driving resetting current through time reset cycle by transistor selector switch and potpourri resistance, write phase transition storage PCM unit to the second logic state, a corresponding write data inputs to second logic state;
One reset timer is used to judge time reset cycle; With
One configuration timer is used to judge time configuration cycle;
Wherein, more than the twice of resetting current for the configuration electric current, the configuration electric current is more than the faradic twice;
Wherein, time configuration cycle is more than the twice of time reset cycle, therefore, phase transition storage PCM unit by reduced-current, continue cycle long period and finish configuration, and by high current, continue cycle short period and finish and reset.
6. a kind of phase transition storage mainboard as claimed in claim 5, wherein, potpourri is the chalcogenide glass layer that fusing point is higher than crystallization point.
7. a kind of phase transition storage mainboard as claimed in claim 6, wherein, potpourri is the potpourri of germanium, antimony and tellurium.
8. non-volatile computer comprises:
Processor device is used to obtain and execution command and write data;
Phase-changing storage device is used to store the instruction and data of binary digit, and wherein every binary digit is represented a chalcogenide glass layer higher than crystallization point temperature, and this of chalcogenide glass layer formation changes faradic variable resistor when reading binary digit;
Wherein, variable-resistance crystalline state representative is stored in first binary logic state of binary digit in the phase-changing storage device, and variable-resistance amorphous state is then represented second binary logic state that is stored in binary digit in the phase-changing storage device;
Local bus control's device, be used to receive the address of from processor device, from the phase-changing storage device that is stored in the from processor unit address, obtain instruction, corresponding data address from phase-changing storage device is carried out data transmission between processor device and phase-changing storage device;
Configuration electric current timer device connects phase-changing storage device, when binary digit is written into first binary logic state, is used for producing a configuration electric current by a configuration cycle, and variable resistor is configured to crystalline state;
The resetting current timer device connects phase-changing storage device, when binary digit is written into second binary logic state, is used for producing a resetting current by a reset cycle, and variable resistor is reset to amorphous state;
Wherein, resetting current is flowed through more than the variable-resistance faradic twice when disposing electric current for read operation for more than 2 times of electric current of configuration;
Wherein configuration cycle is more than the twice of reset cycle;
That is to say, variable resistor by reduced-current, continue cycle long period and finish configuration, by high current, continue cycle short period and finish and reset;
The video phase-changing storage device, be used to store a pixel frame buffer device that shows by display, wherein, pixel is made up of binary digit, the chalcogenide glass layer that fusing point is higher than the crystalline state temperature is represented bit, when reading binary digit, this chalcogenide glass layer forms one can change faradic variable resistor;
Wherein, variable-resistance crystalline state representative is stored in first binary logic state in the phase-changing storage device, and variable-resistance amorphous state representative is stored in second binary logic state in the phase-changing storage device;
Wherein, local bus control's device also is used for the pixel that processor device generates is written to the video phase-changing storage device;
That is to say that frame buffer pixel is stored in the phase-changing storage device;
Wherein, the pixel frame buffer device that is stored in the video phase-changing storage device is retained after power supply is hung up, and non-volatile computer enters Suspend Mode;
Wherein, when power supply is hung up, the instruction and data that is stored in phase-changing storage device will be retained, and non-volatile computer enters Suspend Mode; That is to say that pixel frame buffer device and instruction storage are in nonvolatile memory.
9. non-volatile computer as claimed in claim 8 also comprises:
Local operating system's device for image, the current operation status that is used to store non-volatile computer, local operating system's device for image is stored in the phase-changing storage device;
Wherein, when power supply was hung up, non-volatile computer entered Suspend Mode, and local operating system's device for image still is retained;
Recovery device during power up, is carried out by processor device behind Suspend Mode, is used for carrying out reading command from local operating system's device for image that phase-changing storage device reads;
Wherein, processor device is by carrying out the instruction recovery operation from phase-changing storage device;
That is to say, hang up back local operating system image and still be retained in the phase-changing storage device.
10. non-volatile computer as claimed in claim 9 also comprises:
The peripheral bus control device connects local bus control's device, is used to connect the external unit on local bus control's device and the peripheral bus;
Mass storage device connects the peripheral bus control device, is used to store addressable blocks, and wherein, addressable blocks comprises can not the independent addressing of processed apparatus but the instruction and data piece of piece addressing;
Peripheral operation system device for image is used to store the copy of non-volatile computer current operation system state, and peripheral operation system device for image is stored in the mass storage device;
Wherein, processor device need not to duplicate peripheral operation system device for image in the recovery operation from mass storage device;
That is to say that behind pending operation, need not from the copy of mass storage device transmission current operation system state, the local operating system's device for image in the phase-changing storage device can be retained and be performed.
11. a phase transition storage personal computer comprises:
One microprocessor, be used for the execution command and in local storage space write data;
One phase transition storage is present in the local storage space, the instruction and data that storage can directly be visited by microprocessor;
Wherein, the pixel frame buffer device that is stored in the video phase transition storage is retained after power supply is hung up, and the phase transition storage personal computer enters Suspend Mode;
Wherein, when power supply is hung up, the instruction and data that is stored in phase transition storage will be retained, and the phase transition storage personal computer enters Suspend Mode;
That is to say that pixel frame buffer device and instruction storage are in nonvolatile memory;
The memory cell array of one phase transition storage, each memory cell have the storage binary digit as solid-state potpourri resistance, and each is solid-state to have different resistance;
Wherein, when memory cell when logical one is written as logical zero, through a reset cycle, the response resetting current, thereby potpourri resistance becomes amorphous state from crystalline state;
When memory cell when logical zero is written as logical one, through a configuration cycle, response configuration electric current, thereby resistance becomes crystalline state from amorphous state;
Wherein, amorphous state has higher resistance and sensed amplifier than crystalline state and responds to;
One local bus control is used for transfer instruction and data between phase transition storage and microprocessor;
Display buffer connects the pixel that receives through the microprocessor renewal by local bus control, and this display buffer is used for storage pixel in the phase transition storage that is formed by the memory cell that all has potpourri resistance;
Video Controller, the pixel that is used to drive display buffer is given display, and is shown to the user;
That is to say that pixel and instruction storage are in phase transition storage.
12. phase transition storage personal computer as claimed in claim 11 also comprises:
One peripheral bus controller connects local bus control, is used for the external unit on the access peripheral bus;
One starts ROM (read-only memory), connects the peripheral bus controller, is used to be stored in the performed start-up routine instruction of microprocessor under the initial electric power starting situation; With
One hang-up/recovery instruction is stored in the phase transition storage, can directly be carried out by microprocessor when recovering power supply before hanging up power supply or after the power supply hang-up;
That is to say that the start-up routine instruction that starts ROM (read-only memory) is being carried out by microprocessor under initial electric power starting situation, hang-ups/recovery is instructed to read out from phase transition storage and is used for hang-up/recovery and carries out.
13. phase transition storage personal computer as claimed in claim 12 also comprises:
One mass-memory unit is on first media bus between local bus control and the peripheral bus controller;
One network controller is used to be connected to network, and network controller is positioned on first media bus;
Wherein, external unit comprises:
One flash memory is located on first peripheral bus, connects the peripheral bus controller, is used for storing data in flash memory;
Described startup ROM (read-only memory) is located on second peripheral bus, connects the peripheral bus controller, and storage can be the start-up code that microprocessor is carried out when being used for electric power starting;
One Audio Controller is located on second peripheral bus, connects the peripheral bus controller, is used to send the sound that the user can hear.
14. phase transition storage personal computer as claimed in claim 11 also comprises:
One reset timer is used to judge time reset cycle; With
One configuration timer is used to judge time configuration cycle;
Wherein, more than the twice of resetting current for the configuration electric current, the configuration electric current is more than the faradic twice that is used to read;
Time configuration cycle is more than the twice of time reset cycle;
That is to say that the potpourri resistance in the memory cell is finished configuration by long period, low voltage, finish by short period, high voltage and reset.
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| US11/740,398 US20080270811A1 (en) | 2007-04-26 | 2007-04-26 | Fast Suspend-Resume of Computer Motherboard Using Phase-Change Memory |
| US11/740398 | 2007-04-26 |
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| CN101122865A CN101122865A (en) | 2008-02-13 |
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| CN200710154015.3A Expired - Fee Related CN101122865B (en) | 2007-04-26 | 2007-09-09 | Computer mainboard quick suspending and recovery device using phase-change memory |
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| US (1) | US20080270811A1 (en) |
| CN (1) | CN101122865B (en) |
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| CN101122865A (en) | 2008-02-13 |
| US20080270811A1 (en) | 2008-10-30 |
| TW200842887A (en) | 2008-11-01 |
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