CN101114672A - Grid grounding transistor of electrostatic discharge protective equipment - Google Patents

Grid grounding transistor of electrostatic discharge protective equipment Download PDF

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Publication number
CN101114672A
CN101114672A CNA2006100294814A CN200610029481A CN101114672A CN 101114672 A CN101114672 A CN 101114672A CN A2006100294814 A CNA2006100294814 A CN A2006100294814A CN 200610029481 A CN200610029481 A CN 200610029481A CN 101114672 A CN101114672 A CN 101114672A
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CN
China
Prior art keywords
dopant well
electrostatic discharge
protective equipment
discharge protective
doped region
Prior art date
Application number
CNA2006100294814A
Other languages
Chinese (zh)
Inventor
高荣正
高文玉
黄圣扬
Original Assignee
上海宏力半导体制造有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 上海宏力半导体制造有限公司 filed Critical 上海宏力半导体制造有限公司
Priority to CNA2006100294814A priority Critical patent/CN101114672A/en
Publication of CN101114672A publication Critical patent/CN101114672A/en

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Abstract

The invention provides a grid grounding transistor for a protecting device of electrostatic discharge comprising a doping well area which has the same type with a drain contact area, and a separating structure that makes a resistance area between the drain contact area and a poly gate to be used as a resistance ballast area through which the high current producing by electrostatic discharge can be eliminated in a uniform way in order to avoid the phenomenon of local high current and local heating produced nearby the drain contact area and effectively avoid potential damage of protecting device of electrostatic discharge to realize better effect under the situation of reduction of the size of the resistance ballast area between the drain contact area and a poly gate.

Description

The grid grounding transistor of electrostatic discharge protective equipment

Technical field

The present invention relates to a kind of electrostatic discharge protective equipment (ESD Protection device), particularly in the technology about deep-sub-micrometer, can avoid the grid grounding transistor of the ruined a kind of electrostatic discharge protective equipment of electro-static discharge structure simultaneously.

Background technology

The N type in integrated circuit or the structure of P transistor npn npn as the structure of gg (gate-ground) N/PMOS or other similar form, are widely used in the device assembly of present deep-sub-micrometer electrostatic discharge (ESD) protection.GgN/PMOS mainly is the component characteristic of its parasitic bipolar transistor (Bipolar), when high voltage in a flash takes place, its parasitic bipolar transistor will be triggered and high electric current that suitable its high voltage of guiding is produced to Vss or Vdd end.

See also Fig. 1, this is for using ggN/PMOS assembly circuit structure as electrostatic discharge protective equipment 2 in integrated circuit, moment the forward high voltage can start the parasitic bipolar assembly of NMOS 4, high current steering is held to Vss; Moment, reverse high voltage then started the parasitic bipolar assembly among the PMOS 6, and high current steering is held to Vdd.This kind application principle as shown in Figure 2, when an electrostatic discharge event betides the pin position (Pad) of an input, this ggN/PMOS will be triggered (trigger), and enter rapid commentaries on classics zone (snapback region), and this rapid commentaries on classics in the zone, this ggN/PMOS with clamping across itself a low-potential voltage and keep a high electric current, this static discharge current can be guided away effectively.

See also Fig. 3; when the ggNMOS component application in utilizing non-structure of aiming at voluntarily in the electrostatic discharge protective equipment that metal silicide (Salicide) technology makes; its drain region 8 is to there being the effect of a buffer distance as the resistance buffering area between the polysilicon gate 10; when NPN transistor 12 was triggered, its high electric current is excluding of (homogeneous) relatively evenly.

Yet; in the technology of deep-sub-micrometer; aim at metal silicide 14 voluntarily and be applied to comprise ESD-protection structure interior polysilicon gate 10 and source/drain region 16,8, see also Fig. 4, this will cause between drain region contact 8 and the polysilicon gate 10 and almost have not a particle of the resistance buffering area.When a static high voltage produces; cause parasitic NPN (or PNP) in the ESD-protection structure when transistor is triggered; though the electric current that high voltage produced can exclude; collection utmost point N (the Collector N of right NPN transistor; be equivalent to the drain electrode among the ggNMOS) there is not a resistance buffering area; add it for the structural design of shallow junction (shallowjunction); flowing of high electric current will inhomogeneous (inhomogeneous); there are local high electric current and localized heating phenomenon to produce near causing the drain region; cause protecting structure to suffer potential destruction, and then lose the effect of its electrostatic discharge (ESD) protection.

Therefore, the present invention is directed to above-mentioned problem, propose a kind of grid grounding transistor of electrostatic discharge protective equipment, to solve the above problems.

Summary of the invention

Main purpose of the present invention is; a kind of grid grounding transistor of electrostatic discharge protective equipment is provided; comprise one with the doped well region of drain region homotype; and in it, form an isolation structure; make the drain region to there being the effect of a buffer distance between the polysilicon gate as the resistance buffering area, and by the high electric current that this resistance buffering area produces static discharge can have one uniformly mode it is excluded.

Another object of the present invention is to; a kind of grid grounding transistor of electrostatic discharge protective equipment is provided; the high electric current that the static high voltage produces effectively can be guided away; to avoid near the drain region, producing local high electric current and local heating phenomena, so can effectively avoid ESD-protection structure by potential destruction.

A further object of the present invention is, a kind of grid grounding transistor of electrostatic discharge protective equipment is provided, can make the drain region to the size of the resistance buffering area between the polysilicon gate under the situation of dwindling, realize better effect.

For reaching above-mentioned purpose; the invention provides a kind of grid grounding transistor of electrostatic discharge protective equipment; it comprises the semiconductor substrate; 2 first isolation structures; one polysilicon gate construction; the ion doped region of one source/drain electrode and one second isolation structure; be formed with a N type dopant well and a P type dopant well on this semiconductor-based end; and in N type dopant well and P type dopant well, be formed with two first isolation structures; and the first isolation structure definable goes out an active area; this polysilicon gate construction forms on P type dopant well; and the ion doped region of formation source/drain electrode in the active area of polysilicon gate construction both sides, and second isolation structure that the ion doped region of drain electrode can be divided into two doped regions that is positioned at N type dopant well.

The present invention can exclude it in uniform mode by the high electric current that the resistance buffering area produces static discharge; local high electric current and local heating phenomena have been avoided near the drain region, producing; can effectively avoid ESD-protection structure by potential destruction; can make the drain region to the size of the resistance buffering area between the polysilicon gate under the situation of dwindling, realize better effect.

Further specify the present invention below in conjunction with drawings and Examples.

Description of drawings

Fig. 1 is the line construction schematic diagram of MOS component application in integrated circuit of existing electrostatic discharge protective equipment.

The curve chart of static discharge phenomenon for taking place in Fig. 2.

Fig. 3 is for having the MOS component application now in the structural representation of electrostatic discharge protective equipment.

Fig. 4 is existing transistor arrangement schematic diagram with electrostatic discharge protective equipment of aiming at metal silicide voluntarily.

Fig. 5 is the structure cutaway view of internal circuit of the present invention and electrostatic discharge protective equipment.

Fig. 6 is the structure cutaway view of another embodiment of the present invention.

Label declaration

2 electrostatic discharge (ESD) protections are adorned 28 active area

4NMOS 30 polysilicon gate constructions

6PMOS 32 polysilicon layers

8 drain regions, 34 grid oxic horizons

10 polysilicon gates, 36 clearance walls

12NPN transistor 38 polysilicon layers

14 aim at metal silicide 40 source electrode ion doped regions voluntarily

42 drain electrode ion doping districts, 16 source regions

20 isolation structures of the semiconductor-based ends 44 second

22N type dopant well 46P type dopant well

24P type dopant well 48N type dopant well

26 first isolation structures, 50 baried type doped regions

Embodiment

The present invention is directed to the shortcoming that the conventional electrostatic discharging protection component is being aimed in the metal silicide technology to be produced voluntarily; the present invention includes one with the doped well region of drain region homotype; and in it, form an isolation structure; make the drain region to there being a resistance buffering area between the polysilicon gate; the high electric current that can allow static discharge produce can exclude it in uniform mode, so can not produce local high electric current and localized heating phenomenon near the drain region.

The present invention is a kind of grid grounding transistor of electrostatic discharge protective equipment; at first see also Fig. 5; the present invention includes semiconductor substrate 20; 2 first isolation structures 26; one polysilicon gate construction 30; the ion doped region 42 of one source/drain electrode; 42 and 1 second isolation structure 44; on the semiconductor-based end 20, form a N type dopant well 22 and a P type dopant well 24; in N type dopant well 22 and P type dopant well 24, form first isolation structure 26; and first isolation structure 26 defines an active area 28; and on P type dopant well 24, form polysilicon gate construction 30; polysilicon gate construction 30 comprises a polysilicon layer 32; the clearance wall 36 of one grid oxic horizon 34 and polysilicon layer 32 both sides; and can be formed with a light ion doped region 38 for 36 times at clearance wall; and the ion doped region 40 of formation source/drain electrode in the active area 28 of polysilicon gate construction 30 both sides; 42; the ion doped region 40 of source/drain electrode then; 42 is N type ion doped region; wherein the ion doped region 40 of source electrode is formed on the P type dopant well 24; the ion doped region 42 that second isolation structure 44 drains in N type dopant well 22 is between the polysilicon gate structure 30; and the ion doped region 42 that second isolation structure 44 will drain is divided into two doped regions, and first isolation structure 26; second isolation structure 44 is all fleet plough groove isolation structure (STI).

In addition to the implementation, see also Fig. 6, the present invention also can change N type dopant well 22 shown in Figure 5 into a P type dopant well 46, P type dopant well 24 changes N type dopant well 48 into, the ion doped region 40 of source/drain electrode then, 42 is P type ion doped region, and can in P type dopant well 46 and N type dopant well 48, form a baried type doped region 50, and baried type doped region 50 is all the N type with N type dopant well 48, therefore the present invention uses and can change P type dopant well 46 according to different demands, the polarity of N type dopant well 48 and baried type doped region 50, and be not subjected to the restriction of single situation demand.

Comprehensively described; the grid grounding transistor of electrostatic discharge protective equipment provided by the invention; it can effectively be guided away the high electric current of static high voltage generation; to avoid near the drain region, producing local high electric current and local heating phenomena; so can effectively avoid ESD-protection structure by potential destruction; can make the drain region to the size of the resistance buffering area between the polysilicon gate under the situation of dwindling, realize better effect.

Above-described only is a preferred embodiment of the present invention; be not to be used for limiting scope of the invention process; therefore all equivalent variations and modifications of being done according to the described shape of the present patent application claim, structure, feature and spirit all should be encompassed in protection scope of the present invention.

Claims (9)

1. the grid grounding transistor of an electrostatic discharge protective equipment is characterized in that comprising:
The semiconductor substrate is formed with one first dopant well and one second dopant well on it;
2 first isolation structures, it is formed in this first dopant well and this second dopant well, and this first isolation structure defines an active area;
One polysilicon gate construction, it is formed on this second dopant well;
The ion doped region of one source/drain electrode, it is formed in this active area of these polysilicon gate construction both sides; And
One second isolation structure, it is positioned at this first dopant well, and the ion doped region that this second isolation structure should drain electrode is divided into two doped regions.
2. the grid grounding transistor of electrostatic discharge protective equipment according to claim 1, it is characterized in that: described isolation structure is a fleet plough groove isolation structure.
3. the grid grounding transistor of electrostatic discharge protective equipment according to claim 1, it is characterized in that: the ion doped region of described source electrode is formed on this second dopant well.
4. the grid grounding transistor of electrostatic discharge protective equipment according to claim 1, it is characterized in that: described first dopant well is a N type dopant well, when this second dopant well was P type dopant well, then the ion doped region of this source/drain electrode was a N type ion doped region.
5. the grid grounding transistor of electrostatic discharge protective equipment according to claim 1, it is characterized in that: described first dopant well is a P type dopant well, and this second dopant well is a N type dopant well, and the ion doped region trap of this source/drain electrode is a P type ion doped region.
6. the grid grounding transistor of electrostatic discharge protective equipment according to claim 5 is characterized in that: can in this first dopant well and this second dopant well, form one with the baried type doped region of this second dopant well homotype.
7. the grid grounding transistor of electrostatic discharge protective equipment according to claim 1 is characterized in that: described second isolation structure at the ion doped region of this drain electrode between this polysilicon gate construction.
8. the grid grounding transistor of electrostatic discharge protective equipment according to claim 1 is characterized in that: this polysilicon gate construction comprise a grid oxic horizon, a polysilicon layer with and the clearance wall of both sides.
9. the grid grounding transistor of electrostatic discharge protective equipment according to claim 1 is characterized in that: be formed with a light ion doped region under this clearance wall.
CNA2006100294814A 2006-07-27 2006-07-27 Grid grounding transistor of electrostatic discharge protective equipment CN101114672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNA2006100294814A CN101114672A (en) 2006-07-27 2006-07-27 Grid grounding transistor of electrostatic discharge protective equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA2006100294814A CN101114672A (en) 2006-07-27 2006-07-27 Grid grounding transistor of electrostatic discharge protective equipment

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CN101114672A true CN101114672A (en) 2008-01-30

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CNA2006100294814A CN101114672A (en) 2006-07-27 2006-07-27 Grid grounding transistor of electrostatic discharge protective equipment

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101752373B (en) * 2008-12-19 2011-09-28 上海华虹Nec电子有限公司 Anti-static protection structure and manufacturing method thereof
CN102222609A (en) * 2010-04-16 2011-10-19 立锜科技股份有限公司 Impurity concentration distribution control method of semiconductor component and related semiconductor component
CN102646601A (en) * 2012-04-19 2012-08-22 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
CN107293537A (en) * 2016-03-31 2017-10-24 旺宏电子股份有限公司 Electrostatic discharge protective equipment, memory component and electrostatic discharge protection method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101752373B (en) * 2008-12-19 2011-09-28 上海华虹Nec电子有限公司 Anti-static protection structure and manufacturing method thereof
CN102222609A (en) * 2010-04-16 2011-10-19 立锜科技股份有限公司 Impurity concentration distribution control method of semiconductor component and related semiconductor component
CN102222609B (en) * 2010-04-16 2013-07-31 立锜科技股份有限公司 Impurity concentration distribution control method of semiconductor component and related semiconductor component
CN102646601A (en) * 2012-04-19 2012-08-22 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
CN102646601B (en) * 2012-04-19 2016-09-28 北京燕东微电子有限公司 A kind of semiconductor structure and manufacture method thereof
CN107293537A (en) * 2016-03-31 2017-10-24 旺宏电子股份有限公司 Electrostatic discharge protective equipment, memory component and electrostatic discharge protection method
CN107293537B (en) * 2016-03-31 2020-02-21 旺宏电子股份有限公司 Electrostatic discharge protection device, memory element and electrostatic discharge protection method

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