CN101084625B - Microcontroller having a digital to frequency converter and/or a pulse frequency modulator - Google Patents

Microcontroller having a digital to frequency converter and/or a pulse frequency modulator Download PDF

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CN101084625B
CN101084625B CN 200580041272 CN200580041272A CN101084625B CN 101084625 B CN101084625 B CN 101084625B CN 200580041272 CN200580041272 CN 200580041272 CN 200580041272 A CN200580041272 A CN 200580041272A CN 101084625 B CN101084625 B CN 101084625B
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frequency
pulse
digital
converter
modulator
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CN 200580041272
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Chinese (zh)
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CN101084625A (en )
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斯科特·雷蒙德·芬克
约瑟夫·哈里·朱利谢
约翰尼斯·艾伯塔斯·范尼凯克
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密克罗奇普技术公司
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K7/00Modulating pulses with a continuously-variable modulating signal
    • H03K7/06Frequency or rate modulation, i.e. PFM or PRM

Abstract

A microcontroller having digital to frequency converter and pulse frequency modulator capabilities. The digital to frequency converter (DFC) generates a 50 percent duty cycle square wave signal that may be varied in frequency, wherein the 50 percent duty cycle square wave signal is directly proportional and linear with a count value put into an increment register. The pulse to frequency modulator(PFM) generates pulses having pulse widths of the input clock for each rollover of a counter. The frequency of these pulses is directly proportional and linear with the count value put into the increment register.

Description

具有数字到频率转换器和/或脉冲频率调制器的微控制器 A microcontroller having digital to frequency converter and / or pulse frequency modulator

技术领域 FIELD

[0001] 本发明涉及集成电路微控制器,更明确地说,涉及具有数字到频率转换器和脉冲频率调制器能力的集成电路微控制器。 [0001] The present invention relates to integrated circuit microcontrollers, more particularly, it relates to integrated circuit microcontroller having digital to frequency converter and pulse frequency modulator capabilities.

背景技术 Background technique

[0002] 集成电路微控制器使用时钟来驱动或逐步进行时序闩锁数字电路的操作以及经由数据总线的信息传送。 [0002] The integrated circuit microcontroller uses a clock to drive or step operation timing of the latch circuit and the digital information is transmitted via the data bus. 计时器、计数器、预定标器和存储寄存器也可并入到所述集成电路微控制器中,且可使用所述时钟来进行其操作。 Timers, counters, prescalers, and storage registers may also be incorporated into the integrated circuit microcontroller and may use the clock to its operation. 所述计数器针对每一时钟脉冲递增或递减一个计数,且用于所述计时器、预定标器等。 For each clock pulse the counter is incremented or decremented by one count, and for the timer, prescaler and the like. 微控制器广泛用于功率生成与控制、电子照明镇流器、马达控制和无线电调谐。 Microcontrollers are widely used in power generation and control, electronic lighting ballasts, motor control and radio tuning. 因此,需要集成电路微控制器具有数字到频率转换器(DFC)输出和/或脉冲频率调制器(PFM)输出。 Therefore, a digital to frequency converter (the DFC) output, and / or pulse frequency modulator (PFM) output integrated circuit microcontroller.

发明内容 SUMMARY

[0003] 本发明通过提供具有数字到频率转换器和/或脉冲频率调制器能力的集成电路微控制器来克服上述问题以及现有技术的其它缺点和不足。 [0003] The present invention overcomes the above problems and other disadvantages and deficiencies of the prior art by providing a digital to frequency converter and / or the integrated circuit microcontroller pulse frequency modulator capabilities. 所述数字到频率转换器(DFC) 可产生频率可变的百分之五十工作周期方波信号,其中所述百分之五十工作周期方波信号与输入到增量寄存器中的计数值成正比例且成线性关系。 The digital to frequency converter (the DFC) may generate a variable frequency fifty percent duty cycle square wave signal, wherein said fifty percent duty cycle square wave signal inputted to the count value in the increment register and linear proportional relation. 所述脉冲到频率调制器(PFM)可针对计数器的每次翻转产生具有输入时钟的脉冲宽度的脉冲。 The pulse to frequency modulator (PFM) may generate a pulse each toggle having a pulse width of the input clock for the counter. 这些脉冲的频率与输入到增量寄存器中的计数值成正比例且成线性关系。 Input frequency of these pulses to the count value in the increment register and linear proportional relation.

[0004] 由于DFC可以高频率(高达时钟频率的1/2)进行操作且PFM脉冲的长度非常短(输入时钟脉冲宽度),因此使用具有DFC和/或PFM能力的微控制器的电子系统的电感组件可显著较小,因为输出滤波器可经设计成以较高频率使用。 [0004] Since the DFC may be a high frequency (up to ½ the clock frequency) and the length of operation PFM pulse is very short (input clock pulse width), thus the use of an electronic system having a microcontroller DFC and / or PFM capabilities of inductance component may be significantly smaller, since the output filter may be designed to use a higher frequency. 用于产生DFC和/或PFM信号的逻辑电路也可用于标准计时器/计数器。 Logic for generating DFC and / or PFM signals may also be used in standard timer / counter. 因此,本发明的微控制器能够进行DFC和PFM 产生以及标准计时和计数。 Accordingly, the present invention microcontroller is capable of DFC and PFM generation, and standard timing and counting.

[0005] 根据本发明的特定示范性实施例,集成电路微控制器的DFC和/或PFM可包含内部振荡器(例如,晶体振荡器、RC振荡器、LC振荡器等)和/或提供外部振荡器、选通逻辑、 频率预定标器、同步器、计时器/计数器、全加器、增量寄存器、从属寄存器和死区产生器。 [0005] According to a particular exemplary embodiment of the present invention, the integrated circuit microcontroller and the DFC / PFM or may comprise an internal oscillator (e.g., Crystal Resonator, RC oscillator, the LC oscillator, etc.) and / or providing an external oscillator, gating logic, frequency prescaler, synchronizer, a timer / counter, a full-adder, an increment register, a slave register, and dead band generator. 所述从属寄存器可用于确保具有增量寄存器的数字装置的无假信号操作。 The slave register may be used to ensure that no glitch apparatus having a digital increment register operation.

[0006] 与仅可针对每个时钟脉冲递增一的标准计时器模块的操作相反,本发明的特定示范性实施例可将增量寄存器中的值相加到计时器/计数器中的值,并接着将所得的总和返回到计时器/计数器作为其中的新值。 [0006] and may be incremented by only one operation for each clock pulse of a standard timer module contrast, specific exemplary embodiments of the present invention may be the value of the phase increment register is added to the value of the timer counter /, and the resulting sum is then returned to the timer / counter as a new value therein. 这提供了“以N计数”的能力。 This provides the ability to "count by N" of. 这进一步允许使用高阶位(例如,8位计数器的位7、16位计数器的位15、32位计数器的位31等)来提供百分之五十工作周期输出。 This further allows the use of high-order bit (eg, bit 8-bit counter 7, 16-bit counter 31-bit counter 15, 32, etc.) to provide 50 percent duty cycle output. 当用于DFC输出时,此输出与载入到增量寄存器中的值成正比例且成线性关系。 When used DFC output that is proportional to the value loaded into an increment register and a linear relationship. 全加器的进位位可用作频率可变的用于提供固定脉冲周期的输出,从而提供PFM输出。 Full-adder carry bit is used as variable frequency for providing a fixed pulse period of the output, thereby providing a PFM output.

[0007] 本发明的特定示范性实施例也可具有补充性输出。 Certain exemplary [0007] embodiment of the present invention may also have complementary outputs. 死区产生器可具有死区寄存器,所述死区寄存器可含有死区所需的时钟脉冲的数目,例如,8位死区寄存器可用于在0 到255个死区时钟计数之间进行选择。 Dead band generator may have a dead band register, the dead zone may contain a register number of clock pulses required deadband, e.g., eight dead band register may be used between 0 to 255 clock counts selected deadband.

[0008] 本发明的技术优点是可以高达时钟输入的一半的频率进行变化的DFC输出。 [0008] The technical advantages of the present invention is half the frequency of the clock input may be as high as DFC output changes.

[0009] 另一技术优点是DFC输出与载入到增量寄存器中的值成正比例且成线性关系。 [0009] Another technical advantage is the DFC output is directly proportional to the value loaded into an increment register and a linear relationship.

[0010] 另一技术优点是DFC输出处于百分之五十工作周期。 [0010] Another technical advantage is the DFC output is at 50 percent duty cycle.

[0011] 另一技术优点是可使用从属寄存器来确保增量寄存器的无假信号操作。 [0011] Another technical advantage is a slave register may be used to ensure that the increment register glitch-free operation.

[0012] 另一技术优点是具有以N计数能力的计时器/计数器。 [0012] Another technical advantage is the ability to count N timer / counter.

[0013] 另一技术优点是可以高达时钟输入的一半的频率进行变化且具有输入时钟的脉冲宽度的PFM输出。 [0013] Another technical advantage is half the frequency of the clock input may be varied and has a high output PFM pulse width of the input clock.

[0014] 另一技术优点是PFM输出与载入到增量寄存器中的值成正比例且成线性关系。 [0014] Another technical advantage is the PFM output is directly proportional to the value loaded into an increment register and a linear relationship.

[0015] 另一技术优点是DFC和PFM信号的产生,以及使用同一逻辑模块的标准计时和计数。 [0015] Another technical advantage is generation of DFC and PFM signals, and the logic module using the same standard timing and counting.

[0016] 从下文对实施例的描述将明了其它技术特征和优点,出于揭示的目的且结合附图给出所述描述。 [0016] From the description of the embodiments will be apparent hereinafter Other technical features and advantages, and disclosed for purposes of the description in conjunction with the attached figures.

附图说明 BRIEF DESCRIPTION

[0017] 通过参看结合附图做出的以下描述可获得对本揭示内容及其优点的更完全理解, 在附图中: [0017] A more complete understanding can be obtained by reference to the following description made in conjunction with the accompanying drawings of the present disclosure and advantages thereof, in which:

[0018] 图1是具有数字到频率转换器(DFC)和/或脉冲到频率调制器(PFM)能力的集成电路微控制器的示意性方框图;和 [0018] Figure 1 is a digital to frequency converter (the DFC) and / or pulse to the schematic block diagram of the integrated circuit microcontroller frequency modulator (PFM) capabilities; and

[0019] 图2是根据特定示范性实施例的用于产生DFC和/或PFM的数字逻辑的示意性方框图。 [0019] FIG. 2 is a schematic block diagram of an embodiment of digital logic DFC and / or PFM produced in accordance with certain exemplary embodiments.

[0020] 尽管本发明容易具有各种修改和替代形式,但已在图式中以实例方式展示并在本文中详细描述其特定示范性实施例。 [0020] While the invention is susceptible to various modifications and alternative forms, by way of example has been shown in the drawings and described specific exemplary embodiments thereof in detail herein. 然而,应了解,不希望本文对特定实施例的描述将本发明限于所揭示的特定形式,而相反地,本发明将涵盖属于由所附权利要求书界定的本发明精神与范围内的所有修改、等效物和替代方案。 However, it should be understood, without wishing to be described herein specific embodiments of the present invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications that are within the spirit and scope of the invention defined by the appended claims of the , equivalents, and alternatives.

具体实施方式 detailed description

[0021] 现参看图式,示意性说明本发明的示范性实施例的细节。 [0021] Referring now to the drawings, a schematic illustration of details of an exemplary embodiment of the present invention. 图式中的相同元件将由相同数字表示,且类似元件将由带不同小写字母下标的相同数字表示。 Drawings same elements will be represented by like numbers, and similar elements will be identified by the same numeric subscripts represent different lower case letters.

[0022] 本文使用的时钟速度指的是振荡器用来产生时钟的频率,频率越高,则时钟速度越快。 [0022] Clock speed as used herein refers to an oscillator for generating the clock frequency, the higher the frequency, the faster the clock speed.

[0023] 参看图1,描绘具有数字到频率转换器(DFC)和/或脉冲到频率调制器(PFM)能力的集成电路微控制器的示意性方框图。 [0023] Referring to Figure 1, depicted is a schematic block diagram of an integrated circuit microcontroller having digital to frequency converter (the DFC) and / or pulse to frequency modulator (PFM) capabilities. 集成电路微控制器102可包含输入/输出接口104、 中央处理单元(CPU) 106、时钟振荡器108、计时器114、数字到频率转换器112和脉冲频率调制器110。 The integrated circuit microcontroller 102 may comprise input / output interface 104, a central processing unit (CPU) 106, a clock oscillator 108, timer 114, digital to frequency converter 112, and pulse frequency modulator 110. CPU 106可经由数据与控制总线116将数据与控制信息传送到计时器114、数字到频率转换器112和脉冲频率调制器110。 CPU 106 may be transmitted via the data and control information 116 and control data to the bus timer 114, digital to frequency converter 112, and pulse frequency modulator 110. 时钟信号可从时钟振荡器108经由时钟信号线118和118a耦合到CPU 106、计时器114、数字到频率转换器112和脉冲频率调制器110。 Clock signal may be coupled from the clock oscillator 108 via a clock signal line 118 and 118a to the CPU 106, timer 114, digital to frequency converter 112, and pulse frequency modulator 110.

[0024] 参看图2,其描绘根据特定示范性实施例的用于产生DFC和/或PFM的数字逻辑的示意性方框图。 [0024] Referring to Figure 2, which depicts an example of a schematic block diagram of DFC and / or PFM of the digital logic produced by the particular exemplary embodiment. 总体上由数字200表示的DFC与PFM逻辑可包含内部时钟振荡器202 (所述内部时钟振荡器202可与微控制器102分离或者可为微控制器102的时钟振荡器108)、 时钟多路复用器204、频率预定标器206、同步器208、同步/非同步时钟多路复用器210、死区产生器212、计时器/计数器214、DFC/PFM多路复用器216、全加器218、从属寄存器220、 增量寄存器222和与门224。 DFC and PFM logic generally denoted by the numeral 200 may comprise an internal clock oscillator 202 (the internal clock oscillator 202 may be separate from the microcontroller 102 or may be the clock oscillator 108 of the microcontroller 102), a clock multiplexer a multiplexer 204, a frequency prescaler 206, a synchronizer 208, a synchronized / non-synchronized clock multiplexer 210, a dead zone generator 212, timer / counter 214, DFC / PFM multiplexer 216, a full adder 218, a slave register 220, an increment register 222 and an aND gate 224. 所述与门224的输出2¾适于供应DFC (百分之五十工作周期)或PFM (为时钟的脉冲宽度的脉冲)信号。 The output of AND gate 224 is adapted to supply 2¾ the DFC (50 percent duty cycle) or the PFM (pulse width of the clock pulse) signal. 视需要,与门MO (自反转器238)可具有输出228,所述输出2¾适于供应输出2¾的DFC或PFM信号的互补信号。 Optionally, the AND gate MO (from inverter 238) may have an output 228 adapted to supply the output 2¾ DFC or PFM signal of the complementary output signals of 2¾. 可通过时钟多路复用器204用经由总线116来自(例如)CPU 106的输入248来选择外部时钟输入230或内部振荡器202。 204 via bus 116 may be derived from (e.g.) input 248 of CPU 106 selects the external clock input 230 or the internal oscillator 202 through a clock multiplexer.

[0025] 时钟多路复用器204具有耦合到内部振荡器202的一个输入和适于耦合到外部振荡器(未图示)的另一输入230。 [0025] The clock multiplexer 204 has one input coupled to the internal oscillator 202 and the other adapted for coupling to an external oscillator (not shown), and 230. 可由经由总线116来自(例如)CPU 106的输入248控制选择。 Via bus 116 may be derived from (e.g.) input 248 of CPU 106 controls the selector. 时钟多路复用器204的输出耦合到预定标器206,所述预定标器206可将选定的振荡器频率除以(例如)正整数值。 The output of the clock multiplexer 204 is coupled to the prescaler 206, the prescaler 206 can divide the selected oscillator frequency (for example) a positive integer value. 预定标器206的输出耦合到同步器208的输入和同步/非同步时钟多路复用器210的一个输入。 Output of the prescaler 206 is coupled to an input of the synchronizer 208 and the synchronization / non-synchronized clock multiplexer 210. 同步/非同步时钟多路复用器210的另一输入耦合到同步器208的输出。 Another input synchronization / non-synchronized clock multiplexer 210 is coupled to the output of the synchronizer 208. 同步器208可用于例如在(例如)输入246处发生唤醒事件时使时钟脉冲的断言同步。 Synchronizer 208 may be, for example, in (e.g.) the input clock pulse when a wakeup event occurs at 246 asserts the synchronization. 对经同步或非同步(预定标)的时钟脉冲的选择由同步/非同步时钟多路复用器210执行,且耦合到计时器/计数器214和死区产生器212。 Performed by the synchronous / asynchronous clock selection multiplexer 210 synchronized or synchronized clock pulses (predetermined standard), and coupled to the timer / counter 214 and dead band generator 212.

[0026] 从属寄存器220存储在增量寄存器222中找到的增量值。 [0026] The slave register 220 stores the increment found in the increment register 222 value. 可通过输入244将所述增量值载入到增量寄存器222中。 May be loaded into the increment register 222 through an input 244 to the increment value. 存储在计时器/计数器214中的计数值和存储在从属寄存器220中的增量值在全加器218中加在一起,且在每一时钟脉冲(来自同步/非同步时钟多路复用器210的输出)将结果存储回计时器/计数器214中。 Increment the count value stored in the storage, and the timer / counter 214 in the slave register 220 are added in the full adder 218 together, and at each clock pulse (from the synchronization / non-synchronized clock multiplexer the output 210) the result is stored back into the timer / counter 214. 这实现了“以N计数” 计数器,其中在输出236处的高阶位(例如,8位计数器的位7、16位计数器的位15、32位计数器的位31等)可用于为DFC模式提供百分之五十工作周期输出。 This allows a "count by N" counter 236 at the output of which the high-order bit (e.g., bit 7, 16-bit counter 8-bit counter 15, 32-bit counter 31, etc.) may be used to provide for the DFC mode 50 percent duty cycle output. 当高阶位处于逻辑高时,输出处于逻辑高,且当高阶位处于逻辑低时,输出处于逻辑低。 When the high-order bit is at a logic high, the output is a logic high, and when the high-order bit is at a logic low output at logic low. 在PFM模式中,当计时器/计数器214翻转时,来自全加器218的进位输出234可用于产生固定脉冲周期、可变频率输出。 In the PFM mode, when the timer / counter 214 is turned over, the carry from the full adder 218 output 234 may be used to generate the fixed pulse period, variable frequency output. DFC/PFM多路复用器216用DFC/PFM选择输入232来选择输出236 (DFC-百分之五十工作周期)或234输出(PFM-为时钟的脉冲宽度的脉冲)。 DFC / PFM multiplexer 216 with the DFC / PFM select input 232 to select the output 236 (DFC- fifty percent duty cycle) or the 234 output (PFM-pulse width of the clock pulse).

[0027] 死区产生器212和DFC/PFM多路复用器216的输出可在与门224、反转器238和与门MO中组合,以便在通常相反的逻辑电平输出2¾与2¾之间引入可选择的死区。 Output [0027] The dead zone generator 212 and the DFC / PFM multiplexer 216 may be in the 2¾ 2¾ to output the gate 224, inverter gates 238 and combined with the MO, and is usually in the opposite logic levels selectable dead zone between the introduction. 死区产生器可具有死区寄存器(未图示),所述死区寄存器可含有死区所需的时钟脉冲的数目, 例如可使用8位死区寄存器在输出2¾与2¾之间在0到255个死区时钟计数之间进行选择。 Dead band generator may have a dead band register (not shown), the dead zone may contain a register number of clock pulses required for the dead zone, for example, 8-bit dead band between the output register and 2¾ 0 to 2¾ selecting between a dead-time clock 255 counts. 可通过经由总线116来自(例如)CPU 106的输入242来加载死区寄存器。 242 can be loaded by the dead band register (for example) input from the CPU 106 via the bus 116.

[0028] 因此,本发明非常适于实现所述目的并获得所提及的结果和优点以及其中固有的其它结果和优点。 [0028] Accordingly, the present invention is well adapted to carry out the objects and obtain the ends and advantages mentioned as well as others inherent therein and advantages. 尽管已参考本发明的示范性实施例描绘、描述和界定本发明,但这些参考不隐含对本发明的限制,且不会推断出任何此类限制。 Although depicted embodiment of the present invention with reference to exemplary embodiments, the description and definition of the present invention, but these references does not imply a limitation on the invention, and no such limitation is not inferred. 本发明能够在形式和功能上具有相当大的修改、替代和等效物,正如所属领域的技术人员根据本揭示案可想到的那样。 The present invention is capable of considerable modification, alteration, and equivalents in form and function, as may occur to the skilled person that the present disclosure. 所描绘和描述的本发明实施例仅是示范性的,且并不完全说明本发明的范围。 Embodiments of the invention depicted and described herein are merely exemplary, and are not fully illustrate the scope of the present invention. 因此,希望本发明仅由所附权利要求书的精神和范围加以限制,且同时完全认同在所有方面的等效物。 Accordingly, the invention is intended by the appended claims only the spirit and scope of the restrictions, while fully recognized equivalents in all respects.

Claims (25)

  1. 1. 一种集成电路微控制器,其具有数字到频率转换和脉冲频率调制功能,所述集成电路微控制器包含:中央处理单元;计时器/计数器,其具有时钟输入和高阶位输出;增量寄存器,其具有耦合到所述中央处理单元的输入;全加器,其具有第一输入、第二输入、输出、和进位输出,所述第一输入耦合到所述增量寄存器,所述第二输入耦合到所述计时器/计数器,且所述输出耦合到所述计时器/计数器,其中每次在所述计时器/计数器的时钟输入处接收到时钟信号时,均将存储在所述增量寄存器中的增量值相加到存储在所述计时器/计数器中的计数值;和频率转换/脉冲频率调制多路复用器,其具有耦合到所述计时器/计数器所述高阶位输出的第一输入、耦合到所述全加器的所述进位输出的第二输入、频率转换/脉冲频率调制输出和用于将所述第一输入或所述 An integrated circuit microcontroller having digital to frequency converter and pulse frequency modulation function, the microcontroller integrated circuit comprising: a central processing unit; a timer / counter having a clock input and a high-order bit output; increment register having an input coupled to said central processing unit; full-adder having a first input, a second input, an output, and a carry output, the first input coupled to the increment register, the when said second input coupled to the timer / counter, and the output is coupled to the timer / counter, wherein each time the clock signal is received at a clock input of the timer / counter, are stored in the incremental value of the phase increment register is added to the count value stored in the timer / counter; and a frequency converter / pulse frequency modulation multiplexer having an input coupled to the timer / counter a first input of said high-order bit output, a second input coupled to the carry output of the full adder, a frequency converter / pulse frequency for modulated output and the first input or the 二输入耦合到所述频率转换/脉冲频率调制输出的第三输入,其中所述频率转换/脉冲频率调制多路复用器的所述第三输入耦合到所述中央处理单元。 A second input coupled to the frequency converter / third input pulse frequency modulated output, wherein the frequency conversion / pulse frequency modulator to a third multiplexer input coupled to the central processing unit.
  2. 2.根据权利要求1所述的集成电路微控制器,其进一步包含耦合在所述增量寄存器与所述全加器之间的从属寄存器。 2. The integrated circuit microcontroller according to claim 1, further comprising a slave register coupled between the increment register and the full-adder.
  3. 3.根据权利要求1所述的集成电路微控制器,其进一步包含反转器,其具有耦合到所述频率转换/脉冲频率调制多路复用器的所述输出的输入。 3. The integrated circuit microcontroller according to claim 1, further comprising an inverter having an input coupled to the output of the frequency conversion / pulse frequency modulation multiplexer.
  4. 4.根据权利要求3所述的集成电路微控制器,其进一步包含用于在所述频率转换/脉冲频率调制多路复用器的所述输出与所述反转器的输出之间形成死区的死区产生器。 The integrated circuit microcontroller according to claim 3, further comprising means for forming die between the frequency converter / pulse frequency modulation of the output of the multiplexer and the output of inverter dead-zone generator.
  5. 5.根据权利要求4所述的集成电路微控制器,其进一步包含耦合到所述死区产生器的死区寄存器,其中所述死区寄存器存储所述频率转换/脉冲频率调制多路复用器的所述输出与所述反转器的所述输出之间的死区时钟计数的数目。 5. The integrated circuit microcontroller according to claim 4, further comprising a dead zone coupled to the dead zone generator register, wherein said register stores the dead band frequency converter / pulse frequency modulation multiplex clock count number of dead space between the output of the output of the inverter.
  6. 6.根据权利要求1所述的集成电路微控制器,其进一步包含:同步器,其具有耦合到时钟源的输入和同步时钟输出,其中所述同步器使所述时钟源与事件同步;同步/非同步时钟多路复用器,其具有耦合到所述计时器/计数器的所述时钟输入的输出、耦合到所述时钟源的第一输入和耦合到所述同步时钟输出的第二输入,其中所述同步/非同步时钟多路复用器用于在所述时钟源与所述同步时钟输出之间进行选择以输出所述时钟信号。 6. The integrated circuit microcontroller according to claim 1, further comprising: a synchronizer having an input coupled to the clock source and the synchronized clock output, wherein said clock synchronization enables the source and event synchronization; sync / non-synchronized clock multiplexer having an output coupled to the timer / counter of the clock input, a second input coupled to the clock source and a first input coupled to the synchronized clock output wherein the synchronization / non-synchronized clock multiplexer is used between the clock source and the synchronized clock output to output the selected clock signal.
  7. 7.根据权利要求1所述的集成电路微控制器,其进一步包含耦合到所述计时器/计数器的所述时钟输入的用于划分时钟信号频率的时钟预定标器。 7. The integrated circuit microcontroller according to claim 1, further comprising a clock prescaler coupled to the timer / counter for dividing said clock input clock signal frequency.
  8. 8.根据权利要求1所述的集成电路微控制器,其进一步包含用于选择外部时钟源或内部时钟源以及用于向所述计时器/计数器的所述时钟输入提供时钟信号输出的时钟多路見用器。 8. The integrated circuit microcontroller according to claim 1, further comprising a clock for selecting which external clock source or an internal clock source and means to said clock input of the timer / counter provides a clock signal outputted from the multiplexer Road see Appliances.
  9. 9.根据权利要求1所述的集成电路微控制器,其中所述中央处理单元将所述增量值写入到所述增量寄存器中。 9. The integrated circuit microcontroller according to claim 1, wherein said central processing unit to write to the delta value of the increment register.
  10. 10.根据权利要求1所述的集成电路微控制器,其中所述计时器/计数器的所述高阶位输出具有百分之五十工作周期。 10. The integrated circuit microcontroller according to claim 1, wherein said timer / counter having a high-order bit output of 50 percent duty cycle.
  11. 11.根据权利要求1所述的集成电路微控制器,其中所述全加器的所述进位输出具有等于所述时钟信号的脉冲宽度。 11. The integrated circuit microcontroller according to claim 1, wherein the carry output of the full-adder has a pulse width equal to the clock signal.
  12. 12.根据权利要求5所述的集成电路微控制器,其中所述中央处理单元将所述死区时钟计数的数目写入到所述死区寄存器中。 12. The integrated circuit microcontroller according to claim 5, wherein said central processing unit write the number of the dead-time clock count register to the dead zone.
  13. 13. 一种集成电路微控制器,其包含:中央处理单元;时钟振荡器,其耦合到所述中央处理单元;和数字到频率转换器,其耦合到所述中央处理单元和时钟振荡器,所述数字到频率转换器包含计时器/计数器,其具有时钟输入和高阶位输出,增量寄存器,和全加器,其具有第一输入、第二输入和输出,所述第一输入耦合到所述增量寄存器,所述第二输入耦合到所述计时器/计数器,且所述输出耦合到所述计时器/计数器,其中每次在所述计时器/计数器的所述时钟输入处接收到时钟信号时,均将存储在所述增量寄存器中的增量值相加到存储在所述计时器/计数器中的计数值;其中所述高阶位输出具有百分之五十工作周期,且与存储在所述增量寄存器中的所述增量值成比例。 13. An integrated circuit microcontroller, comprising: a central processing unit; a clock oscillator coupled to said central processing unit; and a digital to frequency converter coupled to said central processing unit and a clock oscillator, the digital to frequency converter comprising a timer / counter having a clock input and a high-order bit output, an increment register, and a full-adder having a first input, a second input and an output, said first input coupled to the increment register, the second input coupled to the timer / counter, and the output is coupled to the timer / counter, wherein each time the clock input of the timer / counter upon receiving the clock signal, both the increment value stored in the increment register is added to the phase count value stored in the timer / counter; wherein the high-order bit output having a 50 percent duty period and the increment in the increment register stored value proportional.
  14. 14. 一种集成电路微控制器,其包含:中央处理单元;时钟振荡器,其耦合到所述中央处理单元;和脉冲频率调制器,其耦合到所述中央处理单元和时钟振荡器,所述脉冲频率调制器包含计时器/计数器,其具有时钟输入和高阶位输出,增量寄存器,和全加器,其具有第一输入、第二输入、输出和进位输出,所述第一输入耦合到所述增量寄存器,所述第二输入耦合到所述计时器/计数器,且所述输出耦合到所述计时器/计数器,其中每次在所述计时器/计数器的所述时钟输入处接收到时钟信号时,均将存储在所述增量寄存器中的增量值相加到存储在所述计时器/计数器中的计数值;其中所述全加器的所述进位输出具有固定的脉冲周期,且与存储在所述增量寄存器中的所述增量值成比例。 14. An integrated circuit microcontroller, comprising: a central processing unit; a clock oscillator coupled to said central processing unit; and a pulse frequency modulator, coupled to the central processing unit and clock oscillator, the said pulse frequency modulator comprising a timer / counter having a clock input and a high-order bit output, an increment register, and a full-adder having a first input, a second input, an output and a carry output, the first input coupled to the increment register, the second input coupled to the timer / counter, and the output is coupled to the timer / counter, wherein each time the clock input of the timer / counter when the clock signal is received, both the increment value stored in the increment register is added to the phase count value stored in the timer / counter; wherein the carry output of the full-adder having a fixed pulse period, the increment and stored in the increment register proportional.
  15. 15.根据权利要求14所述的集成电路微控制器,其中所述固定的脉冲周期是所述时钟输入的脉冲周期。 15. The integrated circuit microcontroller according to claim 14, wherein the fixed pulse period is the pulse period of the clock input.
  16. 16. 一种用具有计时器/计数器和增量寄存器的集成电路微控制器进行数字到频率转换和脉冲频率调制的方法,所述方法包含以下步骤:提供所述计时器/计数器中的计数值;提供所述增量寄存器中的增量值;相加所述计数值与所述增量值,接着在每一时钟脉冲时将结果存储在所述计时器/计数器中;选择所述计时器/计数器的高阶位以进行数字到频率转换输出;和选择从所述相加步骤获得的进位以进行脉冲频率调制输出。 16. A method for digital to frequency conversion and pulse frequency modulation with an integrated circuit microcontroller having a timer / counter and an increment register, said method comprising the steps of: providing a count value of the timer / counter ; provide incremental value of the increment register; adding the count-value and the increment value, at each clock pulse is then stores the result in the timer / counter; selecting the timer order bit / counter for a digital to frequency converter output; and selecting a carry obtained from said step of adding for a pulse frequency modulation output.
  17. 17.根据权利要求16所述的方法,其进一步包含以下步骤:将所述增量值存储在从属寄存器中,其中所述从属寄存器耦合到所述增量寄存器。 17. The method of claim 16, further comprising the step of: the increment value stored in a slave register, wherein said slave register coupled to the increment register.
  18. 18.根据权利要求16所述的方法,其进一步包含以下步骤:反转所述数字到频率转换输出和所述脉冲频率调制输出。 18. The method according to claim 16, further comprising the step of: inverting the digital to frequency converter output and the output pulse frequency modulation.
  19. 19.根据权利要求18所述的方法,其进一步包含以下步骤:在所述数字到频率转换输出与所述经反转的数字到频率转换输出之间产生死区。 19. The method of claim 18, further comprising the step of: said digital to frequency converter output and the reversed between the digitally converted output frequency dead zones.
  20. 20.根据权利要求18所述的方法,其进一步包含以下步骤:在所述脉冲频率调制输出与所述经反转的脉冲频率调制输出之间产生死区。 20. The method of claim 18, further comprising the steps of: generating a dead band between the pulse frequency modulation of the output of the inverted pulse frequency modulation output.
  21. 21.根据权利要求16所述的方法,其进一步包含以下步骤:使所述时钟脉冲与事件同止ο 21. The method of claim 16, further comprising the step of: the same clock and the event stop ο
  22. 22.根据权利要求16所述的方法,其进一步包含以下步骤:对所述时钟脉冲的频率进行预定标。 22. The method of claim 16, further comprising the step of: the frequency of the clock pulses of a predetermined standard.
  23. 23.根据权利要求16所述的方法,其进一步包含以下步骤:用所述微控制器的中央处理单元对所述增量寄存器进行写入。 23. The method according to claim 16, further comprising the step of: writing to the increment register with a central processing unit of the microcontroller.
  24. 24. 一种用具有计时器/计数器和增量寄存器的集成电路微控制器进行数字到频率转换的方法,所述方法包含以下步骤:提供所述计时器/计数器中的计数值; 提供所述增量寄存器中的增量值;相加所述计数值与所述增量值,接着在每一时钟脉冲时将结果存储在所述计时器/计数器中;和选择所述计时器/计数器的高阶位以进行数字到频率转换。 24. A digital integrated circuit microcontroller having a timer / counter and an increment register to the method of frequency conversion, said method comprising the steps of: providing a count value of the timer / counter; providing the delta value increment register; adding the count-value and the increment value, at each clock pulse is then stores the result in the timer / counter; and a selection of the timer / counter in order bit digital to frequency converter.
  25. 25. 一种用具有计时器/计数器和增量寄存器的集成电路微控制器进行脉冲频率调制的方法,所述方法包含以下步骤:提供所述计时器/计数器中的计数值; 提供所述增量寄存器中的增量值;相加所述计数值与所述增量值,接着在每一时钟脉冲时将结果存储在所述计时器/计数器中;和选择从所述相加步骤获得的进位以进行脉冲频率调制。 25. A method for pulse frequency modulation with an integrated circuit microcontroller having a timer / counter and an increment register, said method comprising the steps of: providing a count value of the timer / counter; provided by the incremental amount register; adding the count value and the delta value, and then at each clock pulse will result in the timer / counter memory; and selecting said sum obtained from step to carry pulse frequency modulation.
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