CN101047186B - Memory cell and related memory device - Google Patents
Memory cell and related memory device Download PDFInfo
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- CN101047186B CN101047186B CN2006101723094A CN200610172309A CN101047186B CN 101047186 B CN101047186 B CN 101047186B CN 2006101723094 A CN2006101723094 A CN 2006101723094A CN 200610172309 A CN200610172309 A CN 200610172309A CN 101047186 B CN101047186 B CN 101047186B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Abstract
Memory cells and semiconductor memory devices using the same. The memory cell inclides: A substrate comprises two cross-coupled inverters and first and second pass-gate transistors formed therein, the inverters having a data storage node and a date bar storage node coupled to first terminals of the first and second pass-gate transistors. A first conductive layer is disposed on the substrate and comprises a bit line and a complementary bit line electrically connected to second terminals of the first and second pass-gate transistors respectively. A second conductive layer is disposed on the first conductive layer and comprises two first power lines covering the bit line and the complementary bit line respectively, wherein the first power lines, the bit line and the complementary bit line are parallel.
Description
Technical field
The present invention relates to storage arrangement, particularly a kind of memory cell and relevant storage arrangement.
Background technology
Progress along with complementary metal oxide semiconductors (CMOS) (CMOS) transistor technology with the fast and highly dense intensity of speed, static RAM (SRAM) integrated circuit becomes more and more popular, and the CMOS transistor technology is accounting for principalship in the manufacturing of very lagre scale integrated circuit (VLSIC) at present.In recent decades, the size of semiconductor structure is constantly reduced, and makes semiconductor chip all have on speed, usefulness, circuit level and unit cost greatly and promotes.
Yet, along with the CMOS device size is constantly reduced, also bring more challenges need go to face, for example to high speed, lower powered System on Chip/SoC (system on chip), Embedded static RAM is a very important part, nanometer from generation to generation in each product several static RAMs will be set on chip, in order to increase positioning efficiency, chip size and chip speed, the SRAM memory cell allows to use the metal level holding wire to be used for transfer of data and the control signal wire of striding array (cross-array), yet this will disturb by priming signal, so the positioning efficiency of chip, speed, it is more and more important that the stability of signal interference prevention and memory cell just becomes.Therefore, will need an integrated circuit can allow holding wire to pass through memory cell array, best signal interference prevention can be provided simultaneously.
Summary of the invention
In view of the above problems, the invention provides a kind of memory cell, comprise: substrate, it has inverter and first, second pass transistor of two cross-coupled formed thereon, wherein the inverter of cross-coupled has data memory node and complementary data memory node, and above-mentioned two nodes are coupled to transistorized first end of first, second logical grid (pass-gate) respectively; First conductive layer, it is arranged in the substrate, comprises bit line and paratope line, and above-mentioned bit line and paratope line are coupled to second end of first, second pass transistor respectively; And second conductive layer, it is arranged on first conductive layer, comprises two first power supply signal lines, and above-mentioned two first power supply signal lines are covered in respectively on bit line and the paratope line, and wherein the first power supply signal line, bit line and paratope line are parallel to each other.
The present invention also provides a kind of memory cell, comprising: substrate, and it comprises pass transistor formed thereon; First conductive layer, it is arranged in the substrate, comprises bit line, and this bit line is electrically coupled to first end of pass transistor; And second conductive layer, be arranged on first conductive layer, comprise the first power supply signal line, this first power supply signal line is covered on the bit line, and wherein the first power supply signal line parallel is in bit line.
The present invention also provides a kind of storage arrangement, comprises a plurality of memory arrays, and each memory array comprises a plurality of aforesaid memory cell; And at least one first well region conduction (strap) unit, this first well region conductive unit is electrically coupled to the P well region in the above-mentioned substrate.
According to the present invention, can realize that an integrated circuit can allow holding wire to pass through memory cell array, best signal interference prevention effect can be provided simultaneously.
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularly preferred embodiment, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 is the structural representation of the memory cell of expression 6T-SRAM.
Fig. 2 A～2D is the vertical view of the 6T-SRAM memory cell in the embodiment of the invention.
Fig. 2 E represents another embodiment of memory cell of the present invention.
Fig. 3 A～3E is the vertical view of another embodiment of the 6T-SRAM memory cell among the present invention.
Fig. 3 F represents another embodiment of memory cell of the present invention.
Fig. 4 is the schematic diagram of the memory cell of dynamic random access memory (DRAM).
Fig. 5 A～5D is the vertical view of an embodiment of the DRAM memory cell among the present invention.
Fig. 6 is an embodiment of memory chip.
Embodiment
In an embodiment, embodiments of the present invention are applied to 6T-SRAM and 8T-SRAM, yet any those of ordinary skill in the art all can be by content of the present invention and feature application in the device of other type, for example the SRAM of other type with or SRAM beyond storage arrangement.Therefore, embodiment described herein is only used for explanation, is not in order to limit the present invention.
Fig. 1 is the structural representation of the memory cell of demonstration 6T-SRAM.As shown in the figure, the memory cell of 6T-SRAM comprises first pass transistor (first pass-gate transistor) PG1, the second pass transistor PG2, first pulled transistor (pull-up transistor) PU-1, the second pulled transistor PU-2, first pulldown transistors (pull-down transistor) PD-1 and the second pulldown transistors PD-2.
In action, memory cell can be considered two complementary node NODE-1 and NODE-2.Because node NODE-1 is connected to the grid of the second pulled transistor PU-2, and node NODE-2 is connected to the grid of the first pulled transistor PU-1, so be stored in value meeting of each node and be stored in the value maintenance complementary relationship of another node.For example, when node NODE-1 is a high potential, the second pulled transistor PU-2 will stop electric current to flow to node NODE-2 by power source voltage Vcc.At this moment, second low transistor PD-2 can conducting, makes that stored charge can be discharged into earth terminal among the node NODE-2.Moreover when node NODE-2 is an electronegative potential, the first pulled transistor PU-1 will allow electric current to flow to node NODE-1 by power source voltage Vcc.At this moment, first low transistor PD-1 can conducting, and stored charge is released to earth terminal among the node NODE-1 to avoid.The grid of the first pass transistor PG-1 and the second pass transistor PG-2 is coupled to word line WL, in order to the data read of control store unit with write.The value that node NODE-1 and NODE-2 are stored is read by the bit line and the paratope line that are electrically coupled to sensor amplifier (not icon) respectively.
Fig. 2 A～2D is the vertical view of the 6T-SRAM memory cell in the embodiment of the invention.Specifically, Fig. 2 A is for containing the vertical view of semiconductor element (active area with cover crystal silicon) and the first metal layer (M1); Fig. 2 B is for containing the vertical view of the first metal layer (M1) and second metal level (M2); Fig. 2 C is for containing the vertical view of second metal level (M2) and the 3rd metal level (M3); Fig. 2 D is for containing the vertical view of the 3rd metal level (M3) and the 4th metal level (M4).
Shown in Fig. 2 A, the 6T-SRAM memory cell comprises and is formed at suprabasil first, second pass transistor PG-1 and PG-2, first, second pulled transistor PU-1 and PU2, and first, second pulldown transistors PD-1 and PD-2.In order to illustrate, broad-brush rectangle representative is formed at the contact point signal line on the first metal layer (M1).For example, substrate (not label) can be block materials silicon (bulk Si), SiGe, SOI, non-block materials silicon (non-bulk Si), the thickness of transistorized grid preferably less than
And can have different width, but the grid width of first, second pulldown transistors PD-1 and PD-2 is preferably less than 40nm.Transistorized gate dielectric can be single or multiple lift, and preferably has one deck and be made of oxide, metal oxide, nitrogenize oxygen silicon, high dielectric material or its composition of silicon dioxide, silicon nitride, nitrogenous base, and the thickness of gate oxide preferably less than
In the preferred case, first, second pulled transistor PU-1 and PU-2 are the PMOS transistor that is formed in n type well region or the n moldeed depth well region, and other transistor (for example first, second pass transistor PG-1 and PG-2 and first, second pulldown transistors PD-1 and PD-2) is a nmos pass transistor.The source terminal of first, second pulled transistor PU-1 and PU-2 is electrically connected to the contact point signal line 210 and 212 that the first metal layer (M1) is gone up voltage source (VCC) respectively by connector 214 and 216.
The interior connecting portion 220 that the drain electrode end of the first pulled transistor PU-1, the first pulldown transistors PD-1 and the first pass transistor PG-1 and the grid of the second pulled transistor PU-2 and the second pulldown transistors PD-2 all pass through on the first metal layer (M1) is electrically connected with connector 221,222 and 223.Similarly, the interior connecting portion 224 that all passes through on the first metal layer (M1) of the grid of the drain electrode end of the second pulled transistor PU-2, the second pulldown transistors PD-2 and the second pass transistor PG-2 and the first pulled transistor PU-1 and the first pulldown transistors PD-1 is electrically connected with connector 225,226 and 227.
The source terminal of the first pulldown transistors PD-1 is electrically coupled to earth terminal (VSS by earth terminal (VSS) contact point signal line 228 and connector 229; Be not shown among the figure), and the source terminal of the second pulldown transistors PD-2 is electrically coupled to earth terminal (VSS) by earth terminal (VSS) contact point signal line 230 and connector 231.
The source terminal of the first pass transistor PG-1 is electrically coupled to bit line (BL by contact point signal line 232 and connector 233; In Fig. 2 A, do not show), and the first pass transistor PG-1 is in order to the drain electrode end of electric property coupling bit line (BL) to the first pulled transistor PU-1 and the first pulldown transistors PD-1.The gate terminal of the first pass transistor PG-1 is coupled to word line (WL by contact point signal line on the first metal layer (M1) 234 and connector 235; In Fig. 2 A, do not show).
The source terminal of the second pass transistor PG-2 is electrically coupled to paratope line (/BL by contact point signal line 236 and connector 237; In Fig. 2 A, do not show).Similarly, the second pass transistor PG-2 in order to the electric property coupling paratope line (/BL) to the drain electrode end of the second pulled transistor PU-2 and the second pulldown transistors PD-2.The gate terminal of the second pass transistor PG-2 is coupled to word line (WL) by contact point signal line on the first metal layer (M1) 238 and connector 239.Any those skilled in the art can define cell or memory cell 260 (shown in dotted line) according to aforementioned structure.
N type well region 270 or n moldeed depth well region are formed in the memory cell 260, and substrate is preferably the substrate of p type, come around living n type well region 270 in order to large stretch of p type well region to be provided, and are provided with the NMOS element.N type well region 270 is formed in the substrate by known n type ion implantation technique, makes that PMOS element (transistor) can be formed thereon, for example the first pulled transistor PU-1 and the second pulled transistor PU-2.
Fig. 2 B is the vertical view of the first metal layer (M1) and second metal level (M2), combines in order to the layout with memory cell shown in Fig. 2 A.The second metal level M2 comprise bit line (BL) 242, paratope line (/BL) 244, voltage source signal line 246, contact point signal line 241,243,245 and 247.In this embodiment, voltage source signal line 246 is parallel to bit line 242 and paratope line 244, and is arranged between bit line 242 and the paratope line 244.
Contact point signal line 241 and 243 is electrically coupled to contact point signal line 234 and 238 on the first metal layer (M1) by connector 255 and 256, and the contact point signal line 234 and 238 on the first metal layer (M1) is electrically coupled to the gate terminal of first, second pass transistor PG-1 and PG-2 respectively.Contact point signal line 245 and 247 is electrically coupled to contact point signal line 228 and 230 on the first metal layer (M1) by connector 257 and 258, and the contact point signal line 228 and 230 on the first metal layer (M1) is electrically coupled to the source terminal of first, second pulldown transistors PD-1 and PD-2 respectively.
Fig. 2 C is the vertical view of second metal level (M2) and the 3rd metal level (M3), combines in order to the layout with memory cell shown in Fig. 2 B.The 3rd metal level M3 comprises two earth terminal holding wires 261 and 263, and a word line (WL) 265.Earth terminal holding wire 261 and 263 is electrically coupled to contact point signal line 245 and 247 on second metal level (M2) by connector 271 and 273 respectively, and word line 265 is electrically coupled to contact point signal line 241 and 243 on second metal level (M2) by connector 275 and 277.In this embodiment, word line 265 is parallel to earth terminal holding wire 261 and 263, and be arranged between earth terminal holding wire 261 and 263, and word line 265 and earth terminal holding wire 261 and 263 are perpendicular to bit line (BL) 242, paratope line (/BL) the voltage source signal line 246 on 244 and second metal level (M2).
Fig. 2 D is that (vertical view of M1～M4) combines in order to the layout with memory cell shown in Fig. 2 C first to fourth metal level.The 4th metal level M4 comprises two earth terminal holding wires 267 and 269, perpendicular to the earth terminal holding wire 261 on the 3rd metal level (M3) and 263 and word line 265, and earth terminal holding wire 267 and 269 is electrically connected to earth terminal holding wire 261 and 263 on the 3rd metal level (M3) by connector 281,283,285 and 287, so that form electric power network (power grid).Bit line 242 on second metal level (M2) and paratope line 244 are respectively by the earth terminal holding wire 269 on the 4th metal level (M4) and 267 coverings fully.
Fig. 2 E represents another embodiment of memory cell of the present invention.As shown in the figure, bit line on second metal level (M2) 242 and paratope line 244 are respectively by the earth terminal holding wire 269 on the 4th metal level (M4) " and 267 " partly cover.
Fig. 3 A～3E is the vertical view of another embodiment of 6T-SRAM memory cell among the present invention.Specifically, Fig. 3 A is for containing the vertical view of semiconductor device (active area with cover crystal silicon) and the first metal layer (M1); Fig. 3 B is for containing the vertical view of the first metal layer (M1) and second metal level (M2); Fig. 3 C is for containing the vertical view of second metal level (M2) and the 3rd metal level (M3); Fig. 3 D is for containing the vertical view of the 3rd metal level (M3) and the 4th metal level (M4); Fig. 3 E is first to the 5th metal level (vertical view of M1～M5).
As shown in Figure 3A, this structure identical with shown in Fig. 2 A is so be not repeated at this.
As shown in Fig. 3 B, second metal level (M2) comprises word line (WL) 301 and contact point signal line 302-307.Word line 301 is electrically coupled to contact point signal line 234 and 238 on the first metal layer (M1) by connector 312 and 311 respectively, and contact point signal line 234 and 238 is electrically coupled to the gate terminal of pass transistor PG-1 and PG-2.
Contact point signal line 302 and 303 is electrically coupled to contact point signal line 210 and 212 on the first metal layer (M1) by connector 313 and 314, and contact point signal line 210 and 212 is electrically coupled to the source terminal of the PU-1 and the PU-2 of pulled transistor respectively.Contact point signal line 304 and 305 is electrically coupled to contact point signal line 232 and 236 on the first metal layer (M1) by connector 315 and 316, and contact point signal line 232 and 236 is electrically coupled to the source terminal of the PG-1 and the PG-2 of pass transistor respectively.Contact point signal line 306 and 307 is electrically coupled to contact point signal line 228 and 230 on the first metal layer (M1) by connector 317 and 318, and contact point signal line 228 and 230 is electrically coupled to the source terminal of the PD-1 and the PD-2 of pass transistor respectively.
Fig. 3 C is that (vertical view of M1～M3) combines in order to the layout with memory cell shown in Fig. 3 B first to the 3rd metal level.The 3rd metal level M3 comprises voltage source signal line 321 parallel to each other, bit line (BL) 322, paratope line (/BL) 323 and two earth terminal holding wires 324 and 325.In this embodiment, voltage source signal line 321, bit line (BL) 322 and paratope line (/BL) 323 be arranged between two earth terminal holding wires 324 and 325, and voltage source signal line 321 be arranged at bit line (BL) 322 and paratope line (/BL) between 323.
Voltage source signal line 321 is electrically coupled to contact point signal line 302 and 303 on second metal level (M2) by connector 331 and 332.Bit line 322 is electrically coupled to contact point signal line 304 on second metal level (M2) by connector 333.Paratope line 323 is electrically coupled to contact point signal line 305 on second metal level (M2) by connector 334.Earth terminal holding wire 324 and 325 is electrically coupled to contact point signal line 307 and 306 on second metal level (M2) by connector 335 and 336.In this embodiment, voltage source signal line 321, bit line (BL) 322, paratope line (/BL) 323 and earth terminal holding wire 324 and 325 perpendicular to the word line 301 on second metal level (M2).
Fig. 3 D is that (vertical view of M1～M4) combines in order to the layout with memory cell shown in Fig. 3 C first to fourth metal level.The 4th metal level M4 comprises two earth terminal holding wires 341 and 342.Earth terminal holding wire 341 and 342 is parallel to voltage source signal line 321 on the 3rd metal level (M3), bit line (BL) 322, paratope line (/BL) 323 and earth terminal holding wire 324 and 325.Earth terminal holding wire 341 and 342 is electrically coupled to contact point signal line 324 and 325 on the 3rd metal level (M3) by connector 351 and 352.Bit line (BL) 322 on the 3rd metal level (M3) and paratope line (/BL) 323 respectively by the earth terminal holding wire 341 on the 4th metal level (M4) and 342 coverings fully.
Fig. 3 E is that (vertical view of M1～M5) combines in order to the layout with memory cell shown in Fig. 3 D first to the 5th metal level.The 5th metal level M5 comprises two earth terminal holding wires 361 and 362.Earth terminal holding wire 361 and 362 perpendicular to the voltage source signal line 321 on the 3rd metal level (M3), bit line (BL) 322, paratope line (/BL) 323 and earth terminal holding wire 324 and the 325 and the 4th metal level (M4) on earth terminal holding wire 341 and 342.Earth terminal holding wire 361 and 362 is electrically connected to earth terminal holding wire 341 and 342 on the 4th metal level (M4) by connector 371～374, so that form electric power networks.
Fig. 3 F represents another embodiment of memory cell of the present invention.As shown in the figure, bit line on the 3rd metal level (M3) 322 and paratope line 323 are respectively by the earth terminal holding wire 341 on the 4th metal level (M4) " and 342 " covering of part ground.
Fig. 4 is the schematic diagram of the memory cell of dynamic random access memory (DRAM).As shown in the figure, the memory cell of DRAM comprises switching transistor SW1 and storage capacitance Cst, and wherein the end of storage capacitance Cst is coupled to fixed voltage, for example earth terminal voltage VSS.The grid of switching transistor SW1 is electrically coupled to word line WL, in order to the data read of control store unit with write.The value of being stored among the storage capacitance Cst is read by the bit line that is electrically coupled to sensor amplifier (not icon).
Fig. 5 A～5D is the vertical view of the embodiment of DRAM memory cell among the present invention.Specifically, Fig. 5 A is for containing the vertical view of semiconductor element (active area with cover crystal silicon) and the first metal layer (M1); Fig. 5 B is for containing the vertical view of the first metal layer (M1) and second metal level (M2); Fig. 5 C is for containing the vertical view of second metal level (M2) and the 3rd metal level (M3); Fig. 5 D is for containing the vertical view of the 3rd metal level (M3) and the 4th metal level (M4).
As shown in Fig. 5 A, the DRAM memory cell comprises and is formed at suprabasil switch element SW1, and the drain electrode end of switch element SW1 is coupled to storage capacitance, and its source terminal is electrically coupled to bit line BL (not icon), and its gate terminal is electrically coupled to word line WL (not icon).In order to illustrate, broad-brush rectangle representative is formed at the contact point signal line on the first metal layer (M1).
The grid of switching transistor SW1 is electrically coupled to contact point signal line 401 by connector 402, its source electrode is electrically coupled to contact point signal line 403 by connector 404, and its drain electrode is coupled to storage capacitance Cst by connector 405, for example the electric capacity of capacity plate antenna, channel capacitor, stack electric capacity or other pattern.
Fig. 5 B is the vertical view of first and second metal level (M1, M2), combines in order to the layout with memory cell shown in Fig. 5 A.Second metal level (M2) comprises bit line (BL) 411 and contact point signal line 413.Bit line (BL) 411 is electrically coupled to contact point signal line 403 on the first metal layer (M1) by connector 412, and the contact point signal line 403 on the first metal layer (M1) is electrically coupled to the source terminal of switching transistor SW1.Contact point signal line 413 is electrically coupled to contact point signal line 401 on the first metal layer (M1) by connector 414, and the contact point signal line 401 on the first metal layer (M1) is electrically coupled to the gate terminal of switching transistor SW1.
Fig. 5 C is that (vertical view of M1～M3) combines in order to the layout with memory cell shown in Fig. 5 B first to the 3rd metal level.The 3rd metal level M3 comprises word line (WL) 421 and earth terminal holding wire 423.
Word line 421 is electrically coupled to contact point signal line 413 on second metal level (M2) by connector 422, and earth terminal holding wire 423 is electrically coupled to fixed voltage, for example earthed voltage VSS, VCC ... or the like.In the present embodiment, the bit line 411 on second metal level (M2) is fully covered by 423 of the earth terminal holding wires on the 3rd metal level (M3).Word line 421 is parallel to bit line 411 on second metal level (M2) and the earth terminal holding wire 423 on the 3rd metal level (M3).In certain embodiments, the bit line 411 on second metal level (M2) can be covered by the ground of earth terminal holding wire 423 parts on the 3rd metal level (M3).
Fig. 5 D is that (vertical view of M3～M4) combines in order to the layout with memory cell shown in Fig. 5 C the 3rd to the 4th metal level.The 4th metal level M4 comprises earth terminal holding wire 431, perpendicular to word line on the 3rd metal level (M3) 421 and earth terminal holding wire 423, and earth terminal holding wire 431 is electrically coupled to earth terminal holding wire 423 on the 3rd metal level (M3) by connector 432, so that form electric power networks.
(/earth terminal the holding wire or the voltage source signal line institute that BL) are set at the top fully covers or partly covers, so the present invention can avoid being used for the metallic signal lines of transfer of data on the memory cell and stride the signal that the array control signal line caused and disturb because bit line (BL) and/or paratope line.Therefore, memory cell of the present invention can be promoted the protective capacities that signal disturbs, and allows holding wire can stride across memory cell array to carry out distribution, so that promote the size of positioning efficiency with the speed and the reduction chip of chip.In order to keep minimum resistance drop (IR drop), earth terminal holding wire (VSS) among the present invention and voltage source signal line (VCC) form electric power networks, so that obtain firm power supply signal line and stable in-line memory chip.
In a preferred embodiment, between per two memory arrays, be provided with at least one well region conduction (strap) contact.Fig. 6 is the embodiment of memory chip, and P type substrate 610 has a plurality of memory cell 612 formed thereon.For example, each memory array 620 comprises a plurality of memory cell 612, and each memory cell 612 can be 6T-SRAM or 8T-SRAM.P type well region conduction (strap) unit 615 comprises P well region voltage lead 614, P type doped region, and it is arranged in the substrate 610, and comprises the connector 616 that is coupled to P well region voltage lead 614 and P type doped region.P well region voltage lead 614 is formed at one or more metal levels (for example M1, M2, M3, M4 ...) on, for example, P well region voltage lead 614 is coupled to earth terminal (for example VSS).
N type well region conduction (strap) unit 617 comprises P well region voltage lead 618, P type doped region, and it is arranged in the substrate 610, and comprises the connector 612 that is coupled to P well region voltage lead 618 and P type doped region.P well region voltage lead 614 is formed at one or more metal levels (for example M1, M2, M3, M4 ...) on, for example, P well region voltage lead 618 is coupled to voltage source (for example VCC).
Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; any those of ordinary skill in the art; without departing from the spirit and scope of the present invention; should do a little change and retouching, so protection scope of the present invention should be as the criterion with appended claim institute restricted portion.
Claims (13)
1. a memory cell is characterized in that, comprising:
Substrate, it comprises inverter and first, second pass transistor of two cross-coupled formed thereon, above-mentioned inverter has data memory node and complementary data memory node, and above-mentioned two nodes are coupled to first end of above-mentioned first, second pass transistor respectively;
First conductive layer, it is arranged in the above-mentioned substrate, comprises bit line and paratope line, and this bit line and paratope line are coupled to second end of above-mentioned first, second pass transistor respectively;
Second conductive layer, it is arranged on above-mentioned first conductive layer, comprise two first power supply signal lines, above-mentioned two first power supply signal lines are covered in respectively on above-mentioned bit line and the paratope line, and wherein above-mentioned two first power supply signal lines, bit line and paratope lines are parallel to each other; And
The 3rd conductive layer, it is arranged between above-mentioned first conductive layer and second conductive layer, comprise two the 3rd power supply signal lines, above-mentioned two the 3rd power supply signal lines are perpendicular to above-mentioned bit line and paratope line, and each above-mentioned the 3rd power supply signal line electrically connects above-mentioned two first power supply signal lines, and receive fixed power source voltage, in order to form electric power networks.
2. memory cell as claimed in claim 1 is characterized in that, above-mentioned two first power supply signal lines partly are covered on above-mentioned bit line and the paratope line.
3. memory cell as claimed in claim 1 is characterized in that, above-mentioned two first power supply signal lines fully cover above-mentioned bit line and paratope line.
4. memory cell as claimed in claim 1 is characterized in that, above-mentioned first conductive layer also comprises the second source holding wire, and it is arranged between above-mentioned bit line and the paratope line, and is electrically connected to first power end of the inverter of above-mentioned cross-coupled.
5. memory cell as claimed in claim 1 is characterized in that, above-mentioned the 3rd conductive layer also comprises word line, and this word line is perpendicular to above-mentioned bit line and paratope line, and is electrically connected to the control end of above-mentioned first, second pass transistor.
6. memory cell as claimed in claim 1, it is characterized in that, also comprise the 4th conductive layer, it is arranged between the above-mentioned substrate and first conductive layer, comprise word line, this word line is perpendicular to above-mentioned bit line and paratope line, and be electrically connected to the control end of above-mentioned first, second pass transistor, above-mentioned first conductive layer also comprises two the 4th power supply signal lines, above-mentioned two the 4th power supply signal line parallels are in above-mentioned bit line and paratope line, in order to the second source end of the inverter that is electrically connected to above-mentioned two first power supply signal lines and above-mentioned cross-coupled.
7. a memory cell is characterized in that, comprising:
Substrate, it comprises pass transistor formed thereon;
First conductive layer, it is arranged in the above-mentioned substrate, comprises bit line, and this bit line is electrically coupled to first end of above-mentioned pass transistor;
Second conductive layer, it is arranged on above-mentioned first conductive layer, comprises the first power supply signal line, and this first power supply signal line is covered in above-mentioned bit line, and the wherein above-mentioned first power supply signal line parallel is in above-mentioned bit line;
The 3rd conductive layer, it is arranged on above-mentioned second conductive layer, comprises the second source holding wire, and this second source holding wire is perpendicular to above-mentioned bit line, and above-mentioned first, second power supply signal line is electrically connected to the fixed power source voltage from electric power networks; And
Storage capacitance, it is coupled between second end of certain voltage and above-mentioned pass transistor.
8. memory cell as claimed in claim 7 is characterized in that, the above-mentioned first power supply signal line partly is covered on the above-mentioned bit line.
9. memory cell as claimed in claim 7 is characterized in that, the above-mentioned first power supply signal line fully covers above-mentioned bit line.
10. a memory cell is characterized in that, comprises
Substrate;
First conductive layer, it is arranged in the above-mentioned substrate, comprises bit line and paratope line;
Second conductive layer, it is arranged on above-mentioned first conductive layer, comprise two first power supply signal lines, above-mentioned two first power supply signal lines are covered in respectively on above-mentioned bit line and the paratope line, and above-mentioned two first power supply signal lines, bit line and paratope lines are parallel to each other; And
The 3rd conductive layer, it is arranged between above-mentioned first conductive layer and second conductive layer, comprise two the 3rd power supply signal lines, above-mentioned two the 3rd power supply signal lines are perpendicular to above-mentioned bit line and paratope line, and each above-mentioned the 3rd power supply signal line electrically connects above-mentioned two first power supply signal lines, and receive fixed power source voltage, in order to form electric power networks.
11. a semiconductor storage is characterized in that, comprises
A plurality of memory arrays, each memory array comprise a plurality of memory cell as claimed in claim 1; And
At least one first well region conductive unit, it is electrically coupled to the P well region in the above-mentioned substrate, and the wherein above-mentioned first well region conductive unit is arranged between per two above-mentioned memory arrays.
12. semiconductor storage as claimed in claim 11, it is characterized in that, also comprise at least one second well region conductive unit, it is electrically coupled to the N well region in the above-mentioned substrate, and the wherein above-mentioned second well region conductive unit is arranged between per two above-mentioned memory arrays.
13. semiconductor storage as claimed in claim 12, it is characterized in that, each first well region conductive unit comprises P well region voltage lead, this P well region voltage lead is parallel to above-mentioned bit line, and each second well region conductive unit comprises N well region voltage lead, and this N well region voltage lead is parallel to above-mentioned bit line.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/390,707 US7723806B2 (en) | 2006-03-28 | 2006-03-28 | Memory cells and semiconductor memory device using the same |
| US11/390,707 | 2006-03-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101047186A CN101047186A (en) | 2007-10-03 |
| CN101047186B true CN101047186B (en) | 2010-05-26 |
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| US11908910B2 (en) * | 2020-10-27 | 2024-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having embedded conductive line and method of fabricating thereof |
| WO2023044679A1 (en) * | 2021-09-23 | 2023-03-30 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
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| US7217978B2 (en) * | 2005-01-19 | 2007-05-15 | International Business Machines Corporation | SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and method for making same |
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| US20070235765A1 (en) | 2007-10-11 |
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