CN101038320A - Method for generating testing vector - Google Patents

Method for generating testing vector Download PDF

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Publication number
CN101038320A
CN101038320A CN 200710065266 CN200710065266A CN101038320A CN 101038320 A CN101038320 A CN 101038320A CN 200710065266 CN200710065266 CN 200710065266 CN 200710065266 A CN200710065266 A CN 200710065266A CN 101038320 A CN101038320 A CN 101038320A
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China
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synchronizing circuit
synchronous clock
clock
phase
interval
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CN 200710065266
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Chinese (zh)
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CN100578246C (en
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余娜敏
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北京中星微电子有限公司
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Abstract

The present invention provides a method of generating the test vectors. The method includes: A. the phase of the synchronous clock of the synchronous circuit and the overturning time point of the asynchronous signal are obtained, and a phase interval of the synchronous clock provided for the synchronous circuit is determined; B. the configuration information of the phase locked loop PLL is adjusted to make sure that the synchronous clock phase output according to the configuration information by PLL is in the phase interval calculated in the step A; C. the test vectors are generated by using the adjusted PLL configuration information. In the present invention, test vectors can be generated through adjusting the configuration information of PLL, and in the testing process, said test vectors assure that the synchronous signals output by the synchronous circuit not generate excursion. Thus, the chips having perfect functions can all pass the test and the testing of the robustness of the vectors are improved.

Description

A kind of method that generates test vector

Technical field

The present invention relates to a kind of measuring technology, particularly a kind of method that generates test vector.

Background technology

Increase along with chip integration, complexity and functional requirement, in a lot of digital circuitries, there is the functional module of different clock-domains in chip internal, and the clock signal of the out of phase that the functional module of these different clock-domains is required is provided by phase place phaselocked loop (PLL) circuit of chip internal.Also there are some synchronizing circuits in chip internal, synchronous clock in the clock zone that each synchronizing circuit all provides according to the PLL circuit, the nonsynchronous signal that the functional module of different clock-domains in the chip is exported is sampled, obtain steady synchronizing signal, just the nonsynchronous signal that the functional module of different clock-domains in the chip is exported is synchronized to a clock zone, and the clock zone after this is synchronous is exactly the whole sequential of chip.Synchronizing circuit can be divided into just along sampling type and negative edge sampling type the sampling of nonsynchronous signal, be that synchronizing circuit is sampled to nonsynchronous signal at the rising edge of synchronous clock along the sampling type just wherein, negative edge sampling type is that synchronizing circuit is sampled to nonsynchronous signal at the negative edge of synchronous clock.

Chip will be through the process of emulation verification from being designed into volume production, post-simulation in the emulation verification, consider the internal delay time of different components, and layout and the influence that time-delay brings to chip of coiling scheme, therefore post-simulation is and the essentially identical emulation of real work situation, also is an important means judging that can design chips volume production.At present, use test board and measurement vector carry out post-simulation.Test vector is exactly the signal that comprises the PLL configuration information.Tester table is imported chip with test vector, and PLL provides synchronous clock according to the PLL configuration information that test vector carries for synchronizing circuit in the chip, and synchronizing circuit is according to the synchronous back of synchronous clock output signal.The clock zone of the synchronous back signal of synchronizing circuit output is exactly the clock zone of chip internal, just the whole sequential of chip.Chip is sampled to test vector according to whole sequential, with the output of the test vector after the sampling.In standard delay mode (SDF) file that chip design stage is estimated, record the output signal characteristics of chip under the design sequential, when the chip of putting down in writing in test vector output signal and the SDF file when the output signal characteristics of design sequential is identical, illustrate that chip has passed through vector test, can carry out volume production, the method for judgement is that tester table uses the output signal characteristics of putting down in writing in absolute time contrastive test vector output valve and the SDF file.

At present, the common synchronizing circuit that is used for chip as shown in Figure 1, Fig. 1 is the structural representation of prior art synchronizing circuit, comprises first d type flip flop and second d type flip flop in this synchronizing circuit.The layout of circuit and coiling, and some uncertain factors in producing and making, it is inequality to make that synchronous clock arrives time delay of the clock signal of first d type flip flop and second d type flip flop (CLK) input end, it is also different that nonsynchronous signal arrives the time delay of first d type flip flop and the input end of second d type flip flop, thereby cause drift before and after the synchronizing signal that forms by first d type flip flop and second d type flip flop, the different delayed time situation that synchronous clock and nonsynchronous signal is arrived two triggers is called two kinds of time-delay situations (timing delay case).Drift before and after all or part of generation of the output synchronizing signal of these synchronizing circuits comprises some synchronizing circuits in the chip, if with causing the variation in chip synchronous clock territory, can have influence on the behavior of entire chip sequential.Fig. 2 is just changing synoptic diagram along the synchronous clock territory of sampling type synchronizing circuit in the prior art.As shown in Figure 2, waveform 201 is the whole sequential of chip, and waveform 202 is a chip input test vector signal waveform, and waveform 203 finishes the output of back test vector for chip testing.Wherein waveform 201 is because the variation in chip synchronous clock territory, and the chip sequential of estimating during with design is not exclusively the same, supposes situation about estimating according to design, and chip should begin to gather the input test vector signal at moment t1.But as can be seen from Figure 2, when first rising edge appears in the test vector input signal, first rising edge of chip sequential does not also arrive, therefore can't begin collecting test vector input signal at moment t1 chip, the t2 that arrives up to second rising edge of chip constantly, chip just begins collecting test vector input signal, so the output signal characteristics of putting down in writing in the final test vector output signal characteristics of chip and the SDF file is inequality, and chip can not be by testing.

As seen, the output synchronizing signal drift of prior art chips synchronizing circuit will cause the variation in chip synchronous clock territory, and then influence the behavior of the whole sequential of chip, though the function of chip is still correct, but for can only do absolute time ratio for tester table, can't judge whether chip functions is intact, so just cause the intact chip of some functions can not pass through vector test.At above-mentioned situation, require the volume production slip-stick artist to improve the robustness of test vector at the input and output of complexity, promptly adjust the configuration information of PLL in the test vector, make test vector when the intact chip of input function, the synchronous clock that synchronizing circuit provides according to the PLL configuration information that carries in the test vector according to PLL in the chip, nonsynchronous signal is synchronized to a clock zone, clock after being somebody's turn to do synchronously is the whole sequential of chip, guarantee that chip is identical to the output signal put down in writing in the signal after the sampling of input test vector and the SDF file under this integral body sequential, make tester table after the output signal of using absolute time contrastive test vector output signal and the record of SDF file, the chip that arbitration functions is intact passes through test.But the robustness that improves test vector need take much time and energy is done explication de texte, and a large amount of board test durations, and the manufacturing cost of chip is risen.

Summary of the invention

In view of this, fundamental purpose of the present invention provides a kind of method that generates test vector, and this method can strengthen the robustness of multi-clock zone circuit test vector.

In order to realize the foregoing invention purpose, the invention provides a kind of method that generates test vector, this method comprises:

Point flip-flop transition of A, the phase place of obtaining the synchronizing circuit synchronous clock and nonsynchronous signal, being defined as synchronizing circuit provides between the phase region of synchronous clock;

B, adjust the configuration information of phase place phase-locked loop pll, make PLL according in the synchronous clock phase of configuration information output is between the phase region that steps A calculates;

C, the adjusted PLL configuration information of use generate test vector.

Preferably, the described phase place of obtaining the synchronizing circuit synchronous clock of steps A and nonsynchronous signal flip-flop transition point method be:

According to the phase place and the Frequency Design value of synchronizing circuit synchronous clock, use static timing analysis STA draw the phase place of described synchronizing circuit synchronous clock and nonsynchronous signal by low level to the some flip-flop transition of high level.

On this basis, the method between the described phase region that is defined as synchronizing circuit and provides synchronous clock of steps A is:

The phase place of the described synchronizing circuit synchronous clock that draws and nonsynchronous signal by low level in the flip-flop transition of high level point, select the scope of first clock of synchronizing circuit synchronous clock along the phase place appearance, determine that nonsynchronous signal is by low level first scope that flip-flop transition, point occurred to high level in the synchronizing circuit, in the scope that first clock of synchronous clock occurs along phase place, select with nonsynchronous signal by low level to the underlapped interval of scope that first overturn point of high level occurs, as providing between the phase region of synchronous clock for synchronizing circuit.

After between the phase region of having determined the synchronous clock that synchronizing circuit provides, if the number of synchronizing circuit is more than one, further comprise after the described steps A: get common factor between the phase region of all synchronizing circuit synchronous clocks that will obtain, with between the phase region of interval of getting behind the common factor as all synchronizing circuit synchronous clocks.

Above-mentioned clock is along being the synchronous clock rising edge, and is described in the scope that first clock of synchronous clock occurs along phase place, selects with nonsynchronous signal by the method for low level to the underlapped interval of the scope of first overturn point appearance of high level to be:

In the interval that first rising edge clock border of synchronous clock CPE limits, select to put flip-flop transition interval nonoverlapping interval of border PU qualification with nonsynchronous signal.

Above-mentioned clock be along for also can being the synchronous clock negative edge, in the scope that first clock of synchronous clock occurs along phase place, selects with nonsynchronous signal by the method for low level to the underlapped interval of the scope of first overturn point appearance of high level to be:

In the interval that first clock negative edge border CNE of synchronous clock limits, select to put flip-flop transition interval nonoverlapping interval of border PU qualification with nonsynchronous signal.

Preferably, the method for the adjusted PLL configuration information generation of the described use of step C test vector is:

By adjusting the parameter of test vector, generate the test vector that carries the PLL configuration information.

As seen from the above technical solution, the method for generation test vector provided by the invention is at first obtained the phase place of synchronizing circuit synchronous clock and some flip-flop transition of nonsynchronous signal, and being defined as synchronizing circuit provides between the phase region of synchronous clock; The configuration information that next adjusts the phase place phase-locked loop pll makes PLL according in the synchronous clock phase of configuration information output is between the phase region that calculates; Use adjusted PLL configuration information to generate test vector at last.According to the method described above, the test vector that uses adjusted PLL configuration information to generate, behind the input chip, the synchronous clock that synchronizing circuit in the chip provides according to the PLL configuration information that carries in the test vector according to PLL, one collects nonsynchronous signal surely when the synchronous clock edge occurs, guaranteeing to export synchronizing signal does not drift about, thereby guarantee that the whole sequential of chip is identical with design load, the output signal characteristics that chip is put down in writing in the test vector output signal after the sampling of ordered pair test vector and the SDF file during according to integral body is identical, and tester table can both be by testing with the normal chip of decision-making function.

Description of drawings

Fig. 1 is the structural representation of synchronous clock circuit in the prior art;

Fig. 2 is that prior art chips synchronous clock territory changes synoptic diagram;

Fig. 3 generates the method better embodiment process flow diagram of test vector for the present invention;

Fig. 4 generates the method embodiment process flow diagram of test vector for the present invention;

Fig. 5 is not for just there being the synoptic diagram of overlapping interval along CPEU and PU in the sampling type synchronizing circuit;

Fig. 6 is for just there being the synoptic diagram of overlapping interval along CPEU and PU in the sampling type synchronizing circuit;

Fig. 7 does not have the synoptic diagram of overlapping interval for CNEU in the negative edge sampling type synchronizing circuit and PU;

Fig. 8 has the synoptic diagram of overlapping interval for CNEU in the negative edge sampling type synchronizing circuit and PU.

Embodiment

For making goal of the invention of the present invention, technical scheme and advantage clearer, the present invention is described in further detail below in conjunction with drawings and Examples.

The method of generation test vector provided by the invention is at first obtained the phase place of synchronizing circuit synchronous clock and some flip-flop transition of nonsynchronous signal, and being defined as synchronizing circuit provides between the phase region of synchronous clock; The configuration information that next adjusts the phase place phase-locked loop pll makes PLL according in the synchronous clock phase of configuration information output is between the phase region that calculates; Use adjusted PLL configuration information to generate test vector at last.

Describe the method for generation test vector provided by the invention below in detail.

Referring to Fig. 3, Fig. 3 is the method better embodiment process flow diagram of generation test vector provided by the invention, and this flow process comprises:

Step 301: obtain the phase place of the used synchronous clock of synchronizing circuit and some flip-flop transition of nonsynchronous signal, being defined as synchronizing circuit provides between the phase region of synchronous clock.

In this step, according to the physical circuit that is the synchronizing circuit of chip design, and the synchronous clock phase of synchronizing circuit sampling use and the design load of frequency, report (STA report) by the static timing analysis that static timing analysis (STA) draws, collect the synchronous clock phase of synchronizing circuit and some flip-flop transition of nonsynchronous signal, according to the sampling type of data of collecting and synchronizing circuit, determine between phase region.When synchronizing circuit for just along the sampling type time, in synchronizing circuit, determine the scope that first rising edge of synchronous clock may occur, determine that nonsynchronous signal is by low level first scope that flip-flop transition, point may occur to high level, in the scope that first rising edge of determining may occur, select not and nonsynchronous signal is put the overlapping interval of scope that may occur by low level to first flip-flop transition of high level, as this just along the synchronous clock phase interval of sampling type synchronizing circuit.When synchronizing circuit is negative edge sampling type, in synchronizing circuit, determine the scope that first negative edge of synchronous clock may occur, determine that nonsynchronous signal is by low level first scope that flip-flop transition, point may occur to high level, in the scope that first negative edge of determining may occur, select not and nonsynchronous signal is put the overlapping interval of scope that may occur by low level to first flip-flop transition of high level, as the synchronous clock phase interval of this negative edge sampling type synchronizing circuit.Determined the situation on first clock edge of synchronizing circuit synchronous clock by said method, because synchronous clock is made up of the pulse signal of equal intervals, after the situation of having determined first clock edge, the situation on all clock edges of synchronous clock is all corresponding definite.When more than one of the synchronizing circuit in the chip, each synchronizing circuit said method of all sampling is determined between the phase region of a synchronous clock, get common factor between phase region again, obtain between the phase region of all synchronizing circuit synchronous clocks each synchronizing circuit synchronous clock of gained.

Step 302: adjust the configuration information of PLL, make synchronous clock phase that PLL offers synchronizing circuit between the phase region that step 301 calculates in.

In this step, according to the synchronous clock phase interval that calculates in the step 301, adjust the configuration information of PLL, the synchronous clock phase of PLL output of using this configuration information is all in the interval of calculating.Adjustment can realize that this belongs to those skilled in the art's common practise by the configuration that changes the PLL register.

Step 303: use adjusted PLL configuration information to generate test vector.

In this step, regenerate test vector according to adjusted PLL configuration information.By adjusting the parameter of test vector, make that the test vector after adjusting carries the PLL configuration information.The test vector that regenerates, owing to comprised adjusted PLL configuration information, behind the test vector input chip, PLL provides synchronous clock according to the PLL configuration information that test vector carries for synchronizing circuit, the synchronous clock phase that is provided all between the phase region that step 302 draws in.When synchronizing circuit for just along the sampling type time, before first rising edge of synchronous clock occurs, first of nonsynchronous signal put to the flip-flop transition of high level by low level and occurred, when synchronizing circuit is negative edge sampling type, before first negative edge of synchronous clock occurs, first of nonsynchronous signal put to the flip-flop transition of high level by low level and occurred, when using this test vector that chip is carried out post-simulation like this, synchronizing circuit is when each rising edge or each negative edge occur, one collects nonsynchronous signal surely, make the output synchronizing signal of synchronizing circuit not drift about, thereby make the whole sequential of chip identical with situation about estimating, chip is sampled to the test vector of input under the preface at this moment, with obtain with the SDF file in the identical output test vector of output signal characteristics that loads, strengthened the robustness of test vector.When in the chip a plurality of synchronizing circuit being arranged, according to the synchronous clock phase interval of all synchronizing circuits that calculate, adjust the configuration information of PLL, regenerate test vector according to adjusted PLL information.

Based on above better embodiment, describe the method embodiment of generation test vector provided by the invention below in detail, the present embodiment hypothesis has a plurality of synchronizing circuits.Referring to Fig. 4, Fig. 4 is the method embodiment process flow diagram of generation test vector provided by the invention, and this flow process comprises:

Step 401: physical circuit and the synchronous clock phase of sampling use and the design load of frequency of obtaining all synchronizing circuits of design.

In this step, synchronizing circuit can be just along the sampling type, also can be negative edge sampling type, and the synchronous clock phase that the synchronizing circuit sampling is used comprises synchronous clock rising edge phase place and the negative edge phase place that the synchronizing circuit sampling is used.

Step 402: the information of obtaining according to step 401, draw the synchronous clock phase that all synchronizing circuits samplings are used by STA, and the flip-flop transition of nonsynchronous signal point.

In this step, physical circuit and the synchronous clock phase of sampling use and the design load of frequency according to all synchronizing circuits, the STA report that draws by STA collects the synchronous clock phase that all synchronizing circuits samplings are used in the chip, and the flip-flop transition of nonsynchronous signal point.

Step 403: the information of obtaining according to step 402, at first clock of synchronous clock along selecting in the scope that may occur not and nonsynchronous signal is put the overlapping interval of scope that may occur by low level to first flip-flop transition of high level.

In this step, in the synchronous clock phase of collecting, find out the phase range that first rising edge occurs at each synchronizing circuit, with the boundary definition of this scope is the first rising edge clock border (CPE1) and second clock rising edge border (CPE2), and the interval from CPE1 to CPE2 is between the uncertain region that occurs of first rising edge of synchronous clock (CPEU).Find out the phase range boundary value that first negative edge occurs at each synchronizing circuit and be defined as the first clock negative edge border (CNE1) and second clock negative edge border (CNE2) in the synchronous clock phase of collecting, the interval from CNE1 to CNE2 is between the uncertain region of first negative edge appearance of synchronous clock (CNEU).In all synchronizing circuits of collecting in the flip-flop transition of the nonsynchronous signal point at each synchronizing circuit find out first by low level to the flip-flop transition of high level point scope appears, with the boundary definition of this scope is P1 and P2, nonsynchronous signal all exists with impulse form, and the interval from P1 to P2 is between nonsynchronous signal pulse uncertain region (PU).Difference sampling type according to synchronizing circuit, with a synchronizing circuit is example, if this synchronizing circuit is for just along the sampling type, determine the nonoverlapping interval of CPEU and PU, if this synchronizing circuit is a negative edge sampling type, determine the nonoverlapping interval of CNEU and PU, above-mentioned nonoverlapping interval is the interval of a synchronizing circuit synchronous clock phase.

Step 404: common factor is got in the synchronous clock phase interval that each synchronizing circuit calculates.

In this step, between phase region, will get common factor between all these phase regions, obtain between the phase region of all synchronizing circuit synchronous clocks according to each synchronizing circuit synchronous clock in the chip that calculates in the step 403.

Step 405: adjust the configuration information of PLL, the phase place that makes PLL output synchronous clock between the phase region of all synchronizing circuit synchronous clocks in.

In this step,, adjust the configuration information of PLL by changing the configuration of PLL configuration register, make PLL according to the phase place of this configuration information output synchronous clock in step 404 obtains between the phase region of all synchronizing circuit synchronous clocks.

Step 406: use adjusted PLL configuration information to generate test vector.

In this step, regenerate test vector according to adjusted PLL configuration information.By adjusting the parameter of test vector, make that the test vector after adjusting carries the PLL configuration information.The test vector that regenerates, owing to comprised adjusted PLL configuration information, behind the test vector input chip, PLL provides synchronous clock according to the PLL configuration information that test vector carries for synchronizing circuit, the synchronous clock phase that is provided all between the phase region that step 403 draws in.When synchronizing circuit for just along the sampling type time, before first rising edge of synchronous clock occurs, nonsynchronous signal is occurred by low level first time overturn point to high level, when synchronizing circuit is negative edge sampling type, before first negative edge of synchronous clock occurs, the nonsynchronous signal low level occurs to first time overturn point of high level, when using this test vector that chip is carried out post-simulation like this, synchronizing circuit is when first rising edge or first negative edge occur, one collects nonsynchronous signal surely, guarantee that the synchronizing signal of synchronizing circuit output do not drift about, thereby guaranteed the whole sequential of chip, chip is when the ordered pair test vector is sampled during according to this integral body, with obtain with the SDF file in the identical test vector output signal of output signal put down in writing, normally functioning chip all will strengthen the robustness of test vector by test.When in the chip a plurality of synchronizing circuit being arranged, according to the synchronous clock phase interval of all synchronizing circuits that calculate, adjust the configuration information of PLL, regenerate test vector according to adjusted PLL information.

Above-mentioned steps 401~step 406, the method embodiment flow process of generation test vector provided by the invention has been described, in step 402, may there be different position relations in the interval CPEU, interval CNEU, the interval PU that is made up of P1 and P2 that is made up of CNE1 and CNE2 that are made up of CPE1 and CPE2, will be in step 403 according to the sampling type of synchronizing circuit, concern to determine with instantiation these different situations to be described below between the phase region of synchronizing circuit synchronous clock at these different positions.

At first, along the different situations of sampling type synchronizing circuit, the position that therefore only needs to consider CPEU and PU concerns at just in description.

Referring to Fig. 5, Fig. 5 is not for just there being the synoptic diagram of overlapping interval along CPEU and PU in the sampling type synchronizing circuit.As shown in Figure 5, waveform 501 is for arriving the phase waveform of first trigger in the synchronizing circuit, waveform 502 is for arriving the nonsynchronous signal phase waveform of first trigger in the synchronizing circuit, waveform 503 is for arriving the phase waveform of second trigger in the synchronizing circuit, and waveform 504 is for arriving the nonsynchronous signal phase waveform of second trigger in the synchronizing circuit.According to the described definite boundary method of step 402, determine CPEU and PU, visible in situation shown in Figure 5, CPEU and PU do not have overlapping areas, so CPEU are defined as this in step 403 just along the synchronous clock phase interval of sampling type synchronizing circuit.

Referring to Fig. 6, Fig. 6 is for just there being the synoptic diagram of overlapping interval along CPEU and PU in the sampling type synchronizing circuit.As shown in Figure 6, waveform 601 is for arriving the phase waveform of first trigger in the synchronizing circuit, waveform 602 is for arriving the nonsynchronous signal phase waveform of first trigger in the synchronizing circuit, waveform 603 is for arriving the phase waveform of second trigger in the synchronizing circuit, and waveform 604 is for arriving the nonsynchronous signal phase waveform of second trigger in the synchronizing circuit.Method according to the described definite border of step 402, determine CPEU and PU, visible in situation shown in Figure 6, CPEU and PU have overlapping areas, therefore in step 403, there is not overlapping part to be defined as this CPEU and PU just along the synchronous clock phase interval of sampling type synchronizing circuit.

At last, describe different situations, therefore only need to consider the position relation of CNEU and PU at negative edge sampling type synchronizing circuit.

Referring to Fig. 7, Fig. 7 does not have the synoptic diagram of overlapping interval for CNEU in the negative edge sampling type synchronizing circuit and PU.As shown in Figure 7, waveform 701 is for arriving the phase waveform of first trigger in the synchronizing circuit, waveform 702 is for arriving the nonsynchronous signal phase waveform of first trigger in the synchronizing circuit, waveform 703 is for arriving the phase waveform of second trigger in the synchronizing circuit, and waveform 704 is for arriving the nonsynchronous signal phase waveform of second trigger in the synchronizing circuit.Method according to the described definite border of step 402, determine CNEU and PU, visible in situation shown in Figure 7, CNEU and PU do not have overlapping areas, therefore in step 403, CNEU is defined as the synchronous clock phase interval of this negative edge sampling type synchronizing circuit.

Referring to Fig. 8, Fig. 8 has the synoptic diagram of overlapping interval for CNEU and PU in the negative sampling type synchronizing circuit.As shown in Figure 8, waveform 801 is for arriving the phase waveform of first trigger in the synchronizing circuit, waveform 802 is for arriving the nonsynchronous signal phase waveform of first trigger in the synchronizing circuit, waveform 803 is for arriving the phase waveform of second trigger in the synchronizing circuit, and waveform 804 is for arriving the nonsynchronous signal phase waveform of second trigger in the synchronizing circuit.Method according to the described definite border of step 402, determine CNEU and PU, visible in situation shown in Figure 8, CNEU and PU have overlapping areas, therefore in step 403, there is not overlapping part to be defined as the synchronous clock phase interval of this negative edge sampling type synchronizing circuit CNEU and PU.

In sum, the method of generation test vector provided by the invention, use adjusted PLL configuration information to generate test vector, make synchronous clock phase that PLL configuration information that PLL in the chip carries according to test vector provides for all synchronizing circuits all between the phase region of determining in.When first clock edge of each synchronizing circuit synchronous clock occurred, when first clock edge of each synchronizing circuit synchronous clock occurred, one began the sampling to nonsynchronous signal surely.Can guarantee that thus synchronizing circuit output synchronizing signal do not drift about, the whole sequential that has guaranteed chip is identical with design load, chip is sampled to test vector under the preface at this moment, the test vector output signal identical with output signal characteristics in the SDF file will be obtained, guaranteed that the intact chip of function can both strengthen the robustness of test vector by test.

Enhancing provided by the invention is the method for clock and circuit test vector robustness for a long time, can be applied in the various chips, for example chip for cell phone, hand held television chip and multimedia chip or the like.

Being preferred embodiment of the present invention only below, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (7)

1, a kind of method that generates test vector is characterized in that, this method comprises:
Point flip-flop transition of A, the phase place of obtaining the synchronizing circuit synchronous clock and nonsynchronous signal, being defined as synchronizing circuit provides between the phase region of synchronous clock;
B, adjust the configuration information of phase place phase-locked loop pll, make PLL according in the synchronous clock phase of configuration information output is between the phase region that steps A calculates;
C, the adjusted PLL configuration information of use generate test vector.
2, the method for claim 1 is characterized in that, steps A is described obtain the phase place of synchronizing circuit synchronous clock and nonsynchronous signal flip-flop transition point method be:
According to the phase place and the Frequency Design value of synchronizing circuit synchronous clock, use static timing analysis STA draw the phase place of described synchronizing circuit synchronous clock and nonsynchronous signal by low level to the some flip-flop transition of high level.
3, method as claimed in claim 2 is characterized in that, the method that steps A is described to be defined as synchronizing circuit and to provide between the phase region of synchronous clock is:
The phase place of the described synchronizing circuit synchronous clock that draws and nonsynchronous signal by low level in the flip-flop transition of high level point, select the scope of first clock of synchronizing circuit synchronous clock along the phase place appearance, determine that nonsynchronous signal is by low level first scope that flip-flop transition, point occurred to high level in the synchronizing circuit, in the scope that first clock of synchronous clock occurs along phase place, select with nonsynchronous signal by low level to the underlapped interval of scope that first overturn point of high level occurs, as providing between the phase region of synchronous clock for synchronizing circuit.
4, method as claimed in claim 3, it is characterized in that, the number of described synchronizing circuit is more than one, further comprise after the described steps A: get common factor between the phase region of all synchronizing circuit synchronous clocks that will obtain, with between the phase region of interval of getting behind the common factor as all synchronizing circuit synchronous clocks.
5, method as claimed in claim 3, it is characterized in that, described clock edge is the synchronous clock rising edge, described in the scope that first clock of synchronous clock occurs along phase place, select by the method for low level to be to the underlapped interval of the scope of first overturn point appearance of high level with nonsynchronous signal:
In the interval that first rising edge clock border of synchronous clock CPE limits, select to put flip-flop transition interval nonoverlapping interval of border PU qualification with nonsynchronous signal.
6, method as claimed in claim 3, it is characterized in that, described clock edge is the synchronous clock negative edge, in the scope that first clock of synchronous clock occurs along phase place, select the method in the underlapped interval of the scope that occurs to first overturn point of high level by low level with nonsynchronous signal to be:
In the interval that first clock negative edge border CNE of synchronous clock limits, select to put flip-flop transition interval nonoverlapping interval of border PU qualification with nonsynchronous signal.
7, the method for claim 1 is characterized in that, the method that the adjusted PLL configuration information of the described use of step C generates test vector is:
By adjusting the parameter of test vector, generate the test vector that carries the PLL configuration information.
CN200710065266A 2007-04-09 2007-04-09 Method for generating testing vector CN100578246C (en)

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WO2018113182A1 (en) * 2016-12-22 2018-06-28 深圳市中兴微电子技术有限公司 Method and device for generating test vector, and storage medium

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN102971638B (en) * 2010-07-07 2015-08-19 株式会社爱德万测试 The test unit that semiconductor devices is tested and test method
US9262376B2 (en) 2010-07-07 2016-02-16 Advantest Corporation Test apparatus and test method
CN104035023A (en) * 2013-03-07 2014-09-10 上海宏测半导体科技有限公司 Testing method and system of MCU
CN104035023B (en) * 2013-03-07 2016-12-28 上海宏测半导体科技有限公司 The method of testing of MCU and system
WO2018113182A1 (en) * 2016-12-22 2018-06-28 深圳市中兴微电子技术有限公司 Method and device for generating test vector, and storage medium
CN108226743A (en) * 2016-12-22 2018-06-29 深圳市中兴微电子技术有限公司 The generation method and device of a kind of test vector
CN108226743B (en) * 2016-12-22 2020-04-24 深圳市中兴微电子技术有限公司 Test vector generation method and device

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