CN101001382B - Frame prediction and reset method of AVS vedio standard - Google Patents
Frame prediction and reset method of AVS vedio standard Download PDFInfo
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Abstract
This invention discloses an in-frame forecast and re-set method of an AVS video standard including an in-frame forecast process and a re-set-up process, in which, at least a part of the data in the macro block used in the current re-set-up and forecast comes from a chip storage of a process chip, which increases speed and efficiency of coding and decoding in the in-frame forecast and re-set-up.
Description
Technical field
The invention belongs to technical field of image processing, relate in particular to a kind of video coding and decoding technology of AVS standard.
Background technology
The AVS standard is the autonomous audio/video coding technical standard of formulating of China, wherein has distinctive core technology in the middle of the AVS video and comprises in the conversion of 8*8 frame number, quantification, infra-frame prediction, 1/4 precision pixels interpolation, special inter prediction motion compensation, two-dimensional entropy coding and the deblocking effect ring filtering etc.
Wherein, the AVS intraframe prediction algorithm makes full use of the spatial coherence of image, carries out infra-frame prediction with the pixel around the image block, has improved code efficiency, thereby has reduced the coding bit rate output.In decoding end, according to the difference of intra prediction mode may with its upper left, go up piece, upper right, the data of left piece, lower-left piece and current 8*8 piece predict the corresponding residual values reconstruction of the data that obtain and this piece obtains decoding block.
Yet, needed data will be read into data during infra-frame prediction the frame data memory outside sheet, output to after prediction is rebuild in the outer frame data memory of sheet, frequent has had a strong impact on encoding and decoding speed and efficient with the chip external memory swap data, becomes a bottleneck of infra-frame prediction again.
Summary of the invention
The object of the invention is, a kind of speed is faster, efficient is higher infra-frame prediction and method for reconstructing are provided.
In order to address the above problem, the present invention proposes a kind of infra-frame prediction and method for reconstructing, comprise infra-frame prediction process and process of reconstruction, wherein, in described infra-frame prediction and the process of reconstruction, the data that the current macro prediction is rebuild in each macro block that is utilized have the on-chip memory of part from process chip at least.
Wherein, the data in the last macro block of data in the upper left macro block of data in the last macro block that data in each macro block that is utilized comprise current macro, current macro, current macro and the data of current macro self are rebuild in the prediction of described current macro.
Wherein, at least one is stored in the sheet stored unit of process chip in the data of data in the last macro block of the data in the upper left macro block of the data in the last macro block of described current macro, current macro, current macro and current macro self.
In addition, to rebuild data in the last macro block that is utilized and the data in the upper left macro block be to be stored in after last macroblock prediction reconstruction end in the on-chip memory of process chip to the prediction of described current macro; It is in current macro is expert at the on-chip memory that is stored in process chip before beginning to predict reconstruction that data in the last macro block that is utilized are rebuild in the prediction of described current macro; The data that described current macro prediction is rebuild in the current macro of being utilized are to be stored in after current macro is partly predicted reconstruction in the process chip sheet stored unit.
Wherein, the sub-macro block of 4 of current macro 8*8 byte-sized described in described prediction and the process of reconstruction is all predicted in the outer data storage of sheet that exports process chip after reconstruction finishes together to.
The infra-frame prediction and the method for reconstructing of AVS video standard of the present invention specifically may further comprise the steps:
A, appointment first memory are the current macro memory, and specifying second memory is a last macro block memory;
B, carry out infra-frame prediction according to the method for AVS standard; For the data in each required macro block, from first memory, second memory, the 3rd memory or the 4th memory, read; Wherein, at least one is the on-chip memory of process chip in described four memories;
C, carry out conversion and reconstruction according to the method for AVS standard; Data reconstruction is stored in the current macro memory;
D, judge current macro whether all prediction rebuild and finish; If finish, then continue to carry out, otherwise, turn to step B to carry out;
E, the partial data that next macroblock prediction of current macro is rebuild a required last macro-block line are stored in described the 4th memory; Storage relevant position in described the 3rd memory in the current macro in the current macro row that next macro-block line prediction reconstruction of current macro row is required;
Data in F, the output current macro memory;
G, appointment second memory are the current macro memory, and first memory is a last macro block memory;
H, current macro infra-frame prediction and reconstruction finish.
Wherein, in described step e, the partial data of the last macro-block line that next macroblock prediction reconstruction of current macro is required is meant the data of its upper left macro block that is arranged in a macro-block line that described next macroblock prediction reconstruction is required; The position of data in the 3rd memory in the last macro block that relevant position described in the described step e is utilized when being meant current macro prediction reconstruction.
Whole predictions are rebuild the sub-macro block that is meant 4 8*8 sizes that finishes and are predicted that all reconstruction finishes among the described step D.
As in one embodiment of the present of invention, the appointment to first memory, second memory among described steps A and the step G realizes that by exchanging the data pointer that points to two memories the data in the memory are constant.
The present invention stores current macro in advance by the sheet stored unit that makes full use of process chip and predicts needed other macro block datas when rebuilding, the prediction that does not need outside sheet reading of data the frame data memory can finish whole macro block in infra-frame prediction and process of reconstruction is rebuild, thereby greatly improved the encoding and decoding speed and the efficient of whole coding/decoding system, reduced in the sheet, the outer frequent access data of sheet are to the infra-frame prediction Effect on Performance.
Description of drawings
Fig. 1 is the structured flowchart of an embodiment of the process chip that the present invention is based on;
Fig. 2 is based on the workflow diagram of process chip shown in Figure 1;
Fig. 3 is based on the schematic diagram of flow process shown in Figure 2.
Embodiment
The present invention is by effectively utilizing the process chip built-in storage as infra-frame prediction and rebuild the memory cell of used data, thereby frequent and the outer data storage swap data of sheet have been avoided, and then improved encoding and decoding speed and efficient, also broken a bottleneck of infra-frame prediction and reconstruction.
In order more to help to understand the present invention, briefly draw out some basic compositions of process chip below, set forth the present invention by these composition function block diagrams.Certainly, process chip is very complicated truly, this example only for helped to understand the concise and to the point selection of the present invention part wherein form, the process chip composition frame chart in this example should not limit the present invention
With reference to figure 1, illustrate the present invention based on the structure of an embodiment of process chip.As shown in the figure, process chip 1 comprises:
First memory, size is the 16*16 byte;
Second memory, size is the 16*16 byte;
Described first memory and second memory are used for depositing in turn the current macro block that will predict and rebuild;
The 3rd memory, size is the width of a frame, the data that are used for storing infra-frame prediction and rebuild the required last macro block of the parton macro block of current macro;
The 4th memory, size are a byte, the data that are used for storing infra-frame prediction and rebuild the required upper left macro block of the parton macro block of current macro;
With reference to figure 2, illustrate based on infra-frame prediction of process chip shown in Figure 1 and rebuild flow process.As shown in the figure, first memory, second memory, the 3rd memory and the 4th memory all are positioned at process chip; With reference to figure 2, simultaneously with reference to figure 1, described flow process may further comprise the steps:
Step S100, specifying the current macro memory is first memory, specifying a last macro block processor is second memory; The required movement here can be realized by the sensing of data pointer, also can be other suitable mode etc., does not limit the present invention;
Step S101, method according to the AVS standard is carried out infra-frame prediction, the current macro data that the current macro forecasting institute needs read from the current macro memory, data read from a last macro block memory in the required left macro block, in the required last macro block of parton macro block and the data in the upper left macro block from the 3rd memory and the 4th memory, read respectively; The more intuitive expression of this step can be with reference to figure 3;
Step S102 carries out IDCT (Inverse Digital CosineTransform, inverse discrete cosine transform) conversion and reconstruction according to the method for AVS standard, and data reconstruction is stored in the current macro memory; Can adopt DMA (Direct Memory Access, direct memory access (DMA)) mode consuming time here, to reduce;
Step S103 judges whether current macro predicts that reconstruction finishes; Because here the sub-macro block with the 8*8 byte is the unit of infra-frame prediction, therefore described size is the macro block of 16*16 byte, therefore the sub-macro block that comprises 4 8*8 bytes has only after the whole reconstructions of these 4 8*8 macro blocks finish, and described macro block just is called reconstruction and finishes; Finish if current macro is rebuild, then continue step S104, otherwise execution in step S101;
Step S104 stores in previous byte data to the four memories of corresponding current macro position in the 3rd memory, and its more intuitive process can be with reference to figure 3;
Step S105, the position of corresponding current macro in last column data to the three memories after the reconstruction of storage current macro, its more intuitive process can be with reference to shown in Figure 3; Simultaneously, it is consuming time to reduce to enable dma mode here;
Step S106, the data after the output current macro is rebuild, just the data in the current macro memory outside sheet in the data storage, frame data memory for example; Equally, here also can adopt the dma access mode consuming time to reduce access;
Step S107, a current macro memory and a last macro block memory are exchanged appointment, and just specifying the current macro memory is second memory, and a last macro block memory is a first memory, here the just variation of assigned direction, the data in first memory and the second memory are constant; The change of assigned direction here can realize by the data pointer of an exchange current macro memory and a last macro block memory;
Step S108, the infra-frame prediction and the process of reconstruction of a macro block of end.
Be the infra-frame prediction and the process of reconstruction of a macro block more than, can repeat this flow process for a plurality of macro blocks and get final product.
With reference to figure 3, illustrate one of flow process shown in Figure 2 schematic diagram more intuitively.As shown in the figure, a current macro memory (first memory) and a last macro block memory (second memory) all are the 16*16 byte-sized, the sub-macro block that comprises 4 8*8 byte-sized, in first memory, can find out intuitively and comprise b0, b1, four sub-macro blocks of b2, b3, second memory and first memory are similar, so not shown.
In step S101 shown in Figure 2, described process can be understood with reference to figure 3: in the current macro, the data in the required upper left macro block of 8*8 macro block b0 infra-frame prediction read from the 4th memory; In the current macro, the data in the required last macro block of 8*8 macro block b0 and b1 infra-frame prediction read among the memory block a corresponding with current macro from the 3rd memory; Data in the current macro in the required left macro block of 8*8 macro block b0 and b2 infra-frame prediction read from a last macro block memory second memory; The needed left blocks of data of current macro neutron macro block b1 infra-frame prediction reads from sub-macro block b0; The required last blocks of data of current macro neutron macro block b2 infra-frame prediction reads from sub-macro block b0 and b1; Left piece that current macro neutron macro block b3 is required and last piece data read from sub-macro block b0 and b2 and sub-macro block b1 respectively.
In step S104 shown in Figure 2, described process is promptly preserved in previous byte data B to the four memories of position a of corresponding current macro memory first memory in the 3rd memory shown in mark P1 among Fig. 3; In step S105 shown in Figure 2, be labeled as the process from A to a of P2 among described process such as Fig. 3, promptly preserve the position a of corresponding current macro memory first memory in last column data A to the three memories of current macro memory first memory.
Fig. 3 is used for setting forth more intuitively flow process of the present invention, and not exclusively real embodiment the present invention, be for more help the public to the understanding of technology with openly the present invention fully.Therefore, should not limit the present invention with structure shown in Figure 3.
Those of ordinary skills are to be understood that, for first to fourth memory, also can be that chip external memory, the part that part is utilized process chip utilized the process chip on-chip memory, just listing in the present embodiment all is the situation of process chip on-chip memory, does not here give unnecessary details one by one for other situation.Equally, because the difference of intra prediction mode, predict needed also difference, some situations have just been enumerated in the present embodiment, wherein utilized reconstructed block to be predicted left piece, go up piece and upper left data, for the prediction under other predictive modes, then to data in requisition for other relevant block, for example also may need the data of upper right and lower-left piece etc., equally can be for these used data by the on-chip memory access of process chip.But owing to all be essentially identical on principle for different predictive modes, to those skilled in the art, under the guidance of spirit of the present invention, can draw the How It Works of other patterns by simple inference, therefore no longer the method for other patterns is set forth one by one.
The above is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also are considered as protection scope of the present invention.
Claims (9)
1. the infra-frame prediction of an AVS video standard and method for reconstructing, comprise infra-frame prediction process and process of reconstruction, it is characterized in that in described infra-frame prediction and the process of reconstruction, the data that the current macro prediction is rebuild in each macro block that is utilized have part at least from the process chip on-chip memory;
Wherein, this method specifically may further comprise the steps:
A, appointment first memory are the current macro memory, and specifying second memory is a last macro block memory;
B, carry out infra-frame prediction according to the method for AVS standard; For the data in each required macro block, from first memory, second memory, the 3rd memory or the 4th memory, read; Wherein, at least one is the process chip on-chip memory in described four memories;
C, carry out conversion and reconstruction according to the method for AVS standard; Data reconstruction is stored in the current macro memory;
D, judge current macro whether all prediction rebuild and finish; If finish, then continue to carry out, otherwise, turn to step B to carry out;
E, the partial data that next macroblock prediction of current macro is rebuild a required last macro-block line are stored in described the 4th memory; Storage relevant position in described the 3rd memory in the current macro in the current macro row that next macro-block line prediction reconstruction of current macro row is required;
Data in F, the output current macro memory;
G, appointment second memory are the current macro memory, and first memory is a last macro block memory;
H, current macro infra-frame prediction and reconstruction finish.
2. the method for claim 1, it is characterized in that the data in the last macro block of data in the upper left macro block of data in the last macro block that data in each macro block that is utilized comprise current macro, current macro, current macro and the data of current macro self are rebuild in the prediction of described current macro.
3. method as claimed in claim 2, it is characterized in that at least one is stored in process chip sheet stored unit in the data in the data in the data in the last macro block of described current macro, the upper left macro block of current macro, the last macro block of current macro and the data of current macro self.
4. as claim 2 or 3 described methods, it is characterized in that data and the data in the upper left macro block that described current macro prediction is rebuild in the last macro block that is utilized are to be stored in the process chip on-chip memory after a last macroblock prediction is rebuild end; The data that described current macro prediction is rebuild in the last macro block that is utilized are to be expert in current macro to begin to be stored in the process chip on-chip memory before the prediction reconstruction; The data that described current macro prediction is rebuild in the current macro of being utilized are to be stored in after current macro is partly predicted reconstruction in the process chip sheet stored unit.
5. as each described method in the claim 1 to 3, it is characterized in that the sub-macro block of 4 of current macro 8*8 byte-sized described in described prediction and the process of reconstruction is all predicted after reconstruction finishes and exported the process chip chip external memory together to.
6. method as claimed in claim 4 is characterized in that, the sub-macro block of 4 of current macro 8*8 byte-sized described in described prediction and the process of reconstruction is all predicted after reconstruction finishes and exported the process chip chip external memory together to.
7. method as claimed in claim 5, it is characterized in that, in the described step e, the partial data of the last macro-block line that next macroblock prediction reconstruction of current macro is required is meant the data of its upper left macro block that is arranged in a macro-block line that described next macroblock prediction reconstruction is required; The position of data in the 3rd memory in the last macro block that relevant position described in the described step e is utilized when being meant current macro prediction reconstruction.
8. method as claimed in claim 7 is characterized in that, whole predictions are rebuild the sub-macro block that is meant 4 8*8 sizes that finishes and predicted that all reconstruction finishes among the described step D.
9. method as claimed in claim 8 is characterized in that, the appointment to memory among described steps A and the step G realizes by changing data pointer.
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