CN100573915C - Thin-film transistor and manufacture method thereof - Google Patents

Thin-film transistor and manufacture method thereof Download PDF

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Publication number
CN100573915C
CN100573915C CNB2006100635293A CN200610063529A CN100573915C CN 100573915 C CN100573915 C CN 100573915C CN B2006100635293 A CNB2006100635293 A CN B2006100635293A CN 200610063529 A CN200610063529 A CN 200610063529A CN 100573915 C CN100573915 C CN 100573915C
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amorphous silicon
silicon layer
film transistor
gate insulator
layer
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CN101179096A (en
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颜硕廷
张建雄
张囿雄
郑凯元
谢朝桦
洪肇逸
赖昭志
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Innolux Shenzhen Co Ltd
Innolux Corp
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Innolux Shenzhen Co Ltd
Innolux Display Corp
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Abstract

The present invention relates to a kind of thin-film transistor, it comprises that an insulated substrate, is positioned at grid on this insulated substrate, a gate insulator, that covers this insulated substrate and this grid and is positioned at first amorphous silicon layer, on this gate insulator and is positioned at light dope amorphous silicon layer, on this first amorphous silicon layer and is positioned at second amorphous silicon layer, on this light dope amorphous silicon layer and is positioned at heavily doped amorphous silicon layer and on this second amorphous silicon layer and is positioned at metal electrode layer on this heavily doped amorphous silicon layer.The present invention also provides a kind of method of manufacturing thin film transistor.

Description

Thin-film transistor and manufacture method thereof
Technical field
The present invention relates to a kind of thin-film transistor and manufacture method thereof.
Background technology
Because characteristics such as the liquid crystal indicator tool is light, thin, power savings, it is used widely.The main element of liquid crystal indicator is a liquid crystal panel, liquid crystal panel generally include a thin film transistor base plate, a colored filter substrate and be sandwiched in this thin film transistor base plate and this colored filter substrate between liquid crystal layer.Wherein, thin film transistor base plate comprises a plurality of thin-film transistors and a plurality of pixel region, and these a plurality of thin-film transistors are as the control switch of these a plurality of pixel regions.
Seeing also Fig. 1, is a kind of structural representation of prior art thin-film transistor.This thin-film transistor 100 comprises an insulated substrate 110, one is positioned at the grid 120 on this insulated substrate 110, one covers the gate insulator 130 of this insulated substrate 110 and this grid 120, one is positioned at the amorphous silicon layer 141 on this gate insulator 130, one is positioned at the heavily doped amorphous silicon layer 142 on this amorphous silicon layer 141, one is positioned at the metal electrode layer 150 on this heavily doped amorphous silicon layer 142 and this gate insulator 130, one is covered in the passivation layer 160 of this metal electrode layer 150 and this gate insulator 130.This metal electrode layer 150 comprises an one source pole 151 and a drain electrode 152.
Seeing also Fig. 2, is the flow chart of the manufacture method of this thin-film transistor 100, and this manufacture method comprises the steps: to form a grid (step 101) on insulated substrate; Deposition one gate insulator (step 102) on grid and insulated substrate; On gate insulator, form an amorphous silicon layer (step 103); On amorphous silicon layer, form a heavily doped amorphous silicon layer (step 104); On the heavily doped amorphous silicon layer, form a metal electrode layer (step 105); Deposition one passivation layer (step 106) on metal electrode layer and gate insulator.
Seeing also Fig. 3 to Fig. 8, is each step schematic diagram of the manufacture method of this thin-film transistor 100, and it comprises the steps:
Step 101 provides an insulated substrate 110 as shown in Figure 3, utilizes chemical vapour deposition technique or physical vaporous deposition, deposition one metal level on this insulated substrate 110, and on metal level, be coated with a photoresist.One mask is provided, photoresist is carried out exposure imaging and etching sheet metal forms a grid 120.The material of this insulated substrate 110 is glass, quartz or pottery etc., and the material of this grid 120 is aluminum titanium alloy or chromium etc.
Step 102 is utilized chemical vapour deposition technique as shown in Figure 4, deposition one gate insulator 130 on this insulated substrate 110 and gate pole 120.The material of this gate insulator 130 is silicon nitride or silica etc.
Step 103 is utilized a chemical vapour deposition technique and a masking process as shown in Figure 5, forms an amorphous silicon layer 141 on this gate insulator 130.
Step 104 is utilized chemical vapour deposition technique and gas phase doping method and a masking process as shown in Figure 6, forms a heavily doped amorphous silicon layer 142 on this amorphous silicon layer 141, and wherein, impurity is a phosphonium ion in the gas phase doping method.
Step 105 is utilized chemical vapour deposition technique or physical vaporous deposition as shown in Figure 7, deposition one metal level on this heavily doped amorphous silicon layer 142 and this gate insulator 130, and on metal level, be coated with a photoresist.One mask is provided, photoresist is carried out exposure imaging and etching sheet metal forms a metal electrode layer 150.This metal electrode layer 150 comprises an one source pole 151 and a drain electrode 152.The material of this source electrode 151 and this drain electrode 152 is aluminum titanium alloy or chromium etc.
Step 106 is utilized chemical vapour deposition technique as shown in Figure 8, deposition one passivation layer 160 on this source electrode 151 and drain electrode 152 and this gate insulator 130.The material of this passivation layer 160 is silicon nitride or silica etc.
During these thin-film transistor 100 work, between grid 120 and source electrode 151, apply positive voltage, form a highfield in the insulating barrier 130, this highfield repels the hole on amorphous silicon layer 141 close grid 120 surfaces and attracts electronics, thereby forms a conducting channel with source electrode 151 and drain electrode 152 conductings on the surface of amorphous silicon layer 141 close grids 120.When applying negative voltage between grid 120 and the source electrode 151, the conducting channel of thin-film transistor 100 cuts out, owing to still have a small amount of hole in the conducting channel of amorphous silicon layer 141, under the voltage effect of drain electrode 152 and source electrode 151, form the leakage current of thin-film transistor, along with grid 120 is big with the change of the negative voltage of source electrode 151, increase in the hole, and the electric leakage rheology is big.
Summary of the invention
In order to solve the excessive problem of leakage current in the prior art, be necessary to provide a kind of thin-film transistor that reduces leakage current.
Also be necessary to provide a kind of method of manufacturing thin film transistor that reduces leakage current.
A kind of thin-film transistor, it comprises that an insulated substrate, is positioned at gate insulator, that grid, on this insulated substrate is covered in this insulated substrate and this grid and is positioned at first amorphous silicon layer, on this gate insulator and is positioned at light dope amorphous silicon layer, on this first amorphous silicon layer and is positioned at second amorphous silicon layer, on this light dope amorphous silicon layer and is positioned at heavily doped amorphous silicon layer and on this second amorphous silicon layer and is positioned at metal electrode layer on this heavily doped amorphous silicon layer and this gate insulator.
A kind of method for fabricating thin film transistor, it may further comprise the steps: form a grid on insulated substrate; Deposition one gate insulator on grid and insulated substrate; On gate insulator, form one first amorphous silicon layer; On first amorphous silicon layer, form a light dope amorphous silicon layer; On the light dope amorphous silicon layer, form one second amorphous silicon layer; On second amorphous silicon layer, form a heavily doped amorphous silicon layer; On the heavily doped amorphous silicon layer, form a metal electrode layer.
A kind of method for fabricating thin film transistor, it may further comprise the steps: form a grid on insulated substrate; Deposition one gate insulator on grid and insulated substrate; On gate insulator, form one first amorphous silicon layer; On first amorphous silicon layer, implement plasma treatment and form a phosphonium ion impurity layer; Form one second amorphous silicon layer on the phosphonium ion impurity layer, phosphonium ion partly diffuses to form a light dope amorphous silicon layer to first amorphous silicon layer and second amorphous silicon layer; On second amorphous silicon layer, form a heavily doped amorphous silicon layer; On the heavily doped amorphous silicon layer, form a metal electrode layer; Deposition one passivation layer on metal electrode layer and gate pole insulating barrier.
Thin-film transistor of the present invention and manufacture method thereof are owing to comprise a light dope amorphous silicon layer between gate insulator and amorphous silicon layer, electron concentration increases than electron concentration in the amorphous silicon layer in this light dope amorphous silicon layer, when applying negative voltage between grid and the source electrode, the electron concentration that increases can hinder the hole in (block) or compound (re-combine) conducting channel, make electric leakage rheology main trend be suppressed, the big degree of its electric leakage rheology, many compared to the thin-film transistor mitigation of traditional handicraft.
Description of drawings
Fig. 1 is a kind of structural representation of prior art thin-film transistor.
Fig. 2 is the flow chart of method of manufacturing thin film transistor shown in Figure 1.
Fig. 3 to Fig. 8 is each step schematic diagram of method of manufacturing thin film transistor shown in Figure 1.
Fig. 9 is the structural representation of thin-film transistor first execution mode of the present invention.
Figure 10 is the flow chart of method of manufacturing thin film transistor shown in Figure 9.
Figure 11 to Figure 17 is each step schematic diagram of method of manufacturing thin film transistor shown in Figure 9.
Figure 18 is the structural representation of thin-film transistor second execution mode of the present invention.
Figure 19 is the flow chart of method of manufacturing thin film transistor shown in Figure 180.
Figure 20 to Figure 27 is each step schematic diagram of method of manufacturing thin film transistor shown in Figure 180.
Figure 28 is the flow chart of another manufacture method of thin-film transistor shown in Figure 9.
Figure 29 is the flow chart of another manufacture method of thin-film transistor shown in Figure 180.
Embodiment
Seeing also Fig. 9, is the structural representation of thin-film transistor first execution mode of the present invention.This thin-film transistor 200 comprises an insulated substrate 210, one is positioned at the grid 220 on this insulated substrate 210, one covers the gate insulator 230 of this insulated substrate 210 and this grid 220, one is positioned at the light dope amorphous silicon layer 241 on this gate insulator 230, one is positioned at the amorphous silicon layer 242 on this light dope amorphous silicon layer 241, one is positioned at the heavily doped amorphous silicon layer 243 on this amorphous silicon layer 242, one is positioned at the metal electrode layer 250 on this heavily doped amorphous silicon layer 243 and this gate insulator 230, one covers the passivation layer 260 of this metal electrode layer 250 and this gate insulator 230.This metal electrode layer 250 comprises an one source pole 251 and a drain electrode 252.
Seeing also Figure 10, is the flow chart of the manufacture method of this thin-film transistor 200.This manufacture method comprises the steps: to form a grid (step 201) on insulated substrate; Deposition one gate insulator (step 202) on grid and insulated substrate; On gate insulator, form a light dope amorphous silicon layer (step 203); On the light dope amorphous silicon layer, form an amorphous silicon layer (step 204); On amorphous silicon layer, form a heavily doped amorphous silicon layer (step 205); On the heavily doped amorphous silicon layer, form a metal electrode layer (step 206); Deposition one passivation layer (step 207) on metal electrode layer and gate pole insulating barrier.
Seeing also Figure 11 to Figure 17, is each step schematic diagram of the manufacture method of this thin-film transistor 200, and it comprises the steps:
Step 201 provides an insulated substrate 210 as shown in figure 11, utilizes chemical vapour deposition technique or physical vaporous deposition, deposition one metal level on this insulated substrate 210, and on metal level, be coated with a photoresist.One mask is provided, photoresist is carried out exposure imaging and etching sheet metal forms a grid 220.The material of this insulated substrate 210 is glass, quartz or pottery etc., and the material of this grid 220 is molybdenum or its alloy, aluminum titanium alloy or chromium etc.
Step 202 is utilized chemical vapour deposition technique as shown in figure 12, deposition one gate insulator 230 on this insulated substrate 210 and gate pole 220.The material of this gate insulator 230 is silicon nitride or silica etc.
Step 203 as shown in figure 13, utilize chemical vapour deposition technique and gas phase doping method and a masking process, on this gate insulator 230, form a light dope amorphous silicon layer 241, wherein, impurity is phosphonium ion or arsenic ion in the gas phase doping method, and the thickness of this light dope amorphous silicon layer 241 is less than 60nm.
Step 204 is utilized a chemical vapour deposition technique and a masking process as shown in figure 14, forms an amorphous silicon layer 242 on this light dope amorphous silicon layer 241.
Step 205 is utilized chemical vapour deposition technique and gas phase doping method and a masking process as shown in figure 15, forms a heavily doped amorphous silicon layer 243 on this amorphous silicon layer 242, and wherein, impurity is a phosphonium ion in the gas phase doping method.
Step 206 is utilized chemical vapour deposition technique or physical vaporous deposition as shown in figure 16, deposition one metal level on this heavily doped amorphous silicon layer 243 and this gate insulator 230, and on metal level, be coated with a photoresist.One mask is provided, photoresist is carried out exposure imaging and etching sheet metal forms a metal electrode layer 250.This metal electrode layer 250 comprises an one source pole 251 and a drain electrode 252, and the material of this source electrode 251 and this drain electrode 252 is molybdenum or its alloy, aluminum titanium alloy or chromium etc.
Step 207 is utilized chemical vapour deposition technique as shown in figure 17, deposition one passivation layer 260 on this source electrode 251, this drain electrode 252 and this gate insulator 230, and the material of this passivation layer 260 can be silicon nitride or silica etc.
This thin-film transistor 200 is owing to comprise a light dope amorphous silicon layer 241 between gate insulator 230 and amorphous silicon layer 242, electron concentration increases than electron concentration in the amorphous silicon layer 242 in this light dope amorphous silicon layer 241, when applying negative voltage between grid 220 and the source electrode 251, the electron concentration that increases can hinder the hole in (block) or compound (re-combine) conducting channel, make electric leakage rheology main trend be suppressed, the big degree of its electric leakage rheology relaxes many compared to traditional handicraft.
See also Figure 18, it is the structural representation of thin-film transistor second execution mode of the present invention, this thin-film transistor 300 comprises an insulated substrate 310, one is positioned at the grid 320 on this insulated substrate 310, one is covered in the gate insulator 330 of this insulated substrate 310 and this grid 320, one is positioned at first amorphous silicon layer 341 on this gate insulator 330, one is positioned at the light dope amorphous silicon layer 342 on this first amorphous silicon layer 341, one is positioned at second amorphous silicon layer 343 on this light dope amorphous silicon layer 342, one is positioned at the heavily doped amorphous silicon layer 344 on this second amorphous silicon layer 343, one is positioned at the metal electrode layer 350 on this heavily doped amorphous silicon layer 344 and this gate insulator 330, one covers the passivation layer 360 of this metal electrode layer 350 and this gate insulator 330, and this electrode layer 350 comprises an one source pole 351 and a drain electrode 352.
Seeing also Figure 19, is the flow chart of the manufacture method of this thin-film transistor 300, and this manufacture method comprises the steps: to form a grid (step 301) on insulated substrate; Deposition one gate insulator (step 302) on grid and insulated substrate; On gate insulator, form one first amorphous silicon layer (step 303); On first amorphous silicon layer, form a light dope amorphous silicon layer (step 304); On the light dope amorphous silicon layer, form one second amorphous silicon layer (step 305); On second amorphous silicon layer, form a heavily doped amorphous silicon layer (step 306); On the heavily doped amorphous silicon layer, form a metal electrode layer (step 307); Deposition one passivation layer (step 308) on metal electrode layer and gate pole insulating barrier.
Seeing also Figure 20 to Figure 27, is each step schematic diagram of the manufacture method of this thin-film transistor 300, and it comprises the steps:
Step 301 provides an insulated substrate 310 as shown in figure 20, deposition one metal level on this insulated substrate 310, and on metal level, be coated with a photoresist.One mask is provided, photoresist is carried out exposure imaging and etching sheet metal forms a grid 320.
Step 302 deposits a gate insulator 330 as shown in figure 21 on this insulated substrate 310 and gate pole 320.
Step 303 forms one first amorphous silicon layer 341 as shown in figure 22 on this gate insulator 330, the thickness of this first amorphous silicon layer 341 is less than 60nm.
Step 304 forms a light dope amorphous silicon layer 342 as shown in figure 23 on this first amorphous silicon layer 341.
Step 305 forms one second amorphous silicon layer 343 as shown in figure 24 on this light dope amorphous silicon layer 342.
Step 306 forms a heavily doped amorphous silicon layer 344 as shown in figure 25 on this second amorphous silicon layer 343.
Step 307 deposits a metal level as shown in figure 26 on this heavily doped amorphous silicon layer 344 and this gate insulator 330, and is coated with a photoresist on metal level.One mask is provided, photoresist is carried out exposure imaging and etching sheet metal forms a metal electrode layer 350.This metal electrode layer 350 comprises an one source pole 351 and a drain electrode 352.
Step 308 deposits a passivation layer 360 as shown in figure 27 on this source electrode 351 and drain electrode 352 and this gate insulator 330.
This thin-film transistor 300 is owing to comprise a light dope amorphous silicon layer 342 between first amorphous silicon layer 341 and second amorphous silicon layer 343, electron concentration increases than electron concentration in first amorphous silicon layer 341 and second amorphous silicon layer 343 in this light dope amorphous silicon layer 342, when applying negative voltage between grid 320 and the source electrode 351, the electron concentration that increases can hinder the hole in (block) or compound (re-combine) conducting channel, make electric leakage rheology main trend be suppressed, the big degree of its electric leakage rheology, relax many compared to traditional handicraft, because this light dope amorphous silicon layer 342 is between first amorphous silicon layer 341 and second amorphous silicon layer 343 as conducting channel, the effect in the hole in the electron concentration of its increase obstruction (block) or compound (re-combine) conducting channel is better.
Seeing also Figure 28, is the flow chart of another manufacture method of this thin-film transistor 200.This manufacture method comprises the steps: to form a grid (step 401) on insulated substrate; Deposition one gate insulator (step 402) on grid and insulated substrate; On gate insulator, implement plasma treatment and form a phosphonium ion impurity layer (step 403); Form an amorphous silicon layer on the phosphonium ion impurity layer, phosphonium ion partly diffuses to form a light dope amorphous silicon layer (step 404) to amorphous silicon layer; On amorphous silicon layer, form a heavily doped amorphous silicon layer (step 405); On the heavily doped amorphous silicon layer, form a metal electrode layer (step 406); Deposition one passivation layer (step 407) on metal electrode layer and gate pole insulating barrier.
Seeing also Figure 29, is the flow chart of another manufacture method of this thin-film transistor 300, and this manufacture method comprises the steps: to form a grid (step 501) on insulated substrate; Deposition one gate insulator (step 502) on grid and insulated substrate; On gate insulator, form one first amorphous silicon layer (step 503); On first amorphous silicon layer, implement plasma treatment and form a phosphonium ion impurity layer (step 504); Form one second amorphous silicon layer on the phosphonium ion impurity layer, phosphonium ion partly diffuses to form a light dope amorphous silicon layer (step 505) to first amorphous silicon layer and second amorphous silicon layer; On second amorphous silicon layer, form a heavily doped amorphous silicon layer (step 506); On the heavily doped amorphous silicon layer, form a metal electrode layer (step 507); Deposition one passivation layer (step 508) on metal electrode layer and gate pole insulating barrier.
It is described that thin-film transistor of the present invention is not limited to above-mentioned execution mode, can also use ion implantation as the formation method of light dope amorphous silicon layer and heavily doped amorphous silicon layer, and impurity can also be an arsenic ion.

Claims (4)

1. thin-film transistor, it comprises an insulated substrate, one is positioned at the grid on this insulated substrate, one is covered in the gate insulator of this insulated substrate and this grid, one is positioned at first amorphous silicon layer on this gate insulator, one is positioned at second amorphous silicon layer on this first amorphous silicon layer, and one is positioned at heavily doped amorphous silicon layer and on this second amorphous silicon layer is positioned at metal electrode layer on this heavily doped amorphous silicon layer and this gate insulator; It is characterized in that: this thin-film transistor further comprises a light dope amorphous silicon layer, and this light dope amorphous silicon layer is between this first amorphous silicon layer and this second amorphous silicon layer.
2. the thin-film transistor of stating as claim 1, it is characterized in that: the thickness of this first amorphous silicon layer is less than 60nm.
3. method for fabricating thin film transistor, it may further comprise the steps: form a grid on insulated substrate; Deposition one gate insulator on grid and insulated substrate; On gate insulator, form one first amorphous silicon layer; On first amorphous silicon layer, form one second amorphous silicon layer; On second amorphous silicon layer, form a heavily doped amorphous silicon layer; On the heavily doped amorphous silicon layer, form a metal electrode layer; It is characterized in that: this method for fabricating thin film transistor further forms a light dope amorphous silicon layer, and this light dope amorphous silicon layer is between this first amorphous silicon layer and this second amorphous silicon layer.
4. method for fabricating thin film transistor, it may further comprise the steps: form a grid on insulated substrate; Deposition one gate insulator on grid and insulated substrate; On gate insulator, form one first amorphous silicon layer; On first amorphous silicon layer, form one second amorphous silicon layer; On second amorphous silicon layer, form a heavily doped amorphous silicon layer; On the heavily doped amorphous silicon layer, form a metal electrode layer; It is characterized in that: this method for fabricating thin film transistor further forms a light dope amorphous silicon layer, this light dope amorphous silicon layer is to form a phosphonium ion impurity layer by implement plasma treatment on first amorphous silicon layer, and phosphonium ion partly spreads and forms to first amorphous silicon layer and second amorphous silicon layer.
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