CN100570382C - A kind of integrate circuit testing structure and using method thereof - Google Patents

A kind of integrate circuit testing structure and using method thereof Download PDF

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Publication number
CN100570382C
CN100570382C CNB2006101180238A CN200610118023A CN100570382C CN 100570382 C CN100570382 C CN 100570382C CN B2006101180238 A CNB2006101180238 A CN B2006101180238A CN 200610118023 A CN200610118023 A CN 200610118023A CN 100570382 C CN100570382 C CN 100570382C
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China
Prior art keywords
press welding
welding block
fuse
grid
diode
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Expired - Fee Related
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CNB2006101180238A
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Chinese (zh)
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CN101178423A (en
Inventor
于俊飞
龚斌
陈晨
赵永
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Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
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Publication of CN100570382C publication Critical patent/CN100570382C/en
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Abstract

The present invention has announced a kind of IC test structure and based on a kind of using method of this structure, this structure comprises nmos pass transistor, first press welding block and second press welding block two press welding blocks, diode and fuses, when using this structure, need not be when grid applies negative voltage, the voltage that directly needs is applied to grid is applied on first press welding block,, when applying negative voltage, grid, again negative voltage is applied on second press welding block at needs earlier with blown fuse.

Description

A kind of integrate circuit testing structure and using method thereof
Technical field
A kind of test structure that uses in the integrated circuit testing electrical property, particularly a kind of test structure that can be used in the charge pump test.
Background technology
Current, CP test (charge pump test, charge pumping test) has become a quantitative measurment interface state (interface-states) and oxide layer is gathered the transverse distribution of (Oxide-trapped) electric charge and the strong instrument of energy.Can be used for measuring because of interface state and oxide layer and gather the hot carrier loss that electric charge brings.And be widely used for studying the cross direction profiles and the energy of interface state charge density.
And the fundamental test of CP test is to be based upon on the basic model shown in Figure 1.Transistorized source region and drain region link together and have applied a fixing voltage opposite with substrate.When transistor is anti-phase, press close to surf zone and begin to form dark depletion layer, at this moment, electronics enters channel region from source and drain areas.Part in these electronics can be captured by interface state.When making superficial layer enter accumulated layers for transistorized gate bias voltage, under the reverse biased that is applied must act on, removable electric charge drift again went back to source region and drain region again.But be trapped in that part of electric charge meeting and a large amount of substrate electric charge combinations once more in the interface state, and make substrate produce remaining negative charge.
Just can detect the energy and the electric charge cross direction profiles of interface state electric charge by the electric charge that detects substrate.
But, the NMOS structure diode of present HCL (hot carrier inject, hot carrier injection) monitoring usefulness directly and grid link, be used for protection device not to be subjected to the electricity slurry to cause damaging the influence of (PID, plasma induced damage).As shown in Figure 2, carry out the N type and inject in the zonule at PD place, make the PN junction in N type zone and the formation of P substrate at this PD place, forming one is the diode of P type with the substrate, and with lead the grid of nmos pass transistor is connected to a PD place.
But, this structure, when big negative pressure is arranged on the grid, the diode current flow at PD place, electric current flows to substrate from diode, so can not this kind structure carry out adding at grid the test of negative pressure.
Thereby also just can not carry out the CP test with the test structure of existing this NMOS structure, need the special CP of making test structure to carry out.
Summary of the invention
Test structure at existing HCL monitoring usefulness can not be used for carrying out the problem that CP tests, and the present invention proposes a kind of novel HCL test structure and using method thereof that can be used to do the CP test.
The present invention is connected to the grid of wherein nmos pass transistor on the second press welding block PAD2, and links to each other with another press welding block first press welding block PAD1 by a fuse on the nmos pass transistor structure of existing HCL monitoring usefulness.And the N type district that HCL monitors the diode PD in the NMOS pipe is connected to interconnection line between PAD1 and the fuse, the p type island region of this diode PD is a substrate, so link to each other with substrate.
Like this, with respect to the nmos pass transistor structure of original HCL monitoring usefulness, the test structure that the present invention proposes has structurally increased by one has increased a press welding block and a fuse between diode PD and nmos pass transistor grid.
Like this, when not needing that grid applied negative pressure, what thing the PAD2 in the new construction is not taken over, as the PAD in the original structure, the structure that proposes of the present invention is just consistent with the effect of original structure in this case like this with PAD1.Diode links to each other with the grid of NMOS pipe with PAD2 by interconnection line, the electronics that electricity slurry in the technology is produced can be led away by diode, causes the influence that damages thereby protect nmos pass transistor to avoid the electricity slurry well.
When needs apply negative pressure on grid, under the situation as the CP test, between PAD1 and PAD2, apply high pressure, the fusing fuse.Afterwards, remove high pressure, in the test structure of Xing Chenging, the grid of NMOS pipe just links to each other with PAD2, does not contain diode PD like this.Like this, just can on grid, apply high negative pressure, carry out the CP test and wait the test that need on grid, apply negative pressure.
Use the present invention, only need earlier between the PAD1 of the transistor monitoring of structures that need apply negative pressure and PAD2, to apply high voltage, make resistance wire fusing grid.Can carry out applying the test of negative pressure to these transistors at grid, and to other the nmos pass transistor structure or the transistor arrangement of fusing before the fuse in still contain diode PD, thereby still can suppress the electricity slurry effectively and cause damage.And use the inventive method simple, and convenient, only need fuse and apply high pressure between the transistorized PAD1 of fuse and the PAD2 needs, avoided the manufacturing of special-purpose CP resolution chart.
Description of drawings
Fig. 1 is the basic N channel transistor model that the CP test is adopted;
Fig. 2 is existing HCL monitoring MOS structure;
Fig. 3 is the test structure that the present invention proposes;
Fig. 4 is the synoptic diagram that applies high pressure on PAD1 of the present invention and PAD2;
Fig. 5 be in the present invention at fuse by the structural representation after fusing;
Wherein, the 11st, pulse generator, the 12nd, DC ammeter, the 21st, diode PD, the 31st, fuse.
Embodiment
Present embodiment improves with the structure of nmos pass transistor existing HCL monitoring.Contrast the structure of the monitoring nmos pass transistor of original HCL, see Fig. 2; It is on the second press welding block PAD2 that new test structure is connected to a press welding block at the grid of inciting somebody to action nmos pass transistor wherein, and by fuse 31 and another press welding block promptly the first press welding block PAD1 link to each other, thereby and at N type diffusion region of formation, PD place and diode of P type substrate formation, the N type district of this diode PD is connected to interconnection line between PAD1 and the fuse, sees Fig. 3.
Like this, with respect to the nmos pass transistor structure of original HCL monitoring usefulness, the test structure that the present invention proposes has structurally increased by one has increased a press welding block and a fuse between diode PD and nmos pass transistor grid.
Need to prove, the method for making of the diode PD of the protection usefulness in the present embodiment, promptly the guard method of the n of PD place type injection region is identical with the injection condition of formation source, leakage.
Fuse in the present embodiment forms by the width that reduces a bit of interconnection line between PAD2 and diode PD.The fuse of making like this itself also is the part of interconnection line under the situation of fusing, can play the interconnection line effect, and just connect the width of interconnection line of this fuse than both sides little for the width of this section fuse.When applying high voltage, the effect of fuse is played in fuse place fusing earlier now like this.
The resolution chart that uses present embodiment to propose, when not needing that grid applied negative pressure, what thing PAD2 in the new construction is not taken over, and as the PAD in the original structure, the structure of the present invention's proposition is just consistent with the effect of original structure in this case like this with PAD1.Diode links to each other by the grid of interconnection line with PAD2 and metal-oxide-semiconductor, the electronics that electricity slurry in the technology is produced can be led away by diode, causes the influence that damages thereby protect MOS transistor to avoid the electricity slurry well.
When needs apply negative pressure on grid, under the situation as the CP test, the high positive voltage of on PAD1, exerting pressure, and, see Fig. 4 with PAD2 ground connection, like this owing to be malleation on the PAD1, what diode PD was connected with PAD1 is N type zone, and diode PD oppositely ends like this, and the high pressure between PAD1 and the PAD2 all is applied between the two the interconnection line, because the width of fuse is very little, just fusing under high pressure.Afterwards, remove high pressure, in the test structure of Xing Chenging, the grid of NMOS pipe just links to each other with PAD2, does not contain diode PD, sees Fig. 5 like this.Like this, just can on grid, apply high negative pressure, carry out the CP test and wait the test that need on grid, apply negative pressure.
Use present embodiment, only need earlier between the PAD1 of the transistor monitoring of structures that need apply negative pressure and PAD2, to apply high voltage, make resistance wire fusing grid.Can carry out applying the test of negative pressure to these transistors at grid, and to other the nmos pass transistor structure or the transistor arrangement of fusing before the fuse in still contain diode PD, thereby still can suppress the electricity slurry effectively and cause damage.Thereby can implement as the CP test, need apply the test of negative voltage and not influence the anti-PID performance of other pipes to specific MOS transistor simply and effectively at grid.
Certainly; the present invention can also have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof, those of ordinary skill in the art work as can make various corresponding changes according to the present invention, but these corresponding changes all should belong to the protection domain of claim of the present invention.

Claims (9)

1. IC test structure, comprise nmos pass transistor, first press welding block and second press welding block two press welding blocks, diode and fuses, it is characterized in that, the grid of above-mentioned nmos pass transistor is connected on above-mentioned second press welding block, this second press welding block links to each other with first press welding block with interconnection line by fuse, above-mentioned diode one termination substrate, the other end are connected on the interconnection line between first press welding block and the fuse.
2. IC test structure as claimed in claim 1 is characterized in that above-mentioned fuse is to form by the width that reduces one section interconnection line between first press welding block and diode.
3. as claim 1 or the described IC test structure of claim 2, it is characterized in that above-mentioned diode is to form PN junction by forming a N type diffusion region with P type substrate to constitute.
4. IC test structure as claimed in claim 3, the process conditions that it is characterized in that forming above-mentioned diode N type diffusion region are identical with the process conditions of source electrode that forms the NMOS pipe and drain electrode.
5. a use is as the method for IC test structure as described in any in the claim 1~2, it is characterized in that need not be when grid applies negative voltage, the voltage that directly needs is applied to grid is applied on first press welding block, at needs when grid applies negative voltage, with blown fuse, again negative voltage is applied on second press welding block earlier.
6. the method for IC test structure described in a use such as claim 3 or the claim 4, it is characterized in that need not be when grid applies negative voltage, the voltage that directly needs is applied to grid is applied on first press welding block, at needs when grid applies negative voltage, with blown fuse, again negative voltage is applied on second press welding block earlier.
7. one kind as claim 5 or the described method of claim 6, and the method for the fuse that it is characterized in that fusing is to finish by apply high pressure between first press welding block and second press welding block.
8. a method as claimed in claim 7 when it is characterized in that applying voltage, is connected to first press welding block on the positive voltage, and with the second press welding block ground connection.
9. IC test structure, comprise nmos pass transistor, first press welding block and second press welding block two press welding blocks, diode and fuses, it is characterized in that fuse is also playing the interconnection line effect in this test structure, and to connect the width of lead of this fuse bigger than the width of this fuse on both sides.
CNB2006101180238A 2006-11-07 2006-11-07 A kind of integrate circuit testing structure and using method thereof Expired - Fee Related CN100570382C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2006101180238A CN100570382C (en) 2006-11-07 2006-11-07 A kind of integrate circuit testing structure and using method thereof

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Application Number Priority Date Filing Date Title
CNB2006101180238A CN100570382C (en) 2006-11-07 2006-11-07 A kind of integrate circuit testing structure and using method thereof

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CN100570382C true CN100570382C (en) 2009-12-16

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Publication number Priority date Publication date Assignee Title
CN102253324B (en) * 2011-06-17 2016-01-27 上海集成电路研发中心有限公司 A kind of test structure of MOS device hot carrier's effect and method of testing
CN103969544B (en) * 2014-03-04 2018-02-16 深圳博用科技有限公司 A kind of integrated circuit high pressure pin continuity testing method
CN106898562A (en) * 2015-12-18 2017-06-27 中芯国际集成电路制造(上海)有限公司 The method of the breakdown voltage of semiconductor structure and test grid oxic horizon
CN107393908A (en) * 2017-08-31 2017-11-24 长江存储科技有限责任公司 Mos gate oxygen applied to chip device test cell protects system and method
CN109860150A (en) * 2019-02-28 2019-06-07 德淮半导体有限公司 The test circuit and test method of semiconductor devices

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