CN100565864C - Encapsulation architecture and its making method - Google Patents

Encapsulation architecture and its making method Download PDF

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Publication number
CN100565864C
CN100565864C CN 200810083827 CN200810083827A CN100565864C CN 100565864 C CN100565864 C CN 100565864C CN 200810083827 CN200810083827 CN 200810083827 CN 200810083827 A CN200810083827 A CN 200810083827A CN 100565864 C CN100565864 C CN 100565864C
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surface
carrier
chip
architecture
solid core
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CN 200810083827
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Chinese (zh)
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CN101261976A (en
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张效铨
蔡宗岳
赖逸少
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日月光半导体制造股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73257Bump and wire connectors

Abstract

本发明封装架构及其制造方法,该封装架构包括有一承载器、一固芯架构及一芯片,其中固芯架构在该承载器的第一表面上形成,该固芯架构包括有一凹槽、一堤坝、若干个通孔及若干个焊块,其中这些焊块容纳于通孔中,并与位于该承载器的第一连接垫相对应。 Packet architecture and the manufacturing method of the present invention, the package comprises a carrier framework, a solid-core structure and a chip architecture in which the solid core is formed on a first surface of the carrier, which has a solid core architecture includes a recess, a dams, a plurality of through holes and a plurality of solder bumps, wherein the solder bump is accommodated in the through hole, and the first connection pads located on the corresponding carrier. 芯片嵌置于该固芯架构的凹槽内,且其功能面紧贴于该固芯架构的第一表面上,其第一焊垫与对应的焊块形成电性接触。 A chip embedded in the groove of the fixed core architecture, functional surface and in close contact on the first surface of the solid core architecture, which first pad corresponding to the solder bumps and the electrical contact. 本发明封装架构的芯片可以准确配置于承载器上,不但可简化工艺,还可以使得封装架构内的芯片与承载器之间形成稳定的电性连接效果。 Chip package architecture of the present invention can accurately arranged on the carrier, not only simplifies the process, may be formed such that a stable electrical connection between the chip and the carrier effects within the package structure.

Description

封装架构及其制造方法 Architecture and method for manufacturing the package

【技术领域】 TECHNICAL FIELD

本发明是有关于一种封装架构及其制造方法,特别是有关于一种在承载器上形成有一固晶结构,芯片可嵌设于其中并准确配置于承载器上的新式封装架构及其制造方法。 The present invention relates to a package and a manufacturing method architecture, particularly to a method of forming on a solid carrier having a crystal structure, wherein the chip may be embedded in the new package on the exact configuration and architecture of the carrier and its manufacturing method. 【背景技术】 【Background technique】

由于芯片技术不断朝高频、高脚数的方向发展,单纯依靠传统的打线封装已经无法满足电性上的要求。 As the chip technology continues in the direction of high-frequency, high number of foot development, relying solely on traditional wire package has been unable to meet the requirements of electrical. 芯片倒装封装采用锡铅凸块作为芯片与基板间的连接的封装技术,芯片倒装封装除了可大幅度提高芯片接脚的密度以外, 还可降低噪声干扰、强化电性效能、提高散热性能及缩减封装体积等。 Flip-chip package using solder bumps as an encapsulation technology to connect between the chip and the substrate, flip-chip packaging density can be greatly improved in addition to the chip pins, can reduce noise, to strengthen the electrical performance, improved thermal performance reduce the package size and the like. 但是, 该芯片倒装封装仍有相当多的技术难题需要克服。 However, the flip-chip package there are still many technical problems to overcome. 例如,为确保芯片与基板之间的密合,须以点胶方式来填满芯片与基板间的空隙。 For example, to ensure adhesion between the chip and the substrate, shall dispense pattern to fill the gap between the chip and the substrate. 然而,在点胶作业时,胶体的流动方向很难控制,极易造成充填胶体外溢,污染到位于基板点胶区以外的表面,以致于影响后续的焊线或其它无源元件的装设品质。 However, when dispensing operations, is difficult to control the flow direction of the colloid, the colloid can easily cause spills filling, contaminate the surface of the substrate located outside the dispensing zone, mounted so as to impact the quality of the subsequent wire bonding or other passive elements .

美国专利第6,400,036号提出一种在基板上形成一阻溢提的半导体芯片结构体200,如图l所示,该阻溢堤201位于基板202的芯片接置区2021与外焊垫2022之间的区域中。 U.S. Patent No. 6,400,036 proposes a structure of forming a semiconductor chip overflow barrier put on the substrate member 200, as shown in FIG. L, the bank 201 is located in the overflow barrier counter chip bonding region 2021 between the substrate 202 and the outer pad 2022 area. 然而,虽然该现有的半导体芯片结构体200的阻溢提201可以解决溢胶的问题,但由于基板202与芯片203之间的空隙很小, 而芯片203的接脚数又相当多,因此在封胶工艺中,当要利用封胶204填满基板202与芯片203之间的空隙时,不但要花费很长一段时间,而且对封胶材料的黏度、温度均有相当高的要求,甚至于封胶材料的热膨胀系数也要详细考虑,否则会严重影响该半导体芯片结构体200内部的电性连接的安全性。 However, although the conventional semiconductor chip 200 of the overflow barrier structure 201 can solve the problem mentioned excess glue, but the gap between the substrate 202 and the chip 203 is small, and the number of pins and considerable chip 203, thus in a sealed plastic process, when using a sealant 204 to fill the gap between the substrate 202 and the chip 203, not only it takes a long time, but also on the viscosity sealant material, the temperature requirements are relatively high, even coefficient of thermal expansion of the sealant material should be considered in detail, otherwise it will seriously affect the safety of the electrical internal structure of the semiconductor chip 200 is connected.

为解决上述问题,美国专利第6,138,348号提出一种在基板上形成内连接导电聚合物300的方法,如图2所示,在第一基板301的每一第一接合垫3011上均形成有一导电块3012,在第二基板302的其中一表面形成一有机保护层303,并且第二基板302的每-"第二接合垫3021均分别暴露于该有机保护层303的通孔3031中。当第一基板301设置于第二基板302上时,通过第一接合垫3011、导电块3012及第二接合垫3021的相互连接,可使得第一基板301与第二基板302之间形成电连接。然而,该现有的方法虽可避免在第一基板301与第二基板302之间产生间隙,从而解决封胶困难的问题,爿f旦该方法必须要借助对位接合器(aligner bonder),才能够使得位于第一基板301 上的第一4妻合垫3011与导电块3012对准相应通孑L 3031及第二接合垫3021。 然而,通过对位接合器使第一基板301配置于第二基板302上的方法相当 To solve the above problems, U.S. Patent No. 6,138,348 proposes a method for connecting the conductive polymer is formed on the substrate 300, as shown, each of the first substrate 301 in a first bonding pads 2 are formed on a conductive 3011 block 3012, an organic protective layer 303 is formed on one surface of the second substrate 302 and second substrate 302 of each - "second bonding pad 3021 are exposed to the through holes 3031 are the organic protective layer 303 when the first. when a substrate 301 disposed on the second substrate 302, the first bonding pads 3011, 3012 are connected to each other and the conductive bumps second bonding pad 3021, such that an electrical connection may be between the first substrate 301 and the second substrate 302. However , although the conventional method can avoid a gap between the first substrate 301 and second substrate 302, so as to solve difficult problems sealant, once f valves must be using the method of the bit adapter (aligner bonder), it 4 so that the first can be positioned on the first substrate 301 wife bond pads 3011 are aligned with the corresponding through the conductive block 3012 larvae L 3031 and the second bonding pad 3021. However, by the engagement of the bit 301 moves the first substrate disposed on the second method on the substrate 302 rather 复杂、操作极其不便,该现有的结构设计存在有缺陷,所以仍有进一步改进的必要。 Complex, extremely inconvenient operation, the conventional design there is a defective, so that further improvement is still necessary.

【发明内容】 [SUMMARY]

本发明的主要目的在于提供一种封装架构及其制造方法,其可以筒化封装架构的制造方法,并提高封装架构的电性连接效果。 The main object of the present invention is to provide a framework package and a manufacturing method, which can be cylindrical package manufacturing method of the architecture, and improve the effect of electrically connecting the package architecture.

为达成本发明的前述目的,本发明提供一种封装架构,其包括有: 一承载器、 一固芯架构及一芯片,其中承载器具有相对的一第一表面及一第二表面,该第一表面上具有若干个第一连接垫;固芯架构设置于该承载器上,该固芯架构具有相对的一第一表面及一第二表面,且该固芯架构的第二表面紧贴于该承载器的第一表面上,该固芯架构包括有一凹槽、 一提坝、若干个通孔及若干个焊块,其中凹槽形成于该固芯架构的第一表面上;堤坝位于该凹槽周围;通孔位于该凹槽的区域内并贯穿于该固芯架构的第一表面及第二表面;焊块容纳于通孔中;其中通孔及其内对应的焊块位于该承载器的这些第一连接垫上,并且这些第一连接垫与对应的焊块形成电性接触;以及芯片具有相对的一功能面及一背面,在该功能面上具有若干个第一焊垫,该芯片嵌置于该固 To achieve the above object of the present invention, the present invention provides a packaging structure, comprising: a carrier, a solid-core structure and a chip, wherein the carrier has a first opposing surface and a second surface, said first a first surface having a plurality of connection pads; solid core architecture disposed on the carrier, the solid core architecture having a first opposing surface and a second surface, and the second surface of the solid core architecture close contact on a first surface of the carrier, which has a solid core framework comprises a recess, mention dam, a plurality of through holes and a plurality of solder bumps, wherein a groove is formed on the first surface of the solid core architecture; dam located around the recess; located within the through hole of the recess region and throughout the first and second surfaces of the solid core architecture; pads housed in the through hole; wherein the through-hole and the corresponding pads located at the carrier these's first connection pad and the first connection pad and the corresponding electrical contact pads; and a chip having a functional surface opposite a back surface and having a first plurality of pads on the functional surface, the the embedded chip disposed solid 架构的凹槽内,且其功能面紧贴于该固芯架构的第一表面上,而这些第一焊垫与对应的焊块形成电性接触。 Within the framework of the recess, and the functional surface against the first surface of the solid core architecture, which corresponds to the first pads and solder bumps form electrical contacts.

为达成本发明的前述目的,本发明提供一种封装架构的制造方法,其包 To achieve the above object of the present invention, the present invention provides a method for producing a package architecture, which package

括有以下步骤:提供一承载器,该承载器具有相对的一第一表面及一第二表面,该第一表面上具有若干个第一连接垫;形成一固芯架构于该承载器的第一表面,该固芯架构具有相对的一第一表面及一第二表面,且该固芯架构的第二表面紧贴于该承载器的第一表面,该固芯架构包括有一凹槽,形成于该固芯架构的第一表面上; 一堤坝,位于该凹槽周遭;以及若干个通孔,位于该凹槽的区域内并贯穿于该固芯架构的第一表面及第二表面,且这些通孔位于该承载器的这些第一连接垫上,并将这些第一连接垫暴露于其中;植入若干个焊块于这些通孔中,这些焊块位于该承载器的这些第一连接垫上,并且与这些第一连接垫形成电性接触;以及嵌入一芯片于该固芯架构的凹槽内, 该芯片具有相对的一功能面及一背面,于该功能面上具有若干个第一焊垫, 且该 Comprising the steps of: providing a carrier, the carrier having a first opposing surface and a second surface, the first surface having a first plurality of connection pads; to form a solid core of the architecture of the carrier a surface opposite to the solid core architecture having a first surface and a second surface, and the second surface of the solid core architecture in close contact with the first surface of the carrier, which comprises a solid core architecture groove formed on the first surface of the solid core architecture; a dam, is located around the recess; region and a plurality of through-holes, located in the groove and through the first and second surfaces of the solid core framework, and which are positioned on the carrier is connected to the first pad and the first connection pad exposed therein; a plurality of pads implanted in the through-holes, these solder bumps located on the first carrier is connected to these pads and the first connection pad is formed with the electrical contact; and a chip embedded in the solid core architecture recess opposite the chip has a functional surface and a back surface having a first plurality of bonding to the functional surface pad, and the 能面紧贴于该固芯架构的第一表面上,而这些第一焊垫则与对应的焊块形成电性接触。 We can face in close contact on the first surface of the solid core framework, which are a first electrical contact pad is formed with the corresponding solder bumps.

与现有技术相比较,本发明封装架构的芯片嵌设于固芯架构内并由此准 Compared with the prior art, the present invention is packaged chip architecture is embedded in the solid core and thereby quasi framework

确配置于承载器上,这样不但可简化制造方法,还可以使得封装架构内的芯 Indeed disposed on the carrier, it will not only simplify the manufacturing process so that the core may also be encapsulated within the framework

片与承载器之间形成稳定的电性连接效果。 To form a stable electrical connection between the chip and the carrier effects. 【附图说明】 BRIEF DESCRIPTION

图l是一现有的封装结构的示意图。 Figure l is a schematic view of a conventional package structure.

图2是另一现有的封装结构的示意图。 FIG 2 is a schematic diagram of another conventional packaging structure.

图3A是本发明封装架构的承载器的示意图。 FIG 3A is a schematic diagram of the architecture of the package carrier of the present invention.

图3B是本发明在承载器的第一表面上敷设一涂覆层的示意图。 3B is a coating layer of the present invention is laid on the first surface of the carrier of FIG.

图3C是本发明在承载器的第一表面形成一固芯架构的示意图。 3C is a schematic view of the present invention, a solid core is formed in a first surface of the framework of the carrier.

图3D是本发明在固芯架构的通孔中植入若干个焊块的示意图。 FIG 3D is a schematic view of the implant of the present invention a plurality of solder bump in the through hole of the solid core architecture. 图3E是本发明在固芯架构的凹槽内嵌入一芯片的示意图。 3E is a chip of the present invention is embedded in the recess of a solid core architecture FIG.

图3F是本发明在承载器的第一表面上形成一封胶的示意图。 3F is a schematic view of the present invention is a gel formed on the first surface of the carrier.

图4是本发明封装架构的示意图。 4 is a schematic of the architecture of the package of the present invention.

图5是本发明封装架构的封装方法的流程图。 5 is a flowchart of a method for packaging the package architecture of the present invention. 【具体实施方式】 【Detailed ways】

本实施例将会结合图示对本发明封装架构的制造方法作详细介绍。 The present embodiment will illustrate a method of manufacturing the package in conjunction with the architecture of the present invention will be described in detail.

请参照图3A及图5的步骤a所示,首先须提供一承载器10,该承载器10具有相对的一第一表面11及一第二表面12,且于第一表面11上形成有一芯片接置区14,于该芯片接置区14内形成有若千个第一连接垫13。 Referring to FIG. 3A and FIG. 5 step a, first required to provide a carrier 10, the carrier 10 has a first surface opposite a second surface 11 and 12, and is formed with a chip on the first surface 11 contact region 14 is set, if there are one thousand first connection pad 13 formed within the chip bonding area 14 is set.

请参照图3B所示,在该承载器10的第一表面11上敷设一涂覆层20, 在本实施例中,该涂^1层20是一阻焊层(solder mask )。 Referring to FIG 3B, the laying of a coating layer 20 on the first surface 10 of the carrier 11, in this embodiment, the coat layer 20 ^ 1 is a solder layer (solder mask).

请参照图3C 所示,对该涂覆层20进行蚀刻,以在该承载器10的第一表面11形成一固芯架构30,该固芯架构30具有相对的一第一表面31及一第二表面32,且该固芯架构30的第二表面32紧贴于承载器10的第一表面11上。 Referring to FIG. 3C, etching the coating layer 20 to first surface 11 of the carrier 10 is formed in a solid core architecture 30, 31 and 30 having a first surface opposite to a first of the solid core architecture second surface 32, and the second surface of the solid core 30 of the framework 32 in close contact with the first surface 10 of the carrier 11. 该固芯架构30包括有一凹槽33、 一i是坝34及若干个通孔35。 The solid core architecture 30 includes a recess 33, i is a dam 34 and a plurality of through holes 35. 该凹槽33形成于固芯架构30的第一表面31上。 The recess 33 is formed on a solid core of the first surface 31 on framework 30. 在本实施例中,该凹槽33位于承载器10的芯片接置区14内;该堤坝34位于凹槽33周围,且位于承载器10的芯片接置区14外。 In the present embodiment, the groove 33 is positioned opposite the chip bonding region 14 of the carrier 10; dam 34 located around the recess 33, and is located opposite the chip bonding region 10 of the carrier 14 outside. 这些通孔35位于该凹槽33的区域内并贯穿于该固芯架构30的第一表面31及第二表面32之间,且这些通孔35位于该浮义载器10的这些第一连接垫13上,并将这些第一连接垫13暴露于其中。 The inner region of the recess 33 through the through holes 35 and between the first surface of the solid core 31 of the framework 30 and the second surface 32, and the through-holes 35 is positioned such that the floating carrier sense of the first connector 10 pad 13 and the first connection pad 13 is exposed therein.

在本实施例中,该提坝34的高度小于该芯片50的背面52的高度,如图3E中所示。 In the present embodiment, the lifting height of the dam 34 is less than the height of the back surface 52 of the chip 50, as shown in FIG 3E. 当然,该堤坝34的高度也可等于该芯片50的背面52的高度, 而只须确保芯片50以嵌入的方式置于该凹槽33中即可。 Of course, the height of the dam 34 may also be equal to the height of the back surface 52 of the chip 50, but only ensure that the chip 50 is insert can be disposed in the recess 33.

本发明可以采用干式蚀刻、湿式蚀刻或离子束蚀刻等工艺对该涂覆层20 进行蚀刻。 The present invention is a dry etching, wet etching or ion beam etching and other processes can be used etching the coating layer 20. 需要说明的是,本发明固芯架构30的形成可不限定为对涂覆层20进行蚀刻而形成,也可采用其它方式形成,例如,利用才莫具在该承载器IO Incidentally, to form a solid core architecture of the present invention is not limited to 30 for the coating layer 20 is formed by etching, may also be formed in other ways, e.g., by using only the carrier having Mo IO

的第一表面11形成一固芯架构30,并且该晶圓架构30的各个部分:凹槽33、 一堤坝34及若干个通孔35,可以是一次形成,也可以是各个部分分步形成。 The first surface 11 is formed of a solid core 30 architecture, and the architecture of each wafer portion 30: groove 33, a dam 34 and a plurality of through-holes 35, may be formed at once, or may be formed in various portions of stepwise. 本发明的重点在于:于该承载器10的第一表面11形成一固芯架构30,而非以对该涂覆层20进行蚀刻为目的,如图5的步骤b所示。 Focus of the present invention is that: in the first surface 11 of carrier 10 is formed a solid core architecture 30, rather than in the coating layer 20 is etched for the purpose, as shown in step b of FIG 5.

请参照图3D及图5的步骤c所示,在固芯架构30的这些通孔35中植入若干个焊块40,这些焊块40位于该承载器10的这些第一连接垫13上, 并与第一连接垫13形成电性接触。 Referring to FIG. 3D and FIG. 5 as shown in step C, a plurality of solder bumps 40 implanted in the solid core architecture 35 of the through-holes 30, the solder bump 40 which is located on the carrier 13 a first connection pad 10, and electrical contact with the first connecting pad 13 is formed.

请参照图3E及图5的步骤d所示,在该固芯架构30的凹槽33内嵌入一芯片50,该芯片50具有相对的一功能面51及一背面52,在该功能面51 上设有若干个第一焊垫53,且该功能面51紧贴于该固芯架构30的第一表面31上,这些第一焊垫53与对应的焊块40形成电性接触。 Referring to FIG. 3E shown in FIG. 5 and step d, a chip 50 is embedded in the solid core 30 architecture grooves 33, the chip 50 has a back surface 51 and opposite to a functional surface 52, the surface feature 51 a plurality of first pads 53 and 51 against the surface feature on the first surface 30 of the fixed core architecture 31, the first pad 53 and the solder bump 40 is formed corresponding to the electrical contact.

通过以上制造方法而形成一新式封装架构100,如图3E所示,该封装架构100的芯片50嵌入于固芯架构30内并藉此设置于承载器10上。 And forming a new packet architecture 100, shown in Figure 3E, the architecture of the chip package 100 is embedded in the solid core 50 within the framework 30 and thereby the carrier 10 is provided by the above manufacturing method. 这样,不但可筒化制造方法,还可以在芯片50与承载器IO之间形成稳定的电性连接效果。 Thus, not only the cartridge manufacturing method, may also form a stable effect electrical connection between the chip carrier 50 and the IO.

当然,在上述步骤d之后,本发明封装架构IOO的制造方法还可以另外再进行一回焊步骤,即对第一连接垫13、焊块40及第一焊垫53进行加热, 以使得第一连接垫13、焊块40及第一焊垫53黏结在一起。 Of course, after the step d, the method for producing the package of the present invention IOO architecture may additionally performing a reflow step further, i.e. to the first connection pad 13, the solder bumps 40 and the first pad 53 is heated, so that the first connection pads 13, 40 and a first solder bump pads 53 stick together. 然后,再在该承载器IO的第一表面11上形成一封月交60,如图3F所示,该封胶60覆盖该芯片50、该固芯架构30及该^c载器10的第一表面11。 Then, formed on the first surface of the carrier 11 an IO months post 60, shown in Figure 3F, the encapsulant 60 covers the chip 50, the solid core of the framework 30 and carrier 10 ^ c a surface 11.

请参照图4所示,在本发明封装架构100的承载器10的第一表面11上还可设置若干个第二连接垫15,这些第二连接垫15位于芯片接置区14外。 Referring to FIG. 4, the first surface of the package on the architecture of the present invention, the carrier 10 11 100 may also be provided a plurality of second connection pads 15, the second connection pads 15 is located outside the chip bonding region 14 is set. 另外,在该承载器10的第二表面12上可设置若干个第三连接垫16,其上可植设若干个焊球70。 Further, on the second surface 10 of the carrier 12 may be provided with a plurality of third connection pads 16, which can be implanted on a number of solder balls 70. 再者,该芯片50的背面52上也可设置若干个第二焊垫54。 Further, on the back surface of the chip 5250 may also be provided a plurality of second pad 54. 在此种配置下,在封装过程中,可在封胶之前,进行一打线步骤,以在 In this configuration, during the packaging process, the sealant may be prior to performing a wire bonding step, to the

该芯片50及该承载器IO之间形成若干条焊线80,用以连接芯片50的第二焊垫52及承载器10的第二连接垫15。 It is formed between the chip carrier 50 and the IO plurality of bonding wires 80 for connecting the second bonding pad of the second chip 50 is connected to the carrier 52, and 10 of pad 15. 然后,再进行封胶工艺,以在该承载器10的第一表面11上形成一封胶60,覆盖芯片50、固芯架构30、承载器lO的第一表面ll、焊线80、芯片50的第二焊垫54,以及承载器10的第二连接垫15。 Then, then sealed plastic process to form a gel 60 on the first surface 11 of the carrier 10, 50 covers the chip, the solid core architecture 30, the first surface of the carrier lO ll, the bonding wire 80, chip 50 a second pad 54, and a second carrier 10 is connected to pad 15. 而在封胶之后,该方法还可再包括有植焊球的步骤,即在该承载器10的第三连接垫16上形成若干个焊球70。 And after the encapsulant, the method may further comprise the steps of planting balls, i.e., a plurality of solder balls 70 formed on the third carrier 10 connected to pad 16.

Claims (16)

1.一种封装架构,包括有:一承载器以及一芯片,其中所述承载器具有相对的一第一表面及一第二表面,在第一表面上具有若干个第一连接垫,所述芯片具有相对的一功能面及一背面,在功能面上具有若干个第一焊垫,其特征在于:所述封装架构还包括一设置于所述承载器上的固芯架构,所述固芯架构具有相对的一第一表面及一第二表面,且所述固芯架构的第二表面紧贴于承载器的第一表面上,所述固芯架构包括有:一凹槽、一堤坝、若干个通孔以及若干个焊块,其中所述凹槽形成于所述固芯架构的第一表面上,堤坝位于所述凹槽周围,通孔位于所述凹槽的区域内并贯穿所述固芯架构的第一表面及第二表面,焊块容纳于所述通孔中,其中所述通孔及其内对应的焊块位于所述承载器的所述第一连接垫上,并且所述第一连接垫与对应的焊块形成电性接 1. A package structure, comprising: a chip and a carrier, wherein the carrier has a first opposing surface and a second surface, having a plurality of first connection pads on the first surface, the chip having a functional surface opposite to a back surface and having a plurality of pads on a first surface feature, wherein: said package further comprising a framework disposed on the carrier on a solid core architecture, said solid core framework having a first opposing surface and a second surface, and the second surface of the solid core architecture close contact on the first surface of the carrier, the solid core architecture comprising: a recess, a dam, the region of a plurality of through holes and a plurality of solder bumps, wherein said groove is formed on the first surface of the solid core architecture, the dam is located around the recess, a through hole in said recess and said through a first solid surface and a second surface of the core architecture, solder bumps received in the through hole, wherein the through-hole and the solder bumps located within the corresponding said first connecting pad carrier, and the the first connection pad corresponding to the solder bumps to form electrical contact ,所述芯片嵌置于所述固芯架构的凹槽内,且其功能面紧贴于所述固芯架构的第一表面上,而所述第一焊垫则与对应的焊块形成电性接触。 Within the chip embedded in the solid core architecture disposed grooves, and close contact with the functional surface on the first surface of the solid core framework, and said first pad is formed with the corresponding electrical pads sexual contact.
2. 如权利要求1所述的封装架构,其特征在于:所述封装架构还包括有一封胶,设置于所述承载器的第一表面上,并且覆盖所述芯片、所述固芯架构及所述承载器的第一表面。 2. The package architecture according to claim 1, wherein: said package further comprises a plastic framework, disposed on the first surface of the carrier, and covering the chip, and the solid core architecture a first surface of the carrier device.
3. 如权利要求1所述的封装架构,其特征在于:所述固芯架构的堤坝的高度小于或等于芯片的背面的高度。 The package architecture of claim 1, wherein: said solid core architecture dam height of less than or equal to the height of the back surface of the chip.
4. 如权利要求1所述的封装架构,其特征在于:在所述承载器的第一表面上形成有一芯片接置区,第一连接垫形成于所述芯片接置区内,所述固芯架构的堤坝位于所述芯片接置区外,而所述固芯架构的凹槽的区域位于所述芯片接置区内。 4. The package architecture according to claim 1, wherein: a chip bonding formed on a first surface area facing the carrier, the first connection pads formed on the chip contact zone opposite the solid core architecture dam region located on the opposite outer chip bonding, and the solid core architecture recess located in the area opposite the chip bonding area.
5. 如权利要求4所述的封装架构,其特征在于:在所述承载器的第一表面上还具有若干个第二连接垫,且所述第二连接垫位于所述芯片接置区外, 在所述芯片的背面上还具有若干个第二焊垫,所述封装架构还包括有若干条焊线,连接于所述芯片的第二焊垫与所述承载器的第二连接垫之间。 5. The package architecture of claim 4, wherein: on a first surface of the carrier further having a plurality of second connection pads, and the second external connection pad located opposite the chip bonding region , on the back surface of the chip further having a plurality of second pads, the package further comprising a plurality of schema of bonding wires, is connected to the second connection pads of the second chip pads and the carrier is between.
6. 如权利要求5所述的封装架构,其特征在于:所述封装架构还包括有一封胶,所述封胶覆盖所述芯片、所述固芯架构、所述承载器的第一表面、 所述焊线、所述芯片的第二焊垫,以及所述承载器的第二连接垫。 6. The package architecture of claim 5, wherein: said package further comprises a plastic framework, said sealant covering said chip, said solid core architecture, the first surface of the carrier device, the bonding wire, a second pad of the chip, and a second connection pad of the carrier.
7. 如权利要求1或6所述的封装架构,其特征在于:在所述承载器的第二表面上具有若干个第三连接垫,所述第三连接垫上设置有若干个焊球。 7. The package architecture of claim 1 or claim 6, further comprising: a plurality of third connection pads on the second surface of the carrier, the third connection pad is provided with a plurality of balls.
8. —种封装架构的制造方法,其特征在于:包括有下列步骤: 提供一承载器,所述承载器具有相对的一第一表面及一第二表面,所述第一表面上具有若干个第一连接垫;在所述承载器的第一表面上形成一固芯架构,所述固芯架构具有相对的一第一表面及一第二表面,且所述固芯架构的第二表面紧贴于所述承载器的第一表面,所述固芯架构包括有一凹槽、 一堤坝以及若干个通孔,其中所述凹槽形成于所述固芯架构的第一表面上,所述提坝位于所述凹槽周围,通孔位于所述凹槽的区域内并贯穿于所述固芯架构的第一表面及第二表面,且所述通孔位于所述承载器的第一连接垫上,并将第一连接垫暴露于其中;在所述通孔中植入若千个焊块,所述焊块位于所述承载器的所述第一连接垫上,并且与所述第一连接垫形成电性接触;以及在所述固芯架构的凹槽 8. - Manufacturing method of encapsulation architecture, characterized by: comprising the steps of: providing a carrier, the carrier having a first opposing surface and a second surface, having a plurality of the first surface a first connection pad; second surface is formed on a first surface of the carrier is a solid-core structure, the solid core architecture having a first opposing surface and a second surface, and the solid core architecture tight affixed to the first surface of the carrier, said solid core framework comprises a recess, and a plurality of through holes dams, wherein the grooves are formed on the first surface of the solid core framework, the lifting the dam is located around the recess, the through hole located within said recess region and throughout said first solid core architecture and second surfaces, and said through hole in said first connection pad carrier and wherein the first connection pad is exposed to; implanted in the through-hole when one thousand solder bumps, the solder bumps located on the carrier of said first connection pads, and forming the first electrically connecting pads sexual contact; and said solid core architecture groove 嵌入一芯片,所述芯片具有相对的一功能面及一背面,所述功能面上具有若干个笫一焊垫,且所述功能面紧贴于所述固芯架构的第一表面上,而所述第一焊垫则与对应的焊块形成电性接触。 Embedded in a chip, said chip having a functional surface opposite to a back surface and the functional surface having a plurality of pads Zi, and in close contact with the functional surface on the first surface of the solid core framework, and said first electrical contact pad is formed with the corresponding solder bumps.
9. 如权利要求8所述的封装架构的制造方法,其特征在于:所述制造方法还包括在所述承载器的第一表面上形成一封胶,以覆盖所述芯片、所述固芯架构及所述承载器的第一表面的步骤。 9. The manufacturing method according to claim 8 package architecture, wherein: said manufacturing method further comprising forming an adhesive on a first surface of the carrier, so as to cover said chip, said solid core a first step of the surface structure and the carrier.
10. 如权利要求8所述的封装架构的制造方法,其特征在于:所述固芯架构的堤坝的高度小于或等于所述芯片的背面的高度。 10. The manufacturing method according to claim 8 package architecture, wherein: the height of the dam solid core architecture less than or equal to the height of the back of the chip.
11. 如权利要求8所述的封装架构的制造方法,其特征在于:形成所述固芯架构的步骤包括有在所述承载器的第一表面敷设一涂覆层,并蚀刻所述涂覆层以形成所述固芯架构,对所述涂覆层进行蚀刻采用干式蚀刻、湿式蚀刻或离子束蚀刻。 11. The manufacturing method according to claim 8 package architecture, wherein: said step of forming said coating comprises a solid core framework laying a coating layer on a first surface of the carrier, and etched said core layer to form a solid structure, the coating layer is etched by dry etching, wet etching or ion beam etching.
12. 如权利要求9所述的封装架构的制造方法,其特征在于:在封胶之前,所述方法还包括有回焊步骤,以对第一连接垫、焊块及第一焊垫进行加热,以使得所述第一连接垫、焊块及第一焊垫黏结在一起。 12. The manufacturing method according to claim 9 package architecture, wherein: before the sealant, the method further comprises the step of reflow, to heat the first connection pad, a first solder bump pads and so that the first connection pad, a first solder bump pads and stick together.
13. 如权利要求9所述的封装架构的制造方法,其特征在于:在所述承栽器的第一表面上形成有一芯片接置区,所述第一连接垫形成于所述芯片接置区内,所述固芯架构的堤坝位于所述芯片接置区外,而所述固芯架构的凹槽的区域位于所述芯片接置区内。 13. The method according to claim 9 schema package, wherein: a chip bonding is formed on a region opposing the first bearing surface is planted, the first connection pads formed on the chip bonding opposed region, the solid core architecture dam located outside said chip bonding region opposed, and said solid core architecture recess located in the area opposite the chip bonding area.
14. 如权利要求13所述的封装架构的制造方法,其特征在于:所述承载器的第一表面上具有若干个第二连接垫,且所述第二连接垫位于所述芯片接置区外,所述芯片的背面上具有若干个第二焊垫,在封胶之前,所述方法还包括有一打线步骤,其在芯片及承载器之间形成若干条焊线,用以连接所述芯片的第二焊垫及所述承载器的第二连接垫。 14. The manufacturing method according to claim 13 package architecture, comprising: a plurality of second connection pads on a first surface of the carrier, and the second connection pad located opposite the chip bonding region in addition, having a plurality of second pads on the back surface of the chip, prior to sealant, said method further comprising a wire bonding step of forming a plurality of weld lines between the chip and the carrier, to connect the a second connection pad and the second pad of the chip carrier.
15. 如权利要求14所述的封装架构的制造方法,其特征在于:所述方法还包括在所述承载器的第一表面上形成一封胶,以覆盖芯片、固芯架构、承载器的第一表面、焊线、芯片的第二焊垫,以及承载器的第二连接垫。 The manufacturing method according to claim 14 package architecture, characterized in that: said method further comprises forming an adhesive on a first surface of the carrier to cover the chip, solid-core structure, the carrier a first surface of the second connection pads, bonding wires, a second pad of the chip and the carrier.
16. 如权利要求8或15所述的封装架构的制造方法,其特征在于:所述承载器的第二表面上具有若干个第三连接垫,在封胶之后,所述方法还包括有一植焊球的步骤,在所述承载器的第三连接垫上形成若干个焊球。 The manufacturing method of claim 8 or claim 15 architecture package, wherein: a plurality of third connection pads on the second surface of the carrier, after the sealant, the method further comprising an implant step of solder balls, the carrier in the third connection pad is formed of a plurality of solder balls.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6138348A (en) 1989-12-18 2000-10-31 Polymer Flip Chip Corporation Method of forming electrically conductive polymer interconnects on electrical substrates
US6400036B1 (en) 2000-06-03 2002-06-04 Siliconware Precision Industries Co., Ltd. Flip-chip package structure and method of fabricating the same
CN1457098A (en) 2002-05-09 2003-11-19 旺宏电子股份有限公司 Semiconductor arrangement and producing method thereof
CN101131990A (en) 2006-08-21 2008-02-27 日月光半导体制造股份有限公司 Stacked chip packaging construction

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6138348A (en) 1989-12-18 2000-10-31 Polymer Flip Chip Corporation Method of forming electrically conductive polymer interconnects on electrical substrates
US6400036B1 (en) 2000-06-03 2002-06-04 Siliconware Precision Industries Co., Ltd. Flip-chip package structure and method of fabricating the same
CN1457098A (en) 2002-05-09 2003-11-19 旺宏电子股份有限公司 Semiconductor arrangement and producing method thereof
CN101131990A (en) 2006-08-21 2008-02-27 日月光半导体制造股份有限公司 Stacked chip packaging construction

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